19-1869; Rev 0; 11/07 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Features The MAX16047/MAX16049 EEPROM-configurable system managers monitor, sequence, and track multiple system voltages. The MAX16047 manages up to twelve system voltages simultaneously, and the MAX16049 manages up to eight supply voltages. These devices integrate an analog-to-digital converter (ADC) for monitoring supply voltages, and configurable outputs for sequencing and tracking supplies (during power-up and power-down). Nonvolatile EEPROM registers are configurable for storing upper and lower voltage limits, setting timing and sequencing requirements, and for storing critical fault data for read back following failures. o Operates from 3V to 14V o 1% Accurate 10-Bit ADC Monitors 12/8 Inputs o 12/8 Monitored Inputs with One Overvoltage/ An internal 1% accurate 10-bit ADC measures each input and compares the result to one upper, one lower, and one selectable upper or lower limit. A fault signal asserts when a monitored voltage falls outside the set limits. Up to three independent fault output signals are configurable to assert under various fault conditions. o Closed-Loop Tracking for Up to Four Channels o Two Programmable Fault Outputs and One Reset Output o Six General-Purpose Input/Outputs Configurable as: The integrated sequencer/tracker allows precise control over the power-up and power-down order of up to twelve (MAX16047) or up to eight (MAX16049) power supplies. Four channels (EN_OUT1–EN_OUT4) support closedloop tracking using external series MOSFETs. Six outputs (EN_OUT1–EN_OUT6) are configurable with chargepump outputs to directly drive MOSFETs without closedloop tracking. The MAX16047/MAX16049 include six programmable general-purpose inputs/outputs (GPIOs). In addition to serving as EEPROM-configurable I/O pins, the GPIOs are also configurable as dedicated fault outputs, as a watchdog input or output (WDI/WDO), or as a manual reset (MR). The MAX16047/MAX16049 feature two methods of fault management for recording information during critical fault events. The fault logger records a failure in the internal EEPROM and sets a lock bit protecting the stored fault data from accidental erasure. An I2C/SMBus™-compatible or a JTAG serial interface configures the MAX16047/MAX16049. These devices are offered in a 56-pin 8mm x 8mm TQFN package and are fully specified from -40°C to +85°C. SMBus is a trademark of Intel Corp. One Undervoltage/One Selectable Limit o Nonvolatile Fault Event Logger o Power-Up and Power-Down Sequencing Capability o 12/8 Outputs for Sequencing/Power-Good Indicators Dedicated Fault Output Watchdog Timer Function Manual Reset o I2C/SMBus-Compatible and JTAG Interface o EEPROM-Configurable Time Delays and Thresholds o 100 Bytes of Internal User EEPROM o 56-Pin (8mm x 8mm) TQFN Package o -40°C to +85°C Operating Temperature Range Applications Servers Workstations Storage Systems Networking/Telecom Ordering Information PART TEMP RANGE PINPACKAGE PKG CODE MAX16047ETN+ -40°C to +85°C 56 TQFN-EP** T5688-3 MAX16049ETN+* -40°C to +85°C 56 TQFN-EP** T5688-3 +Denotes a lead-free package. *Future product—contact factory for availability. **EP = Exposed Pad. Selector Guide and Pin Configurations appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX16047/MAX16049 General Description 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers MAX16047/MAX16049 VSUPPLY 10μF OUT IN DC-DC EN MON1 GND +3.3V VCC EN_OUT1 OUT IN SDA DC-DC MAX16047 EN RESET RESET FAULT INT WDI I/O WDO INT GND EN_OUT2– EN_OUT11 OUT IN VCC SCL MON2–MON11 MON12 μC ABP DC-DC DBP EN GND A0 1μF 1μF EN_OUT12 GND 2 EN _______________________________________________________________________________________ MAX16047/MAX16049 Typical Operating Circuit 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers EN_OUT1–EN_OUT6 (configured as charge pump) ...........-0.3V to (VMON1–6 + 6V) Continuous Current (all pins)............................................±20mA Continuous Power Dissipation (TA = +70°C) 56-Pin TQFN (derate 47.6mW/°C above +70°C) .......3810mW* Thermal Resistance θJA ............................……………………………………...21°C/W θJC............................……………………………………..0.6°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C *As per JEDEC 51 Standard, Multilayer Board (PCB). Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 3V to 14V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1) PARAMETER Operating Voltage Range Undervoltage Lockout Undervoltage-Lockout Hysteresis Supply Current SYMBOL VCC VUVLO CONDITIONS RESET output asserted low MIN 3 MAX 14 (Note 2) 2.85 UVLOHYS ICC TYP 1.4 50 VCC = 14V, VEN = 3.3V, no load on any output 3.8 UNITS V V mV 5 mA DBP Regulator Voltage VDBP CDBP = 1µF, no load on any output 2.6 2.7 2.8 V ABP Regulator Voltage VABP CABP = 1µF, no load 2.78 2.88 2.96 V Boot Time tBOOT VCC > VUVLO 0.8 1.5 ms +5 % Internal Timing Accuracy (Note 3) -5 ADC ADC Resolution 10 ADC Total Unadjusted Error (Note 4) ADCERR ADC Integral Nonlinearity ADCINL ADC Differential Nonlinearity ADCDNL ADC Total Monitoring Cycle Time MON_ Input Impedance tCYCLE RIN Bits MON_ range set to ‘00’ in r0Fh–r11h 0.65 MON_ range set to ‘00’ in r0Fh–r11h 0.75 MON_ range set to ‘00’ in r0Fh–r11h 0.95 All channels monitored, no MON_ fault detected (Note 5) 80 % FSR 0.8 LSB 0.8 LSB 100 µs MON1–MON4 46.5 100 MON5–MON12 65 140 kΩ _______________________________________________________________________________________ 3 MAX16047/MAX16049 ABSOLUTE MAXIMUM RATINGS VCC to GND ....................……………………………-0.3V to +15V EN, MON_, SCL, SDA, A0 ........................................-0.3V to +6V GPIO_, EN_OUT7–EN_OUT12, RESET (configured as open drain) to GND.......................-0.3V to +6V EN_OUT1–EN_OUT6 (configured as open-drain) to GND ....................-0.3V to +12V GPIO_, EN_OUT, RESET (configured as push-pull) to GND .........-0.3V to (VDBP + 0.3V) DBP, ABP to GND ......-0.3V to the lower of 3V and (VCC + 0.3V) TCK, TMS, TDI.......................................................-0.3V to +3.6V TDO ..........................................................-0.3V to (VDBP + 0.3V) MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers ELECTRICAL CHARACTERISTICS (continued) (VCC = 3V to 14V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1) PARAMETER ADC MON_ Ranges ADC LSB Step Size EN Input-Voltage Threshold EN Input Current SYMBOL ADCRNG ADCLSB CONDITIONS MIN TYP MON_ range set to ‘00’ in r0Fh–r11h 5.6 MON_ range set to ‘01’ in r0Fh–r11h 2.8 MON_ range set to ‘10’ in r0Fh–r11h 1.4 MON_ range set to ‘00’ in r0Fh–r11h 5.46 MON_ range set to ‘01’ in r0Fh–r11h 2.73 MON_ range set to ‘10’ in r0Fh–r11h 1.36 VTH_EN_R EN voltage rising 0.525 VTH_EN_F EN voltage falling IEN EN Input Voltage Range 0.487 0.500 MAX UNITS V mV 0.512 V -0.5 +0.5 µA 0 5.5 V CLOSED-LOOP TRACKING Tracking Differential Voltage Stop Ramp VTRK VINS_ > VTH_PL, VINS_ < VTH_PG Tracking Differential Voltage Hysteresis Tracking Differential Fault Voltage Track/Sequence Slew-Rate Rising or Falling INS_ Power-Good Threshold Power-Good Threshold Hysteresis VTRK_F TRKSLEW VTH_PG VTH_PL Power-Low Hysteresis VTH_PL_HYS 20 %VTRK 285 330 375 Slew-rate register set to ‘00’ 640 800 960 Slew-rate register set to ‘01’ 320 400 480 Slew-rate register set to ‘10’ 160 200 240 Slew-rate register set to ‘11’ 80 100 120 Power-good register set to ‘00,’ VMON_ = 3.5V 94 95 96 Power-good register set to ‘01,’ VMON_ = 3.5V 91.5 92.5 93.5 Power-good register set to ‘10,’ VMON_ = 3.5V 89 90 91 Power-good register set to ‘11,’ VMON_ = 3.5V 86.5 87.5 88.5 INS_ falling GPIOINR GPIO_ configured as INS_ INSRPD VINS_ = 2V V/s 125 142 %VTH_PG 160 10 INS_ to GND Pulldown Impedance when Enabled mV %VMON_ 0.5 GPIO_ Input Impedance 4 mV VINS_ > VTH_PL, VINS_ < VTH_PG VPG_HYS Power-Low Threshold 150 75 100 100 _______________________________________________________________________________________ mV mV 145 kΩ Ω 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers (VCC = 3V to 14V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.4 V OUTPUTS (EN_OUT_, RESET, GPIO_) Output-Voltage Low VOL Output-Voltage High (Push-Pull) ISINK = 2mA ISOURCE = 100µA 2.4 V 1 Output Leakage (Open Drain) IOUT_LKG GPIO1–GPIO4, VGPIO_ = 3.3V GPIO1–GPIO4, VGPIO_ = 5V EN_OUT_ Overdrive (Charge Pump) (EN_OUT1 to EN_OUT6 Only) Volts above VMON_ EN_OUT_ Pullup Current (Charge Pump) EN_OUT_ Pulldown Current (Charge Pump) VOV µA 1 22 IGATE_ = 0.5µA 4.6 5.1 5.6 V ICHG_UP During power-up/power-down, VGATE_ = 1V 4.5 6 µA ICHG_DOWN During power-up/power-down, VGATE_ = 5V 10 µA INPUTS (A0, GPIO_) Logic-Input Low Voltage VIL Logic-Input High Voltage VIH 0.8 2.0 V V SMBus INTERFACE Logic-Input Low Voltage VIL Input voltage falling Logic-Input High Voltage VIH Input voltage rising 2.0 VCC shorted to GND, SCL/SDA at 0V or 3.3V -1 +1 -1 +1 Input Leakage Current Output-Voltage Low VOL Input Capacitance SMBus TIMING CIN Serial Clock Frequency Bus Free Time Between STOP 0.8 V V ISINK = 3mA 0.4 5 fSCL µA V pF 400 kHz tBUF 1.3 µs START Condition Setup Time tSU:STA 0.6 µs START Condition Hold Time tHD:STA 0.6 µs STOP Condition Setup Time tSU:STO 0.6 µs Clock Low Period tLOW 1.3 µs Clock High Period tHIGH 0.6 µs tSU:DAT 100 ns Data Setup Time Output Fall Time tOF Data Hold Time tHD:DAT Pulse Width of Spike Suppressed tSP 10pF ≤ CBUS ≤ 400pF From 50% SCL falling to SDA change 0.3 30 250 ns 0.9 µs ns _______________________________________________________________________________________ 5 MAX16047/MAX16049 ELECTRICAL CHARACTERISTICS (continued) MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers ELECTRICAL CHARACTERISTICS (continued) (VCC = 3V to 14V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.55 V JTAG INTERFACE TDI, TMS, TCK Logic-Low Input Voltage VIL Input voltage falling TDI, TMS, TCK Logic-High Input Voltage VIH Input voltage rising 2 TDO Logic-Output Low Voltage VOL_TDO VDBP ≥ 2.5V, ISINK = 2mA TDO Logic-Output High Voltage VOH_TDO VDBP ≥ 2.5V, ISOURCE = 200µA 2.4 TDO high impedance -1 Pullup to VDBP 7 TDO Leakage Current TDI, TMS Pullup Resistors RJPU Input/Output Capacitance CI/O V 0.4 V V 10 +1 µA 13 kΩ 5 pF JTAG TIMING TCK Clock Period TCK High/Low Time t1 1000 500 ns t2, t3 50 ns TCK to TMS, TDI Setup Time t4 15 TCK to TMS, TDI Hold Time t5 15 TCK to TDO Delay t6 500 ns TCK to TDO High-Z Delay t7 500 ns 12 ms ns ns EEPROM TIMING EEPROM Byte Write Cycle Time tWR (Note 6) 10.5 Note 1: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at TA = +25°C and TA = +85°C. Specifications at TA = -40°C are guaranteed by design. Note 2: VUVLO is the minimum voltage on VCC to ensure the device is EEPROM configured. Note 3: Applies to RESET, fault, delay, and watchdog timeouts. Note 4: Total unadjusted error is a combination of gain, offset, and quantization error. Note 5: Guaranteed by design. Note 6: An additional cycle is required when writing to configuration memory for the first time. 6 _______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers MAX16047/MAX16049 SDA tBUF tSU:DAT tSU:STA tHD:DAT tLOW tHD:STA tSU:STO SCL tHIGH tHD:STA tR tF START CONDITION STOP CONDITION REPEATED START CONDITION START CONDITION Figure 1. I2C/SMBus Timing Diagram t1 t2 t3 TCK t4 t5 TDI, TMS t6 t7 TDO Figure 2. JTAG Timing Diagram _______________________________________________________________________________________ 7 Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) NORMALIZED MON_ THRESHOLD vs. TEMPERATURE 3.0 2.5 TA = +25°C TA = -40°C 2.0 1.5 1.0 1.008 1.006 1.004 1.002 1.000 0.998 0.996 0.994 0.5 0.990 -45 -30 -15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 15 30 45 60 75 0.995 0.990 0.985 90 -45 -30 -15 0 15 30 45 60 TEMPERATURE (°C) NORMALIZED RESET TIMEOUT PERIOD vs. TEMPERATURE TRANSIENT DURATION vs. THRESHOLD OVERDRIVE (EN) 120 100 80 60 40 MAX16047 toc05 140 1.10 1.08 NORMALIZED RESET TIMEOUT MAX16047 toc04 160 20 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 0 1 -45 -30 -15 100 10 0 15 30 45 60 TEMPERATURE (°C) MON_ PUV THRESHOLD OVERDRIVE vs. TRANSIENT DURATION OUTPUT-VOLTAGE LOW vs. SINK CURRENT DEGLITCH = 16 140 120 100 80 DEGLITCH = 8 60 DEGLITCH = 4 40 20 75 90 0.40 0.35 OUTPUT-VOLTAGE LOW (V) 160 MAX16047 toc06 EN OVERDRIVE (mV) MAX16047 toc07 TRANSIENT DURATION (μs) 1.010 1.005 1.000 TEMPERATURE (°C) VCC (V) TRANSIENT DURATION (μs) 1.020 1.015 0.980 0.975 0.970 2.8V RANGE, HALF SCALE, PUV THRESHOLD 0.992 0 0.30 EN_OUT_ 0.25 GPIO_ 0.20 0.15 0.10 0.05 DEGLITCH = 2 0 0 10 175 340 505 670 835 THRESHOLD OVERDRIVE (mV) 8 1.030 1.025 MAX16047 toc03 3.5 1.010 MAX16047 toc02 TA = +85°C NORMALIZED MON_ THRESHOLD MAX16047 toc01 4.0 NORMALIZED EN THRESHOLD vs. TEMPERATURE NORMALIZED EN_ THRESHOLD VCC SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE ICC (mA) MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers 1000 0 1 2 3 4 SINK CURRENT (mA) _______________________________________________________________________________________ 5 6 75 90 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers OUTPUT-VOLTAGE HIGH vs. SOURCE CURRENT (PUSH-PULL OUTPUT) 4 3 2 2.65 2.60 2.55 2.50 1 2.45 0 2.40 1.0 MAX16047 toc10 MAX16047 toc09 OUTPUT-VOLTAGE HIGH (V) 5 2.70 OUTPUT-VOLTAGE HIGH (V) MAX16047 toc08 6 ADC ACCURACY vs. TEMPERATURE 0.8 TOTAL UNADJUSTED ERROR (%) OUTPUT-VOLTAGE HIGH vs. SOURCE CURRENT (CHARGE-PUMP OUTPUT) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0 1 2 3 4 5 6 7 -1.0 0 SOURCE CURRENT (μA) 100 200 300 400 -45 -30 -15 0 15 30 45 60 75 90 TEMPERATURE (°C) SOURCE CURRENT (μA) TRACKING MODE FET TURN-ON WITH CHARGE PUMP MAX16047 toc12 MAX16047 toc11 VEN_OUT_ 10V/div 0V INS4 INS3 VSOURCE 2V/div 0V INS2 1V/div INS1 IDRAIN 1A/div 0V 0V 20ms/div 20ms/div TRACKING MODE WITH FAST SHUTDOWN SEQUENCING MODE MAX16047 toc13 MAX16047 toc14 INS4 INS4 INS3 INS2 1V/div INS3 1V/div INS2 INS1 INS1 0V 0V 20ms/div 40ms/div _______________________________________________________________________________________ 9 MAX16047/MAX16049 Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.) ADC DNL MIXED MODE MAX16047 toc15 MAX16047 toc16 1.0 0.8 INS3 1V/div INS2 ADC DNL (LSB) 0.6 INS4 INS1 0.4 0.2 0 -0.2 -0.4 -0.6 0V -0.8 -1.0 0 20ms/div 128 256 384 512 640 768 896 1024 INPUT VOLTAGE (DIGITAL CODE) INTERNAL TIMING ACCURACY vs. TEMPERATURE ADC INL 0.6 0.4 0.2 0 -0.2 -0.4 1.04 1.03 1.02 1.01 1.00 0.99 0.98 -0.6 0.97 -0.8 0.96 0.95 -1.0 0 128 256 384 512 640 768 896 1024 INPUT VOLTAGE (DIGITAL CODE) 10 1.05 MAX16047 toc18 0.8 NORMALIZED SLOT DELAY MAX16047 toc17 1.0 ADC INL (LSB) MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers -45 -30 -15 0 15 30 45 TEMPERATURE (°C) ______________________________________________________________________________________ 60 75 90 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers PIN NAME FUNCTION MAX16047 MAX16049 1–8 1–8 9–12 — 13 13 RESET 14 14 A0 15 15 SCL SMBus Serial Clock Input 16 16 SDA SMBus Serial Data Open-Drain Input/Output 17 17 TMS JTAG Test Mode Select 18 18 TDI JTAG Test Data In 19 19 TCK JTAG Test Clock 20 20 TDO JTAG Test Data Out 21, 40 21, 40 GND Ground. Connect all GND connections together. 22 22 GPIO6 23 23 GPIO5 24 24 EN 25–36 9–12, 25–36, 53–56 N.C. MON1–MON8 ADC Monitored Voltage Inputs. Set ADC input range for each MON_ through configuration registers. Measured values are written to ADC registers and can be read back through the I2C or JTAG interface. ADC Monitored Voltage Inputs. Set ADC input range through configuration registers. MON9–MON12 Measured values are written to ADC registers and can be read back through the I2C or JTAG interface. Configurable Reset Output Four-State SMBus Address. Address sampled upon POR. Connect A0 to ground, DBP, SCL, or SDA to program an individual address when connecting multiple devices. See the I2C/SMBus-Compatible Serial Interface section. General-Purpose Input/Output. GPIO6 and GPIO5 are configurable as open-drain or push-pull outputs, dedicated fault outputs, or for watchdog functionality. GPIO5 is configurable as a watchdog input (WDI). GPIO6 is configurable as a watchdog output (WDO). GPIO6 is also configurable for margining. Use the EEPROM to configure GPIO5 and GPIO6. See the General-Purpose Inputs/Outputs section. Analog Enable Input. Apply a voltage greater than the 0.525V (typ) threshold to enable all outputs. The power-down sequence is triggered when EN falls below 0.5V (typ) and all outputs are deasserted. No Connection. Must be left unconnected. ______________________________________________________________________________________ 11 MAX16047/MAX16049 Pin Description MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Pin Description (continued) PIN NAME FUNCTION MAX16047 MAX16049 37 37 ABP Internal Analog Voltage Bypass. Bypass ABP to GND with a 1µF ceramic capacitor. ABP powers the internal circuitry of the MAX16047/MAX16049. Do not use ABP to power any external circuitry. 38 38 VCC Power-Supply Input. Bypass VCC to GND with a 10µF ceramic capacitor. DBP Internal Digital Voltage Bypass. Bypass DBP to GND with a 1µF ceramic capacitor. DBP supplies power to the EEPROM memory, to the internal logic circuitry, and to the internal charge pumps when the programmable outputs are configured as charge pumps. All push-pull outputs are referenced to DBP. Do not use DBP to power any external circuitry. 39 GPIO1 General-Purpose Input/Output 1. Configure GPIO1 as a logic input, a return sense line for closed-loop tracking, an open-drain/push-pull fault output, or an open-drain/pushpull output port. Use the EEPROM to configure GPIO1. See the General-Purpose Inputs/Outputs section. GPIO2 General-Purpose Input/Output 2. GPIO2 is configurable as a logic input, a return sense line for closed-loop tracking, an open-drain/push-pull fault output, or an open-drain/ push-pull output port. Use the EEPROM to configure GPIO2. See the General-Purpose Inputs/Outputs section. GPIO3 General-Purpose Input/Output 3. GPIO3 is configurable as a logic input, a return sense line for closed-loop tracking, an open-drain/push-pull fault output, or an open-drain/ push-pull output port. Use the EEPROM to configure GPIO3. See the General-Purpose Inputs/Outputs section. 44 GPIO4 General-Purpose Input/Output 4. GPIO4 is configurable as a logic input, a return sense line for closed-loop tracking, an open-drain/push-pull fault output, or an open-drain/ push-pull output port. GPIO4 is also configurable as an active-low manual reset, MR. Use the EEPROM to configure GPIO4. See the General-Purpose Inputs/Outputs section. 45–50 45–50 EN_OUT1– EN_OUT6 Output. EN_OUT1–EN_OUT6 are configurable with active-high/active-low logic and with an open-drain or push-pull configuration. Program the EEPROM to configure EN_OUT1–EN_OUT6 as a charge-pump output 5V greater than the monitored input voltage (VMON_ + 5V). EN_OUT1–EN_OUT4 can also be used for closed-loop tracking. 51, 52 51, 52 EN_OUT7– EN_OUT8 Output. Configure EN_OUT_ with active-low/active-high logic and with an open-drain or push-pull configuration. 53–56 — EN_OUT9– EN_OUT12 Output. Configure EN_OUT_ with active-low/active-high logic and with an open-drain or push-pull configuration. — — EP 41 42 43 44 12 39 41 42 43 Exposed Pad. Internally connected to GND. Connect to GND. EP also functions as a heatsink to maximize thermal dissipation. Do not use as the main ground connection. ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers VCC MAX16047 MAX16049 FAULT1 EN FAULT2 LOGIC VTH_EN VOLTAGE SCALING AND MUX WDI WATCHDOG TIMER 10-BIT ADC (SAR) ADC REGISTERS THRESHOLD REGISTERS CLOSED-LOOP TRACKER WDO FAULTPU INS1 INS2 INS3 INS4 GPIO2 GPIO CONTROL MON1– MON12 (MON1– MON8) GPIO1 MARGIN DIGITAL COMPARATORS NONVOLATILE FAULT EVENT LOGGER MR GPIO3 GPIO4 GPIO5 GPIO6 RAM REGISTERS EN_OUT1– EN_OUT4 EEPROM REGISTERS SEQUENCER EN_OUT1– EN_OUT12 (EN_OUT1– EN_OUT8) RESET I2C SLAVE INTERFACE GND A0 SDA SCL JTAG INTERFACE TMS TCK TDI TDO ( ) MAX16049 ONLY. ______________________________________________________________________________________ 13 MAX16047/MAX16049 Functional Diagram MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Register Summary (All Registers 8-Bits Wide) Note: This data sheet uses a specific convention for referring to bits within a particular address location. As an example, r15h[3:0] refers to bits 3 through 0 in register with address 15 hexadecimal. PAGE Extended Default and EEPROM REGISTER DESCRIPTION ADC Conversion Results (Registers r00h to r17h) Input ADC conversion results. ADC writes directly to these registers during normal operation. ADC input ranges (MON1–MON12) are selected with registers r0Fh to r11h. Failed Line Flags (Registers r18h to r19h) Voltage fault flag bits. Flags for each input signal when undervoltage or overvoltage threshold is exceeded. GPIO Data (Registers r1Ah to r1Bh) GPIO state data. Used to read back and control the state of each GPIO. ADC Range Selections (Registers r0Fh to r11h) ADC input voltage range. Selects the voltage range of the monitored inputs. Fault Behavior (Registers r47h to r4Ch) Selects how the device should operate during faults. Options include latch-off or autoretry after fault. The autoretry delay is selectable (r4Fh). Use registers r48h through r4Ch to select fault conditions that trigger a critical fault event. GPIO Configuration (Registers r1Ch to r1Eh) General-purpose input/output configuration registers. GPIOs are configurable as a manual-reset input, a margin disable input, a watchdog timer input and output, logic inputs/outputs, fault-dependent outputs, or as the feedback/pulldown inputs (INS_) for closed-loop tracking. Overvoltage and Undervoltage Thresholds (Registers r23h to r46h) Input overvoltage and undervoltage thresholds. ADC conversion results are compared to overvoltage and undervoltage threshold values stored here. MON_ voltages exceeding threshold values trigger a fault event. Programmable Output Configuration (Registers r1Fh to r22h) Programmable output configurations. Selectable output configurations include: activelow or active-high, open-drain or push-pull outputs. EN_OUT1–EN_OUT6 are configurable as charge-pump outputs and EN_OUT1–EN_OUT4 can be configured for closed-loop tracking. RESET and Fault Outputs (Registers r15h to r1Bh) RESET, FAULT1, and FAULT2 output configuration. Programs the functionality of the RESET, FAULT1, and FAULT2 outputs, as well as which inputs they depend on. Sequencing-Mode Configuration (Registers r50h to r5Bh and r5Eh to r63h) Assign inputs and outputs for sequencing. Select sequence delays (20µs to 1.6s) with registers r50h through r54h. Use register r54h to enable/disable the reverse sequence bit for power-down operation. Software Enable and Margin (Register r4Dh) Use register r4Dh to set the Software Enable bit, to select early warning thresholds and undervoltage/overvoltage, to enable/disable margining, and to enable/disable the watchdog for independent/dependent mode. Watchdog Functionality (Register r55h) Configure watchdog functionality for GPIO5 and GPIO6. Fault Log Results (Registers r00h to r0Eh) ADC conversion results and failed-line flags at the time of a fault. These values are recorded by the fault event logger at the time of a critical fault. EEPROM User EEPROM (Registers r9Ch to rFFh) 14 User-available EEPROM ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Getting Started The MAX16047 is capable of managing up to twelve system voltages simultaneously, and the MAX16049 can manage up to eight system voltages. After bootup, if EN is high and the Software Enable bit is set to ‘0,’ an internal multiplexer cycles through each input. At each multiplexer stop, the 10-bit ADC converts the monitored analog voltage to a digital result and stores the result in a register. Each time the multiplexer finishes a conversion (8.3µs max), internal logic circuitry compares the conversion results to the overvoltage and undervoltage thresholds stored in memory. If a conversion violates a programmed threshold, the conversion can be configured to generate a fault. Logic outputs can be programmed to depend on many combinations of faults. Additionally, faults are programmable to trigger the nonvolatile fault logger, which writes all fault information automatically to the EEPROM and write-protects the data to prevent accidental erasure. The MAX16047/MAX16049 contain both I2C/SMBuscompatible and JTAG serial interfaces for accessing registers and EEPROM. Use only one interface at any given time. For more information on how to access the internal memory through these interfaces, see the I2C/SMBusCompatible Serial Interface and JTAG Serial Interface sections. Registers are divided into three pages with access controlled by special I2C and JTAG commands. The factory-default values at POR (power-on reset) for all RAM registers are ‘0’s. POR occurs when VCC reaches the undervoltage-lockout threshold (UVLO) of 2.85V (max). At POR, the device begins a boot-up sequence. During the boot-up sequence, all monitored inputs are masked from initiating faults and EEPROM contents are copied to the respective register locations. During bootup, the MAX16047/MAX16049 are not accessible through the serial interface. The boot-up sequence can take up to 1.5ms, after which the device is ready for normal operation. RESET is low during boot-up and remains low after boot-up for its programmed timeout period once all monitored channels are within their respective thresholds. During boot-up, the GPIOs and EN_OUTs are high impedance. Accessing the EEPROM The MAX16047/MAX16049 memory is divided into three separate pages. The default page, selected by default at POR, contains configuration bits for all functions of the part. The extended page contains the ADC conversion results and GPIO input and output registers. Finally, the EEPROM page contains all stored configuration information as well as saved fault data and user-defined data. See the Register Map table for more information on the function of each register. During the boot-up sequence, the contents of the EEPROM (r0Fh to r7Dh) are copied into the default page (r0Fh to r7Dh). Registers r00h to r0Eh of the EEPROM page contain saved fault data. The JTAG and I 2C interfaces provide access to all three pages. Each interface provides commands to select and deselect a particular page: • 98h(I 2 C)/09h(JTAG)—Switches to the extended page. Switch back to the default page with 99h(I2C)/0Ah(JTAG). • 9Ah(I 2 C)/0Bh(JTAG)—Switches to the EEPROM page. Switch back to the default page with 9Bh(I2C)/0Ch(JTAG). See the I2C/SMBus-Compatible Serial Interface or the JTAG Serial Interface section. Power Apply 3V to 14V to V CC to power the MAX16047/ MAX16049. Bypass VCC to ground with a 10µF capacitor. Two internal voltage regulators, ABP and DBP, supply power to the analog and digital circuitry within the device. Do not use ABP or DBP to power external circuitry. ABP is a 2.85V (typ) voltage regulator that powers the internal analog circuitry. Bypass the ABP output to GND with a 1µF ceramic capacitor installed as close to the device as possible. DBP is an internal 2.7V (typ) voltage regulator. EEPROM and digital circuitry are powered by DBP. All push-pull outputs are referenced to DBP. DBP supplies the input voltage to the internal charge pumps when the programmable outputs are configured as charge-pump outputs. Bypass the DBP output to GND with a 1µF ceramic capacitor installed as close as possible to the device. ______________________________________________________________________________________ 15 MAX16047/MAX16049 Detailed Description MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Enable To initiate sequencing/tracking and enable monitoring, the voltage at EN must be above 0.525V and the Software Enable bit in r4Dh[0] must be set to ‘0.’ To power down and disable monitoring, either pull EN below 0.5V or set the Software Enable bit to ‘1.’ See Table 1 for the software enable bit configurations. Connect EN to ABP if not used. If a fault condition occurs during the power-up cycle, the EN_OUT_ outputs are powered down immediately, independent of the state of EN. If operating in latch-on fault mode, toggle EN or toggle the Software Enable bit to clear the latch condition and restart the device once the fault condition has been removed. Table 1. EEPROM Software Enable Configurations REGISTER/ EEPROM ADDRESS BIT RANGE DESCRIPTION 0 Software Enable bit 0 = Enabled. EN must also be high to begin sequencing 1 = Disabled (factory default) 1 Margin bit 1 = Margin functionality is enabled 0 = Margin disabled 2 Early Warning Selection bit 0 = Early warning thresholds are undervoltage thresholds 1 = Early warning thresholds are overvoltage thresholds 3 Watchdog Mode Selection bit 0 = Watchdog timer is in dependent mode 1 = Watchdog timer is in independent mode 4Dh [7:4] Not used Voltage Monitoring The MAX16047/MAX16049 feature an internal 10-bit ADC that monitors the MON_ voltage inputs. An internal multiplexer cycles through each of the twelve inputs, taking 100µs (typ) for a complete monitoring cycle. Each acquisition takes approximately 8.3µs. At each multiplexer stop, the 10-bit ADC converts the analog input to a digital result and stores the result in a register. ADC conversion results are stored in registers r00h to r17h in the extended page. Use the I2C or JTAG serial interface to read ADC conversion results. See the I2C/SMBus-Compatible Serial Interface or the JTAG Serial Interface section for more information on accessing the extended page. The MAX16047 provides twelve inputs, MON1–MON12, for voltage monitoring. The MAX16049 provides eight inputs, MON1–MON8, for voltage monitoring. Each input voltage range is programmable in registers r0Fh to r11h (see Table 2). When MON_ configuration 16 registers are set to ‘11,’ MON_ voltages are not monitored or converted, and the multiplexer does not stop at these inputs, decreasing the total cycle time. These inputs cannot be configured to trigger fault conditions. The three programmable thresholds for each monitored voltage include an overvoltage, an undervoltage, and an early warning threshold that can be set in r4Dh[2] to be either an undervoltage or overvoltage threshold. See the Faults section for more information on setting overvoltage and undervoltage thresholds. All voltage thresholds are 8 bits wide. The 8 MSBs of the 10-bit ADC conversion result are compared to these overvoltage and undervoltage thresholds. For any undervoltage or overvoltage condition to be monitored and any faults detected, the MON_ input must be assigned to a particular sequence order. See the Sequencing section for more details on assigning MON_ inputs. ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers MAX16047/MAX16049 Table 2. Input Monitor Ranges and Enables REGISTER/ EEPROM ADDRESS BIT RANGE DESCRIPTION [1:0] MON1 Voltage Range Selection: 00 = From 0 to 5.6V in 5.46mV steps 01 = From 0 to 2.8V in 2.73mV steps 10 = From 0 to 1.4V in 1.36mV steps 11 = MON1 is not converted or monitored [3:2] MON2 Voltage Range Selection: 00 = From 0 to 5.6V in 5.46mV steps 01 = From 0 to 2.8V in 2.73mV steps 10 = From 0 to 1.4V in 1.36mV steps 11 = MON2 is not converted or monitored [5:4] MON3 Voltage Range Selection: 00 = From 0 to 5.6V in 5.46mV steps 01 = From 0 to 2.8V in 2.73mV steps 10 = From 0 to 1.4V in 1.36mV steps 11 = MON3 is not converted or monitored [7:6] MON4 Voltage Range Selection: 00 = From 0 to 5.6V in 5.46mV steps 01 = From 0 to 2.8V in 2.73mV steps 10 = From 0 to 1.4V in 1.36mV steps 11 = MON4 is not converted or monitored [1:0] MON5 Voltage Range Selection: 00 = From 0 to 5.6V in 5.46mV steps 01 = From 0 to 2.8V in 2.73mV steps 10 = From 0 to 1.4V in 1.36mV steps 11 = MON5 is not converted or monitored [3:2] MON6 Voltage Range Selection: 00 = From 0 to 5.6V in 5.46mV steps 01 = From 0 to 2.8V in 2.73mV steps 10 = From 0 to 1.4V in 1.36mV steps 11 = MON6 is not converted or monitored [5:4] MON7 Voltage Range Selection: 00 = From 0 to 5.6V in 5.46mV steps 01 = From 0 to 2.8V in 2.73mV steps 10 = From 0 to 1.4V in 1.36mV steps 11 = MON7 is not converted or monitored [7:6] MON8 Voltage Range Selection: 00 = From 0 to 5.6V in 5.46mV steps 01 = From 0 to 2.8V in 2.73mV steps 10 = From 0 to 1.4V in 1.36mV steps 11 = MON8 is not converted or monitored 0Fh 10h ______________________________________________________________________________________ 17 MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Table 2. Input Monitor Ranges and Enables (continued) REGISTER/ EEPROM ADDRESS BIT RANGE DESCRIPTION [1:0] MON9 Voltage Range Selection*: 00 = From 0 to 5.6V in 5.46mV steps 01 = From 0 to 2.8V in 2.73mV steps 10 = From 0 to 1.4V in 1.36mV steps 11 = MON9 is not converted or monitored [3:2] MON10 Voltage Range Selection*: 00 = From 0 to 5.6V in 5.46mV steps 01 = From 0 to 2.8V in 2.73mV steps 10 = From 0 to 1.4V in 1.36mV steps 11 = MON10 is not converted or monitored [5:4] MON11 Voltage Range Selection*: 00 = From 0 to 5.6V in 5.46mV steps 01 = From 0 to 2.8V in 2.73mV steps 10 = From 0 to 1.4V in 1.36mV steps 11 = MON11 is not converted or monitored [7:6] MON12 Voltage Range Selection*: 00 = From 0 to 5.6V in 5.46mV steps 01 = From 0 to 2.8V in 2.73mV steps 10 = From 0 to 1.4V in 1.36mV steps 11 = MON12 is not converted or monitored 11h *MAX16047 only 18 ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers enabled are not converted by the ADC; they contain the last value acquired before that channel was disabled. The ADC conversion result registers are reset to 00h at boot-up. These registers are not reset when a reboot command is executed. Table 3. ADC Conversion Registers EXTENDED PAGE ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h BIT RANGE [7:0] [7:6] [5:0] [7:0] [7:6] [5:0] [7:0] [7:6] [5:0] [7:0] [7:6] [5:0] [7:0] [7:6] [5:0] [7:0] [7:6] [5:0] [7:0] [7:6] [5:0] [7:0] [7:6] [5:0] [7:0] [7:6] [5:0] [7:0] [7:6] [5:0] [7:0] [7:6] [5:0] [7:0] [7:6] [5:0] DESCRIPTION MON1 ADC Conversion Result (MSB) MON1 ADC Conversion Result (LSB) Reserved MON2 ADC Conversion Result (MSB) MON2 ADC Conversion Result (LSB) Reserved MON3 ADC Conversion Result (MSB) MON3 ADC Conversion Result (LSB) Reserved MON4 ADC Conversion Result (MSB) MON4 ADC Conversion Result (LSB) Reserved MON5 ADC Conversion Result (MSB) MON5 ADC Conversion Result (LSB) Reserved MON6 ADC Conversion Result (MSB) MON6 ADC Conversion Result (LSB) Reserved MON7 ADC Conversion Result (MSB) MON7 ADC Conversion Result (LSB) Reserved MON8 ADC Conversion Result (MSB) MON8 ADC Conversion Result (LSB) Reserved MON9 ADC Conversion Result (MSB)* MON9 ADC Conversion Result (LSB)* Reserved MON10 ADC Conversion Result (MSB)* MON10 ADC Conversion Result (LSB)* Reserved MON11 ADC Conversion Result (MSB)* MON11 ADC Conversion Result (LSB)* Reserved MON12 ADC Conversion Result (MSB)* MON12 ADC Conversion Result (LSB)* Reserved *MAX16047 only ______________________________________________________________________________________ 19 MAX16047/MAX16049 The extended memory page contains the ADC conversion result registers (see Table 3). These registers are also used internally for fault threshold comparison. Voltage-monitoring thresholds are compared with the 8 MSBs of the conversion results. Inputs that are not MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers General-Purpose Inputs/Outputs dependent outputs, or as the feedback inputs (INS_) for closed-loop tracking. When programmed as outputs, GPIOs are open drain or push-pull. See registers r1Ch to r1Eh in Tables 4 and 5 for more detailed information on configuring GPIO1–GPIO6. GPIO1–GPIO6 are programmable general-purpose inputs/outputs. GPIO1–GPIO6 are configurable as a manual reset input, a margin disable input, a watchdog timer input and output, logic inputs/outputs, fault- Table 4. General-Purpose IO Configuration Registers REGISTER/ EEPROM ADDRESS BIT RANGE 1Ch 1Dh DESCRIPTION [2:0] GPIO1 Configuration Register [5:3] GPIO2 Configuration Register [7:6] GPIO3 Configuration Register (LSB) [0] GPIO3 Configuration Register (MSB) [3:1] GPIO4 Configuration Register [6:4] GPIO5 Configuration Register [7] 1Eh GPIO6 Configuration Register (LSB) [1:0] GPIO6 Configuration Register (MSB) [7:2] Reserved Table 5. GPIO Mode Selection CONFIGURATION BITS GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 000 INS1 INS2 INS3 INS4 — MARGIN input 001 Push-pull logic input/output Push-pull logic input/output Push-pull logic input/ output Push-pull logic input/output Push-pull logic input/output Push-pull logic input/output 010 Open-drain logic input/output Open-drain logic input/output Open-drain logic input/ output Open-drain logic input/output Open-drain logic input/ output Open-drain logic input/ output 011 Push-pull Push-pull Push-pull Push-pull Any_Fault output Any_Fault output Any_Fault output Any_Fault output Push-pull FAULT1 output Push-pull FAULT2 output 100 Open-drain Open-drain Open-drain Open-drain Any_Fault output Any_Fault output Any_Fault output Any_Fault output Open-drain FAULT1 output Open-drain FAULT2 output 101 Logic input Logic input Logic input Logic input Logic input Logic input 110 — — — — — Open-drain WDO output 111 — — — MR input WDI input Open-drain FAULTPU output Note: The dash “—” represents a reserved GPIO configuration. Do not set any GPIO to these values. 20 GPIO6 ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers INS_ connections also act as 100Ω pulldowns for closed-loop tracking channels or for other power supplies, if INS_ are connected to the outputs of the supplies. Set the appropriate bits in r4Eh[7:4] to enable pulldown functionality. See Table 12. General-Purpose Logic Inputs/Outputs Configure GPIO1–GPIO6 to be used as general-purpose inputs/outputs. Write values to GPIOs through r1Ah when operating as outputs, and read values from r1Bh when operating as inputs. Register r1Bh is readonly. See Table 6 for more information on reading and writing to the GPIOs as logic inputs/outputs. Both registers r1Ah and r1Bh are located in the extended page and are therefore not loaded from EEPROM on boot-up. Table 6. GPIO Data-In/Data-Out Data EXTENDED PAGE ADDRESS BIT RANGE DESCRIPTION [0] GPIO Logic Output Data 0 = GPIO1 is a logic-low output 1 = GPIO1 is a logic-high output [1] 0 = GPIO2 is a logic-low output 1 = GPIO2 is a logic-high output [2] 0 = GPIO3 is a logic-low output 1 = GPIO3 is a logic-high output [3] 0 = GPIO4 is a logic-low output 1 = GPIO4 is a logic-high output [4] 0 = GPIO5 is a logic-low output 1 = GPIO5 is a logic-high output [5] 0 = GPIO6 is a logic-low output 1 = GPIO6 is a logic-high output 1Ah [7:6] 1Bh Not used [0] GPIO Logic Input Data GPIO1 logic-input state [1] GPIO2 logic-input state [2] GPIO3 logic-input state [3] GPIO4 logic-input state [4] GPIO5 logic-input state [5] GPIO6 logic-input state [7:6] Not used ______________________________________________________________________________________ 21 MAX16047/MAX16049 Voltage Tracking Sense (INS_) Inputs GPIO1–GPIO4 are configurable as feedback sense return inputs (INS_) for closed-loop tracking. Connect the gate of an external n-channel MOSFET to each EN_OUT_ configured for closed-loop tracking. Connect INS_ inputs to the source of the MOSFETs for tracking feedback. Internal comparators monitor INS_ with respect to a control tracking ramp voltage for power-up/powerdown and control each EN_OUT_ voltage. Under normal conditions each INS_ voltage tracks the ramp voltage until the power-good voltage threshold has been reached. The slew rate for the ramp voltage and the INS_ to MON_ power-good threshold are programmable. See the Closed-Loop Tracking section. MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Any_Fault Outputs GPIO1–GPIO4 are configurable as active-low push-pull or open-drain fault-dependent outputs. These outputs assert when any monitored input exceeds an overvoltage, undervoltage, or early warning threshold. FAULT1 and FAULT2 GPIO5 and GPIO6 are configurable as dedicated fault outputs, FAULT1 and FAULT2, respectively. Fault outputs can assert on one or more overvoltage, undervoltage, or early warning conditions for selected inputs. FAULT1 and FAULT2 dependencies are set using registers r15h to r18h. See Table 7. If a fault output depends on more than one MON_, the fault output will assert if one or more MON_ exceeds a programmed threshold voltage. Table 7. FAULT1 and FAULT2 Output Configuration and Dependencies REGISTER/ EEPROM ADDRESS 15h BIT RANGE [0] 1 = FAULT1 is a digital output dependent on MON1 [1] 1 = FAULT1 is a digital output dependent on MON2 [2] 1 = FAULT1 is a digital output dependent on MON3 [3] 1 = FAULT1 is a digital output dependent on MON4 [4] 1 = FAULT1 is a digital output dependent on MON5 [5] 1 = FAULT1 is a digital output dependent on MON6 [6] 1 = FAULT1 is a digital output dependent on MON7 [7] 1 = FAULT1 is a digital output dependent on MON8 [0] 1 = FAULT1 is a digital output dependent on MON9* [1] 1 = FAULT1 is a digital output dependent on MON10* [2] 1 = FAULT1 is a digital output dependent on MON11* [3] 1 = FAULT1 is a digital output dependent on MON12* [4] 1 = FAULT1 is a digital output that depends on the overvoltage thresholds at the input selected by r15h and r16h[3:0] [5] 1 = FAULT1 is a digital output that depends on the undervoltage thresholds at the input selected by r15h and r16h[3:0] [6] 1 = FAULT1 is a digital output that depends on the early warning thresholds at the input selected by r15h and r16h[3:0] [7] 0 = FAULT1 is an active-low digital output 1 = FAULT1 is an active-high digital output [0] 1 = FAULT2 is a digital output dependent on MON1 [1] 1 = FAULT2 is a digital output dependent on MON2 [2] 1 = FAULT2 is a digital output dependent on MON3 [3] 1 = FAULT2 is a digital output dependent on MON4 [4] 1 = FAULT2 is a digital output dependent on MON5 [5] 1 = FAULT2 is a digital output dependent on MON6 [6] 1 = FAULT2 is a digital output dependent on MON7 [7] 1 = FAULT2 is a digital output dependent on MON8 16h 17h 22 DESCRIPTION ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers REGISTER/ EEPROM ADDRESS BIT RANGE DESCRIPTION [0] 1 = FAULT2 is a digital output dependent on MON9* [1] 1 = FAULT2 is a digital output dependent on MON10* [2] 1 = FAULT2 is a digital output dependent on MON11* [3] 1 = FAULT2 is a digital output dependent on MON12* [4] 1 = FAULT2 is a digital output that depends on the overvoltage thresholds at the input selected by r17h and r18h[3:0] [5] 1 = FAULT2 is a digital output that depends on the undervoltage thresholds at the input selected by r17h and 18h[3:0] [6] 1 = FAULT2 is a digital output that depends on the early warning thresholds at the input selected by r17h and r18h[3:0] [7] 0 = FAULT2 is an active-low digital output 1 = FAULT2 is an active-high digital output 18h *MAX16047 only Fault-On Power-Up (FAULTPU) GPIO6 indicates a fault during power-up or powerdown when configured as a “fault-on power-up” output. Under these conditions, all EN_OUT_ voltages are pulled low and fault data is saved to nonvolatile EEPROM. See the Faults section. Watchdog Input (WDI) and Output (WDO) Set r1Eh[1:0] and r1Dh[7] to ‘110’ to configure GPIO6 as WDO. Set r1Dh[6:4] to ‘111’ to configure GPIO5 as WDI. WDO is an open-drain active-low output. See the Watchdog Timer section for more information about the operation of the watchdog timer. MARGIN GPIO6 is configurable as an active-low MARGIN input. Drive MARGIN low before varying system voltages above or below the thresholds to avoid signaling an error. Drive MARGIN high for normal operation. When MARGIN is pulled low or r4Dh[1] is a ‘1,’ the margin function is enabled. FAULT1, FAULT2, Any_Fault, and RESET are latched in their current state. Threshold violations will be ignored, and faults will not be logged. Programmable Outputs (EN_OUT1–EN_OUT12) Manual Reset (MR) GPIO4 is configurable to act as an active-low manual reset input, MR. Drive MR low to assert RESET. RESET remains low for the selected reset timeout period after MR transitions from low to high. See the RESET section for more information on selecting a reset timeout period. The MAX16047 includes twelve programmable outputs, and the MAX16049 includes eight programmable outputs. These outputs are capable of connecting to either the enable (EN) inputs of a DC-DC or LDO power supply or to the gates of series-pass MOSFETs for closed-loop tracking mode, or for charge-pump mode. Selectable output configurations include: active-low or active-high, open-drain or push-pull. EN_OUT1–EN_OUT4 are also configurable for closed-loop tracking, and EN_OUT1– EN_OUT6 can act as charge-pump outputs with no closed-loop tracking. Use the registers r1Fh to r22h to configure outputs. See Table 8 for detailed information on configuring EN_OUT1–EN_OUT12. ______________________________________________________________________________________ 23 MAX16047/MAX16049 Table 7. FAULT1 and FAULT2 Output Configuration and Dependencies (continued) MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Table 8. EN_OUT1–EN_OUT12 Configuration REGISTER/ EEPROM ADDRESS 1Fh 24 BIT RANGE DESCRIPTION [2:0] EN_OUT1 Configuration: 000 = EN_OUT1 is an open-drain active-low output 001 = EN_OUT1 is an open-drain active-high output 010 = EN_OUT1 is a push-pull active-low output 011 = EN_OUT1 is a push-pull active-high output 100 = EN_OUT1 is used in closed-loop tracking 101 = EN_OUT1 is configured with a charge-pump output (MON1 + 5V) capable of driving an external n-channel MOSFET 110 = Reserved 111 = Reserved [5:3] EN_OUT2 Configuration: 000 = EN_OUT2 is an open-drain active-low output 001 = EN_OUT2 is an open-drain active-high output 010 = EN_OUT2 is a push-pull active-low output 011 = EN_OUT2 is a push-pull active-high output 100 = EN_OUT2 is used in closed-loop tracking 101 = EN_OUT2 is configured with a charge-pump output (MON2 + 5V) capable of driving an external n-channel MOSFET 110 = Reserved 111 = Reserved [7:6] EN_OUT3 Configuration (LSBs): 000 = EN_OUT3 is an open-drain active-low output 001 = EN_OUT3 is an open-drain active-high output 010 = EN_OUT3 is a push-pull active-low output 011 = EN_OUT3 is a push-pull active-high output 100 = EN_OUT3 is used in closed-loop tracking 101 = EN_OUT3 is configured with a charge-pump output (MON3 + 5V) capable of driving an external n-channel MOSFET 110 = Reserved 111 = Reserved ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers REGISTER/ EEPROM ADDRESS BIT RANGE [0] [3:1] 20h [6:4] [7] [1:0] 21h [3:2] DESCRIPTION EN_OUT3 Configuration (MSB)—see r1Fh[7:6] EN_OUT4 Configuration: 000 = EN_OUT4 is an open-drain active-low output 001 = EN_OUT4 is an open-drain active-high output 010 = EN_OUT4 is a push-pull active-low output 011 = EN_OUT4 is a push-pull active-high output 100 = EN_OUT4 is used in closed-loop tracking 101 = EN_OUT4 is configured with a charge-pump output (MON4 + 5V) capable of driving an external n-channel MOSFET 110 = Reserved 111 = Reserved EN_OUT5 Configuration: 000 = EN_OUT5 is an open-drain active-low output 001 = EN_OUT5 is an open-drain active-high output 010 = EN_OUT5 is a push-pull active low output 011 = EN_OUT5 is a push-pull active-high output 100 = Reserved. EN_OUT5 is not usable for closed-loop tracking. 101 = EN_OUT5 is configured with a charge-pump output (MON5 + 5V) capable of driving an external n-channel MOSFET 110 = Reserved 111 = Reserved EN_OUT6 Configuration (LSB)—see r21h[1:0] EN_OUT6 Configuration (MSBs): 000 = EN_OUT6 is an open-drain active-low output 001 = EN_OUT6 is an open-drain active-high output 010 = EN_OUT6 is a push-pull active-low output 011 = EN_OUT6 is a push-pull active-high output 100 = Reserved. EN_OUT6 is not useable for closed-loop tracking. 101 = EN_OUT6 is configured with a charge-pump output (MON6 + 5V) capable of driving an external n-channel MOSFET 110 = Reserved 111 = Reserved EN_OUT7 Configuration: 00 = EN_OUT7 is an open-drain active-low output 01 = EN_OUT7 is an open-drain active-high output 10 = EN_OUT7 is a push-pull active-low output 11 = EN_OUT7 is a push-pull active-high output [5:4] EN_OUT8 Configuration: 00 = EN_OUT8 is an open-drain active-low output 01 = EN_OUT8 is an open-drain active-high output 10 = EN_OUT8 is a push-pull active-low output 11 = EN_OUT8 is a push-pull active-high output [7:6] EN_OUT9 Configuration*: 00 = EN_OUT9 is an open-drain active-low output 01 = EN_OUT9 is an open-drain active-high output 10 = EN_OUT9 is a push-pull active-low output 11 = EN_OUT9 is a push-pull active-high output ______________________________________________________________________________________ 25 MAX16047/MAX16049 Table 8. EN_OUT1–EN_OUT12 Configuration (continued) MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Table 8. EN_OUT1–EN_OUT12 Configuration (continued) REGISTER/ EEPROM ADDRESS BIT RANGE DESCRIPTION [1:0] EN_OUT10 Configuration*: 00 = EN_OUT10 is an open-drain active-low output 01 = EN_OUT10 is an open-drain active-high output 10 = EN_OUT10 is a push-pull active-low output 11 = EN_OUT10 is a push-pull active-high output [3:2] EN_OUT11 Configuration*: 00 = EN_OUT11 is an open-drain active-low output 01 = EN_OUT11 is an open-drain active-high output 10 = EN_OUT11 is a push-pull active-low output 11 = EN_OUT11 is a push-pull active-high output [5:4] EN_OUT12 Configuration*: 00 = EN_OUT12 is an open-drain active-low output 01 = EN_OUT12 is an open-drain active high output 10 = EN_OUT12 is a push-pull active-low output 11 = EN_OUT12 is a push-pull active-high output [7:6] Reserved 22h *MAX16047 only Charge-Pump Configuration EN_OUT1–EN_OUT6 can act as high-voltage chargepump outputs to drive up to six external n-channel MOSFETs. During sequencing, an EN_OUT_ output configured this way drives 6µA until the voltage reaches 5V above the corresponding MON_ to fully enhance the external n-channel MOSFET. For example, EN_OUT2 will rise to 5V above MON2. See the Sequencing section for more detailed information on power-supply sequencing. Closed-Loop Tracking Operation EN_OUT1–EN_OUT4 can operate in closed-loop tracking mode. When configured for closed-loop tracking, EN_OUT1–EN_OUT4 are capable of driving the gates of up to four external n-channel MOSFETs. For closedloop tracking, configure GPIO1–GPIO4 as return-sense line inputs (INS_) to be used in conjunction with EN_OUT1–EN_OUT4 and MON1–MON4. See the Closed-Loop Tracking section. 26 Open-Drain Output Configuration Connect an external pullup resistor from the output to an external voltage up to 6V (abs max, EN_OUT7– EN_OUT12) or 12V (abs max, EN_OUT1–EN_OUT6) when configured as an open-drain output. Choose the pullup resistor depending on the number of devices connected to the open-drain output and the allowable current consumption. The open-drain output configuration allows wire-ORed connection. Push-Pull Output Configuration The MAX16047/MAX16049s’ programmable outputs sink 2mA and source 100µA when configured as pushpull outputs. EN_OUT_ State During Power-Up When VCC is ramped from 0V to the operating supply voltage, the EN_OUT_ output is high impedance until VCC is approximately 2.4V and then EN_OUT_ will be in its configured deasserted state. See Figures 3 and 4. RESET is configured as an active-low open-drain output pulled up to V CC through a 10kΩ resistor for Figures 3 and 4. ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers MAX16047 fig04 VCC 2V/div UVLO VCC 2V/div 0V 0V RESET 2V/div 0V RESET 2V/div 0V ASSERTED LOW EN_OUT_ 2V/div 0V 20ms/div HIGH-Z EN_OUT_ 2V/div 0V 10ms/div Figure 3. RESET and EN_OUT_ During Power-Up, EN_OUT_ Is in Open-Drain Active-Low Configuration Sequencing Each EN_OUT_ has one or more associated MON_ inputs, facilitating the voltage monitoring of multiple power supplies. To sequence a system of power supplies safely, the output voltage of a power supply must be good before the next power supply may turn on. Connect EN_OUT_ outputs to the enable input of an external power supply and connect MON_ inputs to the output of the power supply for voltage monitoring. More than one MON_ may be used if the power supply has multiple outputs. Sequence Order The MAX16047/MAX16049 utilize a system of ordered slots to sequence multiple power supplies. To determine the sequence order, assign each EN_OUT_ to a slot ranging from Slot 0 to Slot 11. EN_OUT_(s) assigned to Slot 0 are turned on first, followed by outputs assigned to Slot 1, and so on through Slot 11. Multiple EN_OUT_s assigned to the same slot turn on at the same time. Each slot has a built-in configurable sequence delay (registers r50h to r54h) ranging from 20µs to 1.6s. During a reverse sequence, slots are turned off in reverse order starting from Slot 11. The MAX16047/MAX16049 may be configured to power-down in simultaneous mode or in reverse sequence mode as set in r54h[4]. See Tables 9, 10, and 11 for the EN_OUT_ slot assignment bits, and Tables 12 and 13 for the sequence delays. Monitoring Inputs While Sequencing An enabled MON_ input may be assigned to a slot ranging from Slot 1 to Slot 12. Monitoring inputs are always checked at the beginning of a slot. The inputs are given the power-up fault delay within which they Figure 4. RESET and EN_OUT_ During Power-Up, EN_OUT_ Is in Push-Pull Active-High Configuration must satisfy the programmed undervoltage limit; otherwise a fault condition will occur. This undervoltage limit cannot be disabled during power-up and power-down. EN_OUT_s configured for open-drain, push-pull, or charge-pump operation are always asserted at the end of a slot, following the sequence delay. See Tables 9, 10, and 11 for the MON_ slot assignment bits. Slot 0 does not monitor any MON_ input. Instead, Slot 0 waits for the Software Enable bit r4Dh[0] to be a logic ‘0’ and for the voltage on EN to rise above 0.525V before asserting any assigned outputs. Outputs assigned to Slot 0 are asserted before the Slot 0 sequence delay. Generally, Slot 0 controls the enable inputs of power supplies that are first in the sequence. Similarly, Slot 12 does not control any EN_OUT_ outputs. Rather, Slot 12 monitors assigned MON_ inputs and then enters the power-on state. Generally, Slot 12 monitors the last power supplies in the sequence. The power-up sequence is complete when any MON_ inputs assigned to Slot 12 exceed their undervoltage thresholds and the sequence delay is expired. If no MON_ inputs are assigned to Slot 12, the power-up sequence is complete after the slot sequence delay is expired. The output rail(s) of a power supply should be monitored by one or more MON_ inputs placed in the succeeding slot, ensuring that the output of the supply is not checked until it has first been turned on. For example, if a power supply uses EN_OUT1 located in Slot 3 and has two monitoring inputs, MON1 and MON2, they must both be assigned to Slot 4. In this example, EN_OUT1 turns on at the end of Slot 3. At the start of Slot 4, MON1 and MON2 must exceed the undervoltage threshold before the programmed power-up fault delay; otherwise a fault triggers. ______________________________________________________________________________________ 27 MAX16047/MAX16049 MAX16047 fig03 MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers RESET Deassertion After any MON_ inputs assigned to Slot 12 exceed their undervoltage thresholds, the reset timeout begins. When the reset timeout completes, RESET deasserts. The reset timeout period is set in r19h[6:4]. See Table 21. Power-Down Power-down starts when EN is pulled low or the Software Enable bit is set to ‘1.’ Power down EN_OUT_s simultaneously or in reverse sequence mode by setting the Reverse Sequence bit (r54h[4]) appropriately. In reverse sequence mode (r54h[4] set to ‘1’), the EN_OUT_s assigned to Slot 11 deassert, the MAX16047/MAX16049 wait for the Slot 11 sequence delay and then proceed to Slot 10, and so on until the EN_OUT_s assigned to Slot 0 turn off. When simultaneous power-down is selected (r54h[4] set to ‘0’), all EN_OUT_s turn off at the same time. Table 9. MON_ and EN_OUT_ Slot Assignment Registers REGISTER/ EEPROM ADDRESS 56h 57h 58h 59h 5Ah 5Bh 5Eh 5Fh 60h 61h 62h 63h BIT RANGE [3:0] DESCRIPTION MON1 Slot Assignment Register [7:4] MON2 Slot Assignment Register [3:0] MON3 Slot Assignment Register [7:4] MON4 Slot Assignment Register [3:0] MON5 Slot Assignment Register [7:4] MON6 Slot Assignment Register [3:0] MON7 Slot Assignment Register [7:4] MON8 Slot Assignment Register [3:0] MON9 Slot Assignment Register* [7:4] MON10 Slot Assignment Register* [3:0] MON11 Slot Assignment Register* [7:4] MON12 Slot Assignment Register* [3:0] EN_OUT1 Slot Assignment Register [7:4] EN_OUT2 Slot Assignment Register [3:0] EN_OUT3 Slot Assignment Register [7:4] EN_OUT4 Slot Assignment Register [3:0] EN_OUT5 Slot Assignment Register [7:4] EN_OUT6 Slot Assignment Register [3:0] EN_OUT7 Slot Assignment Register [7:4] EN_OUT8 Slot Assignment Register [3:0] EN_OUT9 Slot Assignment Register* [7:4] EN_OUT10 Slot Assignment Register* [3:0] EN_OUT11 Slot Assignment Register* [7:4] EN_OUT12 Slot Assignment Register * *MAX16047 only 28 ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers MAX16047/MAX16049 Table 10. MON_ Slot Assignment CONFIGURATION BITS DESCRIPTION 0000 MON_ is not assigned to a slot 0001 MON_ is assigned to Slot 1 0010 MON_ is assigned to Slot 2 0011 MON_ is assigned to Slot 3 0100 MON_ is assigned to Slot 4 0101 MON_ is assigned to Slot 5 0110 MON_ is assigned to Slot 6 0111 MON_ is assigned to Slot 7 1000 MON_ is assigned to Slot 8 1001 MON_ is assigned to Slot 9 1010 MON_ is assigned to Slot 10 1011 MON_ is assigned to Slot 11 1100 MON_ is assigned to Slot 12 1101 Not used 1110 Not used 1111 Not used Table 11. EN_OUT_ Slot Assignment CONFIGURATION BITS DESCRIPTION 0000 EN_OUT_ is not assigned to a slot 0001 EN_OUT_ is assigned to Slot 0 0010 EN_OUT_ is assigned to Slot 1 0011 EN_OUT_ is assigned to Slot 2 0100 EN_OUT_ is assigned to Slot 3 0101 EN_OUT_ is assigned to Slot 4 0110 EN_OUT_ is assigned to Slot 5 0111 EN_OUT_ is assigned to Slot 6 1000 EN_OUT_ is assigned to Slot 7 1001 EN_OUT_ is assigned to Slot 8 1010 EN_OUT_ is assigned to Slot 9 1011 EN_OUT_ is assigned to Slot 10 1100 EN_OUT_ is assigned to Slot 11 1101 Not used 1110 Not used 1111 Not used ______________________________________________________________________________________ 29 MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Table 12. Sequence Delays and Fault Recovery REGISTER/ EEPROM ADDRESS BIT RANGE [1:0] [3:2] 4Eh INS1 Pulldown Resistor Enable 0 = Pulldown resistor for INS1 is disabled 1 = Pulldown resistor for INS1 is enabled [5] INS2 Pulldown Resistor Enable 0 = Pulldown resistor for INS2 is disabled 1 = Pulldown resistor for INS2 is enabled [6] INS3 Pulldown Resistor Enable 0 = Pulldown resistor for INS3 is disabled 1 = Pulldown resistor for INS3 is enabled [7] INS4 Pulldown Resistor Enable 0 = Pulldown resistor for INS4 is disabled 1 = Pulldown resistor for INS4 is enabled [3] [5:4] [7:6] 30 Power-Up Fault Timeout 00 = 25ms 01 = 50ms 10 = 100ms 11 = 200ms Power-Down Fault Timeout 00 = 25ms 01 = 50ms 10 = 100ms 11 = 200ms [4] [2:0] 4Fh DESCRIPTION Autoretry Timeout 000 = 20µs 001 = 12.5ms 010 = 25ms 011 = 50ms 100 = 100ms 101 = 200ms 110 = 400ms 111 = 1.6s Fault Recovery Mode 0 = Autoretry procedure is performed following a fault event 1 = Latch-off on fault Slew Rate 00 = 800V/s 01 = 400V/s 10 = 200V/s 11 = 100V/s Fault Deglitch 00 = 2 conversions 01 = 4 conversions 10 = 8 conversions 11 = 16 conversions ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers MAX16047/MAX16049 Table 12. Sequence Delays and Fault Recovery (continued) REGISTER/ EEPROM ADDRESS 50h BIT RANGE [2:0] Slot 0 Sequence Delay [5:3] Slot 1 Sequence Delay [7:6] [0] 51h [3:1] [6:4] [7] 52h 53h Slot 2 Sequence Delay (LSBs) Slot 2 Sequence Delay (MSB)—see r50h[7:6] Slot 3 Sequence Delay Slot 4 Sequence Delay Slot 5 Sequence Delay (LSB)—see r52h[1:0] [1:0] Slot 5 Sequence Delay [4:2] Slot 6 Sequence Delay [7:5] Slot 7 Sequence Delay [2:0] Slot 8 Sequence Delay [5:3] Slot 9 Sequence Delay [7:6] Slot 10 Sequence Delay (LSBs) [0] [3:1] 54h DESCRIPTION [4] [7:5] Slot 10 Sequence Delay (MSB)—see r53h[7:6] Slot 11 Sequence Delay Reverse Sequence 0 = Power down all EN_OUT_s at the same time (simultaneously) 1 = Controlled power-down will be reverse of power-up sequence Not used Table 13. Slot Sequence Delay Selection CONFIGURATION BITS SLOT SEQUENCE DELAY 000 20µs 001 12.5ms 010 25ms 011 50ms 100 100ms 101 200ms 110 400ms 111 1.6s ______________________________________________________________________________________ 31 MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Closed-Loop Tracking The MAX16047/MAX16049 track up to four voltages during any time slot except Slot 0 and Slot 12. Configure GPIO1–GPIO4 as sense line inputs (INS_) to monitor tracking voltages. Configure GPIO6 as FAULTPU to indicate tracking faults, if desired. See the General-Purpose Inputs/Outputs section for information on configuring GPIOs. For closed-loop tracking, use MON1, EN_OUT1, and INS1 together to form a complete channel. Use MON2, EN_OUT2, and INS2 to form a second complete channel. Use MON3, EN_OUT3, and INS3 together to form a third channel; and use MON4, EN_OUT4, and INS4 to form a fourth channel. VIN VOUT MON_ ADC MUX EN_OUT_ INS_ GATE DRIVE LOGIC VTH_PG REFERENCE RAMP When configured for closed-loop tracking, assign each EN_OUT_ to the same slot as its associated single monitoring input (MON_). For example, if EN_OUT2 is assigned to Slot 3, the monitoring input is MON2 and must be assigned to Slot 3. This is because the MON_ input, checked at the start of the slot, must be valid before tracking can begin. Tracking begins immediately and must finish before the power-up fault timeout expires, or a fault will trigger. EN_OUT_ configured for closed-loop tracking cannot be assigned to Slot 0. The tracking control circuitry includes a ramp generator and a comparator control block for each tracked voltage (see the Functional Diagram and Figure 5). The comparator control block compares each INS_ voltage with a control voltage ramp. If INS_ voltages vary from the control ramp by more than 150mV (typ), the comparator control block signals an alert that dynamically stops the ramp until the slow INS_ voltage rises to within the allowed voltage window. The total tracking time is extended under these conditions, but must still complete within the selected power-up/power-down fault timeout. The power-up/power-down tracking fault timeout period is adjustable through r4Eh[3:0]. A voltage difference between any two tracking INS_ voltages exceeding 330mV generates a tracking fault, forcing all EN_OUT_ voltages low and generating a fault log. If configured as FAULTPU, GPIO6 asserts when a tracking fault occurs. The comparator control blocks also monitor INS_ voltages with respect to input (MON_) voltages. Under normal conditions each INS_ tracks the control ramp until the INS_ voltages reach the configured power-good 32 100Ω Figure 5. Closed-Loop Tracking (PG) thresholds, set as a programmable percentage of the MON_ voltage. Use register r64h to set the PG thresholds (Table 14). Once PG is detected, the external n-channel FET saturates with 5V (typ) applied between gate and source. The slew rate for the control ramp is programmable from 100V/s to 800V/s in r4Fh[5:4] (see Table 12). Power-down initiates when EN is forced low or when the Software Enable bit in r4Dh[0] is set to ‘1.’ If the Reverse Sequence bit is set (r54h[4]) INS_ voltages follow a falling reference ramp to ground as long as MON_ voltages remain high enough to supply the required voltage/current. If a monitored voltage drops faster than the control ramp voltage or the corresponding MON_ voltage falls too quickly, power-down tracking operation is terminated and all EN_OUT_ voltages are immediately forced to ground. If the Reverse Sequence bit is set to ‘0,’ all EN_OUT_ voltages are forced low simultaneously. ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers down resistors may also be used with EN_OUT1– EN_OUT4 channels not configured for closed-loop tracking, which is useful to discharge the output capacitors of a DC-DC converter during shutdown. For this case, configure the GPIO as an INS_ input and set the 100Ω pulldown bit, but do not enable closed-loop tracking. Connect the INS_ input to the output of the power supply. Table 14. Power-Good (PG) Thresholds REGISTER/ EEPROM ADDRESS BIT RANGE DESCRIPTION [1:0] 00 = PG is asserted when monitored VMON1 is 95% of VINS1 01 = PG is asserted when monitored VMON1 is 92.5% of VINS1 10 = PG is asserted when monitored VMON1 is 90% of VINS1 11 = PG is asserted when monitored VMON1 is 87.5% of VINS1 [3:2] 00 = PG is asserted when monitored VMON2 is 95% of VINS2 01 = PG is asserted when monitored VMON2 is 92.5% of VINS2 10 = PG is asserted when monitored VMON2 is 90% of VINS2 11 = PG is asserted when monitored VMON2 is 87.5% of VINS2 [5:4] 00 = PG is asserted when monitored VMON3 is 95% of VINS3 01 = PG is asserted when monitored VMON3 is 92.5% of VINS3 10 = PG is asserted when monitored VMON3 is 90% of VINS3 11 = PG is asserted when monitored VMON3 is 87.5% of VINS3 [7:6] 00 = PG is asserted when monitored VMON4 is 95% of VINS4 01 = PG is asserted when monitored VMON4 is 92.5% of VINS4 10 = PG is asserted when monitored VMON4 is 90% of VINS4 11 = PG is asserted when monitored VMON4 is 87.5% of VINS4 64h ______________________________________________________________________________________ 33 MAX16047/MAX16049 The MAX16047/MAX16049 include selectable internal 100Ω pulldown resistors to ensure that tracked voltages are not held high by large external capacitors during a fault event. The pulldowns help to ensure that monitored INS_ voltages are fully discharged before the next power-up cycle is initiated. These pulldowns are high impedance during normal operation. Set r4Eh[7:4] to ‘1’ to enable the pulldown resistors (Table 12). These pull- MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Faults The MAX16047/MAX16049 monitor the input (MON_) channels and compare the results with an overvoltage threshold, an undervoltage threshold, and a selectable overvoltage or undervoltage early warning threshold. Based on these conditions, the MAX16047/MAX16049 can assert various fault outputs and save specific information about the channel conditions and voltages into the nonvolatile EEPROM. Once a critical fault event occurs, the failing channel condition, ADC conversions at the time of the fault, or both may be saved by configuring the event logger. The event logger records a single failure in the internal EEPROM and sets a lock bit which protects the stored fault data from accidental erasure on a subsequent power-up. The MAX16047/MAX16049 are capable of measuring overvoltage and undervoltage fault events. Fault condi- tions are detected at the end of each ADC conversion. An overvoltage event occurs when the voltage at a monitored input exceeds the overvoltage threshold for that input. An undervoltage fault occurs when the voltage at a monitored input falls below the undervoltage threshold. Fault thresholds are set in registers r23h to r46h as shown in Table 15. Disabled inputs are not monitored for fault conditions and are skipped over by the input multiplexer. Only the upper 8 bits of a conversion result are compared with the programmed fault thresholds. The general-purpose inputs/outputs (GPIO1–GPIO6) can be configured as Any_Fault outputs or dedicated FAULT1 and FAULT2 outputs to indicate fault conditions. These fault outputs are not masked by the critical fault enable bits shown in Table 17. See the GeneralPurpose Inputs/Outputs section for more information on configuring GPIOs as fault outputs. Table 15. Fault Thresholds REGISTER/ EEPROM ADDRESS DESCRIPTION REGISTER/ EEPROM ADDRESS DESCRIPTION MON1 Early Warning Threshold 35h MON7 Early Warning Threshold 24h MON1 Overvoltage Threshold 36h MON7 Overvoltage Threshold 25h MON1 Undervoltage Threshold 37h MON7 Undervoltage Threshold 26h MON2 Early Warning Threshold 38h MON8 Early Warning Threshold 27h MON2 Overvoltage Threshold 39h MON8 Overvoltage Threshold 28h MON2 Undervoltage Threshold 3Ah MON8 Undervoltage Threshold 29h MON3 Early Warning Threshold 3Bh MON9 Early Warning Threshold* 2Ah MON3 Overvoltage Threshold 3Ch MON9 Overvoltage Threshold* 2Bh MON3 Undervoltage Threshold 3Dh MON9 Undervoltage Threshold* 2Ch MON4 Early Warning Threshold 3Eh MON10 Early Warning Threshold* 2Dh MON4 Overvoltage Threshold 3Fh MON10 Overvoltage Threshold* 2Eh MON4 Undervoltage Threshold 40h MON10 Undervoltage Threshold* 2Fh MON5 Early Warning Threshold 41h MON11 Early Warning Threshold* 30h MON5 Overvoltage Threshold 42h MON11 Overvoltage Threshold* 31h MON5 Undervoltage Threshold 43h MON11 Undervoltage Threshold* 32h MON6 Early Warning Threshold 44h MON12 Early Warning Threshold* 33h MON6 Overvoltage Threshold 45h MON12 Overvoltage Threshold* 34h MON6 Undervoltage Threshold 46h MON12 Undervoltage Threshold* 23h *MAX16047 only 34 ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Fault Flags Fault flags indicate the fault status of a particular input. The fault flag of any monitored input in the device can be read at any time from registers r18h and r19h in the extended page, as shown in Table 16. Clear a fault flag by writing a ‘1’ to the appropriate bit in the flag register. Unlike the fault signals sent to the fault outputs, these bits are masked by the critical fault enable bits (see Table 17). The fault flag will only be set if the matching enable bit in the critical fault enable register is also set. Critical Faults If a specific input threshold is critical to the operation of the system, an automatic fault log can be configured to shut down all the EN_OUT_s and trigger a transfer of fault information to EEPROM. For a fault condition to trigger a critical fault, set the appropriate enable bit in registers r48h to r4Ch (see Table 17). Logged fault information is stored in EEPROM registers r00h to r0Eh (see Table 18). Once a fault log event occurs, the EEPROM is locked and must be unlocked to enable a new fault log to be stored. Write a ‘1’ to r5Dh[1] to unlock the EEPROM. Fault information can be configured to store ADC conversion results and/or fault flags in registers r01h and r02h. Select the critical fault configuration in r47h[1:0]. Set r47h[1:0] to ‘11’ to turn off the fault logger. All stored ADC results are 8 bits wide. Table 16. Fault Flags EXTENDED PAGE ADDRESS 18h 19h BIT RANGE DESCRIPTION [0] 1 = MON1 conversion exceeds overvoltage or undervoltage thresholds [1] 1 = MON2 conversion exceeds overvoltage or undervoltage thresholds [2] 1 = MON3 conversion exceeds overvoltage or undervoltage thresholds [3] 1 = MON4 conversion exceeds overvoltage or undervoltage thresholds [4] 1 = MON5 conversion exceeds overvoltage or undervoltage thresholds [5] 1 = MON6 conversion exceeds overvoltage or undervoltage thresholds [6] 1 = MON7 conversion exceeds overvoltage or undervoltage thresholds [7] 1 = MON8 conversion exceeds overvoltage or undervoltage thresholds [0] 1 = MON9 conversion exceeds overvoltage or undervoltage thresholds* [1] 1 = MON10 conversion exceeds overvoltage or undervoltage thresholds* [2] 1 = MON11 conversion exceeds overvoltage or undervoltage thresholds* [3] 1 = MON12 conversion exceeds overvoltage or undervoltage thresholds* [7:4] Not used *MAX16047 only ______________________________________________________________________________________ 35 MAX16047/MAX16049 Deglitch Fault conditions are detected at the end of each conversion. If the voltage on an input falls outside a monitored threshold for one acquisition, the input multiplexer remains on that channel and performs several successive conversions. To trigger a fault, the input must stay outside the threshold for a certain number of acquisitions as determined by the deglitch setting in r4Fh[7:6] (see Table 19). MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Table 17. Critical Fault Configuration and Enable Bits REGISTER/ EEPROM ADDRESS 47h 48h 49h 4Ah 4Bh 36 BIT RANGE DESCRIPTION [1:0] Critical Fault Log Control 00 = Failed lines and ADC conversion values save to EEPROM upon critical fault 01 = Failed line flags only saved to EEPROM upon critical fault 10 = ADC conversion values only saved to EEPROM upon critical fault 11 = No information saved upon critical fault [7:2] Not used [0] 1 = Fault log triggered when MON1 is below its undervoltage threshold [1] 1 = Fault log triggered when MON2 is below its undervoltage threshold [2] 1 = Fault log triggered when MON3 is below its undervoltage threshold [3] 1 = Fault log triggered when MON4 is below its undervoltage threshold [4] 1 = Fault log triggered when MON5 is below its undervoltage threshold [5] 1 = Fault log triggered when MON6 is below its undervoltage threshold [6] 1 = Fault log triggered when MON6 is below its undervoltage threshold [7] 1 = Fault log triggered when MON8 is below its undervoltage threshold [0] 1 = Fault log triggered when MON9 is below its undervoltage threshold* [1] 1 = Fault log triggered when MON10 is below its undervoltage threshold* [2] 1 = Fault log triggered when MON11 is below its undervoltage threshold* [3] 1 = Fault log triggered when MON12 is below its undervoltage threshold* [4] 1 = Fault log triggered when MON1 is above its overvoltage threshold [5] 1 = Fault log triggered when MON2 is above its overvoltage threshold [6] 1 = Fault log triggered when MON3 is above its overvoltage threshold [7] 1 = Fault log triggered when MON3 is above its overvoltage threshold [0] 1 = Fault log triggered when MON5 is above its overvoltage threshold [1] 1 = Fault log triggered when MON6 is above its overvoltage threshold [2] 1 = Fault log triggered when MON7 is above its overvoltage threshold [3] 1 = Fault log triggered when MON8 is above its overvoltage threshold [4] 1 = Fault log triggered when MON9 is above its overvoltage threshold* [5] 1 = Fault log triggered when MON10 is above its overvoltage threshold* [6] 1 = Fault log triggered when MON11 is above its overvoltage threshold* [7] 1 = Fault log triggered when MON12 is above its overvoltage threshold* [0] 1 = Fault log triggered when MON1 is above/below its early earning threshold [1] 1 = Fault log triggered when MON2 is above/below its early warning threshold [2] 1 = Fault log triggered when MON3 is above/below its early warning threshold [3] 1 = Fault log triggered when MON4 is above/below its early warning threshold [4] 1 = Fault log triggered when MON5 is above/below its early warning threshold [5] 1 = Fault log triggered when MON6 is above/below its early warning threshold [6] 1 = Fault log triggered when MON7 is above/below its early warning threshold [7] 1 = Fault log triggered when MON8 is above/below its early warning threshold ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers REGISTER/ EEPROM ADDRESS BIT RANGE 4Ch DESCRIPTION [0] 1 = Fault log triggered when MON9 is above/below its early warning threshold* [1] 1 = Fault log triggered when MON10 is above/below its early warning threshold* [2] 1 = Fault log triggered when MON11 is above/below its early warning threshold* [3] 1 = Fault log triggered when MON12 is above/below its early warning threshold* [7:4] MAX16047/MAX16049 Table 17. Critical Fault Configuration and Enable Bits (continued) Not used *MAX16047 only Table 18. Fault Log EEPROM EEPROM ADDRESS BIT RANGE [5] [6] Power-Up/Power-Down Fault Register Slot where power-up/power-down fault is detected Tracking Fault Bits If ‘0,’ tracking fault occurred on MON1/EN_OUT1/INS1 If ‘0,’ tracking fault occurred on MON2/EN_OUT2/INS2 If ‘0,’ tracking fault occurred on MON3/EN_OUT3/INS3 [7] [0] If ‘0,’ tracking fault occurred on MON4/EN_OUT4/INS4 If ‘1,’ fault occurred on MON1 [1] If ‘1,’ fault occurred on MON2 [2] [3] If ‘1,’ fault occurred on MON3 If ‘1,’ fault occurred on MON4 [4] If ‘1,’ fault occurred on MON5 [5] If ‘1,’ fault occurred on MON6 [6] [7] If ‘1,’ fault occurred on MON7 If ‘1,’ fault occurred on MON8 [0] If ‘1,’ fault occurred on MON9* [1] If ‘1,’ fault occurred on MON10* [2] [3] If ‘1,’ fault occurred on MON11* If ‘1,’ fault occurred on MON12* [3:0] 00h 01h 02h DESCRIPTION [4] [7:4] Not used 03h [7:0] MON_ ADC Fault Information (only the 8 MSBs of converted channels are saved following a fault event) MON1 conversion result at the time the fault log was triggered 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] MON2 conversion result at the time the fault log was triggered MON3 conversion result at the time the fault log was triggered MON4 conversion result at the time the fault log was triggered MON5 conversion result at the time the fault log was triggered MON6 conversion result at the time the fault log was triggered MON7 conversion result at the time the fault log was triggered MON8 conversion result at the time the fault log was triggered MON9 conversion result at the time the fault log was triggered* MON10 conversion result at the time the fault log was triggered* MON11 conversion result at the time the fault log was triggered* MON12 conversion result at the time the fault log was triggered* *MAX16047 only ______________________________________________________________________________________ 37 MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Power-Up/Power-Down Faults All EN_OUTs are deasserted if an overvoltage or undervoltage fault is detected during power-up/power-down. Under these conditions, information of the failing slot is stored in EEPROM r00h[3:0] unless the fault register is configured not to store any information by setting r47h[1:0] to ‘11’ (see Table 17). If there is a tracking fault on a channel configured for closed-loop tracking, a fault log operation occurs and the bits representing the failed tracking channels are set to ‘0’ unless the fault register is configured not to store any information by setting r47h[1:0] to ‘11’ (see Table 17). Autoretry/Latch Mode For critical faults, the MAX16047/MAX16049 can be configured for one of two fault management methods: autoretry or latch-on-fault. Set r4Fh[3] to ‘0’ to select autoretry mode. In this configuration, the device will shut down after a critical fault event then restart following a configurable delay. Use r4Fh[2:0] to select an autoretry delay from 20µs to 1.6s. See Table 19 for more information on setting the autoretry delay. Set r4Fh[3] to ‘1’ to select the latch-on-fault mode. In this configuration EN_OUT_s are deasserted after a critical fault event. The device does not re-initiate the power-up sequence until EN is toggled or the Software Enable bit is reset to ‘0.’ See the Enable section for more information on setting the Software Enable bit. If fault information is stored in EEPROM (see the Critical Faults section) and autoretry mode is selected, set an autoretry delay greater than the time required for the storing operation. If fault information is stored in EEPROM and latch-on-fault mode is chosen, toggle EN or reset the Software Enable bit only after the completion of the storing operation. If saving information about the failed lines only, ensure a delay of at least 60ms before the restart procedure. Otherwise, ensure a minimum 204ms timeout. This ensures that ADC conversions are completed and values are stored correctly in EEPROM. See Table 20 for more information about required fault log operation periods. Table 19. Fault Recovery Configuration REGISTER/ EEPROM ADDRESS BIT RANGE [2:0] [3] 4Fh 38 DESCRIPTION Autoretry Delay 000 = 20µs 001 = 12.5ms 010 = 25ms 011 = 50ms 100 = 100ms 101 = 200ms 110 = 400ms 111 = 1.6s Fault Recovery Mode 0 = Autoretry procedure is performed following a fault event 1 = Latchoff on fault [5:4] Slew Rate 00 = 800V/s 01 = 400V/s 10 = 200V/s 11 = 100V/s [7:6] Fault Deglitch 00 = 2 conversions 01 = 4 conversions 10 = 8 conversions 11 = 16 conversions ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers FAULT CONTROL REGISTER r47h[1:0] MINIMUM REQUIRED SHUTDOWN PERIOD (ms) DESCRIPTION 00 Failed lines and ADC values saved 204 01 Failed lines saved 60 10 ADC values saved 168 11 No information saved N/A RESET The reset output, RESET, is asserted during powerup/power-down and deasserts following the reset timeout period once the power-up sequence is complete. The power-up sequence is complete when any MON_ inputs assigned to Slot 12 exceed their undervoltage thresholds. If no MON_ inputs are assigned to Slot 12, the power-up sequence is complete after the slot sequence delay is expired. RESET is a configurable output that monitors selected MON_ voltages during normal operation. Use r19h[1:0] to configure RESET to assert on an overvoltage fault, undervoltage fault, or both. Use r19h[3:2] to configure RESET as an active-high/active-low push-pull/opendrain output. If desired, configure GPIO4 as a manual reset input, MR, and pull MR low to assert RESET. RESET includes a programmable timeout. See Table 21 for RESET dependencies and configuration registers. Table 21. RESET Configuration and Dependencies REGISTER/ EEPROM ADDRESS BIT RANGE [1:0] 19h DESCRIPTION RESET OUTPUT CONFIGURATION 00 = RESET is asserted if at least one of the selected inputs exceeds its undervoltage threshold 01 = RESET is asserted if at least one of the selected inputs exceeds its early warning threshold 10 = RESET is asserted if at least one of the selected inputs exceeds its overvoltage threshold 11 = RESET is asserted if any of the selected inputs exceeds undervoltage or overvoltage thresholds [2] 0 = RESET is an active-low output 1 = RESET is an active-high output [3] 0 = RESET is a open-drain output 1 = RESET is an push-pull output [6:4] [7] RESET TIMEOUT 000 = 25µs 001 = 2ms 010 = 25ms 011 = 100ms 100 = 200ms 101 = 400ms 110 = 800ms 111 = 1600ms Reserved ______________________________________________________________________________________ 39 MAX16047/MAX16049 Table 20. EEPROM Fault Log Operation Period MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Table 21 . RESET Configuration and Dependencies (continued) REGISTER/ EEPROM ADDRESS 1Ah 1Bh BIT RANGE DESCRIPTION [0] RESET DEPENDENCIES 1 = RESET is dependent on MON1 [1] 1 = RESET is dependent on MON2 [2] 1 = RESET is dependent on MON3 [3] 1 = RESET is dependent on MON4 [4] 1 = RESET is dependent on MON5 [5] 1 = RESET is dependent on MON6 [6] 1 = RESET is dependent on MON7 [7] 1 = RESET is dependent on MON8 [0] 1 = RESET is dependent on MON9* [1] 1 = RESET is dependent on MON10* [2] 1 = RESET is dependent on MON11* [3] 1 = RESET is dependent on MON12* [7:4] Reserved *MAX16047 only Watchdog Timer The watchdog timer can operate together with or independently of the MAX16047/MAX16049. When operating in dependent mode, the watchdog is not activated until the sequencing is complete and RESET is deasserted. When operating in independent mode, the watchdog timer is independent of the sequencing operation and activates immediately after VCC exceeds the UVLO threshold and the boot phase is complete. Set r4Dh[3] to ‘0’ to configure the watchdog in dependent mode. Set r4Dh[3] to ‘1’ to configure the watchdog in independent mode. See Table 22 for more information on configuring the watchdog timer in dependent or independent mode. Dependent Watchdog Timer Operation The watchdog timer can be used to monitor µP activity in two modes. Flexible timeout architecture provides an adjustable watchdog startup delay of up to 128s, allowing complicated systems to complete lengthy boot-up routines. An adjustable watchdog timeout allows the supervisor to provide quick alerts when processor activity fails. After each reset event (VCC drops below UVLO then returns above UVLO, software reboot, manual reset (MR), EN input going low then high, or watchdog reset) and once sequencing is complete, the watchdog startup delay provides an extended time for the system to power up and fully initialize all µP and system components before assuming responsibility for 40 routine watchdog updates. Set r55h[6] to ‘1’ to enable the watchdog startup delay. Set r55h[6] to ‘0’ to disable the watchdog startup delay. The normal watchdog timeout period, tWDI, begins after the first transition on WDI before the conclusion of the long startup watchdog period, tWDI_STARTUP (Figures 6 and 7). During the normal operating mode, WDO asserts if the µP does not toggle WDI with a valid transition (high-to-low or low-to-high) within the standard timeout period, tWDI. WDO remains asserted until WDI is toggled or RESET is asserted (Figure 7). While EN is low, or r55h[7] is a ‘0,’ the watchdog timer is in reset. The watchdog timer does not begin counting until the power-on mode is reached and RESET is deasserted. The watchdog timer is reset and WDO deasserts any time RESET is asserted (Figure 8). The watchdog timer will be held in reset while RESET is asserted. The watchdog can be configured to control the RESET output as well as the WDO output. RESET is pulsed low for the reset timeout, t RP, when the watchdog timer expires and the Watchdog Reset Output Enable bit (r55h[7]) is set to ‘1.’ Therefore, WDO pulses low for a short time (approximately 1µs) when the watchdog timer expires. RESET is not affected by the watchdog timer when the RESET Output Enable bit (r55h[7]) is set to ‘0.’ See Table 23 for more information on configuring watchdog functionality. ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers MAX16047/MAX16049 VTH LAST MON_ < tWDI tWDI_STARTUP WDI < tWDI tRP RESET Figure 6. Normal Watchdog Startup Sequence VCC < tWDI WDI < tWDI > tWDI < tWDI < tWDI < tWDI < tWDI 0V tWDI VCC WDO 0V Figure 7. Watchdog Timer Operation VCC < tWDI WDI < tWDI < tWDI tWDI tRP < tWDI_STARTUP < tWDI 0V VCC RESET 0V VCC WDO 0V 1μs Figure 8. Watchdog Startup Sequence with Watchdog Reset Enable Bit (r55h[7]) Set to ‘1’ ______________________________________________________________________________________ 41 MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Table 22. Watchdog Mode Selection REGISTER/ EEPROM ADDRESS BIT RANGE DESCRIPTION 0 Software Enable Bit 0 = Enabled. EN must also be high to begin sequencing. 1 = Disabled (factory default) 1 Margin Bit 1 = Margin functionality is enabled 0 = Margin disabled 2 Early Warning Selection Bit 0 = Early warning thresholds are undervoltage thresholds 1 = Early warning thresholds are overvoltage thresholds 3 Watchdog Mode Selection Bit 0 = Watchdog timer is in dependent mode 1 = Watchdog timer is in independent mode 4Dh [7:4] Not used Table 23. Watchdog Enables and Configuration REGISTER/ EEPROM ADDRESS BIT RANGE [2:0] Watchdog Timeout 000 = 1ms 001 = 4ms 010 = 12.5ms 011 = 50ms 100 = 200ms 101 = 800ms 110 = 1.6s 111 = 3.2s [4:3] Watchdog Startup Delay 00 = 25.6s 01 = 51.2s 10 = 102.4s 11 = 128s 55h 42 DESCRIPTION [5] Watchdog Enable 1 = Watchdog enabled 0 = Watchdog disabled [6] Watchdog Startup Delay Enable 1 = Watchdog startup delay enabled 0 = Watchdog startup delay disabled [7] Watchdog RESET Output Enable 1 = Watchdog timeout asserts RESET output 0 = Watchdog timeout does not assert RESET output ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers low for 3 system clock cycles or approximately 1µs. If the Watchdog RESET Output Enable bit (r55h[7]) is set to ‘0,’ when the WDT expires, WDO will be asserted but RESET will not be affected. Miscellaneous Table 24 lists several miscellaneous programmable items. Register r5Ch provides storage space for a userdefined configuration or firmware version number. Bit r5Dh[0] locks and unlocks the configuration registers. Bit r5Dh[1] locks and unlocks EEPROM addresses 00h to 11h. The r65h[2:0] bits contain a read-only manufacturing revision code. Write data to EEPROM r5Dh as normally done; however, to toggle a bit in register r5Dh, write a ‘1’ to that bit. Table 24. Miscellaneous Settings REGISTER/ EEPROM ADDRESS BIT RANGE 5Ch [7:0] User Identification. 8 bits of memory for user-defined identification [0] Configuration Lock 0 = Configuration registers writable 1 = Configuration registers (RAM and EEPROM) [except r5Dh] locked [1] EEPROM Lock Flag (set automatically after fault log is triggered): 0 = EEPROM is not locked. A triggered fault log stores fault information to EEPROM. 1 = EEPROM addresses 00h to 11h are locked. Write a ‘1’ to this bit to toggle the flag. 5Dh 65h DESCRIPTION [7:2] Not used [2:0] Manufacturing revision code. This register is read only. Not stored in EEPROM. [7:3] Not used ______________________________________________________________________________________ 43 MAX16047/MAX16049 Independent Watchdog Timer Operation When r4Dh[3] is ‘1,’ the watchdog timer operates in the independent mode. In the independent mode, the watchdog timer operates as if it were a separate chip. The watchdog timer is activated immediately upon VCC exceeding UVLO and once the boot-up sequence is finished. If RESET is asserted by the sequencer state machine, the watchdog timer and WDO will not be affected. There will be a long startup delay if r55h[6] is a ‘1.’ If r55h[6] is a ‘0,’ there will not be a long startup delay. In independent mode, if the Watchdog RESET Output Enable bit r55h[7] is set to ‘1,’ when the watchdog timer expires, WDO will be asserted then RESET will be asserted. WDO will then be deasserted. WDO will be MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers I2C/SMBus-Compatible Serial Interface The MAX16047/MAX16049 feature an I2C/SMBus-compatible 2-wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX16047/MAX16049 and the master device at clock rates up to 400kHz. Figure 1 shows the 2-wire interface timing diagram. The MAX16047/MAX16049 are transmit/receive slave-only devices, relying upon a master device to generate a clock signal. The master device (typically a µC) initiates a data transfer on the bus and generates SCL to permit that transfer. A master device communicates to the MAX16047/ MAX16049 by transmitting the proper address followed by command and/or data words. The slave address input, A0, is capable of detecting four different states, allowing multiple identical devices to share the same serial bus. The slave address is described further in the Slave Address section. Each transmit sequence is framed by a START (S) or REPEATED START (SR) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. SCL is a logic input, while SDA is an open-drain input/output. SCL and SDA both require external pullup resistors to generate the logic-high voltage. Use 4.7kΩ for most applications. SDA Bit Transfer Each clock pulse transfers one data bit. The data on SDA must remain stable while SCL is high (Figure 9); otherwise the MAX16047/MAX16049 registers a START or STOP condition (Figure 10) from the master. SDA and SCL idle high when the bus is not busy. START and STOP Conditions Both SCL and SDA idle high when the bus is not busy. A master device signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. The master device issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. A STOP condition frees the bus for another transmission. The bus remains active if a REPEATED START condition is generated, such as in the block read protocol (see Figure 1). Early STOP Conditions The MAX16047/MAX16049 recognize a STOP condition at any point during transmission except if a STOP condition occurs in the same high pulse as a START condition. This condition is not a legal I2C format; at least one clock pulse must separate any START and STOP condition. REPEATED START Conditions A REPEATED START (SR) may be sent instead of a STOP (P) condition to maintain control of the bus during a read operation. The START (S) and REPEATED START (SR) conditions are functionally identical. SDA SCL SCL DATA LINE STABLE, CHANGE OF DATA ALLOWED DATA VALID Figure 9. Bit Transfer 44 S P START CONDITION STOP CONDITION Figure 10. START and STOP Conditions ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Slave Address Use the slave address input, A0, to allow multiple identical devices to share the same serial bus. Connect A0 to GND, DBP (or an external supply voltage greater than 2V), SCL, or SDA to set the device address on the bus. See Table 25 for a listing of all possible 8-bit addresses. Table 25. Setting the I2C/SMBus Slave Address A0 SLAVE ADDRESS 0 101000X 1 101001X SCL 101010X SDA 101011X X = Don’t Care. CLOCK PULSE FOR ACKNOWLEDGE 1 2 8 9 SCL SDA BY TRANSMITTER S NACK SDA BY RECEIVER ACK Figure 11. Acknowledge ______________________________________________________________________________________ 45 MAX16047/MAX16049 Acknowledge The acknowledge bit (ACK) is the 9th bit attached to any 8-bit data word. The receiving device always generates an ACK. The MAX16047/MAX16049 generate an ACK when receiving an address or data by pulling SDA low during the 9th clock period (Figure 11). When transmitting data, such as when the master device reads data back from the MAX16047/MAX16049, the device waits for the master device to generate an ACK. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if the receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. The MAX16047/MAX16049 generate a NACK after the command byte is received during a software reboot, while writing to the EEPROM, or when receiving an illegal memory address. MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Send Byte The send byte protocol allows the master device to send one byte of data to the slave device (see Figure 12). The send byte presets a register pointer address for a subsequent read or write. The slave sends a NACK instead of an ACK if the master tries to send a memory address or command code that is not allowed. If the master sends 94h or 95h, the data is ACK, because this could be the start of the write block or read block. If the master sends a STOP condition before the slave asserts on ACK, the internal address pointer does not change. If the master sends 96h, this signifies a software reboot. The send byte procedure is the following: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends an 8-bit memory address or command code. 5) The addressed slave asserts an ACK (or NACK) on SDA. 6) The master sends a STOP condition. Receive Byte The receive byte protocol allows the master device to read the register content of the MAX16047/MAX16049 (see Figure 12). The EEPROM or register address must be preset with a send byte or write word protocol first. Once the read is complete, the internal pointer increases by one. Repeating the receive byte protocol reads the contents of the next address. The receive byte procedure follows: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a read bit (high). 3) The addressed slave asserts an ACK on SDA. 4) The slave sends 8 data bits. 5) The master asserts a NACK on SDA. 6) The master generates a STOP condition. Write Byte The write byte protocol (see Figure 12) allows the master device to write a single byte in the default page, 46 extended page, or EEPROM page, depending on which page is currently selected. The write byte procedure is the following: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends an 8-bit memory address. 5) The addressed slave asserts an ACK on SDA. 6) The master sends an 8-bit data byte. 7) The addressed slave asserts an ACK on SDA. 8) The master sends a STOP condition. To write a single byte, only the 8-bit memory address and a single 8-bit data byte are sent. The data byte is written to the addressed location if the memory address is valid. The slave will assert a NACK at step 5 if the memory address is not valid. Read Byte The read byte protocol (see Figure 12) allows the master device to read a single byte located in the default page, extended page, or EEPROM page depending on which page is currently selected. The read byte procedure is the following: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) 5) 6) 7) The master sends an 8-bit memory address. The addressed slave asserts an ACK on SDA. The master sends a REPEATED START condition. The master sends the 7-bit slave address and a read bit (high). 8) The addressed slave asserts an ACK on SDA. 9) The slave sends an 8-bit data byte. 10) The master asserts a NACK on SDA. 11) The master sends a STOP condition. If the memory address is not valid, it is NACKed by the slave at step 5 and the address pointer is not modified. ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Using command code 98h allows access to the extended page, which contains registers for ADC conversion results, and GPIO input/output data. Use command code 99h to return to the default page. Send command code 9Ah to access the EEPROM page. Once command code 9Ah has been sent, all addresses are recognized as EEPROM addresses only. Send command code 9Bh to return to the default page. Table 26. Command Codes COMMAND CODE 94h ACTION Write Block 95h Read Block 96h Reboot EEPROM in Register File 97h Trigger Fault Store to EEPROM 98h Extended Page Access On 99h Extended Page Access Off 9Ah EEPROM Page Access On 9Bh EEPROM Page Access Off Block Write The block write protocol (see Figure 12) allows the master device to write a block of data (1 byte to 16 bytes) to memory. The destination address should be preloaded by a previous send byte command; otherwise the block write command begins to write at the current address pointer. After the last byte is written, the address pointer remains preset to the next valid address. If the number of bytes to be written causes the address pointer to exceed FFh for EEPROM or 7Dh for configuration registers, the address pointer stays at FFh or 7Dh, overwriting this memory address with the remaining bytes of data. The last data byte sent is stored at register address FFh. The slave generates a NACK at step 5 if the command code is invalid or if the device is busy, and the address pointer is not altered. The block write procedure is the following: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends the 8-bit command code for block write (94h). 5) The addressed slave asserts an ACK on SDA. 6) The master sends the 8-bit byte count (1 byte to 16 bytes), n. 7) The addressed slave asserts an ACK on SDA. 8) The master sends 8 bits of data. 9) The addressed slave asserts an ACK on SDA. 10) Repeat steps 8 and 9 n - 1 times. 11) The master sends a STOP condition. Block Read The block read protocol (see Figure 12) allows the master device to read a block of up to 16 bytes from memory. Read fewer than 16 bytes of data by issuing an early STOP condition from the master, or by generating a NACK with the master. The destination address should be preloaded by a previous send byte command; otherwise the block read command begins to read at the current address pointer. If the number of bytes to be read causes the address pointer to exceed FFh for the configuration register or EEPROM, the address pointer stays at FFh and the last data byte read is from register rFFh. The block read procedure is the following: 1) The master sends a START condition. 2) The master sends the 7-bit slave address and a write bit (low). 3) The addressed slave asserts an ACK on SDA. 4) The master sends 8 bits of the block read command (95h). 5) The slave asserts an ACK on SDA, unless busy. 6) The master generates a REPEATED START condition. 7) The master sends the 7-bit slave address and a read bit (high). ______________________________________________________________________________________ 47 MAX16047/MAX16049 Command Codes The MAX16047/MAX16049 use eight command codes for block read, block write, and other commands. See Table 26 for a list of command codes. To initiate a software reboot, send 96h using the send byte format. A software-initiated reboot is functionally the same as a hardware-initiated power-on reset. During boot-up, EEPROM configuration data in the range of 0Fh to 7Dh is copied to the same register addresses in the default page. Send command code 97h to trigger a fault store to EEPROM. Configure the Critical Fault Log Control register (r47h) to store ADC conversion results and/or fault flags in registers once the command code has been sent. MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers 8) The slave asserts an ACK on SDA. 9) The slave sends the 8-bit byte count (16). 10) The master asserts an ACK on SDA. 12) The master asserts an ACK on SDA. 13) Repeat steps 11 and 12 up to fifteen times. 14) The master asserts a NACK on SDA. 11) The slave sends 8 bits of data. 15) The master sends a STOP condition. SEND BYTE FORMAT S RECEIVE BYTE FORMAT ADDRESS WR 7 BITS 0 ACK DATA ACK P S 8 BITS DATA BYTE: PRESETS THE INTERNAL ADDRESS POINTER OR REPRESENTS A COMMAND. SLAVE ADDRESS: EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. ADDRESS WR 7 BITS 1 ACK NACK DATA P 8 BITS SLAVE ADDRESS: EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. DATA BYTE: PRESETS THE INTERNAL ADDRESS POINTER OR REPRESENTS A COMMAND. WRITE BYTE FORMAT S ADDRESS WR 7 BITS 0 ACK COMMAND ACK DATA ACK P SLAVE TO MASTER 8 BITS 8 BITS DATA BYTE: DATA GOES INTO THE REGISTER (OR EEPROM LOCATION) SET BY THE COMMAND BYTE. COMMAND BYTE: SELECTS REGISTER OR EEPROM LOCATION YOU ARE WRITING TO. SLAVE ADDRESS: EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. MASTER TO SLAVE READ BYTE FORMAT S SLAVE ADDRESS WR ACK COMMAND ACK 7 BITS 0 8 BITS SR COMMAND BYTE: PREPARES DEVICE FOR FOLLOWING READ. SLAVE ADDRESS: EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. SLAVE ADDRESS WR 7 BITS 1 ACK DATA BYTE NACK P 8 BITS SLAVE ADDRESS: EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. DATA BYTE: DATA COMES FROM THE REGISTER SET BY THE COMMAND BYTE. BLOCK WRITE FORMAT S ADDRESS WR ACK COMMAND ACK BYTE COUNT= N 7 BITS 0 8 BITS 8 BITS SLAVE ADDRESS: EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. ACK COMMAND BYTE: DESTINATION ADDRESS DATA BYTE DATA BYTE ACK 1 ... 8 BITS ACK DATA BYTE N ACK P 8 BITS 8 BITS DATA BYTE: DATA GOES INTO THE REGISTER SET BY THE COMMAND BLOCK READ FORMAT S ADDRESS WR 7 BITS 0 ACK COMMAND ACK SLAVE ADDRESS: EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. S = START CONDITION P = STOP CONDITION SR = REPEATED START CONDITION D.C. = DON'T CARE 8 BITS COMMAND BYTE: PREPARES DEVICE FOR BLOCK OPERATION. SR ADDRESS WR 7 BITS 1 ACK SLAVE ADDRESS: EQUIVALENT TO CHIPSELECT LINE OF A 3-WIRE INTERFACE. BYTE COUNT= N ACK 8 BITS DATA BYTE 1 8 BITS ACK DATA BYTE ... 8 BITS ACK DATA BYTE NACK N 8 BITS DATA BYTE: DATA IS READ FROM THE REGISTER (OR EEPROM LOCATION) SET BY THE COMMAND CODE ACK = ACKNOWLEDGE, SDA PULLED LOW DURING RISING EDGE OF SCL NACK = NOT ACKNOWLEGE, SDA LEFT HIGH DURING RISING EDGE OF SCL ALL DATA IS CLOCKED IN/OUT OF THE DEVICE ON RISING EDGES OF SCL = SDA TRANSISTIONS FROM HIGH TO LOW DURING PERIOD OF SCL = SDA TRANSISTIONS FROM LOW TO HIGH DURING PERIOD OF SCL Figure 12: I2C/SMBus Protocols 48 P ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers REGISTERS AND EEPROM do not support IEEE 1149.1 boundary-scan functionality. The MAX16047/MAX16049 contain extra JTAG instructions and registers not included in the JTAG specification that provide access to internal memory. The extra instructions include LOAD ADDRESS, WRITE, READ, REBOOT, SAVE, and USERCODE. 01100 01011 01010 01001 01000 00111 MEMORY WRITE REGISTER [LENGTH = 8 BITS] 00110 MUX 1 MEMORY READ REGISTER [LENGTH = 8 BITS] 00101 MEMORY ADDRESS REGISTER [LENGTH = 8 BITS] 00100 USER CODE REGISTER [LENGTH = 32 BITS] 00011 IDENTIFICATION REGISTER [LENGTH = 32 BITS] BYPASS REGISTER [LENGTH = 1 BIT] 00000 11111 COMMAND DECODER 01100 RSTEEPADD 01011 SETEEPADD 01010 RSTEXTRAM 01001 SETEXTRAM 01000 SAVE 00111 REBOOT VDB INSTRUCTION REGISTER [LENGTH = 5 BITS] RPU TDI MUX 2 TMS TDO TEST ACCESS PORT (TAP) CONTROLLER TCK Figure 13. JTAG Block Diagram ______________________________________________________________________________________ 49 MAX16047/MAX16049 JTAG Serial Interface The MAX16047/MAX16049 contain a JTAG port that complies with a subset of the IEEE 1149.1 specification. Either the I2C or the JTAG interface may be used to access internal memory; however, only one interface is allowed to run at a time. The MAX16047/MAX16049 MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Test Access Port (TAP) Controller State Machine The TAP controller is a finite state machine that responds to the logic level at TMS on the rising edge of TCK. See Figure 14 for a diagram of the finite state machine. The possible states are described below: Test-Logic-Reset: At power-up, the TAP controller is in the test-logic-reset state. The instruction register contains the IDCODE instruction. All system logic of the device operates normally. This state can be reached from any state by driving TMS high for five clock cycles. Run-Test/Idle: The run-test/idle state is used between scan operations or during specific tests. The instruction register and test data registers remain idle. 1 Select-DR-Scan: All test data registers retain their previous state. With TMS low, a rising edge of TCK moves the controller into the capture-DR state and initiates a scan sequence. TMS high during a rising edge on TCK moves the controller to the select-IR-scan state. Capture-DR: Data can be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected test data register does not allow parallel loads, the test data register remains at its current value. On the rising edge of TCK, the controller goes to the shift-DR state if TMS is low or it goes to the exit1-DR state if TMS is high. TEST-LOGIC-RESET 0 0 RUN-TEST/IDLE 1 SELECT-DR-SCAN 1 SELECT-IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 1 1 EXIT1-DR 0 PAUSE-DR PAUSE-IR 0 1 0 1 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR UPDATE-IR 0 1 Figure 14. TAP Controller State Diagram 50 1 EXIT1-IR 0 1 0 SHIFT-IR 0 1 0 1 ______________________________________________________________________________________ 0 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Shift-IR: In this state, the shift register in the instruction register connects between TDI and TDO and shifts data one stage for every rising edge of TCK toward the TDO serial output while TMS is low. The parallel outputs of the instruction register as well as all test data registers remain at their previous states. A rising edge on TCK with TMS high moves the controller to the exit1-IR state. A rising edge on TCK with TMS low keeps the controller in the shift-IR state while moving data one stage through the instruction shift register. Exit1-IR: A rising edge on TCK with TMS low puts the controller in the pause-IR state. If TMS is high on the rising edge of TCK, the controller enters the update-IR state. Pause-IR: Shifting of the instruction shift register halts temporarily. With TMS high, a rising edge on TCK puts the controller in the exit2-IR state. The controller remains in the pause-IR state if TMS is low during a rising edge on TCK. Exit2-IR: A rising edge on TCK with TMS high puts the controller in the update-IR state. The controller loops back to shift-IR if TMS is low during a rising edge of TCK in this state. Update-IR: The instruction code that has been shifted into the instruction shift register latches to the parallel outputs of the instruction register on the falling edge of TCK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on TCK with TMS low puts the controller in the run-test/idle state. With TMS high, the controller enters the select-DR-scan state. Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 5 bits in length. When the TAP controller enters the shift-IR state, the instruction shift register connects between TDI and TDO. While in the shift-IR state, a rising edge on TCK with TMS low shifts the data one stage toward the serial output at TDO. A rising edge on TCK in the exit1-IR state or the exit2-IR state with TMS high moves the controller to the update-IR state. The falling edge of that same TCK latches the data in the instruction shift register to the instruction register parallel output. Instructions supported by the MAX16047/MAX16049 and the respective operational binary codes are shown in Table 27. ______________________________________________________________________________________ 51 MAX16047/MAX16049 Shift-DR: The test data register selected by the current instruction connects between TDI and TDO and shifts data one stage toward its serial output on each rising edge of TCK while TMS is low. On the rising edge of TCK, the controller goes to the exit1-DR state if TMS is high. Exit1-DR: While in this state, a rising edge on TCK puts the controller in the update-DR state. A rising edge on TCK with TMS low puts the controller in the pause-DR state. Pause-DR: Shifting of the test data registers halts while in this state. All test data registers retain their previous state. The controller remains in this state while TMS is low. A rising edge on TCK with TMS high puts the controller in the exit2-DR state. Exit2-DR: A rising edge on TCK with TMS high while in this state puts the controller in the update-DR state. A rising edge on TCK with TMS low enters the shift-DR state. Update-DR: A falling edge on TCK while in the updateDR state latches the data from the shift register path of the test data registers into a set of output latches. This prevents changes at the parallel output because of changes in the shift register. On the rising edge of TCK, the controller goes to the run-test/idle state if TMS is low or goes to the select-DR-scan state if TMS is high. Select-IR-Scan: All test data registers retain their previous states. The instruction register remains unchanged during this state. With TMS low, a rising edge on TCK moves the controller into the capture-IR state. TMS high during a rising edge on TCK puts the controller back into the test-logic-reset state. Capture-IR: Use the capture-IR state to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of TCK. If TMS is high on the rising edge of TCK, the controller enters the exit1-IR state. If TMS is low on the rising edge of TCK, the controller enters the shift-IR state. MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Table 27. JTAG Instruction Set INSTRUCTION HEX CODE SELECTED REGISTER/ACTION BYPASS 1Fh Bypass. Mandatory instruction code. IDCODE 00h Manufacturer ID code and part number User code (user-defined ID) USERCODE 03h LOAD ADDRESS 04h Load address register content READ DATA 05h Memory read WRITE DATA 06h Memory write REBOOT 07h Resets the device SAVE 08h Stores current fault information in EEPROM Extended page access on SETEXTRAM 09h RSTEXTRAM 0Ah Extended page access off SETEEPADD 0Bh EEPROM page access on RSTEEPADD 0Ch EEPROM page access off BYPASS: When the BYPASS instruction is latched into the instruction register, TDI connects to TDO through the 1-bit bypass test data register. This allows data to pass from TDI to TDO without affecting the device’s normal operation. IDCODE: When the IDCODE instruction is latched into the parallel instruction register, the identification data register is selected. The device identification code is loaded into the identification data register on the rising edge of TCK following entry into the capture-DR state. Shift-DR can be used to shift the identification code out serially through TDO. During test-logic-reset, the IDCODE instruction is forced into the instruction register. The identification code always has a ‘1’ in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. See Table 28. Table 28. 32-Bit Identification Code MSB LSB Version (4 bits) Device ID (16 bits) Manufacturer ID (11 bits) Fixed value (1 bit) 0000 0000000000000001 00011001011 1 USERCODE: When the USERCODE instruction latches into the parallel instruction register, the user-code data register is selected. The device user-code loads into the user-code data register on the rising edge of TCK following entry into the capture-DR state. Shift-DR can be used to shift the user-code out serially through TDO. See Table 29. This instruction may be used to help identify multiple MAX16047/MAX16049 devices connected in a JTAG chain. Table 29. 32-Bit User-Code Data MSB LSB D.C. (don’t cares) 00000000000000000 52 I2C/SMBus slave address See Table 31 User identification (firmware version) r5Ch[7:0] contents ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers REBOOT: This is an extension to the standard IEEE 1149.1 instruction set to initiate a software controlled reset to the MAX16047/MAX16049. When the REBOOT instruction latches into the instruction register, the MAX16047/MAX16049 resets and immediately begins the boot-up sequence. SAVE: This is an extension to the standard IEEE 1149.1 instruction set that triggers a fault log. The current ADC conversion results along with fault information are saved to EEPROM depending on the configuration of the Critical Fault Log Control register (r47h). SETEXTRAM: This is an extension to the standard IEEE 1149.1 instruction set that allows access to the extended page. Extended registers include ADC conversion results, DACOUT enables, and GPIO input/output data. RSTEXTRAM: This is an extension to the standard IEEE 1149.1 instruction set. Use RSTEXTRAM to return to the default page and disable access to the extended page. SETEEPADD: This is an extension to the standard IEEE 1149.1 instruction set that allows access to the EEPROM page. Once the SETEEPADD command has been sent, all addresses are recognized as EEPROM addresses only. RSTEEPADD: This is an extension to the standard IEEE 1149.1 instruction set. Use RSTEEPADD to return to the default page and disable access to the EEPROM. Applications Information Unprogrammed Device Behavior When the EEPROM has not been programmed using the JTAG or I2C interface, the default configuration of the EN_OUT_ outputs is open-drain active-low. If it is necessary to hold an EN_OUT_ high or low to prevent prema- ture startup of a power supply before the EEPROM is programmed, connect a resistor to ground or the supply voltage. Avoid connecting a resistor to ground if the output is to be configured as open-drain with a separate pullup resistor. Device Behavior at Power-Up When VCC is ramped from 0V, the RESET output is high impedance until VCC reaches 1.4V, at which point it is driven low. All other outputs are high impedance until VCC reaches 2.85V, when the EEPROM contents are copied into register memory, and after which the outputs assume their programmed states. Maintaining Power During a Fault Condition Power to the MAX16047/MAX16049 must be maintained for a specific period of time to ensure a successful EEPROM fault log operation during a fault that removes power to the circuit. The amount of time required depends on the settings in the fault control register (r47h[1:0]) according to Table 30. Table 30. EEPROM Fault Log Operation Period FAULT CONTROL REGISTER VALUE r47h[1:0] DESCRIPTION REQUIRED PERIOD tFAULT_SAVE (ms) 00 Failed lines and ADC values saved 204 01 Failed lines saved 60 10 ADC values saved 168 11 No information saved N/A Maintain power for shutdown during fault conditions in applications where the always-on power supply cannot be relied upon by placing a diode and a large capacitor between the voltage source, VIN, and VCC (Figure 15). The capacitor value depends on VIN and the time delay required, tFAULT_SAVE. Use the following formula to calculate the capacitor size: C= tFAULT_SAVE × ICC(MAX) VIN − VDIODE − VCC(MIN) where the capacitance is in Farads and tFAULT_SAVE is in seconds. ICC(MAX) is 5mA, VDIODE is the voltage drop across the diode, and VUVLO is 2.85V. For example, with a VIN of 14V, a diode drop of 0.7V, and a tFAULT_SAVE of 0.204s, the minimum required capacitance is 100µF. ______________________________________________________________________________________ 53 MAX16047/MAX16049 LOAD ADDRESS: This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the MAX16047/MAX16049. When the LOAD ADDRESS instruction latches into the instruction register, TDI connects to TDO through the 8-bit memory address test data register during the shift-DR state. READ DATA: This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the MAX16047/MAX16049. When the READ instruction latches into the instruction register, TDI connects to TDO through the 8-bit memory read test data register during the shift-DR state. WRITE DATA: This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the MAX16047/MAX16049. When the WRITE instruction latches into the instruction register, TDI connects to TDO through the 8-bit memory write test data register during the shift-DR state. MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers VIN VCC C MAX16047 MAX16049 If more than six series-pass MOSFETs are required for an application, additional series-pass p-channel MOSFETS may be connected to outputs configured as active-low open drain (Figure 17). Connect a pullup resistor from the gate to the source of the MOSFET, and ensure the absolute maximum ratings of the MAX16047/MAX16049 are not exceeded. VIN GND VOUT MON_ EN_OUT_ INS_ GATE DRIVE ADC MUX Figure 15. Power Circuit for Shutdown During Fault Conditions LOGIC Driving High-Side MOSFET Switches The MAX16047/MAX16049 use external n-channel MOSFET switches for voltage tracking applications. To configure the part for closed-loop voltage tracking using series-pass MOSFETs, configure up to four of the programmable outputs (EN_OUT1–EN_OUT4) of the MAX16047/MAX16049 as closed-loop tracking outputs and configure up to four of the GPIOs as sense-return inputs (INS1–INS4). Connect the EN_OUT_ output to the gate of an n-channel MOSFET, connect the source of the MOSFET to the INS_ feedback input, and monitor the drain side of the MOSFET with the corresponding MON_ input (see Figure 16). Both the input and the output must be assigned to the same slot (see the Closed–Loop Tracking section). Configure the power-up and powerdown slew rates in the configuration registers. To provide additional control over power-down, enable the internal 100Ω pulldown resistors on the INS_ connections. Up to six of the programmable outputs (EN_OUT1– EN_OUT6) of the MAX16047/MAX16049 may be configured as charge-pump outputs. In this case, they can drive the gates of series-pass n-channel MOSFETS without closed-loop tracking functionality. When configured in this way, these outputs act as simple power switches to turn on the voltage supply rails. Approximate the slew rate, SR, using the following formula: SR = ICP (CGATE + CEXT ) VTH_PG REFERENCE RAMP 100Ω Figure 16. Closed-Loop Tracking S VIN D R MON_ VOUT G EN_OUT_ MAX16047 MAX16049 where ICP is the 6µA (typ) charge-pump source current, CGATE is the gate capacitance of the MOSFET, and CEXT is the capacitance connected from the gate to ground. Power-down is not well controlled due to the absence of the 100Ω pulldowns. Figure 17. Connection for a p-Channel Series-Pass MOSFET 54 ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Layout and Bypassing Bypass DBP and ABP each with a 1µF ceramic capacitor to GND. Bypass VCC with a 10µF capacitor to ground. Avoid routing digital return currents through a sensitive analog area, such as an analog supply input return path or ABP’s bypass capacitor ground connection. Use dedicated analog and digital ground planes. Connect the capacitors as close as possible to the device. Table 31. Recommended MOSFETs MANUFACTURER Fairchild Vishay MAX VDS (V) VGS_TH (V) RDS(ON) AT VGS = 4.5V (mΩ) IMAX AT 50mV VOLTAGE DROP (A) Qg (typ) (nC) FDC633N 30 0.67 42 1.19 11 Super SOT-6 FDP8030L FDB8030L 30 1.5 4.5 11.11 120 TO-220 TO-263AB FDD6672A 30 1.2 9.5 5.26 33 TO-252 SO-8 PART PACKAGE FDS8876 30 2.5 10.2 2.94 15 Si7136DP 20 3 4.5 11.11 24.5 SO-8 Si4872DY 30 1 10 5 27 SO-8 SUD50N02-09P 20 3 17 2.94 10.5 Si1488DH 20 0.95 49 1.02 6 SOT-363 SC70-6 IRL3716 20 3 4.8 10.4 53 TO220AB D2PAK TO-262 IRL3402 20 0.7 10 5 78 (max) TO220AB IRL3715Z 20 2.1 15.5 3.22 7 TO220AB D2PAK TO-262 IRLM2502 20 1.2 45 1.11 8 SOT23-3 Micro3 International Rectifier TO-252 ______________________________________________________________________________________ 55 MAX16047/MAX16049 Simple slew-rate control is accomplished by adding a capacitor from the gate to ground. The slew rate is approximated by the RC charge curve of the pullup resistor acting with the capacitor from gate to ground. Note that the power-off is not well controlled due to the absence of the 100Ω pulldowns. Ensure that MOSFETs have a low gate-to-source threshold (VGS_TH) and RDS(ON). See Table 31 for recommended n-channel MOSFETs. 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers MAX16047/MAX16049 Register Map 56 PAGE ADDRESS READ/WRITE Ext 00h R MON1 ADC Result Register (MSB) DESCRIPTION Ext 01h R MON1 ADC Result Register (LSB) Ext 02h R MON2 ADC Result Register (MSB) Ext 03h R MON2 ADC Result Register (LSB) Ext 04h R MON3 ADC Result Register (MSB) Ext 05h R MON3 ADC Result Register (LSB) Ext 06h R MON4 ADC Result Register (MSB) Ext 07h R MON4 ADC Result Register (LSB) Ext 08h R MON5 ADC Result Register (MSB) Ext 09h R MON5 ADC Result Register (LSB) Ext 0Ah R MON6 ADC Result Register (MSB) Ext 0Bh R MON6 ADC Result Register (LSB) Ext 0Ch R MON7 ADC Result Register (MSB) Ext 0Dh R MON7 ADC Result Register (LSB) Ext 0Eh R MON8 ADC Result Register (MSB) Ext 0Fh R MON8 ADC Result Register (LSB) Ext 10h R MON9 ADC Result Register (MSB)* Ext 11h R MON9 ADC Result Register (LSB)* Ext 12h R MON10 ADC Result Register (MSB)* Ext 13h R MON10 ADC Result Register (LSB)* Ext 14h R MON11 ADC Result Register (MSB)* Ext 15h R MON11 ADC Result Register (LSB)* Ext 16h R MON12 ADC Result Register (MSB)* Ext 17h R MON12 ADC Result Register (LSB)* Ext 18h R/W Fault Register—Failed Line Flags Ext 19h R/W Fault Register—Failed Line Flags Ext 1Ah R/W Ext 1Bh R GPIO Data Out GPIO Data In Ext 1Ch–1Dh R/W Reserved Default 00h–0Bh R/W Reserved EEPROM 00h R/W Power-Up Fault Registers EEPROM 01h R/W Failed Line Flags (Fault Registers) EEPROM 02h R/W Failed Line Flags (Fault Registers) EEPROM 03h R/W MON1 Conversion Result at Time of Fault EEPROM 04h R/W MON2 Conversion Result at Time of Fault EEPROM 05h R/W MON3 Conversion Result at Time of Fault EEPROM 06h R/W MON4 Conversion Result at Time of Fault EEPROM 07h R/W MON5 Conversion Result at Time of Fault EEPROM 08h R/W MON6 Conversion Result at Time of Fault EEPROM 09h R/W MON7 Conversion Result at Time of Fault ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers PAGE ADDRESS READ/WRITE DESCRIPTION EEPROM 0Ah R/W EEPROM 0Bh R/W MON9 Conversion Result at Time of Fault* EEPROM 0Ch R/W MON10 Conversion Result at Time of Fault* EEPROM 0Dh R/W MON11 Conversion Result at Time of Fault* EEPROM 0Eh R/W MON12 Conversion Result at Time of Fault* Def/EE 0Fh R/W ADC MON4–MON1 Voltage Ranges Def/EE 10h R/W ADC MON8–MON5 Voltage Ranges Def/EE 11h R/W ADC MON12–MON9 Voltage Ranges* Def/EE 12h–14h R/W Reserved Def/EE 15h R/W FAULT1 Dependencies Def/EE 16h R/W FAULT1 Dependencies Def/EE 17h R/W FAULT2 Dependencies Def/EE 18h R/W FAULT2 Dependencies Def/EE 19h R/W RESET Output Configuration Def/EE 1Ah R/W RESET Output Dependencies Def/EE 1Bh R/W RESET Output Dependencies Def/EE 1Ch R/W GPIO Configuration Def/EE 1Dh R/W GPIO Configuration Def/EE 1Eh R/W GPIO Configuration Def/EE 1Fh R/W EN_OUT1–EN_OUT3 Output Configuration Def/EE 20h R/W EN_OUT3–EN_OUT6 Output Configuration Def/EE 21h R/W EN_OUT6–EN_OUT9 Output Configuration* Def/EE 22h R/W EN_OUT10–EN_OUT12 Output Configuration* Def/EE 23h R/W MON1 Early Warning Threshold Def/EE 24h R/W MON1 Overvoltage Threshold Def/EE 25h R/W MON1 Undervoltage Threshold Def/EE 26h R/W MON2 Early Warning Threshold Def/EE 27h R/W MON2 Overvoltage Threshold Def/EE 28h R/W MON2 Undervoltage Threshold Def/EE 29h R/W MON3 Early Warning Threshold Def/EE 2Ah R/W MON3 Overvoltage Threshold Def/EE 2Bh R/W MON3 Undervoltage Threshold Def/EE 2Ch R/W MON4 Early Warning Threshold Def/EE 2Dh R/W MON4 Overvoltage Threshold Def/EE 2Eh R/W MON4 Undervoltage Threshold Def/EE 2Fh R/W MON5 Early Warning Threshold Def/EE 30h R/W MON5 Overvoltage Threshold Def/EE 31h R/W MON5 Undervoltage Threshold Def/EE 32h R/W MON6 Early Warning Threshold Def/EE 33h R/W MON6 Overvoltage Threshold MON8 Conversion Result at Time of Fault ______________________________________________________________________________________ 57 MAX16047/MAX16049 Register Map (continued) 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers MAX16047/MAX16049 Register Map (continued) 58 PAGE ADDRESS READ/WRITE Def/EE 34h R/W MON6 Undervoltage Threshold DESCRIPTION Def/EE 35h R/W MON7 Early Warning Threshold Def/EE 36h R/W MON7 Overvoltage Threshold Def/EE 37h R/W MON7 Undervoltage Threshold Def/EE 38h R/W MON8 Early Warning Threshold Def/EE 39h R/W MON8 Overvoltage Threshold Def/EE 3Ah R/W MON8 Undervoltage Threshold Def/EE 3Bh R/W MON9 Early Warning Threshold* Def/EE 3Ch R/W MON9 Overvoltage Threshold* Def/EE 3Dh R/W MON9 Undervoltage Threshold* Def/EE 3Eh R/W MON10 Early Warning Threshold* Def/EE 3Fh R/W MON10 Overvoltage Threshold* Def/EE 40h R/W MON10 Undervoltage Threshold* Def/EE 41h R/W MON11 Early Warning Threshold* Def/EE 42h R/W MON11 Overvoltage Threshold* Def/EE 43h R/W MON11 Undervoltage Threshold* Def/EE 44h R/W MON12 Early Warning Threshold* Def/EE 45h R/W MON12 Overvoltage Threshold* Def/EE 46h R/W MON12 Undervoltage Threshold* Def/EE 47h R/W Fault Control Def/EE 48h R/W Faults Causing Emergency EEPROM Save Def/EE 49h R/W Faults Causing Emergency EEPROM Save Def/EE 4Ah R/W Faults Causing Emergency EEPROM Save Def/EE 4Bh R/W Faults Causing Emergency EEPROM Save Def/EE 4Ch R/W Faults Causing Emergency EEPROM Save Def/EE 4Dh R/W Software Enable/MARGIN Def/EE 4Eh R/W Power-Up/Power-Down Pulldown Resistors Def/EE 4Fh R/W Autoretry, Slew Rate, and ADC Fault Deglitch Def/EE 50h R/W Sequence Delays Def/EE 51h R/W Sequence Delays Def/EE 52h R/W Sequence Delays Def/EE 53h R/W Sequence Delays Def/EE 54h R/W Sequence Delays/Reverse-Sequence Bit Def/EE 55h R/W Watchdog Timer Setup Def/EE 56h R/W MON2–MON1 Slot Assignment from Slot 1 to Slot 12 Def/EE 57h R/W MON4–MON3 Slot Assignment from Slot 1 to Slot 12 Def/EE 58h R/W MON6–MON5 Slot Assignment from Slot 1 to Slot 12 Def/EE 59h R/W MON8–MON7 Slot Assignment from Slot 1 to Slot 12 Def/EE 5Ah R/W MON10–MON9 Slot Assignment from Slot 1 to Slot 12* ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers PAGE ADDRESS READ/WRITE Def/EE 5Bh R/W MON12–MON11 Slot Assignment from Slot 1 to Slot 12* Def/EE 5Ch R/W Customer Firmware Version Def/EE 5Dh R/W EEPROM and Configuration Lock Def/EE 5Eh R/W EN_OUT2–EN_OUT1 Slot Assignment from Slot 0 to Slot 11 Def/EE 5Fh R/W EN_OUT4–EN_OUT2 Slot Assignment from Slot 0 to Slot 11 Def/EE 60h R/W EN_OUT6–EN_OUT5 Slot Assignment from Slot 0 to Slot 11 Def/EE 61h R/W EN_OUT8–EN_OUT7 Slot Assignment from Slot 0 to Slot 11 Def/EE 62h R/W EN_OUT10–EN_OUT9 Slot Assignment from Slot 0 to Slot 11* Def/EE 63h R/W EN_OUT12–EN_OUT11 Slot Assignment from Slot 0 to Slot 11* Def/EE 64h R/W Def/EE 65h R Def/EE 66h–93h — EEPROM 9Ch–FFh R/W DESCRIPTION INS Power-Good (PG) Thresholds Manufacturing Revision Code Reserved User EEPROM *MAX16047 only Note: Ext refers to registers contained in the extended page, Default refers to registers contained in the default page, EEPROM refers to EEPROM memory locations, and Def/EE refers to locations that are stored in EEPROM and loaded into the same addresses in the default page on boot-up. Selector Guide GENERAL-PURPOSE INPUTS/OUTPUTS SEQUENCING OUTPUTS 12 6 12 8 6 8 PART VOLTAGE DETECTOR INPUTS MAX16047ETN+ MAX16049ETN+ Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ 59 MAX16047/MAX16049 Register Map (continued) 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers GPIO3 GPIO4 EN_OUT1 EN_OUT2 EN_OUT3 EN_OUT4 EN_OUT5 EN_OUT6 EN_OUT8 55 54 53 52 EN_OUT7 56 EN_OUT9 EN_OUT10 EN_OUT11 TOP VIEW EN_OUT12 MAX16047/MAX16049 Pin Configurations 51 50 49 48 47 46 45 44 43 + MON1 1 42 GPIO2 MON2 2 41 GPIO1 MON3 3 40 GND MON4 4 39 DBP MON5 5 38 VCC MON6 6 37 ABP MON7 7 36 N.C. MON8 8 35 N.C. MON9 9 34 N.C. MON10 10 33 N.C. MON11 11 32 N.C. 31 N.C. MAX16047 *EP MON12 12 RESET 13 30 N.C. A0 14 29 N.C. N.C. N.C. N.C. N.C. EN_OUT2 EN_OUT1 GPIO4 GPIO3 EN GPIO5 GND GPIO6 TDO TCK TDI TMS SCL SDA 15 16 17 18 19 20 21 22 23 24 25 26 27 28 EN_OUT3 EN_OUT4 EN_OUT5 55 54 53 52 EN_OUT6 56 EN_OUT7 EN_OUT8 N.C. N.C. N.C. N.C. TQFN (8mm x 8mm) 51 50 49 48 47 46 45 44 43 + MON1 1 42 GPIO2 MON2 2 41 GPIO1 MON3 3 40 GND MON4 4 39 DBP MON5 5 38 VCC MON6 6 37 ABP MON7 7 36 N.C. MON8 8 35 N.C. N.C. 9 34 N.C. N.C. 10 33 N.C. N.C. 11 32 N.C. 31 N.C. RESET 13 30 N.C. A0 14 29 N.C. MAX16049 *EP N.C. 12 N.C. N.C. N.C. N.C. EN GPIO5 GND GPIO6 TDO TCK TDI TMS SCL SDA 15 16 17 18 19 20 21 22 23 24 25 26 27 28 TQFN (8mm x 8mm) *EP = EXPOSED PAD 60 ______________________________________________________________________________________ 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers 56L THIN QFN.EPS PACKAGE OUTLINE 56L THIN QFN, 8x8x0.8mm 21-0135 E 1 2 ______________________________________________________________________________________ 61 MAX16047/MAX16049 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX16047/MAX16049 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) PACKAGE OUTLINE 56L THIN QFN, 8x8x0.8mm 21-0135 E 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 62 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.