19-0870; Rev 2; 6/10 KIT ATION EVALU E L B A AVAIL EEPROM-Based System Monitors with Nonvolatile Fault Memory Features The MAX16031/MAX16032 EEPROM-configurable system monitors feature an integrated 10-bit analog-todigital converter (ADC) designed to monitor voltages, temperatures, and current in complex systems. These EEPROM-configurable devices allow enormous flexibility in selecting operating ranges, upper and lower limits, fault output configuration, and operating modes with the capability of storing these values within the device. The MAX16031 monitors up to eight voltages, three temperatures (one internal/two external remote temperature diodes), and a single current. The MAX16032 monitors up to six voltages and two temperatures (one internal/one remote temperature diode). Each of these monitored parameters is muxed into the ADC and written to its respective register that can be read back through the SMBus™ and JTAG interface. Measured values are compared to the user-configurable upper and lower limits. For voltage measurements, there are two undervoltage and two overvoltage limits. For current and temperature, there are two sets of upper limits. Whenever the measured value is outside its limits, an alert signal is generated to notify the processor. Independent outputs are available for overcurrent, overtemperature, and undervoltage/overvoltage that are configured to assert on assigned channels. There are also undedicated fault outputs that are configured to offer a secondary limit for temperature, current, or voltage fault or provide a separate overvoltage output. o Supply Voltage Operating Range of 2.85V to 14V o Monitors Up to Eight Voltages (Single-Ended or Pseudo-Differential) with 1% Accuracy o EEPROM-Configurable Limits Two Undervoltage and Two Overvoltage Two Overtemperature Two Overcurrent o High-Side Current-Sense Amplifier with Overcurrent Output (MAX16031 Only) o Monitors Up to Three Temperatures (1 Internal/2 Remote) o Nonvolatile Fault Memory Stores Fault Conditions for Later Retrieval o Two Additional Configurable Fault Outputs o Two Configurable GPIOs o SMBus/I2C-Compatible Interface with ALERT Output and Bus Timeout Function o JTAG Interface o 7mm x 7mm, 48-Pin TQFN Package Applications Servers Workstations PART TEMP RANGE PIN-PACKAGE MAX16031ETM+ -40°C to +85°C 48 TQFN-EP* MAX16032ETM+ -40°C to +85°C 48 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. IN2 1 N.C. DXP1 DXN1 N.C. (DXP2) N.C. (DXN2) N.C. (CS+) N.C. (CS-) N.C. N.C. VCC VCC Pin Configuration IN1 During a major fault event, such as a system shutdown, the MAX16031/MAX16032 automatically copy the internal ADC registers into the nonvolatile EEPROM registers that then are read back for diagnostic purposes. The MAX16031/MAX16032 offer additional GPIOs that are used for voltage sequencing, additional fault outputs, a manual reset input, or read/write logic levels. A separate current-sense amplifier with an independent output allows for fast shutoff during overcurrent conditions. The MAX16031/MAX16032 are available in a 7mm x 7mm TQFN package and are fully specified from -40°C to +85°C. Ordering Information 48 47 46 45 44 43 42 41 40 39 38 37 IN3 2 35 GND IN4 3 34 DBP N.C. 4 33 TDO N.C. 5 32 N.C. N.C. 6 N.C. 7 29 TDI IN5 9 28 TCK IN6 10 27 TMS 26 RESET EP 13 14 15 16 17 18 19 20 21 22 23 24 RBP SDA SCL A0 A1 ALERT OVERT N.C. (OVERC) FAULT2 25 FAULT1 GPIO2 N.C. (IN8) 12 GND Telecom ( ) MAX16031 ONLY SMBus is a trademark of Intel Corp. 30 N.C. GND 8 GPIO1 Networking 31 N.C. MAX16031 MAX16032 N.C. (IN7) 11 Storage Systems 36 ABP + TQFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX16031/MAX16032 General Description EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Selector Guide VOLTAGE MONITORS TEMPERATURE SENSORS SINGLE ENDED DIFFERENTIAL INT EXT CURRENTSENSE AMPS MAX16031ETM+ 8 4 1 2 1 4 2 MAX16032ETM+ 6 3 1 1 — 4 2 PART FAULT GPIOs OUTPUTS Typical Application Circuit 5V 5V DC-DC EN 1.5V 1.5V DC-DC 3.3V 3.3V DC-DC EN 1.2V 1.2V DC-DC 12V BUS 2.5V 2.5V DC-DC EN 0.9V 0.9V LINEAR 1.8V 1.8V DC-DC EN 3.3V AUX CS+ CS- IN1 IN2 IN3 IN4 IN5 VCC 1µF IN6 IN7 IN8 ALERT INT SCL SCL SDA SDA µC GPIO1 RESET RESET SYSTEM RESET DXP1 MAX16031 FAULT1 FAULT2 DXN1 DXP2 OVERT TO FAN CONTROL OVERC DXN2 GPIO2 DBP ABP 1µF 1µF RBP GND A0 A1 TMS TCK TDI TDO 2.2µF TMS SYSTEM JTAG HEADER TCK TDI MANUAL RESET SWITCH TO OTHER JTAG DEVICES TDO 2 _______________________________________________________________________________________ WARNING INDICATORS EEPROM-Based System Monitors with Nonvolatile Fault Memory Input/Output Current (all except DXN1, DXN2, SDA, and ALERT) ..................20mA Continuous Power Dissipation (TA = +70°C) 48-Pin, 7mm x 7mm TQFN (derate 27.8mW/°C above +70°C) ........................2222.2mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature .....................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+250°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 2.9V to 14V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1) PARAMETER Operating Voltage Range Undervoltage Lockout Undervoltage Lockout Hysteresis Supply Current SYMBOL CONDITIONS VCC VUVLO MIN 2.90 Minimum voltage at VCC to access the digital interfaces VUVLOHYS ICC TYP MAX UNITS 14.00 V 2.8 V 5 mA 100 Static (EEPROM not accessed) 3 mV ADC DC ACCURACY Resolution Total Unadjusted Error TA = -40°C to +85°C 10 Bits 0.9 % FSR Integral Nonlinearity 1 LSB Differential Nonlinearity 1 LSB ADC Total Monitoring Cycle Time tCYCLE ADC IN_ Voltage Ranges Reference Voltage VRBP Eight supply inputs, three temperatures, and current sense 80 Register map bit set to 00 (LSB = 5.46mV) 5.6 Register map bit set to 01 (LSB = 2.73mV) 2.8 Register map bit set to 10 (LSB = 1.36mV) 1.4 1.306 1.4 100 µs V 1.414 V 5.6 V 80 kΩ IN_ ANALOG INPUT Absolute Input Voltage Range (Referenced to GND) 0 Input Impedance 30 50 _______________________________________________________________________________________ 3 MAX16031/MAX16032 ABSOLUTE MAXIMUM RATINGS VCC to GND ............................................................-0.3V to +15V IN_, FAULT_, SCL, SDA, OVERT to GND.................-0.3V to +6V A0, A1, TCK, TMS, TDI to GND ................................-0.3V to +6V OVERC, RESET, GPIO_, ALERT to GND..................-0.3V to +6V RBP, ABP, DBP to GND ...-0.3V to lower of (6V and VCC + 0.3V) TDO, DXP1, DXP2 to GND..........................-0.3V to VDBP + 0.3V CS+, CS- to GND ...................................................-0.3V to +30V (CS+ - CS-) ............................................................................±5V DXN1, DXN2 to GND.............................................-0.3V to +0.8V SDA, ALERT Current ...........................................-1mA to +50mA DXN1, DXN2 Current ............................................................1mA MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.9V to 14V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS Percent of programmed threshold Input Hysteresis MIN TYP r5Ch[5] = 0 0.78 r5Ch[5] = 1 1.17 MAX UNITS % RESET OUTPUT Reset Timeout Period tRP r20h[5:3] = 000; from MR going high 22.5 25 27.5 r20h[5:3]= 001 2.25 2.5 2.75 r20h[5:3]= 010 9 10 11 r20h[5:3]= 011 36 40 44 r20h[5:3]= 100 144 160 176 r20h[5:3]= 101 576 640 704 r20h[5:3]= 110 1152 1280 1408 r20h[5:3]= 111 2304 2560 2816 µs ms TEMPERATURE MEASUREMENTS Internal Sensor Measurement Error (Note 2) ±3 °C External Remote Diode Temperature Measurement Error (Note 2) ±5 °C 0.5 °C Temperature Measurement Resolution Temperature Measurement Noise 0.1 °C External Diode Drive High Internal sensor 84 µA External Diode Drive Low 6 µA Diode Drive Current Ratio 14 DXN_ Impedance to GND 1.8 kΩ 0.1 °C/V Power-Supply Rejection PSR Internal sensor, DC condition CURRENT SENSE CS+ Input Voltage Range Input Bias Current VCS+ 3 VCS+ = VCS- 14 25 ICS- VCS- = VCS+ 3 8 25 28.5 A = 48 Primary Current-Sense Differential Thresholds Primary Current-Sense Threshold Secondary Overcurrent Threshold Timeout 4 28 ICS+ VCSTH CSHYS VCS+ - VCS- 21.5 A = 24 45 50 55 A = 12 92 100 108 A=6 190 200 210 V µA mV Percent of VCSTH 0.5 % r5Ch[1:0] = 00 50 µs r5Ch[1:0] = 01 3.6 4 4.4 r5Ch[1:0] = 10 14.4 16 17.6 r5Ch[1:0] = 11 57.6 64 70.4 _______________________________________________________________________________________ ms EEPROM-Based System Monitors with Nonvolatile Fault Memory (VCC = 2.9V to 14V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL Current-Sense Analog Input Range CONDITIONS VCS+ - VCS- ADC Current-Sense Measurement Accuracy A=6 MIN TYP 232 A = 12 116 A = 24 58 A = 48 29 -4 ±0.2 +4 VSENSE = 50mV, (A = 6, 12 only) -10 ±1.2 +10 VSENSE = 25mV ±2 VSENSE = 10mV ±10 Common-Mode Rejection Ratio CMRRCS Power-Supply Rejection Ratio PSRRCS OVERC Output Leakage Current IOVERCLKG OVERC Output Low Voltage VOLOVERC OVERC Propagation Delay tOVERC -3 VCS+ > 4V UNITS mV VSENSE = 150mV, (A = 6 only) VSENSE = 20mV to 100mV, VCS+ = 12V, A = 6 Gain Accuracy MAX +3 % % 80 dB 80 dB 1 IOUT = 3mA VSENSE - VCSTH > 10% x VCSTH µA 0.4 V 5 µs SMBus INTERFACE (SCL, SDA) Logic-Input Low Voltage VIL Input voltage falling Logic-Input High Voltage VIH Input voltage rising 2.0 GND or 5.5V (VCC = 5.5V) VSCL, VSDA -1 Input Leakage Current Output Low Voltage VOL Input Capacitance CIN 0.8 V V +1 ISINK = 3mA 0.4 5 µA V pF ALERT, FAULT_, AND GPIO_ OUTPUTS ALERT, FAULT_, and GPIO_ Output Low Voltage ISINK = 3mA ALERT, FAULT_, and GPIO_ Leakage Current V ALERT, V FAULT, VGPIO_ = 5.5V or GND -1 0.4 V +1 µA GPIO_ (INPUT) Logic-Low Voltage GPIO_ voltage falling Logic-High Voltage GPIO_ voltage rising 0.8 2.0 V V SMBus ADDRESS (A0 and A1) Address Logic-Low 0.4 Address Logic-High 1.4 V V High-Impedance Leakage Current Maximum current to achieve highimpedance logic level -1 +1 µA Input Leakage Current 0 to 3V, VCC = 3V -12 +12 µA _______________________________________________________________________________________ 5 MAX16031/MAX16032 ELECTRICAL CHARACTERISTICS (continued) MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory ELECTRICAL CHARACTERISTICS (continued) (VCC = 2.9V to 14V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz SMBus TIMING (see Figure 1) Serial-Clock Frequency fSCL Bus Free Time Between STOP and START Conditions tBUF 1.3 µs START Condition Setup Time tSU:STA 0.6 µs START Condition Hold Time tHD:STA 0.6 µs STOP Condition Setup Time tSU:STO 0.6 µs Clock Low Period tLOW 1.3 µs Clock High Period tHIGH 0.6 µs Data Setup Time tSU:DAT Output Fall Time tOF 100 Data Hold Time tHD:DAT From 50% SCL falling to SDA change 0.3 tTIMEOUT SCL time low for reset 25 Minimum Pulse Width Ignored SMBus Timeout ns CBUS = 10pF to 400pF 250 ns 0.9 µs 35 ms 0.4 V 30 ns JTAG INTERFACE (see Figure 2) TDI, TMS, TCK Logic-Low Input Voltage VIL Input voltage falling TDI, TMS, TCK Logic-High Input Voltage VIH Input voltage rising TDO Logic-Output Low Voltage VOL ISINK = 4mA TDO Logic-Output High Voltage VOH ISOURCE = 1mA 2.2 TDO high impedance -10 Pullup to VDBP 6.5 TDO Leakage Current TDI, TMS Pullup Resistors RJPU I/O Capacitance CI/O TCK Clock Period TCK High/Low Time 2.2 V V +10 µA 16 kΩ V 10 50 t1 t2, t3 0.4 pF 1000 (Note 3) 60 500 ns ns TCK to TMS, TDI Setup Time t4 15 ns TCK to TMS, TDI Hold Time t5 35 ns TCK to TDO Delay t6 500 ns TCK to TDO High-Impedance Delay t7 500 ns tD-PO 4 ms 11 ms MISCELLANEOUS Power-On Delay Single-Byte EEPROM Write Cycle Delay (Note 4) Note 1: Limits to -40°C are guaranteed by design. Note 2: Guaranteed by design. Note 3: TCK stops either high or low. Note 4: An additional cycle is required when writing to configuration memory for the first time. 6 _______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 SDA tBUF tSU:DAT tSU:STA tHD:DAT tLOW tHD:STA tSU:STO SCL tHIGH tHD:STA tR tF START CONDITION STOP CONDITION REPEATED START CONDITION START CONDITION Figure 1. SMBus Interface Timing Diagram t1 t2 t3 TCK t4 t5 TDI, TMS t6 t7 TDO TRI-STATE ONLY Figure 2. JTAG Interface Timing Diagram _______________________________________________________________________________________ 7 Typical Operating Characteristics (Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted.) NORMALIZED IN_ THRESHOLD vs. TEMPERATURE TA = -40°C 1.5 1.0 1.01 1.00 0.99 0.5 0.98 0 0.97 MAX16031 toc03 1.02 1.05 NORMALIZED RESET TIMEOUT PERIOD ICC (mA) 2.0 NORMALIZED RESET TIMEOUT PERIOD vs. TEMPERATURE MAX16031 toc02 TA = +85°C TA = +25°C 2.5 1.03 NORMALIZED IN_ THRESHOLD 3.0 MAX16031 toc01 VCC SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE 1.04 1.03 1.02 1.01 1.00 0.99 0.98 0.97 0.96 2 4 6 8 10 12 0.95 -40 14 -15 10 35 85 60 -40 -15 10 35 60 VCC (V) TEMPERATURE (°C) TEMPERATURE (°C) OUTPUT VOLTAGE LOW vs. SINK CURRENT ADC INTEGRAL NONLINEARITY vs. INPUT VOLTAGE ADC DIFFERENTIAL NONLINEARITY vs. INPUT VOLTAGE 350 0.40 0.30 300 150 ADC DNL (LSB) ADC INL (LSB) 200 0.10 0 -0.10 -0.20 100 0.10 0.05 0.20 250 0.15 85 MAX16031 toc06 0.50 MAX16031 toc04 400 MAX16031 toc05 0 OUTPUT VOLTAGE LOW (mV) 0 -0.05 -0.10 -0.30 50 -0.15 -0.40 0 -0.20 -0.50 0 1 2 3 4 5 6 7 0 INPUT VOLTAGE (DIGITAL CODE) REFERENCE VOLTAGE vs. TEMPERATURE ADC HALF-SCALE VOLTAGE INPUT 1.48 REFERENCE VOLTAGE (V) 800 700 600 500 400 300 1.46 1.44 1.42 1.40 1.38 1.36 200 1.34 100 1.32 0 MAX16031 toc08 1.50 MAX16031 toc07 1000 1.30 507 508 509 510 511 ADC OUTPUT CODE 8 128 256 384 512 640 768 896 1024 INPUT VOLTAGE (DIGITAL CODE) NOISE HISTOGRAM 900 0 128 256 384 512 640 768 896 1024 SINK CURRENT (mA) COUNTS (THOUSANDS) MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory 512 513 -40 -15 10 35 60 TEMPERATURE (°C) _______________________________________________________________________________________ 85 EEPROM-Based System Monitors with Nonvolatile Fault Memory 0 -1 4 3 2 1 0 -1 -2 TEMPERATURE ERROR (°C) 1 MAX16031 toc10 2 5 TEMPERATURE ERROR (°C) MAX16031 toc09 -3 -2 -4 -3 -5 -10 15 40 90 65 0 15 30 45 60 75 100 10 CURRENT-SENSE ACCURACY vs. VSENSE CURRENT-SENSE PRIMARY THRESHOLD vs. VSENSE OVERDRIVE -4 -5 -6 -7 -8 MAX16031 toc13 MAX16031 toc12 -3 8 6 4 2 0 -2 -9 -4 -10 2 3 4 5 6 7 DXP-DXN CAPACITANCE (nF) 8 9 CURRENT-SENSE PRIMARY THRESHOLD (µs) TEMPERATURE ERROR vs. DXP-DXN CAPACITANCE -2 1 1 90 105 LEAKAGE RESISTANCE (MΩ) 0 0 PATH = DXP TO VCC (+5V) REMOTE DIODE TEMPERATURE (°C) -1 TEMPERATURE ERROR (°C) -30 -15 PATH = DXP TO GND TEMPERATURE (°C) CURRENT-SENSE ACCURACY (%) -35 15 10 5 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 2.0 MAX16031 toc14 TEMP SENSOR ACCURACY (°C) 3 TEMPERATURE ERROR vs. LEAKAGE RESISTANCE TEMPERATURE ERROR vs. REMOTE DIODE TEMPERATURE MAX16031 toc11 INTERNAL TEMPERATURE SENSOR ACCURACY vs. TEMPERATURE 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 23 46 69 92 115 138 161 184 207 230 VSENSE (mV) 0 20 40 60 80 100 VSENSE OVERDRIVE (mV) _______________________________________________________________________________________ 9 MAX16031/MAX16032 Typical Operating Characteristics (continued) (Typical values are at VCC = 3.3V, TA = +25°C, unless otherwise noted.) MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory Pin Description PIN MAX16031 1 2 MAX16032 1 2 NAME FUNCTION IN2 Supply Monitor Input 2. IN2 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN1 and IN2 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. IN3 Supply Monitor Input 3. IN3 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN3 and IN4 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. 3 3 IN4 Supply Monitor Input 4. IN4 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN3 and IN4 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. 4–7, 30, 31, 32, 39, 40, 47 4–7, 11, 12, 23, 30, 31, 32, 39, 40–44, 47 N.C. No Connection. Leave unconnected. Do not use. 8, 13, 35 8, 13, 35 GND 9 10 11 10 9 10 — Ground. Connect all GND pins together. IN5 Supply Monitor Input 5. IN5 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN5 and IN6 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. IN6 Supply Monitor Input 6. IN6 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN5 and IN6 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. IN7 Supply Monitor Input 7. IN7 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN7 and IN8 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. Supply Monitor Input 8. IN8 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN7 and IN8 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. 12 — IN8 14 14 GPIO1 Configurable General-Purpose Input/Output 1 15 15 GPIO2 Configurable General-Purpose Input/Output 2 16 16 RBP ADC Reference Bypass. RBP is an internally generated 1.4V reference for the ADC. Bypass RBP to GND with a 2.2µF capacitor. Do not use RBP to power any additional circuitry. 17 17 SDA SMBus Serial-Data, Open-Drain Input/Output 18 18 SCL SMBus Serial-Clock Input 19 19 A0 SMBus Address Input 0. Connect to DBP, GND, or leave unconnected to select the desired device address. 20 20 A1 SMBus Address Input 1. Connect to DBP, GND, or leave unconnected to select the desired device address. ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory PIN MAX16031 MAX16032 NAME FUNCTION 21 21 ALERT SMBus Alert Open-Drain Output. ALERT follows the SMBALERT# signal functionality described in Appendix A of the SMBus 2.0 Specification. ALERT asserts when the device detects a fault, thereby interrupting the host processor to query which device on the serial bus detected faults. 22 22 OVERT Overtemperature, Open-Drain Output. OVERT asserts when an overtemperature condition is detected. 23 — OVERC Overcurrent, Open-Drain Output. OVERC asserts when the primary overcurrent threshold is exceeded. 24 24 FAULT2 Configurable Open-Drain Fault Output 2 25 25 FAULT1 Configurable Open-Drain Fault Output 1 26 26 RESET 27 27 TMS JTAG Test Mode Select Input. Internally pulled up to VDBP with a 10kΩ resistor. 28 28 TCK JTAG Test Clock Input Configurable Open-Drain Reset Output 29 29 TDI JTAG Test Data Input. Internally pulled up to VDBP with a 10kΩ resistor. 33 33 TDO JTAG Test Data Output 34 34 DBP Internal Digital Voltage Regulator Output. Connect a 1µF bypass capacitor from DBP to GND. Do not use DBP to power external circuitry. 36 36 ABP Internal Analog Voltage Regulator Output. Connect a 1µF bypass capacitor from ABP to GND. Do not use ABP to power external circuitry. 37, 38 37, 38 VCC Device Power Supply. Bypass VCC to GND with a 1µF capacitor. 41 — CS- Current-Sense Negative Input. Must be biased between 3V to 28V for proper operation. 42 — CS+ Current-Sense Positive Input. Must be biased between 3V to 28V for proper operation. 43 — DXN2 Remote Diode 2 Negative Input. If remote sensing is not used, connect DXP2 to DXN2. 44 — DXP2 Remote Diode 2 Positive Input. If remote sensing is not used, connect DXP2 to DXN2. 45 45 DXN1 Remote Diode 1 Negative Input. If remote sensing is not used, connect DXP1 to DXN1. 46 46 DXP1 Remote Diode 1 Positive Input. If remote sensing is not used, connect DXP1 to DXN1. 48 48 IN1 Supply Monitor Input 1. IN1 is internally sampled by the ADC. It is configurable for unipolar/ bipolar and single-ended/pseudo-differential. In pseudo-differential mode, IN1 and IN2 form the + and - of the differential pair. Each input must stay within the specified ADC IN_ voltage range. — — EP Exposed Pad. Connect EP to ground. EP is internally connected to GND. Do not use as the main ground connection. ______________________________________________________________________________________ 11 MAX16031/MAX16032 Pin Description (continued) EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Functional Diagram VCC INTERNAL TEMPERATURE SENSOR CIRCUITRY OSCILLATOR IN1 10-BIT ADC ANALOG REGULATOR ABP DIGITAL REGULATOR DBP 1.4V INTERNAL REFERENCE RBP INPUT RANGE SELECTION FAULT1 REGISTERS IN2 INPUT RANGE SELECTION IN3 INPUT RANGE SELECTION IN4 INPUT RANGE SELECTION IN5 INPUT RANGE SELECTION IN6 INPUT RANGE SELECTION *IN7 INPUT RANGE SELECTION *IN8 INPUT RANGE SELECTION FAULT COMPARATORS FAULT2 OVERT RESET MULTIPLEXER GPIO1 GPIO2 SDA SCL EEPROM SMBus SERIAL INTERFACE ALERT A0 A1 DXP1 DXN1 *DXP2 EXTERNAL TEMPERATURE SENSOR CIRCUITRY TMS *DXN2 *CS+ *CS- CURRENT-SENSE AMPLIFIER/ COMPARATOR MAX16031/ MAX16032 JTAG SERIAL INTERFACE TCK TDI TDO OVERC *MAX16031 ONLY 12 ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory REGISTER ADDRESS EEPROM MEMORY ADDRESS READ/ WRITE 00h — R IN1 ADC Result Register (MSB) 01h — R IN1 ADC Result Register (LSB) 02h — R IN2 ADC Result Register (MSB) 03h — R IN2 ADC Result Register (LSB) 04h — R IN3 ADC Result Register (MSB) 05h — R IN3 ADC Result Register (LSB) 06h — R IN4 ADC Result Register (MSB) 07h — R IN4 ADC Result Register (LSB) 08h — R IN5 ADC Result Register (MSB) MAX16031/MAX16032 Table 1. Address Map DESCRIPTION 09h — R IN5 ADC Result Register (LSB) 0Ah — R IN6 ADC Result Register (MSB) 0Bh — R IN6 ADC Result Register (LSB) 0Ch — R IN7 ADC Result Register (MSB)* 0Dh — R IN7 ADC Result Register (LSB)* 0Eh — R IN8 ADC Result Register (MSB)* 0Fh — R IN8 ADC Result Register (LSB)* 10h — R Internal Temperature Sensor ADC Result Register (MSB) 11h — R Internal Temperature Sensor ADC Result Register (LSB) 12h — R Remote Temperature Sensor 1 ADC Result Register (MSB) 13h — R Remote Temperature Sensor 1 ADC Result Register (LSB) 14h — R Remote Temperature Sensor 2 ADC Result Register (MSB) 15h — R Remote Temperature Sensor 2 ADC Result Register (LSB) 16h — R Current-Sense ADC Result Register 17h 97h R/W Voltage Monitoring Input ADC Range Selection (IN1–IN4) 18h 98h R/W Voltage Monitoring Input ADC Range Selection (IN5–IN8) 19h 99h R/W Current-Sense Gain/Primary Threshold and Remote Temperature Sensor 1 Gain Trim 1Ah 9Ah R/W Voltage Monitoring Input Enable R/W Internal/Remote Temperature Sensor, Current Sense, and ALERT Enables and Remote Temperature Sensor 1 Offset Trim 1Bh 9Bh 1Ch 9Ch R/W Voltage Monitoring Input Single-Ended/Differential and Unipolar/Bipolar Selection 1Dh 9Dh R/W FAULT1 Dependency Selection 1Eh 9Eh R/W FAULT2 Dependency Selection 1Fh 9Fh R/W OVERT Dependency Selection 20h A0h R/W RESET Dependency and Timeout Selection 21h A1h R/W RESET IN1–IN8 Dependency Selection 22h A2h R/W GPIO1 Configuration 23h A3h R/W GPIO1 Dependency Selection 24h A4h R/W GPIO2 Configuration ______________________________________________________________________________________ 13 MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory Table 1. Address Map (continued) REGISTER ADDRESS EEPROM MEMORY ADDRESS READ/ WRITE 25h A5h R/W GPIO2 Dependency Selection 26h A6h R/W IN1 Primary Undervoltage Threshold 27h A7h R/W IN1 Primary Overvoltage Threshold 28h A8h R/W IN1 Secondary Undervoltage Threshold 14 DESCRIPTION 29h A9h R/W IN1 Secondary Overvoltage Threshold 2Ah AAh R/W IN2 Primary Undervoltage Threshold 2Bh ABh R/W IN2 Primary Overvoltage Threshold 2Ch ACh R/W IN2 Secondary Undervoltage Threshold 2Dh ADh R/W IN2 Secondary Overvoltage Threshold 2Eh AEh R/W IN3 Primary Undervoltage Threshold 2Fh AFh R/W IN3 Primary Overvoltage Threshold 30h B0h R/W IN3 Secondary Undervoltage Threshold 31h B1h R/W IN3 Secondary Overvoltage Threshold 32h B2h R/W IN4 Primary Undervoltage Threshold 33h B3h R/W IN4 Primary Overvoltage Threshold 34h B4h R/W IN4 Secondary Undervoltage Threshold 35h B5h R/W IN4 Secondary Overvoltage Threshold 36h B6h R/W IN5 Primary Undervoltage Threshold 37h B7h R/W IN5 Primary Overvoltage Threshold 38h B8h R/W IN5 Secondary Undervoltage Threshold 39h B9h R/W IN5 Secondary Overvoltage Threshold 3Ah BAh R/W IN6 Primary Undervoltage Threshold 3Bh BBh R/W IN6 Primary Overvoltage Threshold 3Ch BCh R/W IN6 Secondary Undervoltage Threshold 3Dh BDh R/W IN6 Secondary Overvoltage Threshold 3Eh BEh R/W IN7 Primary Undervoltage Threshold* 3Fh BFh R/W IN7 Primary Overvoltage Threshold* 40h C0h R/W IN7 Secondary Undervoltage Threshold* 41h C1h R/W IN7 Secondary Overvoltage Threshold* 42h C2h R/W IN8 Primary Undervoltage Threshold* 43h C3h R/W IN8 Primary Overvoltage Threshold* 44h C4h R/W IN8 Secondary Undervoltage Threshold* 45h C5h R/W IN8 Secondary Overvoltage Threshold* 46h C6h R/W Internal Temperature Sensor Primary Overtemperature Threshold (MSB) 47h C7h R/W Internal Temperature Sensor Secondary Overtemperature Threshold (MSB) 48h C8h R/W Remote Temperature Sensor 1 Primary Overtemperature Threshold 49h C9h R/W Remote Temperature Sensor 1 Secondary Overtemperature Threshold 4Ah CAh R/W Remote Temperature Sensor 2 Primary Overtemperature Threshold ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory REGISTER ADDRESS EEPROM MEMORY ADDRESS READ/ WRITE 4Bh CBh R/W 4Ch CCh R/W Overcurrent Secondary Threshold DESCRIPTION Remote Temperature Sensor 2 Secondary Overtemperature Threshold 4Dh CDh R/W Remote Temperature Sensor Primary/Secondary Overtemperature Threshold (LSBs). External Temperature Sensor 2 Offset Trim 4Eh CEh R/W Remote Temperature Sensor 1/2 Primary/Secondary Overtemperature Threshold (LSBs) 4Fh CFh R/W Remote Temperature Sensor 2 Gain Trim 50h D0h R/W Remote Temperature Sensor Short/Open Status 51h D1h R/W IN1–IN8 Primary Threshold Fault Status 52h D2h R/W IN1–IN8 Secondary Threshold Fault Status 53h D3h R/W Temperature/Current Threshold Fault Status 54h D4h R/W Remote Temperature Sensor Short/Open Fault Mask 55h D5h R/W IN1–IN8 Primary Threshold Fault Mask 56h D6h R/W IN1–IN8 Secondary Threshold Fault Mask 57h D7h R/W Temperature/Current Threshold Fault Mask 58h D8h R/W IN1–IN8 Primary Undervoltage Faults Triggering Fault EEPROM 59h D9h R/W IN1–IN8 Primary Overvoltage Faults Triggering Fault EEPROM 5Ah DAh R/W Temperature/Current Faults Triggering Fault EEPROM 5Bh DBh R/W Temperature Filter Selection and Postboot Fault Mask Time 5Ch DCh R/W Threshold Fault Options and Overcurrent Fault Timeout 5Dh DDh — 5Eh DEh R/W Customer Firmware Version 5Fh DFh R/W EEPROM and Configuration Lock 60h–7Fh E0h–FFh — — 80h R IN1–IN8 Primary Threshold Fault Status at Time of Fault — 81h R IN1–IN8 Secondary Threshold Fault Status at Time of Fault — 82h R Temperature/Current Threshold Fault Status at Time of Fault — 83h R IN1 Conversion Result at Time of Fault — 84h R IN2 Conversion Result at Time of Fault — 85h R IN3 Conversion Result at Time of Fault — 86h R IN4 Conversion Result at Time of Fault — 87h R IN5 Conversion Result at Time of Fault — 88h R IN6 Conversion Result at Time of Fault — 89h R IN7 Conversion Result at Time of Fault* — 8Ah R IN8 Conversion Result at Time of Fault* — 8Bh R Internal Temperature Sensor Conversion Result at Time of Fault — 8Ch R Remote Temperature Sensor 1 Conversion Result at Time of Fault — 8Dh R Remote Temperature Sensor 2 Conversion Result at Time of Fault* — 8Eh R Current-Sense Conversion Result at Time of Fault* Reserved Reserved *MAX16031 only. ______________________________________________________________________________________ 15 MAX16031/MAX16032 Table 1. Address Map (continued) MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory Detailed Description Getting Started The MAX16031/MAX16032 contain both I2C/SMBus and JTAG serial interfaces for accessing registers and EEPROM. Use only one interface at any given time. For more information on how to access the internal memory through these interfaces, see the I2C/SMBus-Compatible Serial Interface and JTAG Serial Interface sections. This data sheet uses a specific convention for referring to bits within a particular address location. As an example, r15h[3:0] refers to bits 3 through 0 in register with address 15 hexadecimal. The factory-default values at power-on reset (POR) for all EEPROM locations are zeros. POR occurs when VCC reaches the undervoltage lockout (UVLO) of 2.8V. At POR, the device begins a boot-up sequence. During the boot-up sequence, all monitored inputs are masked from initiating faults and EEPROM contents are copied to the respective register locations. The boot-up sequence takes up to 1.81ms. Monitoring is disabled for up to 16s past the boot-up sequence by programming r5Bh[3:0] (see the Miscellaneous Settings section). RESET is low during boot-up and remains low after boot-up for its programmed timeout period after all monitored channels are within their respective thresholds. The MAX16031/MAX16032 monitor up to eight voltages, up to one current, and up to three temperatures. After boot-up, an internal multiplexer cycles through each input. At each multiplexer stop, the 10-bit ADC converts the analog parameter to a digital result and stores the result in a register. Each time the multiplexer completes a cycle, internal logic compares the conversion results to the thresholds stored in memory. When a conversion vio- lates a programmed threshold, the conversion is configured to generate a fault. Logic outputs are programmed to depend on many combinations of faults. Additionally, faults are programmed to trigger a fault log, whereby all fault information is automatically written to EEPROM. Voltage Monitoring The MAX16031 provides eight inputs, IN1–IN8, for voltage monitoring. The MAX16032 provides six inputs, IN1–IN6, for voltage monitoring. Each input voltage range is programmable through r17h[7:0] and r18h[7:0] (see Table 2). Voltage monitoring for each input is enabled through r1Ah[7:0] (see Table 2). There are four programmable thresholds per voltage monitor input: primary undervoltage, secondary undervoltage, primary overvoltage, and secondary overvoltage. All voltage thresholds are 8 bits wide. Only the 8 most significant bits of the conversion result are compared to the thresholds. See the Miscellaneous Settings section to set the amount of hysteresis for the thresholds. See Table 1 for an address map of all voltage monitor input threshold registers. ADC inputs are configurable for two different modes: pseudo-differential and single-ended (see Table 3). In pseudo-differential mode, two inputs make up a differential pair. Psuedo-differential conversions are performed by taking a single-ended conversion at each input of a differential pair and then subtracting the results. The pseudo-differential mode is selectable for unipolar or bipolar operation. Unipolar differential operation allows only positive polarities of differential voltages. Bipolar differential operation allows negative and positive polarities of differential voltages. Bipolar conversions are in two’s complement format. For example, Table 2. Input Monitor Ranges and Enables REGISTER ADDRESS 17h 16 EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION [1:0] IN1 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved [3:2] IN2 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved [5:4] IN3 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved [7:6] IN4 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved 97h ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 2. Input Monitor Ranges and Enables (continued) REGISTER ADDRESS 18h 1Ah EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION [1:0] IN5 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved [3:2] IN6 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved [5:4] IN7 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved [7:6] IN8 Voltage Range Selection: 00 = 5.6V, 01 = 2.8V 10 = 1.4V, 11 = Reserved 98h [0] IN1 Monitoring Enable: 0 = IN1 monitoring disabled 1 = IN1 monitoring enabled [1] IN2 Monitoring Enable: 0 = IN2 monitoring disabled 1 = IN2 monitoring enabled [2] IN3 Monitoring Enable: 0 = IN3 monitoring disabled 1 = IN3 monitoring enabled [3] IN4 Monitoring Enable: 0 = IN4 monitoring disabled 1 = IN4 monitoring enabled [4] IN5 Monitoring Enable: 0 = IN5 monitoring disabled 1 = IN5 monitoring enabled [5] IN6 Monitoring Enable: 0 = IN6 monitoring disabled 1 = IN6 monitoring enabled [6] IN7 Monitoring Enable: 0 = IN7 monitoring disabled 1 = IN7 monitoring enabled [7] IN8 Monitoring Enable: 0 = IN8 monitoring disabled 1 = IN8 monitoring enabled 9Ah ______________________________________________________________________________________ 17 MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory a -1V differential input (range of 5.6V) gives a decimal code of -183, which is 1101001001 in two’s complement binary form. In single-ended mode, conversions are performed between a single input and ground. When single-ended mode is selected, conversions are always unipolar regardless of r1Ch[7:4]. The singleended and pseudo-differential ADC mode equations are shown below. Unipolar single-ended mode: ⎛ VIN− ⎞ X ADC = INT ⎜ × 1024⎟ ⎝ VRANGE ⎠ where XADC is the resulting code in decimal, VIN- is the voltage at a voltage monitoring input, and VRANGE is the selected range programmed in r17h and r18h. Bipolar/unipolar pseudo-differential mode: ⎛ VIN+ ⎞ ⎞ ⎛ VIN− X ADC = INT ⎜ × 1024⎟ − INT ⎜ × 1024 ⎝ VRANGE ⎠ ⎠ ⎝ VRANGE where XADC is the resulting code in decimal, VIN+ is the voltage at a positive input of a differential voltage monitoring input pair, VIN- is the voltage at a negative input of a differential voltage monitoring input pair, and VRANGE is the selected ADC IN_ voltage range programmed in r17h and r18h. Table 3. IN1–IN8 ADC Input Mode Selection REGISTER ADDRESS 1Ch 18 EEPROM MEMORY ADDRESS BIT RANGE DESCRIPTION [0] IN1/IN2 Single-Ended/Pseudo-Differential: 0 = IN1 and IN2 conversions are single-ended. 1 = IN1 and IN2 conversions are pseudo-differential (IN1 to IN2). [1] IN3/IN4 Single-Ended/Pseudo-Differential: 0 = IN3 and IN4 conversions are single-ended. 1 = IN3 and IN4 conversions are pseudo-differential (IN3 to IN4). [2] IN5/IN6 Single-Ended/Pseudo-Differential: 0 = IN5 and IN6 conversions are single-ended. 1 = IN5 and IN6 conversions are pseudo-differential (IN5 to IN6). [3] IN7/IN8 Single-Ended/Pseudo-Differential: 0 = IN7 and IN8 conversions are single-ended. 1 = IN7 and IN8 conversions are pseudo-differential (IN7 to IN8). [4] IN1/IN2 Unipolar/Bipolar: 0 = IN1 and IN2 conversions are unipolar. 1 = IN1 and IN2 conversions are bipolar (two’s complement). [5] IN3/IN4 Unipolar/Bipolar: 0 = IN3 and IN4 conversions are unipolar. 1 = IN3 and IN4 conversions are bipolar (two’s complement). [6] IN5/IN6 Unipolar/Bipolar: 0 = IN5 and IN6 conversions are unipolar. 1 = IN5 and IN6 conversions are bipolar (two’s complement). [7] IN7/IN8 Unipolar/Bipolar: 0 = IN7 and IN8 conversions are unipolar. 1 = IN7 and IN8 conversions are bipolar (two’s complement). 9Ch ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory I TH = VCSTH RSENSE where ITH is the current threshold to be set, VCSTH is the threshold set by r19h[1:0], and RSENSE is the value VMON CS+ CS- RSENSE - TO ADC MUX of the sense resistor. See Table 4 for a description of r19h. The ADC output for a current-sense conversion is: ( V × AV X ADC = SENSE × 28 VRBP − ) 1 where XADC is the 8-bit decimal ADC result, VSENSE is VCS+ - VCS-, AV is the current-sense voltage gain set by r19h[1:0], and VRBP is the reference voltage at RBP (1.4V typical). OVERC is latched when the primary overcurrent threshold is exceeded by programming r5Ch[4]. The latch is cleared by writing a ‘1’ to r53h[6]. OVERC depends only on the primary overcurrent threshold. Other fault outputs are programmed to depend on the secondary overcurrent threshold. The secondary overcurrent threshold is implemented through ADC conversions and digital comparisons. The secondary overcurrent threshold contains programmable time delay options located in r5Ch[1:0]. Primary and secondary currentsense faults are enabled/disabled through r1Bh[3]. *AV + Temperature Monitoring VL The MAX16031 provides two sets of remote diode inputs, DXP1/DXN1 and DXP2/DXN2, and one internal temperature sensor. The MAX16032 provides one set, DXP1/DXN1, and one internal temperature sensor. Calibration registers provide adjustments for gain and offset to accommodate different types of remote diodes. The internal temperature sensor circuitry is factory trimmed. In addition to offset/gain trimming, a programmable lowpass filter is provided. See Figure 4 for the block diagram of the temperature sensor circuitry. The remote diode is actually a diode-connected transistor. See Application Notes AN1057 and AN1944 for information on error budget and several transistor manufacturers. MAX16031 LOAD + OVERC + - *VCSTH *ADJUSTABLE BY r19h [1:0] Figure 3. Current-Sense Block Diagram Table 4. Overcurrent Primary Threshold and Remote Temperature Sense Gain Trim REGISTER ADDRESS 19h 4Fh EEPROM MEMORY ADDRESS 99h CFh BIT RANGE DESCRIPTION [1:0] Overcurrent Primary Threshold and Current-Sense Gain Setting: 00 = 200mV threshold, AV = 6V/V 01 = 100mV threshold, AV = 12V/V 10 = 50mV threshold, AV = 24V/V 11 = 25mV threshold, AV = 48V/V [7:2] Remote Temperature Sensor 1 Gain Trim. Note bit 6 is inverted. [5:0] Remote Temperature Sensor 1 Gain Trim [7:6] Not used ______________________________________________________________________________________ 19 MAX16031/MAX16032 Current Monitoring The MAX16031 provides current-sense inputs CS+/CSand a current-sense amplifier for current monitoring (see Figure 3). There are two programmable currentsense thresholds: primary overcurrent and secondary overcurrent. For fast fault detection, the primary overcurrent threshold is implemented with an analog comparator connected to the OVERC output. The primary threshold equation is: MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory Table 5. Temperature Data Format ABP IHIGH ILOW DXP_ - TO ADC MUX + VBIAS ~ 100mV DXN_ IBIAS ABP TEMPERATURE (°C) DIGITAL CODE +128 1100000000 +125 1011111010 +100 1011010000 +25.5 1000110011 0 1000000000 -10 0111101100 -75 0101101010 -100 0100111000 -128 0100000000 Diode fault 0000000000 Reading ADC Results Figure 4. Remote Temperature Sensor Amplifier Circuitry The ADC converts the internal sensor and remote sensor amplifier outputs. Each time the ADC converts all enabled parameters, the temperature conversions are compared to the temperature threshold registers (r46h to r4Bh and r4Dh). Unlike the voltage input comparators, the temperature threshold comparators are 10 bits wide. OVERT is the designated output for temperature faults, although other outputs are programmed to depend on temperature faults as well. See the Programmable Inputs/Outputs section for more information on programming output dependencies. See the Faults section for more information on setting temperature fault thresholds. The remote temperature sensor amplifier detects a short or open between DXP_ and DXN_. The detection of these events is programmed to cause a fault. Temperature thresholds and conversions are in a two’s complement temperature format, where 1 LSB corresponds to 0.5°C. The data format for temperature conversions is illustrated in Table 5. Offset and gain errors for remote temperature sensor measurements are user-trimmed through gain registers r19h[7:2]/r4Fh[5:0] and offset registers r1Bh[7:5]/r4D[6:4], as shown in Tables 4 and 6. The gain value trims the high (56µA) drive current source to compensate for the n-factor of the remote diode. The offset value is multiplied by 4 and added to the conversion result numerically. The MAX16031/MAX16032 contain an internal lowpass filter at DXN_ and DXP_ to reduce noise. See the Miscellaneous Settings section for more information on programming the filter cutoff frequency. 20 ADC conversion results are read from the ADC conversion registers through the I2C/SMBus-compatible or JTAG interfaces (see Table 7). These registers are also used for fault threshold comparison. Voltage monitoring thresholds are compared with only the first 8 MSBs of the conversion results. Programmable Inputs/Outputs The MAX16031 provides two general fault outputs, FAULT1 and FAULT2, one reset output RESET, one temperature fault output OVERT, one current fault output OVERC, two general-purpose inputs/outputs GPIO1 and GPIO2, and one SMBALERT#-compatible output ALERT. The MAX16032 provides the same except OVERC. All outputs are open drain and require pullup resistors. Fault outputs do not latch except for OVERC, which either latches or does not latch depending on the configuration bit in r5Ch. Individual fault flag bits, however, latch (see the Faults section) and must be cleared one bit at a time by writing a byte containing all zeros except for a single ‘1’ in the bit to be cleared. The general outputs, FAULT1 and FAULT2, are identical in functionality and are programmed to depend on overvoltage, undervoltage, overtemperature, and overcurrent parameters. See r1Dh and r1Eh in Table 8 for more detailed information regarding the general fault output dependencies. The reset output RESET provides many programmable output dependencies as well as reset timeouts. See r20h and r21h in Table 8 for detailed information on RESET output dependencies and timeouts. The temperature fault output OVERT indicates temperature-related faults. OVERT is programmed to depend on any primary temperature threshold and/or the remote diode open/short flags. OVERT latches low dur- ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 6. Temperature Sensor Fault Enable, Current-Sense Fault Enable, SMBALERT# Enable, and Temperature Offset Trim REGISTER ADDRESS 1Bh 4Dh EEPROM MEMORY ADDRESS BIT RANGE [0] Internal Temperature Sensor Faults Enable: 0 = Internal temperature sensor faults disabled 1 = Internal temperature sensor faults enabled [1] Remote Temperature Sensor 1 Faults Enable: 0 = Remote temperature sensor 1 faults disabled 1 = Internal temperature sensor 1 faults enabled [2] Remote Temperature Sensor 2 Faults Enable: 0 = Remote temperature sensor 2 faults disabled 1 = Remote temperature sensor 2 faults enabled [3] Current-Sense Fault Enable: 0 = Current-sense faults disabled 1 = Current-sense faults enabled [4] SMBALERT# Enable (ALERT): 0 = SMBALERT# disabled 1 = SMBALERT# enabled 9Bh CDh DESCRIPTION [7:5] Remote Temperature Sensor 1 Offset Trim: Offset = 4 × X, where X is the two’s-complement 3-bit temperature code (1 LSB = 0.5°C). Since X is multiplied by 4, the offset LSB size is 2°C, allowing a total offset adjustment of ±6°C. [1:0] Internal Temperature Sensor Primary Overtemperature Threshold LSB [3:2] Internal Temperature Sensor Secondary Overtemperature Threshold LSB [6:4] Remote Temperature Sensor 2 Offset Trim: Offset = 4 × X, where X is the two’s-complement 3-bit temperature code (1 LSB = 0.5°C). Since X is multiplied by 4, the offset LSB size is 2°C, allowing a total offset adjustment of ±6°C. [7] Not used. ing diode open/short fault conditions, and the corresponding diode open/short flags must be cleared to release the latch. See r1Fh in Table 8 for more information on OVERT output dependencies. The current fault output OVERC indicates overcurrent events. OVERC only depends on the primary analog overcurrent threshold. See the Current Monitoring section for more information about the current-sense amplifier and the primary threshold. The secondary overcurrent threshold is set digitally and is used by other outputs. The secondary threshold also has a programmable timeout option (see Miscellaneous Settings section). GPIO1 and GPIO2 are programmable as logic inputs, manual reset inputs, logic outputs, or fault dependent outputs. See r22h–r25h in Table 8 for more detailed information on GPIO1/GPIO2 functionality. GPIO1 and GPIO2 assert low when configured as a fault output. ALERT is an SMBALERT#-compatible fault interrupt output. When enabled, it is logically ANDed with outputs RESET, FAULT1, FAULT2, OVERT, OVERC, and GPIO1/GPIO2 (only if enabled as fault outputs). When any fault output is asserted, ALERT also asserts, interrupting the SMBus master to query the fault. The master needs to answer MAX16031/MAX16032 with a specific SMBus command (ARA) to retrieve the slave address of the interrupting device. See the I2C/SMBusCompatible Serial Interface section for more details. ______________________________________________________________________________________ 21 MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory Table 7. ADC Conversion Registers 22 REGISTER ADDRESS EEPROM MEMORY ADDRESS 00h — 01h — 02h — 03h — 04h — 05h — 06h — 07h — 08h — 09h — 0Ah — 0Bh — 0Ch — 0Dh — 0Eh — 0Fh — 10h — 11h — 12h — 13h — 14h — 15h — 16h — BIT RANGE DESCRIPTION [7:0] IN1 ADC Conversion Result (MSB) [1:0] IN1 ADC Conversion Result (LSB) [7:2] Reserved [7:0] IN2 ADC Conversion Result (MSB) [1:0] IN2 ADC Conversion Result (LSB) [7:2] Reserved [7:0] IN3 ADC Conversion Result (MSB) [1:0] IN3 ADC Conversion Result (LSB) [7:2] Reserved [7:0] IN4 ADC Conversion Result (MSB) [1:0] IN4 ADC Conversion Result (LSB) [7:2] Reserved [7:0] IN5 ADC Conversion Result (MSB) [1:0] IN5 ADC Conversion Result (LSB) [7:2] Reserved [7:0] IN6 ADC Conversion Result (MSB) [1:0] IN6 ADC Conversion Result (LSB) [7:2] Reserved [7:0] IN7 ADC Conversion Result (MSB) [1:0] IN7 ADC Conversion Result (LSB) [7:2] Reserved [7:0] IN8 ADC Conversion Result (MSB) [1:0] IN8 ADC Conversion Result (LSB) [7:2] Reserved [7:0] Internal Temperature Sensor ADC Conversion Result (MSB) [1:0] Internal Temperature Sensor ADC Conversion Result (LSB) [7:2] Reserved [7:0] Remote Temperature Sensor 1 ADC Conversion Result (MSB) [1:0] Remote Temperature Sensor 1 ADC Conversion Result (LSB) [7:2] Reserved [7:0] Remote Temperature Sensor 2 ADC Conversion Result (MSB) [1:0] Remote Temperature Sensor 2 ADC Conversion Result (LSB) [7:2] Reserved [7:0] Current-Sense ADC Conversion Result ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory REGISTER ADDRESS 1Dh 1Eh 1Fh EEPROM MEMORY ADDRESS 9Dh 9Eh 9Fh BIT RANGE DESCRIPTION [0] 1 = FAULT1 depends on the secondary undervoltage thresholds of all enabled IN1–IN8. [1] 1 = FAULT1 depends on the primary overvoltage thresholds of all enabled IN1–IN8. [2] 1 = FAULT1 depends on the secondary overvoltage thresholds of all enabled IN1–IN8. [3] 1 = FAULT1 depends on the secondary overtemperature threshold of the internal temperature sensor. [4] 1 = FAULT1 depends on the secondary overtemperature threshold of remote temperature sensor 1. [5] 1 = FAULT1 depends on the secondary overtemperature threshold of remote temperature sensor 2. [6] 1 = FAULT1 depends on the secondary overcurrent threshold. [7] Reserved [0] 1 = FAULT2 depends on the secondary undervoltage thresholds of all enabled IN1–IN8. [1] 1 = FAULT2 depends on the primary overvoltage thresholds of all enabled IN1–IN8. [2] 1 = FAULT2 depends on the secondary overvoltage thresholds of all enabled IN1–IN8. [3] 1 = FAULT2 depends on the secondary overtemperature threshold of the internal temperature sensor. [4] 1 = FAULT2 depends on the secondary overtemperature threshold of remote temperature sensor 1. [5] 1 = FAULT2 depends on the secondary overtemperature threshold of remote temperature sensor 2. [6] 1 = FAULT2 depends on the secondary overcurrent threshold. [7] Reserved [0] 1 = OVERT depends on the primary overtemperature threshold of the internal temperature sensor. [1] 1 = OVERT depends on the primary overtemperature threshold of the remote temperature sensor 1. [2] 1 = OVERT depends on the primary overtemperature threshold of the remote temperature sensor 2. ______________________________________________________________________________________ 23 MAX16031/MAX16032 Table 8. Output Dependencies MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory Table 8. Output Dependencies (continued) REGISTER ADDRESS 1Fh 20h 24 EEPROM MEMORY ADDRESS 9Fh BIT RANGE DESCRIPTION [3] 1 = OVERT depends on the diode short flag of remote temperature sensor 1. OVERT latches when the diode is shorted. Clear the latch by writing to r50h. [4] 1 = OVERT depends on the diode open flag of remote temperature sensor 1. OVERT latches when the diode is open. Clear the latch by writing to r50h. [5] 1 = OVERT depends on the diode short flag of remote temperature sensor 2. OVERT latches when the diode is shorted. Clear the latch by writing to r50h. [6] 1 = OVERT depends on the diode open flag of remote temperature sensor 2. OVERT latches when the diode is open. Clear the latch by writing to r50h. [7] Reserved [2:0] RESET Configuration: 000 = RESET has no dependencies; asserts during boot and boot-up timeout and then deasserts indefinitely. 001 = RESET depends on the primary undervoltage thresholds at inputs that are selected by r21h[7:0]. 010 = RESET depends on the primary overvoltage thresholds at inputs that are selected by r21h[7:0]. 011 = RESET depends on both the primary undervoltage and overvoltage thresholds at those inputs that are selected by r21h[7:0]. 100 = RESET depends on the primary undervoltage thresholds at inputs that are selected by r21h[7:0] and the internal temperature sensor primary overtemperature threshold. 101 = RESET depends on both the primary undervoltage and overvoltage thresholds at those inputs that are selected by r21h[7:0] and the internal temperature sensor primary overtemperature threshold. 110 = RESET depends on the primary undervoltage thresholds at inputs that are selected by r21h[7:0] and each internal/remote temperature sensor primary overtemperature threshold. 111 = RESET depends on both the primary undervoltage and overvoltage thresholds at those inputs that are selected by r21h[7:0] and each internal/remote temperature sensor primary overtemperature threshold. [5:3] RESET Timeout: 000 = 25µs 001 = 2.5ms 010 = 10ms 011 = 40ms 100 = 160ms 101 = 640ms 110 = 1280ms 111 = 2560ms [7:6] Reserved A0h ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory REGISTER ADDRESS 21h 22h EEPROM MEMORY ADDRESS A1h BIT RANGE DESCRIPTION [0] 1 = RESET depends on IN1 with thresholds defined by r20h[2:0]. [1] 1 = RESET depends on IN2 with thresholds defined by r20h[2:0]. [2] 1 = RESET depends on IN3 with thresholds defined by r20h[2:0]. [3] 1 = RESET depends on IN4 with thresholds defined by r20h[2:0]. [4] 1 = RESET depends on IN5 with thresholds defined by r20h[2:0]. [5] 1 = RESET depends on IN6 with thresholds defined by r20h[2:0]. [6] 1 = RESET depends on IN7 with thresholds defined by r20h[2:0]. [7] 1 = RESET depends on IN8 with thresholds defined by r20h[2:0]. [2:0] GPIO1 Output Dependencies: 000 = GPIO1 is a digital input that is read from r22h[7]. 001 = GPIO1 is a digital manual reset input that asserts RESET when asserted. The state of GPIO1 is read from r22h[7]. 010 = GPIO1 is a digital output that is written to through r22h[6]. 011 = GPIO1 is a digital fault output that depends on conditions selected by r23h[6:0]. 100 = GPIO1 is a digital output that depends on primary thresholds at the input selected by r22h[5:3]. 101 =GPIO1 is a digital output that depends on primary thresholds at the input selected by r22h[5:3] and on conditions selected by r23h[6:0]. 110 = Reserved 111 = Reserved [5:3] GPIO1 Single-Input Primary Threshold Voltage Monitor (r22h[2:0] = 100 or 101 only). GPIO1 asserts low when any primary threshold of this input is exceeded: 000 = IN1 001 = IN2 010 = IN3 011 = IN4 100 = IN5 101 = IN6 110 = IN7 111 = IN8 A2h [6] GPIO1 Output (write to this bit): 1 = GPIO1 is set high if GPIO1 is configured as an output. 0 = GPIO1 is set low if GPIO1 is configured as an output. [7] GPIO1 Input State (read from this bit): 1 = Indicates that GPIO1 is high regardless if GPIO1 is set as an output or input. 0 = Indicates that GPIO1 is low regardless if GPIO1 is set as an output or input. ______________________________________________________________________________________ 25 MAX16031/MAX16032 Table 8. Output Dependencies (continued) MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory Table 8. Output Dependencies (continued) REGISTER ADDRESS 23h 24h 26 EEPROM MEMORY ADDRESS A3h BIT RANGE DESCRIPTION [0] 1 = GPIO1 depends on the secondary undervoltage thresholds of all enabled IN1–IN8. [1] 1 = GPIO1 depends on the primary overvoltage thresholds of all enabled IN1–IN8. [2] 1 = GPIO1 depends on the secondary overvoltage thresholds of all enabled IN1–IN8. [3] 1 = GPIO1 depends on the secondary overtemperature threshold of the internal temperature sensor. [4] 1 = GPIO1 depends on the secondary overtemperature threshold of remote temperature sensor 1. [5] 1 = GPIO1 depends on the secondary overtemperature threshold of remote temperature sensor 2. [6] 1 = GPIO1 depends on the secondary overcurrent threshold. [7] Reserved [2:0] GPIO2 Output Dependencies: 000 = GPIO2 is a digital input that is read from r24h[7]. 001 = GPIO2 is a digital manual reset input that asserts RESET when asserted. The state of GPIO2 is read from r24h[7]. 010 = GPIO2 is a digital output that is written to through r24h[6]. 011 = GPIO2 is a digital fault output that depends on conditions selected by r25h[6:0]. 100 = GPIO2 is a digital output that depends on primary thresholds at the input selected by r24h[5:3]. 101 = GPIO2 is a digital output that depends on primary thresholds at the input selected by r24h[5:3] and on conditions selected by r25h[6:0]. 110 = Reserved 111 = Reserved [5:3] GPIO2 Single-Input Primary Threshold Voltage Monitor (r24h[2:0] = 100 or 101 only). GPIO2 asserts low when the primary threshold of this input is exceeded: 000 = IN1 001 = IN2 010 = IN3 011 = IN4 100 = IN5 101 = IN6 110 = IN7 111 = IN8 A4h [6] GPIO2 Output (write to this bit): 1 = GPIO2 is set high if GPIO2 is configured as an output. 0 = GPIO2 is set low if GPIO2 is configured as an output. [7] GPIO2 Input (read from this bit): 1 = Indicates that GPIO2 is high regardless if GPIO2 is set as an output or input. 0 = Indicates that GPIO2 is low regardless if GPIO2 is set as an output or input. ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory REGISTER ADDRESS 25h EEPROM MEMORY ADDRESS BIT RANGE A5h DESCRIPTION [0] 1 = GPIO2 depends on the secondary undervoltage thresholds of all enabled IN1–IN8. [1] 1 = GPIO2 depends on the primary overvoltage thresholds of all enabled IN1–IN8. [2] 1 = GPIO2 depends on the secondary overvoltage thresholds of all enabled IN1–IN8. [3] 1 = GPIO2 depends on the secondary overtemperature threshold of the internal temperature sensor. [4] 1 = GPIO2 depends on the secondary overtemperature threshold of remote temperature sensor 1. [5] 1 = GPIO2 depends on the secondary overtemperature threshold of remote temperature sensor 2. [6] 1 = GPIO2 depends on the secondary overcurrent threshold. [7] Reserved Faults The MAX16031/MAX16032 offer many configurable options for detecting and managing system faults. Fault thresholds are set in r26h–r4Eh, as shown in Table 9. Any threshold that is configured to cause a fault can be masked at any time from causing a fault by setting bits in r54h–r57h, as shown in Table 10. Fault flags indicate the fault status of a particular input. The fault flag of any monitored input in the device can be read at any time from r50h–r53h, as shown in Table 11. Clear a fault flag by writing a ‘1’ to the appropriate bit in the flag register. Table 9. Fault Thresholds REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE 26h A6h [7:0] IN1 Primary Undervoltage Threshold 27h A7h [7:0] IN1 Primary Overvoltage Threshold 28h A8h [7:0] IN1 Secondary Undervoltage Threshold 29h A9h [7:0] IN1 Secondary Overvoltage Threshold 2Ah AAh [7:0] IN2 Primary Undervoltage Threshold DESCRIPTION 2Bh ABh [7:0] IN2 Primary Overvoltage Threshold 2Ch ACh [7:0] IN2 Secondary Undervoltage Threshold 2Dh ADh [7:0] IN2 Secondary Overvoltage Threshold 2Eh AEh [7:0] IN3 Primary Undervoltage Threshold 2Fh AFh [7:0] IN3 Primary Overvoltage Threshold 30h B0h [7:0] IN3 Secondary Undervoltage Threshold 31h B1h [7:0] IN3 Secondary Overvoltage Threshold 32h B2h [7:0] IN4 Primary Undervoltage Threshold 33h B3h [7:0] IN4 Primary Overvoltage Threshold ______________________________________________________________________________________ 27 MAX16031/MAX16032 Table 8. Output Dependencies (continued) MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory Table 9. Fault Thresholds (continued) REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE 34h B4h [7:0] IN4 Secondary Undervoltage Threshold 35h B5h [7:0] IN4 Secondary Overvoltage Threshold 36h B6h [7:0] IN5 Primary Undervoltage Threshold 37h B7h [7:0] IN5 Primary Overvoltage Threshold 38h B8h [7:0] IN5 Secondary Undervoltage Threshold 39h B9h [7:0] IN5 Secondary Overvoltage Threshold 3Ah BAh [7:0] IN6 Primary Undervoltage Threshold 3Bh BBh [7:0] IN6 Primary Overvoltage Threshold 3Ch BCh [7:0] IN6 Secondary Undervoltage Threshold 3Dh BDh [7:0] IN6 Secondary Overvoltage Threshold 3Eh BEh [7:0] IN7 Primary Undervoltage Threshold 3Fh BFh [7:0] IN7 Primary Overvoltage Threshold 40h C0h [7:0] IN7 Secondary Undervoltage Threshold 41h C1h [7:0] IN7 Secondary Overvoltage Threshold 42h C2h [7:0] IN8 Primary Undervoltage Threshold 43h C3h [7:0] IN8 Primary Overvoltage Threshold 44h C4h [7:0] IN8 Secondary Undervoltage Threshold 45h C5h [7:0] IN8 Secondary Overvoltage Threshold 46h C6h [7:0] Internal Temperature Sensor Primary Overtemperature Threshold MSB (2 LSBs are in r4Dh[1:0]). 47h C7h [7:0] Internal Temperature Sensor Secondary Overtemperature Threshold MSB (2 LSBs are in r4Dh[3:2]). 48h C8h [7:0] Remote Temperature Sensor 1 Primary Overtemperature Threshold MSB (2 LSBs are in r4Eh[1:0]). 49h C9h [7:0] Remote Temperature Sensor 1 Secondary Overtemperature Threshold MSB (2 LSBs are in r4Eh[3:2]). 4Ah CAh [7:0] Remote Temperature Sensor 2 Primary Overtemperature Threshold MSB (2 LSBs are in r4Eh[5:4]). 4Bh CBh [7:0] Remote Temperature Sensor 2 Secondary Overtemperature Threshold MSB (2 LSBs are in r4Eh[7:6]). 4Ch CCh 4Dh CDh [7:0] Current-Sense Secondary Threshold [1:0] [3:2] [6:4] Internal Temperature Sensor Primary Overtemperature Threshold LSB Internal Temperature Sensor Secondary Overtemperature Threshold LSB Remote Temperature Sensor 2, Offset Trim [7] 4Eh 28 DESCRIPTION CEh Not used [1:0] Remote Temperature Sensor 1 Primary Overtemperature Threshold LSB [3:2] Remote Temperature Sensor 1 Secondary Overtemperature Threshold LSB [5:3] Remote Temperature Sensor 2 Primary Overtemperature Threshold LSB [7:6] Remote Temperature Sensor 2 Secondary Overtemperature Threshold LSB ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 10. Fault Masks REGISTER ADDRESS 54h EEPROM MEMORY ADDRESS D4h BIT RANGE [0] 1 = Short-circuit detection at remote temperature sensor 1 is masked. [1] 1 = Open-circuit detection at remote temperature sensor 1 is masked. [2] 1 = Short-circuit detection at remote temperature sensor 2 is masked. [3] 1 = Open-circuit detection at remote temperature sensor 2 is masked. [7:4] 55h 56h 57h D5h D6h D7h DESCRIPTION Not used. [0] 1 = IN1 primary overvoltage and undervoltage faults are masked. [1] 1 = IN2 primary overvoltage and undervoltage faults are masked. [2] 1 = IN3 primary overvoltage and undervoltage faults are masked. [3] 1 = IN4 primary overvoltage and undervoltage faults are masked. [4] 1 = IN5 primary overvoltage and undervoltage faults are masked. [5] 1 = IN6 primary overvoltage and undervoltage faults are masked. [6] 1 = IN7 primary overvoltage and undervoltage faults are masked. [7] 1 = IN8 primary overvoltage and undervoltage faults are masked. [0] 1 = IN1 secondary overvoltage and undervoltage faults are masked. [1] 1 = IN2 secondary overvoltage and undervoltage faults are masked. [2] 1 = IN3 secondary overvoltage and undervoltage faults are masked. [3] 1 = IN4 secondary overvoltage and undervoltage faults are masked. [4] 1 = IN5 secondary overvoltage and undervoltage faults are masked. [5] 1 = IN6 secondary overvoltage and undervoltage faults are masked. [6] 1 = IN7 secondary overvoltage and undervoltage faults are masked. [7] 1 = IN1 secondary overvoltage and undervoltage faults are masked. [0] 1 = Internal temperature sensor primary overtemperature fault masked. [1] 1 = Remote temperature sensor 1 primary overtemperature fault masked. [2] 1 = Remote temperature sensor 2 primary overtemperature fault masked. [3] 1 = Internal temperature sensor secondary overtemperature fault masked. [4] 1 = Remote temperature sensor 1 secondary overtemperature fault masked. [5] 1 = Remote temperature sensor 2 secondary overtemperature fault masked. [6] 1 = Current-sense primary overcurrent fault masked. [7] 1 = Current-sense secondary overcurrent fault masked. ______________________________________________________________________________________ 29 MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory Table 11. Fault Flags REGISTER ADDRESS 50h EEPROM MEMORY ADDRESS D0h BIT RANGE [0] 1 = Short circuit detected at remote temperature sensor 1. [1] 1 = Open circuit detected at remote temperature sensor 1. [2] 1 = Short circuit detected at remote temperature sensor 2. [3] 1 = Open circuit detected at remote temperature sensor 2. [7:4] 51h 52h 53h 30 D1h D2h D3h DESCRIPTION Not used. [0] 1 = IN1 conversion result exceeds primary overvoltage or undervoltage thresholds. [1] 1 = IN2 conversion result exceeds primary overvoltage or undervoltage thresholds. [2] 1 = IN3 conversion result exceeds primary overvoltage or undervoltage thresholds. [3] 1 = IN4 conversion result exceeds primary overvoltage or undervoltage thresholds. [4] 1 = IN5 conversion result exceeds primary overvoltage or undervoltage thresholds. [5] 1 = IN6 conversion result exceeds primary overvoltage or undervoltage thresholds. [6] 1 = IN7 conversion result exceeds primary overvoltage or undervoltage thresholds. [7] 1 = IN8 conversion result exceeds primary overvoltage or undervoltage thresholds. [0] 1 = IN1 conversion result exceeds secondary overvoltage or undervoltage thresholds. [1] 1 = IN2 conversion result exceeds secondary overvoltage or undervoltage thresholds. [2] 1 = IN3 conversion result exceeds secondary overvoltage or undervoltage thresholds. [3] 1 = IN4 conversion result exceeds secondary overvoltage or undervoltage thresholds. [4] 1 = IN5 conversion result exceeds secondary overvoltage or undervoltage thresholds. [5] 1 = IN6 conversion result exceeds secondary overvoltage or undervoltage thresholds. [6] 1 = IN7 conversion result exceeds secondary overvoltage or undervoltage thresholds. [7] 1 = IN8 conversion result exceeds secondary overvoltage or undervoltage thresholds. [0] 1 = Internal temperature sensor conversion exceeds its primary overtemperature threshold. [1] 1 = Remote temperature sensor 1 conversion exceeds its primary overtemperature threshold. [2] 1 = Remote temperature sensor 2 conversion exceeds its primary overtemperature threshold. [3] 1 = Internal temperature sensor conversion exceeds its secondary overtemperature threshold. [4] 1 = Remote temperature sensor 1 conversion exceeds its secondary overtemperature threshold. [5] 1 = Remote temperature sensor 2 conversion exceeds its secondary overtemperature threshold. [6] 1 = Current-sense conversion exceeds its primary overcurrent threshold. [7] 1 = Current-sense conversion exceeds its secondary overcurrent threshold. ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 Table 12. Fault Log Dependency REGISTER ADDRESS 58h 59h 5Ah EEPROM BIT MEMORY RANGE ADDRESS D8h D9h DAh DESCRIPTION [0] 1 = Fault log triggered when IN1 is below its primary undervoltage threshold. [1] 1 = Fault log triggered when IN2 is below its primary undervoltage threshold. [2] 1 = Fault log triggered when IN3 is below its primary undervoltage threshold. [3] 1 = Fault log triggered when IN4 is below its primary undervoltage threshold. [4] 1 = Fault log triggered when IN5 is below its primary undervoltage threshold. [5] 1 = Fault log triggered when IN6 is below its primary undervoltage threshold. [6] 1 = Fault log triggered when IN7 is below its primary undervoltage threshold. [7] 1 = Fault log triggered when IN8 is below its primary undervoltage threshold. [0] 1 = Fault log triggered when IN1 is above its primary overvoltage threshold. [1] 1 = Fault log triggered when IN2 is above its primary overvoltage threshold. [2] 1 = Fault log triggered when IN3 is above its primary overvoltage threshold. [3] 1 = Fault log triggered when IN4 is above its primary overvoltage threshold. [4] 1 = Fault log triggered when IN5 is above its primary overvoltage threshold. [5] 1 = Fault log triggered when IN6 is above its primary overvoltage threshold. [6] 1 = Fault log triggered when IN7 is above its primary overvoltage threshold. [7] 1 = Fault log triggered when IN8 is above its primary overvoltage threshold. [0] 1 = Fault log triggered when current sense is above its primary overcurrent threshold. [1] 1 = Fault log triggered when internal temperature sensor is above its overtemperature threshold. [2] 1 = Fault log triggered when remote temperature sensor 1 is above its overtemperature threshold. [3] 1 = Fault log triggered when remote temperature sensor 2 is above its overtemperature threshold. [7:4] Not used. Fault Logging If a specific input threshold is critical to the operation of the system, an automatic fault log is configured to trigger a transfer of fault information to EEPROM. The fault log dependencies are configured through r58h–r5Ah, as shown in Table 12. Logged fault information is read from EEPROM locations r80h–r8Eh, as shown in Table 13. Once a fault log event occurs, the fault log feature is locked and must be reset to enable a new fault log to be stored. Write a ‘1’ to r5Fh[1] to reset the fault log. Fault information always contains the fault flag registers and is configured to also include the ADC result registers through r5Ch[7] (see the Miscellaneous Settings section). All stored ADC results are the 8 MSBs of the result. Miscellaneous Settings Table 14 shows several miscellaneous programmable items. Register r5Bh contains boot-up timeout and remote temperature sensor filter cutoff settings. Register r5Ch[1:0] sets the secondary overcurrent threshold timeout, which is the amount of delay after an overcurrent condition before the overcurrent condition becomes a fault. All voltage thresholds include two selectable hysteresis options programmed by r5Ch[5]. When r5Ch[6] = 1, the conditions programmed to cause a fault log event must happen for two consecutive ADC cycles rather than just one to provide an improvement in noise immunity. Register r5Ch[7] controls whether the ADC result registers are stored in EEPROM after a fault log. Register r5Eh provides storage space for a user-defined configuration or firmware version number. Register r5Fh[0] locks and unlocks the EEPROM and register set. Register r5Fh[1] indicates whether a fault log event occurred and the corresponding fault information is locked in EEPROM. Further fault log conditions will not write new fault information to the fault EEPROM until a ‘1’ is written to r5Fh[1]. ______________________________________________________________________________________ 31 MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory Table 13. Fault Log EEPROM REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE — 80h [7:0] Copy of r51h[7:0] at the time the fault log was triggered. — 81h [7:0] Copy of r52h[7:0] at the time the fault log was triggered. — 82h [7:0] Copy of r53h[7:0] at the time the fault log was triggered. — 83h [7:0] IN1 conversion result at the time the fault log was triggered. — 84h [7:0] IN2 conversion result at the time the fault log was triggered. 8 MSBs only. — 85h [7:0] IN3 conversion result at the time the fault log was triggered. 8 MSBs only. — 86h [7:0] IN4 conversion result at the time the fault log was triggered. 8 MSBs only. — 87h [7:0] IN5 conversion result at the time the fault log was triggered. 8 MSBs only. — 88h [7:0] IN6 conversion result at the time the fault log was triggered. 8 MSBs only. — 89h [7:0] IN7 conversion result at the time the fault log was triggered. 8 MSBs only. — 8Ah [7:0] IN8 conversion result at the time the fault log was triggered. 8 MSBs only. DESCRIPTION — 8Bh [7:0] Internal temperature sensor conversion result at the time the fault log was triggered. 8 MSBs from 10-bit ADC conversion. — 8Ch [7:0] Remote temperature sensor 1 conversion result at the time the fault log was triggered. 8 MSBs from 10-bit ADC conversion. — 8Dh [7:0] Remote temperature sensor 2 conversion result at the time the fault log was triggered. 8 MSBs from 10-bit ADC conversion. — 8Eh [7:0] Current-sense conversion result at the time the fault log was triggered. I2C/SMBus-Compatible Serial Interface The MAX16031/MAX16032 feature an I2C/SMBus-compatible 2-wire (SDA and SCL) serial interface for communication with a master device. All possible communication formats are shown in Figure 5. The slave address and SMBALERT# are described further in the following subsections. Figure 1 shows a detailed 2-wire interface timing diagram. For descriptions of the I2C and SMBus protocol and terminology, refer to the I 2 C-Bus Specification Version 2.1 and the System Management Bus (SMBus) Specification Version 2.0. The MAX16031/MAX16032 allow 2-wire communication up to 400kHz. SDA and SCL require external pullup resistors. Slave Address The slave address inputs, A0 and A1, are each capable of detecting three different states, allowing nine identical devices to share the same serial bus. Connect A0 and A1 to GND, DBP, or leave as not connected (N.C.). See Table 15 for a listing of all possible 7-bit address input connections and their corresponding serial-bus addresses. 32 SMBALERT# SMBALERT# is an optional interrupt signal defined in Appendix A of the SMBus Specification. The MAX16031/MAX16032 provide output ALERT as this interrupt signal. If enabled, ALERT asserts if any one of the following outputs asserts: FAULT1, FAULT2, RESET, OVERT, or OVERC. Additionally, if a GPIO_ is configured for a fault output, a fault at this output also causes ALERT to assert. ALERT deasserts when all fault conditions are removed (i.e., when all fault outputs are high). Typically ALERT is connected to all other SMBALERT# open-drain signals in the system, creating a wired-OR function with all SMBALERT# outputs. When the master is interrupted by its SMBALERT# input, it stops or finishes the current bus transfer and places an alert response address (ARA) on the bus. The slave that pulled the SMBALERT# signal low acknowledges the ARA and places its own address on the bus, identifying itself to the master as the slave that caused the interrupt. The 7-bit ARA is ‘0001100’ and the R/W bit is a don’t care. ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory S ADDRESS 7 bits Receive Byte Format R/W ACK 0 COMMAND ACK P ADDRESS S 8 bits Slave Address: Address of the slave on the serial interface bus. ADDRESS 7 bits R/W ACK 7 bits DATA 1 NACK P 8 bits Slave Address: Address of the slave on the serial interface bus. Data Byte: Presets the internal address pointer or represents a command. Write Byte Format S MAX16031/MAX16032 Send Byte Format Data Byte: Data is read from the location pointed to by the internal address pointer. SMBALERT# R/W ACK 0 COMMAND ACK DATA 8 bits Slave Address: Address of the slave on the serial interface bus. ACK P S 8 bits Data Byte: Data is written to the locations set by the internal address pointer. Command Byte: Sets the internal address pointer. ADDRESS R/W ACK 0001100 D.C. Alert Response Address: Only the device that interrupted the master responds to this address. DATA NACK P 8 bits Slave Address: Slave places its own address on the serial bus. Read Byte Format S SLAVE ADDRESS 7 bits R/W ACK 0 COMMAND ACK SR SLAVE ADDRESS 8 bits Slave Address: Address of the slave on the serial interface bus. 7 bits R/W ACK DATA BYTE NACK P 8 bits 1 Data Byte: Data is written to the locations set by the internal address pointer. Command Byte: Sets the internal address pointer. Block Write Format S ADDRESS 7 bits WR ACK 0 COMMAND ACK BYTE COUNT = N 8 bits Slave Address: Address of the slave on the serial interface bus. ACK DATA BYTE 1 ACK DATA BYTE … ACK DATA BYTE N ACK 8 bits 8 bits Command Byte: FAh 8 bits Slave to master P 8 bits Master to slave Data Byte: Data is written to the locations set by the internal address pointer. Block Read Format S ADDRESS 7 bits WR ACK 0 COMMAND 8 bits Slave Address: Address of the slave on the serial interface bus. S = START Condition P = STOP Condition Sr = Repeated START Condition D.C. = Don’t Care Command Byte: FBh ACK SR ADDRESS 7 bits WR ACK BYTE COUNT = N 1 Slave Address: Address of the slave on the serial interface bus. 8 bits ACK DATA BYTE N ACK DATA BYTE … ACK DATA BYTE N NACK 8 bits 8 bits P 8 bits Data Byte: Data is read from the locations set by the internal address pointer. ACK = Acknowledge, SDA pulled low during rising edge of SCL. NACK = Not acknowledge, SDA left high during rising edge of SCL. All data is clocked in/out of the device on rising edges of SCL. = SDA transitions from high to low during period of SCL. = SDA transitions from low to high during period of SCL. Figure 5. Communication Formats ______________________________________________________________________________________ 33 MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory Table 14. Miscellaneous Settings REGISTER ADDRESS EEPROM MEMORY ADDRESS BIT RANGE [3:0] 5Bh DBh [6:4] [7] [1:0] 5Ch DCh [2] [4:3] [5] 34 DESCRIPTION Postboot Timeout (all faults and outputs masked): 0h = No timeout 1h = 0.974ms 2h = 2.030ms 3h = 3.978ms 4h = 8.038ms 5h = 15.99ms 6h = 31.99ms 7h = 63.99ms 8h = 128ms 9h = 256.0ms Ah = 512ms Bh = 1024ms Ch = 2048ms Dh = 4096ms Eh = 8192ms Fh = 16384ms Temperature Sensor Lowpass Filter Cutoff: 000 = No filter 001 = 2.53Hz 010 = 5.06Hz 011 = 10.1Hz 100 = 20.2Hz 101 = 40.5Hz 110 = 81Hz 111 = 162Hz Not used. Overcurrent Secondary Threshold Timeout: 00 = No delay 01 = 3.98ms 10 = 16ms 11 = 64ms Latch OVERC: 0 = No latch 1 = Latched after assertion Not used. Threshold Hysteresis (all thresholds): 0 = 0.78% 1 = 1.17% ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory REGISTER ADDRESS 5Ch 5Eh EEPROM MEMORY ADDRESS BIT RANGE [6] Consecutive Faults on Primary Thresholds: 0 = Fault occurs after primary threshold is exceeded one time (normal operation). 1 = Fault occurs after primary threshold is exceeded twice. [7] Fault Log ADC Conversions Option: 0 = When a fault log is triggered, only fault flags are saved in EEPROM. 1 = When a fault log is triggered, fault flags and ADC conversion results (8 MSBs) are saved in EEPROM. DCh DEh [7:0] [0] 5Fh DESCRIPTION DFh [1] [7:2] Firmware Version. 8 bits of memory for user-defined firmware version number. Configuration Lock: Write a ‘1’ to r5Fh[0] to toggle this register bit. 0 = Register and EEPROM configuration unlocked. 1 = Register and EEPROM configuration locked. Fault Log EEPROM Lock Flag (set automatically after fault log is triggered): Write a ‘1’ to r5Fh[1] to toggle this register bit. 0 = EEPROM is not locked. A triggered fault log stores fault information to EEPROM. 1 = A fault log has been triggered. Write a ‘1’ to this bit to clear the flag and allow a new fault log to be triggered. Not used. Table 15. Setting the I2C/SMBus Slave Address A1 A0 BUS ADDRESS GND GND 0011000 GND N.C. 0011001 GND DBP 0011010 N.C. GND 0101001 N.C. N.C. 0101010 N.C. DBP 0101011 DBP GND 1001100 DBP N.C. 1001111 DBP DBP 1001110 Special Commands The MAX16031/MAX16032 provide software reboot and fault log commands. A software reboot initiates the boot-up sequence, which normally occurs at POR. During boot-up, EEPROM configuration data is copied to registers. To initiate a software reboot, send 0xFC using the send byte format. A software-initiated fault log is functionally the same as a hardware-initiated fault log. During a fault log, ADC registers and fault information are logged in EEPROM. To trigger a software initiated fault log, send 0xFD using the send byte format. JTAG Serial Interface The MAX16031/MAX16032 contain an IEEE 1149.1- compliant JTAG port in addition to the I2C/SMBus-compatible serial bus. Either interface may be used to access internal memory; however, only one interface is allowed to run at a time. All digital I/Os on the MAX16031/MAX16032 are IEEE 1149.1 boundary-scan compliant, and contain the typical JTAG boundary scan cells that allow the inputs/outputs to be polled or forced high/low using standard JTAG instructions. The MAX16031/MAX16032 contain extra JTAG instructions and registers not included in the JTAG specification that provide access to internal memory. The extra instructions are: LOAD ADDRESS, WRITE, READ, REBOOT, SAVE, and USERCODE. The extra registers are: memory address, memory write, memory read, and user-code data. See Figure 6 for a block diagram of the JTAG interface. Test Access Port (TAP) Controller State Machine The TAP controller is a finite state machine that responds to the logic level at TMS on the rising edge of TCK. See Figure 7 for a diagram of the finite state machine. Test-Logic-Reset: At power-up, the TAP controller is in the test-logic-reset state. The instruction register contains the IDCODE instruction. All system logic of the device operates normally. ______________________________________________________________________________________ 35 MAX16031/MAX16032 Table 14. Miscellaneous Settings (continued) MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory REGISTERS AND EEPROM 01101 01100 MEMORY WRITE REGISTER [LENGTH = 8 BITS] 01010 MEMORY READ REGISTER [LENGTH = 8 BITS] 01001 MEMORY ADDRESS REGISTER [LENGTH = 8 BITS] 01000 BOUNDARY SCAN REGISTER [LENGTH = 198 BITS] 00001 00010 USER CODE REGISTER [LENGTH = 32 BITS] 00100 IDENTIFICATION REGISTER [LENGTH = 32 BITS] 00000 BYPASS REGISTER [LENGTH = 1 BIT] 11111 MUX 1 COMMAND DECODER 01101 01100 SAVE REBOOT VDBP INSTRUCTION REGISTER [LENGTH = 5 BITS] RPU MUX 2 TDI TMS TCK TDO TEST ACCESS PORT (TAP) CONTROLLER Figure 6. JTAG Block Diagram Run-Test/Idle: The run-test/idle state is used between scan operations or during specific tests. The instruction register and test data registers remain idle. Select-DR-Scan: All test data registers retain their previous state. With TMS low, a rising edge of TCK moves the controller into the capture-DR state and initiates a scan sequence. TMS high during a rising edge on TCK moves the controller to the select-IR-scan state. Capture-DR: Data are parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected test data register does not allow parallel loads, the test data register remains at its current value. On the rising edge of TCK, the controller goes to the shift-DR state if TMS is low or it goes to the exit1-DR state if TMS is high. 36 Shift-DR: The test data register selected by the current instruction is connected between TDI and TDO and shifts data one stage toward its serial output on each rising edge of TCK while TMS is low. On the rising edge of TCK, the controller goes to the exit1-DR state if TMS is high. Exit1-DR: While in this state, a rising edge on TCK puts the controller in the update-DR state. A rising edge on TCK with TMS low puts the controller in the pause-DR state. Pause-DR: Shifting of the test data registers is halted while in this state. All test data registers retain their previous state. The controller remains in this state while TMS is low. A rising edge on TCK with TMS high puts the controller in the exit2-DR state. ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MAX16031/MAX16032 1 TEST-LOGIC-RESET 0 0 RUN-TEST/IDLE 1 SELECT-DR-SCAN 1 SELECT-IR-SCAN 0 1 0 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR PAUSE-IR 0 1 0 1 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 SHIFT-IR 0 1 0 1 UPDATE-IR 0 1 0 Figure 7. TAP Controller State Diagram Exit2-DR: A rising edge on TCK with TMS high while in this state puts the controller in the update-DR state. A rising edge on TCK with TMS low enters the Shift-DR state. Update-DR: A falling edge on TCK while in the updateDR state latches the data from the shift register path of the test data registers into a set of output latches. This prevents changes at the parallel output because of changes in the shift register. On the rising edge of TCK, the controller goes to the run-test/idle state if TMS is low or it goes to the select-DR-scan state if TMS is high. Select-IR-Scan: All test data registers retain their previous state. The instruction register remains unchanged during this state. With TMS low, a rising edge on TCK moves the controller into the capture-IR state. TMS high during a rising edge on TCK puts the controller back into the test-logic-reset state. Capture-IR: Use the capture-IR state to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of TCK. If TMS is high on the rising edge of TCK, the controller enters the exit1-IR state. If TMS is low on the rising edge of TCK, the controller enters the shift-IR state. Shift-IR: In this state, the shift register in the instruction register is connected between TDI and TDO and shifts data one stage for every rising edge of TCK toward the TDO serial output while TMS is low. The parallel outputs of the instruction register as well as all test data registers remain at their previous states. A rising edge on TCK with TMS high moves the controller to the exit1-IR state. A rising edge on TCK with TMS low keeps the controller in the shift-IR state while moving data one stage through the instruction shift register. ______________________________________________________________________________________ 37 MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory Exit1-IR: A rising edge on TCK with TMS low puts the controller in the pause-IR state. If TMS is high on the rising edge of TCK, the controller enters the update-IR state. Pause-IR: Shifting of the instruction shift register is halted temporarily. With TMS high, a rising edge on TCK puts the controller in the exit2-IR state. The controller remains in the pause-IR state if TMS is low during a rising edge on TCK. Exit2-IR: A rising edge on TCK with TMS high puts the controller in the update-IR state. The controller loops back to shift-IR if TMS is low during a rising edge of TCK in this state. Update-IR: The instruction code that has been shifted into the instruction shift register is latched to the parallel outputs of the instruction register on the falling edge of TCK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on TCK with TMS low puts the controller in the run-test/idle state. With TMS high, the controller enters the select-DR-scan state. Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 5 bits in length. When the TAP controller enters the shift-IR state, the instruction shift register is connected between TDI and TDO. While in the shift-IR state, a rising edge on TCK with TMS low shifts the data one stage toward the serial output at TDO. A rising edge on TCK in the exit1-IR state or the exit2-IR state with TMS high moves the controller to the update-IR state. The falling edge of that same TCK latches the data in the instruction shift register to the instruction register parallel output. Instructions supported by the MAX16031/MAX16032 and their respective operational binary codes are shown in Table 16. SAMPLE/PRELOAD: This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the device are sampled at the boundary scan test data register without interfering with the normal operation of the device by using the capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the boundary scan test data register through TDI using the shift-DR state. BYPASS: When the BYPASS instruction is latched into the instruction register, TDI connects to TDO through the 1-bit bypass test data register. This allows data to pass from DTDI to TDO without affecting the device’s normal operation. EXTEST: This instruction allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction register, the following actions occur. Once enabled through the update-IR state, the parallel outputs of all digital outputs are driven. The boundary scan test data register is connected between TDI and TDO. The capture-DR samples all digital inputs into the boundary scan test data register. IDCODE: When the IDCODE instruction is latched into the parallel instruction register, the identification test data register is selected. The device identification code is loaded into the identification test data register on the rising edge of TCK following entry into the capture-DR state. Shift-DR is used to shift the identification code out serially through TDO. During test-logic-reset, the identification code is forced into the instruction register. The ID code always has a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. See Table 17. Table 16. JTAG Instruction Set 38 INSTRUCTION BINARY CODE BYPASS 11111 Bypass SELECTED REGISTER/ACTION IDCODE 00000 Identification SAMPLE/PRELOAD 00001 Boundary scan EXTEST 00010 Boundary scan USERCODE 00100 User-code data LOAD ADDRESS 01000 Memory address READ DATA 01001 Memory read WRITE DATA 01010 Memory write REBOOT 01100 Resets the device SAVE 01101 Stores current fault information in EEPROM ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory MSB LSB Version (4 bits) Device ID (16 bits) Manufacturer ID (11 bits) Fixed value (1 bit) 0000 0000000000000001 00011001011 1 Table 18. 32-Bit User-Code Data MSB D.C. (don’t cares) I2C/SMBus Slave Address User identification (firmware version) 00000000000000000 See Table 15 r5Eh[7:0] contents USERCODE: When the USERCODE instruction is latched into the parallel instruction register, the usercode data register is selected. The device user code is loaded into the user-code data register on the rising edge of TCK following entry into the capture-DR state. Shift-DR is used to shift the user code out serially through TDO. See Table 18. LOAD ADDRESS: This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the MAX16031/MAX16032. When the LOAD ADDRESS instruction is latched into the instruction register, TDI connects to TDO through the 8-bit memory address test data register during the shift-DR state. READ: This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the MAX16031/MAX16032. When the READ instruction is latched into the instruction register, TDI connects to TDO through the 8-bit memory read test data register during the shift-DR state. WRITE: This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the MAX16031/MAX16032. When the WRITE instruction is latched into the instruction register, TDI connects to TDO through the 8-bit memory write test data register during the shift-DR state. REBOOT: This is an extension to the standard IEEE 1149.1 instruction set to initiate a software-controlled reset to the MAX16031/MAX16032. When the REBOOT instruction is latched into the instruction register, the MAX16031/MAX16032 reset and immediately begin their boot-up sequence. SAVE: This is an extension to the standard IEEE 1149.1 instruction set that triggers a fault log. When the SAVE instruction is latched into the instruction register, the MAX16031/MAX16032 copy fault information from registers to EEPROM. Boundary Scan The boundary scan feature allows access to all the digital I/O connections of the MAX16031/MAX16032. If the sample/preload or the EXTEST instruction is loaded into the instruction register, TDI connects to TDO through the 198-bit boundary scan register. Each digital I/O pin corresponds to 1 bit (or 2 bits, in the case of the A0 and A1 pins) of the boundary scan register. The rest of the boundary scan bits are reserved and are loaded with zeros. When the sample/preload instruction is executed, the current state of the digital outputs is latched into the boundary scan register and is shifted out through TDO. This instruction may be executed without interrupting normal operation of the part. When the EXTEST instruction is executed, the boundary scan register bits supersede the normal functionality of the I/O pins: an output mirrors the state of the corresponding boundary scan register bit. Table 19 lists the function of each boundary scan register bit. Since the I2C address select pins have three possible states, 2 boundary scan register bits are required to represent them. These bits are defined in Table 20. Applications Information Layout and Bypassing Bypass VCC, DBP, and ABP each with a 1µF capacitor to GND. Bypass RBP with a 2.2µF capacitor to GND. Avoid routing digital return currents through a sensitive analog area, such as an analog supply input return path or ABP’s bypass capacitor ground connection. Use dedicated analog and digital ground planes. ______________________________________________________________________________________ 39 MAX16031/MAX16032 Table 17. 32-Bit Identification Code MAX16031/MAX16032 EEPROM-Based System Monitors with Nonvolatile Fault Memory Table 20. Address Pin State Decode Table 19. Boundary Cell Order DESCRIPTION/PIN A0A A0B A0 PIN STATE 0–147 Reserved 00 High impedance 148 GPIO1 (output) 01 Low 149 GPIO2 (output) 10 High 150 SDA (output) 11 Not defined 151 ALERT 152 FAULT2 153 FAULT1 154 OVERT 155 RESET BOUNDARY CELL NO. 40 Chip Information PROCESS: BiCMOS 156 OVERC 157–182 Reserved 183 GPIO2 (input) Package Information 184 GPIO1 (input) 185 SDA (input) 186 A0b 187 A0a For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 188 A1b 189 A1a PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 190 SCL 48 TQFN-EP T4877-6 21-0144 90-0132 191–197 Reserved ______________________________________________________________________________________ EEPROM-Based System Monitors with Nonvolatile Fault Memory REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 0 7/07 Initial release 1 10/07 Revised the Ordering Information. — 1 2 6/10 Revised the Pin Description. 11 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 41 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX16031/MAX16032 Revision History