ZARLINK ZL50012QCG1

ZL50012
Flexible 512-ch Digital Switch
Data Sheet
Features
•
April 2006
512 channel x 512 channel non-blocking switch at
2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s operation
•
Rate conversion between the ST-BUS inputs and
ST-BUS outputs
•
Per-stream ST-BUS input with data rate selection
of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s
•
Per-stream ST-BUS output with data rate
selection of 2.048 Mb/s, 4.096 Mb/s or
8.192 Mb/s; the output data rate can be different
than the input data rate
•
Ordering Information
160 Pin LQFP
Trays
144 Ball LBGA Trays
160 Ball LQFP* Trays, Bake & Drypack
144 Ball LBGA** Trays, Bake & Drypack
*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
ZL50012/QCC
ZL50012/GDC
ZL50012QCG1
ZL50012GDG2
-40°C to +85°C
Per-stream high impedance control output for
every ST-BUS output with fractional bit
advancement
•
Per-channel high impedance output control
•
Per-channel message mode
•
Per-channel pseudo random bit sequence
(PRBS) pattern generation and bit error detection
•
Control interface compatible to Motorola nonmultiplexed CPUs
•
Per-stream input channel and input bit delay
programming with fractional bit delay
•
•
Per-stream output channel and output bit delay
programming with fractional bit advancement
Connection memory block programming
capability
•
IEEE-1149.1 (JTAG) test port
•
Multiple frame pulse outputs and reference clock
outputs
•
3.3V I/O with 5 V tolerant input
•
Per-channel constant throughput delay
VDD
STi0-15
S/P Converter
FPi
CKi
Input Timing
VSS
RESET
Data Memory
ODE
P/S Converter
Output HiZ Control
Output Timing
CKo1
FPo2
Registers
CKo2
IC0 - 4
CLKBYPS
ICONN0 - 2
TCK
TRST
TDI
TDO
TMS
DTA
D15 - 0
A11 - 0
CS
R/W
DS
TM1
TM2
Test Port
SG1
FPo0
CKo0
FPo1
Internal
APLL
VSS_APLL
STOHZ0-15
Connection Memory
Microprocessor
Interface
and
VDD_APLL
STo0-15
Figure 1 - ZL50012 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2002-2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL50012
Data Sheet
Applications
•
Small and medium digital switching platforms
•
Access Servers
•
Time Division Multiplexers
•
Computer Telephony Integration
•
Digital Loop Carriers
Description
The device has sixteen ST-BUS inputs (STi0-15) and sixteen ST-BUS outputs (STo0-15). It is a non-blocking digital
switch with 512 64 kb/s channels and performs rate conversion between the ST-BUS inputs and ST-BUS outputs.
The ST-BUS inputs accept serial input data streams with the data rate of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s on
a per-stream basis. The ST-BUS outputs deliver serial output data streams with the data rate of 2.048 Mb/s,
4.096 Mb/s or 8.192 Mb/s on a per-stream basis. The device also provides sixteen high impedance control outputs
(STOHZ 0-15) to support the use of external high impedance control buffers.
The ZL50012 has features that are programmable on per-stream or per-channel basis including message mode,
input bit delay, output bit advancement, constant throughput delay and high impedance output control.
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Zarlink Semiconductor Inc.
ZL50012
Data Sheet
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1 ST-BUS Input Data Rate and Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.1 ST-BUS Input Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.2 Frame Pulse Input and Clock Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.3 ST-BUS Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1.4 Improved Input Jitter Tolerance with Frame Boundary Determinator . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 ST-Bus Output Data Rate and Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.1 ST-Bus Output Operation Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.2 Frame Pulse Output and Clock Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.3 ST-BUS Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3 Serial Data Input Delay and Serial Data Output Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.1 Input Channel Delay Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.2 Input Bit Delay Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.3 Fractional Input Bit Delay Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.4 Output Channel Delay Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.5 Output Bit Delay Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.6 Fractional Output Bit Advancement Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3.7 External High Impedance Control, STOHZ 0 to 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4 Data Delay Through The Switching Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.5.1 Connection Memory Block Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.6 Bit Error Rate (BER) Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.7 Quadrant frame programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.8 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.0 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.0 JTAG Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3 Test Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.0 Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.0 Detail Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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Zarlink Semiconductor Inc.
ZL50012
Data Sheet
List of Figures
Figure 1 - ZL50012 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - 24 mm x 24 mm LQFP (JEDEC MS-026) Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3 - 13 mm x 13 mm 144 Ball LBGA Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4 - Input Timing when (CKIN2 to CKIN0 bits = 010) in the Control Register . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5 - Input Timing when (CKIN2 to CKIN0 bits = 001) in the Control Register . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6 - Input Timing when (CKIN2 to CKIN0 bits = 000) in the Control Register . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7 - ST-BUS Input Timing for Various Input Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8 - FPo0 and CKo0 Output Timing when the CKFP0 bit = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9 - FPo0 and CKo0 Output Timing when the CKFP0 bit = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10 - FPo1 and CKo1 Output Timing when the CKFP1 bit = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11 - FPo1 and CKo1 Output Timing when the CKFP1 bit = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12 - FPo2 and CKo2 Output Timing when the CKFP2 bit = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13 - FPo2 and CKo2 Output Timing when the CKFP2 bit = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14 - ST-BUS Output Timing for Various Output Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15 - Input Channel Delay Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16 - Input Bit Delay Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17 - Output Channel Delay Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18 - Output Bit Delay Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19 - Fractional Output Bit Advancement Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20 - Example: External High Impedance Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 21 - Data Throughput Delay when input and output channel delay are disabled for Input Ch0 switched to
Output Ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 22 - Data Throughput Delay when input channel delay is enabled and output channel delay is disabled for
Input Ch0 switched to Output Ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 23 - Data Throughput Delay when input channel delay is disabled and output channel delay is enabled for
Input Ch0 switch to Output Ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 24 - Data Throughput Delay when input and output channel delay are enabled for Input Ch0 switched to
Output Ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 25 - Frame Pulse Input and Clock Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 26 - Frame Boundary Timing with Input Clock (cycle-to-cycle) Variation . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 27 - Frame Boundary Timing with Input Frame Pulse (cycle-to-cycle) Variation . . . . . . . . . . . . . . . . . . . . 57
Figure 28 - Input and Output Frame Boundary Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 29 - FPo0 and CKo0 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 30 - FPo1 and CKo1 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 31 - FPo2 and CKo2 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 32 - ST-BUS Inputs (STi0 - 15) Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 33 - ST-BUS Outputs (STo0 - 15) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 34 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 35 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 36 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 37 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 38 - Reset Pin Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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ZL50012
Data Sheet
List of Tables
Table 1 - FPi and CKi Input Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2 - FPo0 and CKo0 Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3 - FPo1 and CKo1 Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4 - FPo2 and CKo2 Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 5 - Variable Range for Input Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6 - Variable Range for Output Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 7 - Data Throughput Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8 - Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 9 - Definition of the Four Quadrant Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10 - Quadrant Frame 0 LSB Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11 - Quadrant Frame 1 LSB Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12 - Quadrant Frame 2 LSB Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13 - Quadrant Frame 3 LSB Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 14 - Address Map for Device Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 15 - Control Register (CR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 16 - Internal Mode Selection (IMS) Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 17 - BER Start Receiving Register (BSRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 18 - BER Length Register (BLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 19 - BER Count Register (BCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 20 - Stream Input Control Register 0 to 7 (SICR0 to SICR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 21 - Stream Input Control Register 8 to 15 (SICR8 to SICR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 22 - Stream Input Delay Register 0 to 7 (SIDR0 to SIDR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 23 - Stream Input Delay Register 8 to 15 (SIDR8 to SIDR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 24 - Stream Output Control Register 0 to 7 (SOCR0 to SOCR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 25 - Stream Output Control Register 8 to 15 (SOCR8 to SOCR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 26 - Stream Output Offset Register 0 to 7 (SOOR0 to SOOR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 27 - Stream Output Offset Register 8 to 15 (SOOR8 to SOOR15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 28 - Address Map for Memory Locations (512 x 512 DX, MSB of address = 1). . . . . . . . . . . . . . . . . . . . . . 52
Table 29 - Connection Memory Bit Assignment when the CMM bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 30 - Connection Memory Bits Assignment when the CMM bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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ZL50012
Data Sheet
Changes Summary
The following table captures the changes from the July 2004 issue.
Page
Item
Change
18
2.1.4, “Improved Input Jitter Tolerance with
Frame Boundary Determinator“
•
Added a new section to describe the improved
input jitter tolerance with the frame boundary
determinator.
37
Table 15 -, “Control Register (CR) Bits“ bits , “FBDMODE“ and , “FBDEN“
•
Renamed bit 15 from Unused to FBDMODE and
added description to clarify the frame boundary
determinator operation.
•
Clarified FBDEN description.
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Data Sheet
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107
108
109
110
111
112
113
114
115
116
117
118
119
120
NC
NC
STo12
STo13
STo14
STo15
STOHZ 12
STOHZ 13
STOHZ 14
STOHZ 15
VSS
VDD
D0
D1
D2
D3
D4
D5
D6
D7
VSS
VDD
D8
D9
D10
D11
D12
D13
D14
D15
DTA
VSS
VDD
CS
R/W
DS
A0
A1
NC
NC
NC
NC
A2
A3
A4
VSS
VDD
A5
A6
A7
A8
A9
A10
A11
VSS
VDD
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
VSS
VDD
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
VSS
VDD
RESET
TDo
NC
NC
160 Pin LQFP
24 mm x 24 mm
0.5mm pin pitch
JEDEC MS-026
(Top View)
NC
NC
VSS
CKo1
FPo1
CKo0
FPo0
VDD
VSS
ICONN3
ICONN2
NC
IC4
IC3
IC2
IC1
IC0
VDD
CLKBYPS
VSS
ICONN1
NC3
VSS
VDD_APLL
VSS_APLL
NC2
NC1
TM2
TM1
SG1
VDD
VSS
CKi
FPi
TDi
TRST
TCK
TMS
NC
NC
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 2 - 24 mm x 24 mm LQFP (JEDEC MS-026) Pinout Diagram
10
Zarlink Semiconductor Inc.
NC
NC
VDD
VSS
STOHZ 11
STOHZ 10
STOHZ 9
STOHZ 8
STo11
STo10
STo9
STo8
VDD
VSS
STOHZ 7
STOHZ 6
STOHZ 5
STOHZ 4
STo7
STo6
STo5
STo4
VDD
VSS
STOHZ 3
STOHZ 2
STOHZ 1
STOHZ 0
STo3
STo2
STo1
STo0
VDD
VSS
ODE
CKo2
FPo2
VDD
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
ZL50012
Data Sheet
PINOUT DIAGRAM: (as viewed through top of package)
A1 corner identified by metallized marking, mould indent, ink dot or right-angled corner
1
2
3
4
5
6
7
8
9
10
11
12
A
ODE
FPo2
FPo0
ICONN
3
IC1
IC0
ICONN
1
NC3
TM1
CKi
TDi
TCK
B
CKo2
CKo1
FPo1
CKo0
IC3
IC2
CLK
BYPS
VDD_
APLL
SG1
FPi
TRST
TMS
C
STo2
STo1
STOHZ
0
ICONN
2
NC
NC
IC4
NC2
NC1
TM2
TDo
STi15
D
STo3
STo0
STOHZ
1
VSS
VDD
VDD
VDD
VSS_
APLL
VSS
STi8
RESET
STi14
E
STo5
STo4
STOHZ STOHZ
3
2
VSS
VSS
VSS
VSS
VDD
STi9
STi13
STi12
F
STo6
STo7
STOHZ
4
VDD
VSS
VSS
VSS
VSS
VDD
STi7
STi10
STi11
STOHZ STOHZ STOHZ
6
7
5
VDD
VSS
VSS
VSS
VSS
STi1
STi6
STi5
STi4
VDD
VSS
VSS
VSS
VSS
STi0
DS
STi2
STi3
VSS
D2
VDD
VDD
VDD
A10
A9
A8
A11
G
H
STo9
STo10
STo8
J
STo11
STOHZ STOHZ
11
8
K
STOHZ STOHZ
9
15
STo15
STOHZ
13
D1
D5
CS
D10
D11
A5
A4
A7
L
STOHZ
10
STo12
STo13
D3
D15
D4
D7
D12
D14
A2
A3
A6
M
STo14
STOHZ STOHZ
12
14
D0
DTA
D6
D8
D9
D13
A0
A1
R/W
Figure 3 - 13 mm x 13 mm 144 Ball LBGA Pinout Diagram
11
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
Pin Description
LQFP Pin
Number
LBGA Ball
Number
10, 23, 33,
43, 48, 58,
68, 78, 92,
102, 113,
127, 136,
146, 156
D5, D6, D7
E9
F4, F9
G4
H4
J6, J7, J8
VDD
9, 18, 21,
32, 38, 47,
57, 67, 77,
91, 101,
112, 126,
135, 145,
155
D4, D9
E5, E6, E7, E8
F5, F6, F7, F8
G5, G6, G7,
G8
H5, H6, H7, H8
J4
Vss (GND)
3
B12
TMS
Test Mode Select (3.3 V Tolerant Input with internal pullup): JTAG signal that controls the state transitions of the TAP
controller. This pin is pulled high by an internal pull-up resistor
when it is not driven.
4
A12
TCK
Test Clock (5 V Tolerant Input): Provides the clock to the
JTAG test logic.
5
B11
TRST
Test Reset (3.3 V Tolerant Input with internal pull-up):
Asynchronously initializes the JTAG TAP controller by putting it
in the Test-Logic-Reset state. This pin should be pulsed low
during power-up to ensure that the device is in the normal
functional mode. When JTAG is not being used, this pin should
be pulled low during normal operation.
6
A11
TDi
Test Serial Data In (3.3 V Tolerant Input with internal pullup): JTAG serial test instructions and data are shifted in on this
pin. This pin is pulled high by an internal pull-up resistor when it
is not driven.
7
B10
FPi
ST-BUS Frame Pulse Input (5 V Tolerant Input): This pin
accepts the frame pulse which stays low for 61 ns, 122 ns or
244 ns at the frame boundary. The frame pulse associating
with the highest input data rate has to be applied to this pin.
The frame pulse frequency is 8 kHz. The device also accepts
positive frame pulse if the FPINP bit is high in the Internal
Mode Selection register.
8
A10
CKi
ST-BUS Clock Input (5 V Tolerant Input): This pin accepts a
4.096 MHz, 8.192 MHz or 16.384 MHz clock. The input clock
frequency has to be equal to or greater than twice of the
highest input data rate. The clock falling edge defines the input
frame boundary. The device also allows the clock rising edge to
define the frame boundary by programming the CKINP bit in
the Internal Mode Selection register.
Name
Description
Power Supply for the device: +3.3 V
Ground.
12
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
Pin Description (continued)
LQFP Pin
Number
LBGA Ball
Number
Name
Description
11
B9
SG1
APLL Test Control (3.3 V Input with internal pull-down): For
normal operation, this input MUST be low.
12
A9
TM1
APLL Test Pin 1: For normal operation, this input MUST be
low.
13
C10
TM2
APLL Test Pin 2: For normal operation, this input MUST be
low.
14, 15, 19
C9, C8, A8
NC1, NC2,
NC3
16
D8
Vss_APLL
Ground for the APLL Circuit.
17
B8
VDD_APLL
Power Supply for the on-chip Analog Phase Lock Loop
(APLL) Circuit: +3.3 V
20
A7
ICONN1
Internal Connection: In normal mode, this pin must be low.
22
B7
CLKBYPS
Test Clock Input: For device testing only, in normal operation,
this input MUST be low.
24 - 28
A6, A5, B6,
B5, C7
IC0 - 4
Internal connection (3.3 V Tolerant Inputs with internal
pull-down):
In normal mode, these pins must be low.
30, 31
C4, A4
ICONN2 - 3
Internal Connection: In normal mode, these pins must be low.
34
A3
FPo0
ST-BUS Frame Pulse Output 0 (5 V Tolerance Three-state
Output): ST-BUS frame pulse output which stays low for
244 ns or 122 ns at the output frame boundary. Its frequency is
8 KHz. The polarity of this signal can be changed using the
Internal Mode Selection register.
35
B4
CKo0
ST-BUS Clock Output 0 (5 V Tolerant Three-state Output):
A 4.094 MHz or 8.192 MHz clock output. The clock falling edge
defines the output frame boundary. The polarity of this signal
can be changed using the Internal Mode Selection register.
36
B3
FPo1
ST-BUS Frame Pulse Output 1 (5 V Tolerant Three-state
Output): ST-BUS frame pulse output which stays low for 61 ns
or 122 ns at the output frame boundary. Its frequency is 8 KHz.
The polarity of this signal can be changed using the Internal
Mode Selection register.
37
B2
CKo1
ST-BUS Clock Output 1 (5 V Tolerant Three-state Output):
A 16.384 MHz or 8.192 MHz clock output. The clock falling
edge defines the output frame boundary. The polarity of this
signal can be changed using the Internal Mode Selection
register.
No Connection: These pins MUST be left unconnected.
13
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
Pin Description (continued)
LQFP Pin
Number
LBGA Ball
Number
Name
Description
44
A2
FPo2
ST-BUS Frame Pulse Output 2 (5V Tolerant High Speed
Three-state Output): ST-BUS frame pulse output which stays
low for 30 ns or 61 ns at the frame boundary. Its frequency is
8 KHz. The polarity of this signal can be changed using the
Internal Mode Selection register.
45
B1
CKo2
ST-BUS Clock Output 2 (5 V Tolerant High Speed Threestate Output): A 32.768 MHz or 16.384 MHz clock output. The
clock falling edge defines the output frame boundary. The
polarity of this signal can be changed using the Internal Mode
Selection register.
46
A1
ODE
Output Drive Enable (5 V Tolerant Input): This is the
asynchronously output enable control for the STo0 - 15 and the
output driven high control for the STOHZ 0 - 15 serial outputs.
When it is high, the STo0 - 15 and STOHZ 0 - 15 are enabled.
When it is low, the STo0 - 15 are in the high impedance state
and the STOHZ 0 - 15 are driven high.
49 - 52
59 - 62
69 - 72
83 - 86
D2, C2, C1, D1
E2, E1, F1, F2
H3, H1, H2, J1
L2, L3, M1, K3
STo0 - 3
STo4 - 7
STo8 - 11
STo12 - 15
Serial Output Streams 0 to 15 (5 V Tolerant Three-state
Outputs): The data rate of these output streams can be
selected independently using the stream control output
registers. In the 2.048 Mb/s mode, these pins have serial TDM
data streams at 2.048 Mb/s with 32 channels per stream. In the
4.096 Mb/s mode, these pins have serial TDM data streams at
4.096 Mb/s with 64 channels per stream. In the 8.192 Mb/s
mode, these pins have serial TDM data streams at 8.192 Mb/s
with 128 channels per stream.
53 - 56
63 - 66
73 - 76
87 - 90
C3, D3, E4, E3
F3, G3, G1,
G2
J3, K1, L1, J2
M2, K4, M3,
K2
STOHZ 0 - 3
STOHZ 4 - 7
STOHZ 8 11
STOHZ 12 15
Serial Output Streams High Impedance Control 0 to 15 (5 V
Tolerant Three-state Outputs): These pins are used to enable
(or disable) external three-state buffers. When a output channel
is in the high impedance state, the STOHZ drives high for the
duration of the corresponding output channel. When the STo
channel is active, the STOHZ drives low for the duration of the
corresponding output channel.
93 - 96
97 - 100
103 - 106
107 - 110
M4, K5, J5, L4
L6, K6, M6, L7
M7, M8, K8,
K9
L8, M9, L9, L5
D0 - D3
D4 - D7
D8 - D11
D12 - D15
Data Bus 0 - 15 (5 V Tolerant I/Os): These pins form the 16-bit
data bus of the microprocessor port.
111
M5
DTA
Data Transfer Acknowledgment (5 V Tolerant Three-state
Output): This active low output indicates that a data bus
transfer is complete. A pull-up resistor is required to hold this
pin at HIGH level.
114
K7
CS
Chip Select (5 V Tolerant Input): Active low input used by the
microprocessor to enable the microprocessor port access.
14
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
Pin Description (continued)
LQFP Pin
Number
LBGA Ball
Number
Name
Description
115
M12
R/W
Read/Write (5 V Tolerant Input): This input controls the
direction of the data bus lines (D0-D15) during a
microprocessor access.
116
H10
DS
Data Strobe (5 V Tolerant Input): This active low input works
in conjunction with CS to enable the microprocessor port read
and write operations.
117, 118
123 - 125
128 - 130
131 - 134
M10, M11
L10, L11, K11
K10, L12, K12
J11, J10, J9,
J12
A0 - A1
A2 - A4
A5 - A7
A8 - A11
Address 0 - 11 (5 V Tolerant Inputs): These pins form the 12bit address bus to the internal memories and registers.
137 - 139
140 - 142
143, 144
147 - 149
150 - 152
153, 154
H9, G9, H11
H12, G12, G11
G10, F10
D10, E10, F11
F12, E12, E11
D12, C12
STi0 - 2
STi3 - 5
STi6 - 7
STi8 - 10
STi11- 13
STi14 - 15
Serial Input Streams 0 to 15 (5 V Tolerant Inputs): The data
rate of these input streams can be selected independently
using the stream input control registers. In the 2.048 Mb/s
mode, these pins accept serial TDM data streams at
2.048 Mb/s with 32 channels per stream. In the 4.096 Mb/s
mode, these pins accept serial TDM data streams at
4.096 Mb/s with 64 channels per stream. In the 8.192 Mb/s
mode, these pins accept serial TDM data streams at
8.192 Mb/s with 128 channels per stream.
Unused serial input pins are required to connect to either Vdd
or ground, through an external pull-up resistors or external pulldown resistor.
157
D11
RESET
Device Reset (5 V Tolerant Input): This input (active LOW)
puts the device in its reset state that disables the STo0 - 15
drivers and drives the STOHZ 0 - 15 outputs to high. It also
clears the device registers and internal counters. To ensure
proper reset action, the reset pin must be low for longer than
1 ms. Upon releasing the reset signal to the device, the first
microprocessor access can take place after 600 µs due to the
time required to stabilize the APLL block from the power down
state.
158
C11
TDo
Test Serial Data Out (3 V Tolerant Three-state Output):
JTAG serial data is output on this pin on the falling edge of
TCK. This pin is held in high impedance state when JTAG is not
enabled.
1, 2, 29,
39 - 42,
79 - 82,
119 - 122,
159, 160
C5, C6
NC
No Connection Pins. These pins are not connected to the
device internally.
15
Zarlink Semiconductor Inc.
ZL50012
1.0
Data Sheet
Device Overview
The device uses the ST-BUS input frame pulse and the ST-BUS input clock to define the input frame boundary and
timing for the ST-BUS input streams with various data rates (2.048 Mb/s, 4.096 Mb/s and/or 8.192 Mb/s). The
output frame boundary is defined by the output frame pulses and the output clock timing for the ST-BUS output
streams with various data rates (2.048 Mb/s, 4.096 Mb/s and/or 8.192 Mb/s).
By using Zarlink’s message mode capability, microprocessor data can be broadcast to the data output streams on a
per channel basis. This feature is useful for transferring control and status information for external circuits or other
ST-BUS devices.
A non-multiplexed microprocessor port allows users to program the device with various operating modes and
switching configurations. Users can use the microprocessor port to perform register read/write, connection memory
read/write and data memory read operations. The microprocessor port has a 12-bit address bus, a 16-bit data bus
and four control signals.
The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
2.0
Functional Description
A functional block diagram of the ZL50012 is shown in Figure 1 on page 1.
2.1
ST-BUS Input Data Rate and Input Timing
The device has sixteen ST-BUS serial data inputs. Any of the sixteen inputs can be programmed to accept different
data rates, 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s.
2.1.1
ST-BUS Input Operation Mode
Any ST-BUS input can be programmed to accept the 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s data using Bit 0 to 2 in
the stream input control registers, SICR0 to SICR15 as shown in Table 20 on page 42 and Table 21 on page 44.
The maximum number of input channels is 512 channels. External pull-up or pull-down resistors are required for
any unused ST-BUS inputs.
2.1.2
Frame Pulse Input and Clock Input timing
The frame pulse input FPi accepts the frame pulse used for the highest input data rate. The frame pulse is an
8 kHz input signal which stays low for 244 ns, 122 ns or 61 ns for the input data rate of 2.048 Mb/s, 4.096 Mb/s or
8.192 Mb/s respectively. The frequency of CKi must be twice the highest data rate. For example, if users present
the ZL50012 with 2.048 Mb/s and 8.192 Mb/s input data, the device should be programmed to accept the input
clock of 16.384 MHz and the frame pulse which stays low for 61 ns.
Users have to program the CKIN2 - 0 bits in the Control Register (CR), for the width of the frame pulse low cycle
and the frequency of the input clock. See Table 1 for the programming of the CKIN0, CKIN1 and CKIN2 bits in the
Control Register.
CKIN2 - 0 bits
FPi Low Cycle
CKi
Highest Input Data Rate
000
61 ns
16.384 MHz
8.192 Mb/s
001
122 ns
8.192 MHz
4.096 Mb/s
010
244 ns
4.096 MHz
2.048 Mb/s
011 - 111
Reserved
Table 1 - FPi and CKi Input Programming
16
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
The device also accepts positive or negative input frame pulse and ST-BUS input clock formats via the
programming of the FPINP and CKINP bits in the Internal Mode Selection (IMS) register. By default, the device
accepts the negative input clock format.
Figure 4, Figure 5 and Figure 6 describe the usage of CKIN2 - 0, FPINP and CKINP in the Internal Mode Selection
(IMS) register:
FPi
(8kHz)
FPINP = 0
FPi
FPINP = 1
CKi
(4.096MHz)
CKINP = 0
CKi
(4.096MHz)
CKINP = 1
Input Frame Boundary
Input Frame Boundary
Figure 4 - Input Timing when (CKIN2 to CKIN0 bits = 010) in the Control Register
FPi
FPINP = 0
FPi
FPINP = 1
CKi
(8.192MHz)
CKINP = 0
CKi
(8.192MHz)
CKINP = 1
Input Frame Boundary
Input Frame Boundary
Figure 5 - Input Timing when (CKIN2 to CKIN0 bits = 001) in the Control Register
FPi
FPINP = 0
FPi
FPINP = 1
CKi
(16.384MHz)
CKINP = 0
CKi
(16.384MHz)
CKINP = 1
Input Frame Boundary
Input Frame Boundary
Figure 6 - Input Timing when (CKIN2 to CKIN0 bits = 000) in the Control Register
17
Zarlink Semiconductor Inc.
ZL50012
2.1.3
Data Sheet
ST-BUS Input Timing
When the negative input frame pulse and negative input clock formats are used, the input frame boundary is
defined by the falling edge of the CKi input clock while the FPi is low. When the input data rate is 2.048 Mb/s,
4.096 Mb/s or 8.192 Mb/s, there are 32, 64 or 128 channels per every ST-BUS frame respectively. Figure 7 shows
the details:
FPi
(8kHz)
CKi
(4.096MHz)
FPi
CKi
(8.192MHz)
FPi
CKi
(16.384MHz)
Channel 31
Channel 0
STi
(2.048Mb/s)
7
0
5
6
3
4
2
1
0
7
6
5
Channel 0
STi
(8.192Mb/s)
4
3
7
0
Channel 63
Channel 0
STi
(4.096Mb/s)
1
2
1
0
Channel 1
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Input Frame Boundary
6
5
4
3
Channel 126
2
1
0
7
Channel 127
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
Input Frame Boundary
Figure 7 - ST-BUS Input Timing for Various Input Data Rates
2.1.4
Improved Input Jitter Tolerance with Frame Boundary Determinator
The ZL50012 has a Frame Boundary Determinator (FBD) allowing substantial increase of the CKi input clock jitter
tolerance. The FBD circuit is enabled by setting the Control Register bits FBDEN and FBDMODE to HIGH. By
default the FBD is disabled. Both the FBDEN and FBDMODE bits should be set HIGH during normal operation. The
device can have 20 ns of input clock jitter tolerance (on CKi and FPi) when the FBD is fully enabled.
18
Zarlink Semiconductor Inc.
ZL50012
2.2
Data Sheet
ST-Bus Output Data Rate and Output Timing
The device has sixteen ST-BUS serial data outputs. Any of the sixteen outputs can be programmed to deliver
different data rates at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s.
2.2.1
ST-Bus Output Operation Mode
Any ST-Bus output can be programmed to deliver the data at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s mode using Bit
0 to 2 in the Stream Output Control Register, SOCR0 to SOCR15 as shown in Table 24 on page 48 and Table 25 on
page 49.
2.2.2
Frame Pulse Output and Clock Output Timing
The device offers three frame pulse outputs, FPo0, FPo1 and FPo2. All output frame pulses are 8kHz output
signals. By default, output frame boundary is defined by the falling edge of the CKo0, CKo1 or CKo2 output clocks
while the FPo0, FPo1 or FPo2 output frame pulse goes low respectively.
In addition to the default settings, users can also select different output frame pulse low cycles and output clock
frequencies by programming the CKFP0, CKFP1 and CKFP2 bits in the Control Register. See Table 2, Table 3 and
Table 4 for the bit usage in the Control Register:
CKFP0
FPo0
Low Cycle
CKo0
0
244 ns
4.096 MHz
1
122 ns
8.192 MHz
Table 2 - FPo0 and CKo0 Output Programming
CKFP1
FPo1
CKo1
0
61 ns
16.384 MHz
1
122 ns
8.192 MHz
Table 3 - FPo1 and CKo1 Output Programming
CKFP2
FPo2
CKo2
0
30 ns
32.768 MHz
1
61 ns
16.384 MHz
Table 4 - FPo2 and CKo2 Output Programming
19
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
The device also delivers positive or negative output frame pulse and ST-BUS output clock formats via the
programming of the FP0P, FP1P, FP2P, CK0P, CK1P and CK2P bits in the Internal Mode Selection (IMS) register.
By default, the device delivers the negative output frame pulse and negative output clock formats.
Figure 8 to Figure 13 describe the usage of the CKFP0, CKFP1, CKFP2, FP0P, FP1P, FP2P, CK0P, CK1P and
CK2P in the Control Register and Internal Mode Selection Register:
FPo0
(8 kHz)
FP0P = 0
FPo0
FP0P = 1
CKo0
(4.096 MHz)
CKOP = 0
CKo0
(4.096 MHz)
CKOP = 1
Figure 8 - FPo0 and CKo0 Output Timing when the CKFP0 bit = 0
FPo0
FPOP = 0
FPo0
FPOP =1
CKo0
(8.192 MHz)
CKOP = 0
CKo0
(8.192 MHz)
CKOP = 1
Figure 9 - FPo0 and CKo0 Output Timing when the CKFP0 bit = 1
FPo1
FP1P = 0
FPo1
FP1P = 1
CKo1
(16.384 MHz)
CK1P = 0
CKo1
(16.384 MHz)
CK1P = 1
Figure 10 - FPo1 and CKo1 Output Timing when the CKFP1 bit = 0
20
Zarlink Semiconductor Inc.
ZL50012
FPo1
FP1P = 0
FPo1
FP1P =1
CKo1
(8.192 MHz)
CK1P = 0
CKo1
(8.192 MHz)
CK1P = 1
Figure 11 - FPo1 and CKo1 Output Timing when the CKFP1 bit = 1
FPo2
FP2P = 0
FPo2
FP2P = 1
CKo2
(32.768 MHz)
CK2P = 0
CKo2
(32.768 MHz)
CK2P = 1
Figure 12 - FPo2 and CKo2 Output Timing when the CKFP2 bit = 0
FPo2
FP2P = 0
FPo2
FP2P = 1
CKo2
(16.384 MHz)
CK2P = 0
CKo2
(16.384 MHz)
CK2P = 1
Figure 13 - FPo2 and CKo2 Output Timing when the CKFP2 bit = 1
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Zarlink Semiconductor Inc.
Data Sheet
ZL50012
2.2.3
Data Sheet
ST-BUS Output Timing
By default, the output frame boundary is defined by the falling edge of the CKo0, CKo1 or CKo2 output clock while
the FPo0, FPo1 or FPo2 output frame pulse goes low respectively. When the output data rates are 2.048 Mb/s,
4.096 Mb/s and 8.192 Mb/s, there are 32, 64 or 128 output channels per every ST-BUS frame respectively. Figure
14 describes the details.
FPo0
(8 kHz)
CKo
(4.096 MHz)
FPo0 or FPo1
CKo0 or CKo1
(8.192 MHz)
FPo1 or FPo2
CKo1 or CKo2
(16.384 MHz)
FPo2
CKo2
(32.768 MHz)
Channel 31
Channel 0
STo
(2.048 Mb/s)
7
0
5
6
3
4
2
1
0
7
6
5
Channel 0
STo
(8.192 Mb/s)
4
3
7
0
Channel 63
Channel 0
STo
(4.096 Mb/s)
1
2
1
0
Channel 1
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Output Frame Boundary
6
5
Channel 126
4
3
2
1
Channel 127
Figure 14 - ST-BUS Output Timing for Various Output Data Rates
Zarlink Semiconductor Inc.
7
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
Output Frame Boundary
22
0
ZL50012
2.3
Data Sheet
Serial Data Input Delay and Serial Data Output Offset
Various registers are provided to adjust the input and output delays for every input and every output data stream.
The input and output channel delay can vary from 0 to 31, 0 to 63 and 0 to 127 channel(s) for the 2.048 Mb/s,
4.096 Mb/s and 8.192 Mb/s modes respectively.
The input and output bit delay can vary from 0 to 7 bits. The fractional input bit delay can vary from 1/4, 1/2, 3/4 to
4/4 bit. The fractional output bit advancement can vary from 0, 1/4, 1/2 to 3/4 bit.
2.3.1
Input Channel Delay Programming
This feature allows each input stream to have a different input frame boundary with respect to the input frame
boundary defined by the FPi and CKi. By default, all input streams have channel delay of zero such that Ch0 is the
first channel that appears after the input frame boundary (see Figure 15).
The input channel delay programming is enabled by setting Bit 3 to 9 in the Stream Input Delay Register (SIDR).
The input channel delay can vary from 0 to 31, 0 to 63 and 0 to 127 for the 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s
modes respectively.
FPi
Last Channel
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Delay = 1
Last Channel
STiX
Channel Delay = 1
Last Channel -1
Ch 1
Ch 0
STiX
Channel Delay = 0
(Default)
Last Channel -2
Ch 0
Last Channel -1
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Delay = 2
Last Channel -1
STiX
Channel Delay = 2
Note: X = 0 to 15
Last Channel
Ch0
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Last Channel -2
7 6 5 4 3 2 1 0 7 6
Note: Last Channel = 31, 63, 127 for 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s mode respectively
Input Frame Boundary
Figure 15 - Input Channel Delay Timing Diagram
2.3.2
Input Bit Delay Programming
In addition to the input channel delay programming, the input bit delay programming feature provides users with
more flexibility when designing the switch matrices at high speed, in which the delay lines are easily created on
PCM highways which are connected to the switch matrix cards.
By default, all input streams have zero bit delay such that Bit 7 is the first bit that appears after the input frame
boundary, see Figure 16. The input delay is enabled by Bit 0 to 2 in the Stream Input Delay Registers (SIDR). The
input bit delay can vary from 0 to 7 bits.
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Zarlink Semiconductor Inc.
ZL50012
2.3.3
Data Sheet
Fractional Input Bit Delay Programming
In addition to the input bit delay feature, the device allows users to change the sampling point of the input bit. By
default, the sampling point is at 3/4 bit. Users can change the sampling point to 1/4, 1/2, 3/4 or 4/4 bit position by
programming Bit 3 and 4 of the Stream Input Control Registers (SICR).
FPi
Ch0
Last Channel
STiX
Bit Delay = 0
(Default)
3
2
1
0
7
6
5
4
Ch1
3
2
1
0
7
6
5
3
2
1
0
7
6
4
Bit Delay = 1
STiX
Bit Delay = 1
4
3
Ch1
Ch0
Last Channel
2
1
0
7
6
5
4
5
Note: X = 0 to 15
Input Frame Boundary
Note: Last Channel = 31, 63, 127 for 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s mode respectively
Figure 16 - Input Bit Delay Timing Diagram
2.3.4
Output Channel Delay Programming
This feature allows each output stream to have a different output frame boundary with respect to the output frame
boundary defined by the output frame pulse (FPo0, FPo1 and FPo2) and the output clock (CKo0, CKo1 or CKo2).
By default, all output streams have zero channel delay such that Ch 0 is the first channel that appears after the
output frame boundary as shown in Figure 17. Different output channel delay can be set by programming Bit 5 to 11
in the Stream Output Offset Registers (SOOR). The output channel delay can vary from 0 to 31, 0 to 63 and 0 to
127 for the 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s modes respectively.
FPo
Ch 0
SToX
Channel Delay = 0
(Default)
SToX
Channel Delay = 2
Last Channel -2
Ch 0
Delay = 2
Last Channel
Last Channel -1
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Last Channel -1
Last Channel
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Delay = 1
Last Channel
SToX
Channel Delay = 1
Last Channel -1
Ch 1
Ch0
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Last Channel -2
7 6 5 4 3 2 1 0 7 6
Note: X = 0 to 15 Note: Last Channel = 31, 63, 127 for 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s mode respectively
Output Frame Boundary
Figure 17 - Output Channel Delay Timing Diagram
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Zarlink Semiconductor Inc.
ZL50012
2.3.5
Data Sheet
Output Bit Delay Programming
This feature is used to delay the output data bit of individual output streams with respect to the output frame
boundary. Each output stream can have its own bit delay value.
By default, all output streams have zero bit delay such that Bit 7 is the first bit that appears after the output frame
boundary (see Figure 18 on page 25). Different output bit delay can be set by programming Bit 2 to 4 in the Stream
Output Offset Registers. The output bit delay can vary from 0 to 7 bits.
FPo
Last Channel
SToX
Bit Delay = 0
(Default)
3
2
1
Ch0
0
7
6
5
4
Ch1
3
2
1
0
7
6
5
4
Bit Delay = 1
SToX
Bit Delay = 1
3
4
2
Ch1
Ch0
Last Channel
1
7
0
6
5
4
3
2
1
0
7
6
5
Note: X = 0 to 15
Output Frame Boundary
Note: Last Channel = 31, 63, 127 for 2.048Mb/s, 4.096Mb/s and 8.192Mb/s mode respectively
Figure 18 - Output Bit Delay Timing Diagram
2.3.6
Fractional Output Bit Advancement Programming
In addition to the output bit delay, the device is also capable of performing fractional output bit advancement. This
feature offers a better resolution for the output bit delay adjustment. The fractional output bit advancement is useful
in compensating for various parasitic loadings on the serial data output pins.
By default, all output streams have zero fractional bit advancement such that Bit 7 is the first bit that appears after
the output frame boundary as shown in Figure 19. The fractional output bit advancement is enabled by Bit 0 to 1 in
the Stream Output Offset Registers. The fractional bit advancement can vary from 0, 1/4, 1/2 or 3/4 bit.
FPo
Ch0
Last Channel
SToY
Fractional Bit Adv. = 0
(Default)
Bit 1
Bit 7
Bit 0
Bit 6
Fractional Bit Advancement = 1/4 bit
Last Channel
SToY
Fractional Bit Adv. = 1/4 bit
Bit 1
Ch0
Bit 7
Bit 0
Bit 6
Note: Y = 0 to 15
Output Frame Boundary
Note: Last Channel = 31, 63, 127 for 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s mode respectively
Figure 19 - Fractional Output Bit Advancement Timing Diagram
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Zarlink Semiconductor Inc.
ZL50012
2.3.7
Data Sheet
External High Impedance Control, STOHZ 0 to 15
The STOHZ 0 to 15 outputs are provided to control the external tristate ST-BUS drivers for per-channel high
impedance operations. The STOHZ outputs are sent out in 32, 64 or 128 timeslots corresponding to the output
channels for 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s output streams respectively. Each control timeslot lasts for
one channel time.
When the ODE pin is high, the STOHZ 0 - 15 are enabled. When the ODE pin or the RESET pin is low, the STOHZ
0 - 15 are driven high. STOHZ outputs are also driven high if their corresponding ST-BUS outputs are not in use.
Figure 20 gives an example when channel 2 of a given ST-BUS output is programmed in the high impedance state,
the corresponding STOHZ pin drives high for one channel time at the channel 2 timeslot.
By default, the output timing of the STOHZ signals follow the same timing as their corresponding STo signals
including any user-programmed output channel and bit delay and fractional bit advancement. In addition, the device
allows users to advance the STOHZ signals from their default positions to a maximum of four 15.2 ns steps (or four
1/4 bit steps) using Bit 3 to 5 of the Stream Output Control Register (SOCR). Bit 6 in the Stream Output Control
Register selects the step resolution as 15.2 ns or 1/4 data bit. The additional advancement feature allows the
STOHZ signals to better match the high impedance timing required by the external ST-BUS drivers.
FPo
HiZ
SToY
Last Ch
Ch0
Ch1
Ch2
Ch3
Last Ch -2 Last Ch-1
STOHZ Y
(Default = No Adv.)
STOHZ Advancement (Programmable in 4 steps of 15.2 ns or 1/4 bit)
STOHZ Y
(With Adv.)
Note: Y = 0 to 15
Output Frame Boundary
Note: Last Channel = 31, 63, 127 for 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s mode respectively
Figure 20 - Example: External High Impedance Control Timing
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Zarlink Semiconductor Inc.
Last Ch
Ch0
ZL50012
2.4
Data Sheet
Data Delay Through The Switching Paths
To maintain the channel integrity in the constant delay mode, the usage of the input channel delay and output
channel delay modes affect the data delay through various switching paths due to additional data buffers. The
usage of these data buffers is enabled by the input and output channel delay bits (STIN#CD6-0 and STO#CD6-0) in
the Stream Input Delay and Stream Output Offset Registers. However, the input and output bit delay or the input
and output fractional bit offset have no impact on the overall data throughput delay.
In the following paragraphs, the data throughput delay (T) is expressed as a function of ST-BUS frames, input
channel number (m), output channel number (n), input channel delay (α) and output channel delay (β). Table 5
describes the variable range for input streams and Table 6 describes the variable range for output streams. Table 7
summarizes the data throughput delay under various input channel and output channel delay conditions.
Input Stream
Data Rate
Input Channel
Number (m)
Possible Input channel delay (α)
2 Mb/s
0 to 31
1 to 31
4 Mb/s
0 to 63
1 to 63
8 Mb/s
0 to 127
1 to 127
Table 5 - Variable Range for Input Streams
Output Stream
Data Rate
Output Channel
Number (n)
Possible Output channel
delay (β)
2 Mb/s
0 to 31
1 to 31
4 Mb/s
0 to 63
1 to 63
8 Mb/s
0 to 127
1 to 127
Table 6 - Variable Range for Output Streams
Input Channel Delay OFF
Output Channel Delay OFF
T = 2 frames + (n-m)
Input Channel Delay ON
Output Channel Delay OFF
Input Channel Delay OFF
Output Channel Delay ON
Input Channel Delay ON
Output Channel Delay ON
T = 3 frames - α + (n-m)
T = 2 frames + β + (n-m)
T= 3 frames - α + β + (n-m)
Table 7 - Data Throughput Delay
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Zarlink Semiconductor Inc.
ZL50012
Data Sheet
By default, when the input channel delay and output channel delay are set to zero, the data throughput delay (T) is:
T = 2 frames + (m-n). Figure 21 shows the throughput delay when the input Ch0 is switched to the output Ch0.
Frame
Serial Input Data
(No Delay)
Frame N+1
Frame N
Frame N Data
Frame N+2
Frame N+1Data
Frame N+3
Frame N+4
Frame N+5
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
2 Frames + 0
Serial Output Data
(No Delay)
Frame N-2 Data
Frame N-1 Data
Figure 21 - Data Throughput Delay when input and output channel delay are disabled for Input
Ch0 switched to Output Ch0
When the input channel delay is enabled and the output channel delay is disabled, the data throughput delay is: T =
3 frames - α + (m-n). Figure 22 shows the data throughput delay when the input Ch0 is switched to the output Ch0.
Frame
Serial Input Data
(α = 1)
Frame N
Frame N+1
Frame N Data
Frame N+2
Frame N+1 Data
Frame N+3
Frame N+2 Data
Frame N+3 Data
Frame N+4
Frame N+4 Data
Frame N+5
Frame N+5 Data
Input Channel Delay (from 1 to max# of channels, programmed by the STIN#CD6-0 bit)
Serial Input Data
(α > 1)
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
3 Frames - α + 0
3 Frames - 1 channel + 0
Serial Output Data
(No Delay)
Frame N-3 Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Figure 22 - Data Throughput Delay when input channel delay is enabled and output channel
delay is disabled for Input Ch0 switched to Output Ch0
When the input channel delay is disabled and the output channel delay is enabled, the throughput delay is: T = 2
frames + β + (m-n). Figure 23 shows the data throughput delay when the input Ch0 is switched to the output Ch0.
Frame
Serial Input
(No Delay)
Frame N
Frame N Data
Frame N+1
Frame N+2
Frame N+1 Data
Frame N+2 Data
Frame N+3
Frame N+3 Data
Frame N+4
Frame N+4 Data
Frame N+5
Frame N+5 Data
2 Frames + 1 + 0
Serial Output Data
(β = 1)
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
Output Channel Delay: (from 1 to max# of channels,
programmed by the STO#CD6-0 bit)
2 Frames + β + 0
Serial Output Data
(β > 1)
Frame N-3 Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Figure 23 - Data Throughput Delay when input channel delay is disabled and output channel
delay is enabled for Input Ch0 switch to Output Ch0
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Zarlink Semiconductor Inc.
ZL50012
Data Sheet
When the input channel delay and the output channel delay are enabled, the data throughput delay is: T = 3 frames
- α + β + (m-n). Figure 24 shows the data throughput delay when the input Ch0 is switched to the output Ch0.
Frame
Serial Input Data
(α = 1)
Frame N
Frame N+1
Frame N Data
Frame N+1 Data
Frame N+2
Frame N+3
Frame N+2 Data
Frame N+3 Data
Frame N+4
Frame N+4 Data
Frame N+5
Frame N+5 Data
Input Channel Delay:(from 1 to max# of channels, programmed by the STIN#CD6-0 bit)
Serial Input Data
(α > 1)
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
3 Frames - α + 1 + 0
3 Frames - 1 + 1 + 0
Serial Output Data
(β = 1)
Frame N-3 Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Output Channel Delay: (from 1 to max# of channels,
programmed by the STO#CD6-0 bit)
3 Frames - α + β + 0
3 Frames - 1 + β + 0
Serial Output Data
(β > 1)
Frame N-4 Data
Frame N-3 Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Figure 24 - Data Throughput Delay when input and output channel delay are enabled for Input
Ch0 switched to Output Ch0
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Zarlink Semiconductor Inc.
ZL50012
2.5
Data Sheet
Connection Memory Description
The connection memory is 12-bit wide. There are 512 memory locations to support the ST-BUS serial outputs
STo0-15. The address of each connection memory location corresponds to an output destination stream number
and an output channel address. See Table 28 on page 52 for the connection memory address map.
When Bit 0 of the connection memory is low, Bit 1 to 7 define the source (input) channel address and Bit 8 to 11
define the source (input) stream address. Once the source stream and channel addresses are programmed by the
microprocessor, the contents of the data memory at the selected address are switched to the mapped output
stream and channel. See Table 29 on page 53 for details on the memory bit assignment when Bit 0 of the
connection memory is low.
When Bit 0 of the connection memory is high, Bit 1 and 2 define the per-channel control modes of the output
streams, the per-channel high impedance output control, the per-channel message and the per-channel BER test
modes. In the message mode, the 8-bit message data located in Bit 3 to 10 of the connection memory will be
transferred directly to the mapped output stream. See Table 30 on page 53 for details on the memory bit
assignment when Bit 0 of the connection memory is high.
2.5.1
Connection Memory Block Programming
This feature allows fast initialization of the entire connection memory after power up. When block programming
mode is enabled, the content of Bit 1 to 3 in the Internal Mode Selection (IMS) Register will be loaded into Bit 0 to 2
of all the 512 connection memory locations. The other bit positions of the connection memory will be loaded
with zeros.
Memory block programming procedure:
(Assumption: The MBPE and MBPS bits are both low at the start of the procedure)
•
Program Bit 1 to 3 (BPD0 to BPD2) in the IMS (Internal Mode Selection) register.
•
Set the Memory Block Programming Enable (MBPE) bit in the Control Register to high to enable the block
programming mode.
•
Set the Memory Block Programming Start (MBPS) bit to high in the IMS Register to start the block
programming. The BPD0 to BPD2 bits will be loaded into Bit 0 to 2 of the connection memory. The other bit
positions of the connection memory will be loaded with zeros. The memory content after block programming
is shown in Table 8.
•
It takes 50µs for the connection memory to be loaded with the bit pattern defined by the BPD0 to BPD2 bits.
•
After loading the bit pattern to the entire connection memory, the device will reset the MBPS bit to low,
indicating that the process has finished.
•
Upon completion of the block programming, set the MBPE bit from high to low to disable the block
programming mode.
Note: Once the block programming is started, it can be terminated at any time prior to completion by setting the
MBPS bit or the MBPE bit to low. If the MBPE bit is used to terminate the block programming before completion,
users have to set the MBPS bit from high to low before enabling other device operation.
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
BPD2
BPD1
BPD0
Table 8 - Connection Memory in Block Programming Mode
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Zarlink Semiconductor Inc.
ZL50012
2.6
Data Sheet
Bit Error Rate (BER) Test
The ZL50012 has one on-chip BER transmitter and one BER receiver. The transmitter can transmit onto a single
STo output stream only. The transmitter provides a BER sequence (215-1 Pseudo Random Code) which can start
from any channel in the frame and lasts from one channel up to one frame time (125 µs). The transmitter output
channel(s) are specified by programming the connection memory location(s) corresponding to the channel(s) of the
selected output stream: Bit 0 to 2 of the connection memory location(s) should be programmed to the BER test
mode (see Table 30 on page 53).
Multiple connection memory locations can be programmed for BER test such that the BER patterns can be
transmitted for several output channels which are consecutive. If the transmitting output channels are not
consecutive, the BER receiver will not compare the bit patterns correctly.
The number of output channels which the BER transmitter occupies also has to be the same as the number of
channels defined in the BER Length Register. The BER Length Register defines how many BER channels to be
monitored by the BER receiver.
Registers used for setting up the BER test are as follows:
•
Control Register (CR) - The CBER bit is used to clear the bit error counter and the BER Count Register
(BCR). The SBER bit is used to start or stop the BER transmitter and BER receiver.
•
BER Start Receiving Register (BSRR) - Defines the input stream and channel from where the BER
sequence will start to be compared.
•
BER Length Register (BLR) - Defines how many channels the sequence will last.
•
BER Count Register (BCR) - Contains the number of counted errors. When the error count reaches Hex
FFFF, the bit error counter will stop so that it will not overflow. Consequently the BER Count Register will
also stop at FFFF. The CBER bit in the Control Register is used to reset the bit error counter and the BER
Count Register.
As described above, the SBER bit in the control register controls the BER transmitter and receiver. To carry out the
BER test, users should set the SBER bit to zero to disable the BER transmitter during the programming of the
connection memory for the BER test. When the BER transmitter is disabled, the transmitter output is all ones.
Hence any output channel whose connection memory has been programmed to BER test mode will also output all
ones. Upon the completion of programming the connection memory for the BER test, set the SBER bit to one to
start the BER transmitter and receiver for the BER testing. They must be allowed to run for several frames (2
frames plus the network delay between STo and STi) before the BER receiver can correctly identify errors in the
pattern. Thus after this time the bit error counter should be reset by using the CBER bit in the Control Register - set
CBER to one then back to zero. From now on, the count will be the actual number of errors which occurred during
the test. The count will stop at FFFF and the counter will not increment even if more errors occurred.
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Zarlink Semiconductor Inc.
ZL50012
2.7
Data Sheet
Quadrant frame programming
By programming the input stream control registers (SICR0 to 15), users can divide one frame of input data into four
quadrant frames and can force the Least Significant Bit (LSB, bit 0 in Figure 7 on page 18), of every input channel
in these quadrants into "1" for the bit robbed signaling purpose. The four quadrant frames are defined as shown in
Table 9.
Data Rate
Quadrant 0
Quadrant 1
Quadrant 2
Quadrant 3
2.048 Mb/s
Ch 0 to 7
Ch 8 to 15
Ch 16 to 23
Ch 24 to 31
4.096 Mb/s
Ch 0 to 15
Ch 16 to 31
Ch 32 to 47
Ch 48 to 63
8.192 Mb/s
Ch 0 to 31
Ch 32 to 63
Ch 64 to 95
Ch 96 to 127
Table 9 - Definition of the Four Quadrant Frames
When a quadrant frame enable bit (STIN#QEN0, STIN#QEN1, STIN#QEN2 or STIN#QEN3) is set to high, the LSB
of every input channels in the quadrant is forced to "1". See Table 10 to Table 13 for details:
STIN#QEN0
Action
1
Replace LSB of every channel in Quadrant 0 with "1"
0
No bit replacement occurs in Quadrant 0
Table 10 - Quadrant Frame 0 LSB Replacement
STIN#QEN1
Action
1
Replace LSB of every channel in Quadrant 1 with "1"
0
No bit replacement occurs in Quadrant 1
Table 11 - Quadrant Frame 1 LSB Replacement
STIN#QEN2
Action
1
Replace LSB of every channel in Quadrant 2 with "1"
0
No bit replacement occurs in Quadrant 2
Table 12 - Quadrant Frame 2 LSB Replacement
STIN#QEN3
Action
1
Replace LSB of every channel in Quadrant 3 with "1"
0
No bit replacement occurs in Quadrant 3
Table 13 - Quadrant Frame 3 LSB Replacement
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ZL50012
2.8
Data Sheet
Microprocessor Port
The device supports the non-multiplexed microprocessor. The microprocessor port consists of a 16-bit parallel data
bus (D0 to 15), a 12-bit address bus (A0 to 11) and four control signals (CS, DS, R/W and DTA). The parallel
microprocessor port provides fast access to the internal registers, the connection and the data memories.
The connection memory locations can be read or written via the 16-bit microprocessor port. On the other hand, the
data memory locations can only be read (but not written) from the microprocessor port.
For the connection memory write operation, D0 to 11 of the data bus will be used and D12 to 15 are ignored (D12 to
15 should be driven low). For the connection memory read operation, D0 to D11 will be used and D12 to D15 will
output zeros. For the data memory read operation, D0 to D7 will be used and D8 to D15 will output zeros.
See Table 28 on page 52 for the address mapping of the data memory. Refer to Figure 36 on page 65 for the
microprocessor port timing.
3.0
Device Reset and Initialization
The RESET pin is used to reset the device. When the pin is low, it synchronously puts the device in its reset state.
It disables the STo0 - 15 outputs, drives the STOHZ 0 - 15 outputs to high, clears the device registers and the
internal counters.
Upon power up, the device should be initialized as follows:
•
Set ODE pin to low to disable the STo0-15 output and to drive the STOHZ 0-15 to high.
•
Set the TRST pin to low to disable the JTAG TAP controller.
•
Reset the device by pulsing the RESET pin to low for longer than 1ms.
•
After releasing the RESET pin from low to high, wait for 600 µs for the APLL module to be stabilized before
starting the first microprocessor port access cycle.
•
Program the register to define the frequency of the CKi input.
•
Wait for 600 µs for the APLL module to be stabilized before starting the next microprocessor port access
cycle.
•
Use the memory block programming mode to initialize the connection memory.
•
Release the ODE pin to high after the connection memory is programmed such that bus contention will not
occur at the serial stream outputs STo0-15.
4.0
JTAG Support
The ZL50012 JTAG interface conforms to the Boundary-Scan IEEE1149.1 standard. The operation of the
boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
4.1
Test Access Port (TAP)
The Test Access Port (TAP) accesses the ZL50012 test functions. It consists of three input pins and one output pin
as follows:
•
Test Clock Input (TCK) - TCK provides the clock for the test logic. The TCK does not interfere with any onchip clock and thus remains independent in the functional mode. The TCK permits shifting of test data into or
out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering
with the on-chip logic.
•
Test Mode Select Input (TMS) - The TAP Controller uses the logic signals received at the TMS input to
control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is
internally pulled to Vdd when it is not driven from an external source.
33
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
•
Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a
test data register, depending on the sequence previously applied to the TMS input. Both registers are
described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses.
This pin is internally pulled to Vdd when it is not driven from an external source.
•
Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or data register are serially shifted out towards the TDO. The data out of the
TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan
cells, the TDO driver is set to a high impedance state.
•
Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to Vdd when it is not driven
from an external source.
4.2
Instruction Register
The ZL50012 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a fourbit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP
Controller is in its shifted-IR state. These instructions are subsequently decoded to achieve two basic functions: to
select the test data register that may operate while the instruction is current and to define the serial test data
register path that is used to shift data between TDI and TDO during data register scanning.
4.3
Test Data Register
As specified in IEEE 1149.1, the ZL50012 JTAG Interface contains three test data registers:
•
The Boundary-Scan Register - The Boundary-Scan register consists of a series of Boundary-Scan cells
arranged to form a scan path around the boundary of the ZL50012 core logic.
•
The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from
TDI to its TDO.
•
The Device Identification Register - The JTAG device ID for the ZL50012 is 0C35C14BH.
Version<31:28>:
0000
Part No. <27:12>:
1100 0011 0101 1100
Manufacturer ID<11:1>: 0001 0100 101
LSB<0>:
1
4.4
BSDL
A BSDL (Boundary Scan Description Language) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149 test interface.
34
Zarlink Semiconductor Inc.
ZL50012
5.0
Data Sheet
Register Address Mapping
External
Address
A11 - A0
CPU
Access
000H
R/W
Control Register, CR
001H
R/W
Internal Mode Selection, IMS
010H
R/W
BER Start Receive Register, BSRR
011H
R/W
BER Length Register, BLR
Register
012H
Read Only
BER Count Register, BCR
030H
Read Only
Reserved
031H
Read Only
Reserved
032H
Read Only
Reserved
100H
R/W
Stream0 Input Control Register, SICR0
101H
R/W
Stream0 Input Delay Register, SIDR0
102H
R/W
Stream1 Input Control Register, SICR1
103H
R/W
Stream1 Input Delay Register, SIDR1
104H
R/W
Stream2 Input Control Register, SICR2
105H
R/W
Stream2 Input Delay Register, SIDR2
106H
R/W
Stream3 Input Control Register, SICR3
107H
R/W
Stream3 Input Delay Register, SIDR3
108H
R/W
Stream4 Input Control Register, SICR4
109H
R/W
Stream4 Input Delay Register, SIDR4
10AH
R/W
Stream5 Input Control Register, SICR5
10BH
R/W
Stream5 Input Delay Register, SIDR5
10CH
R/W
Stream6 Input Control Register, SICR6
10DH
R/W
Stream6 Input Delay Register, SIDR6
10EH
R/W
Stream7 Input Control Register, SICR7
10FH
R/W
Stream7 Input Delay Register, SIDR7
110H
R/W
Stream8 Input Control Register, SICR8
111H
R/W
Stream8 Input Delay Register, SIDR8
112H
R/W
Stream9 Input Control Register, SICR9
113H
R/W
Stream9 Input Delay Register, SIDR9
114H
R/W
Stream10 Input Control Register, SICR10
115H
R/W
Stream10 Input Delay Register, SIDR10
116H
R/W
Stream11 Input Control Register, SICR11
117H
R/W
Stream11 Input Delay Register, SIDR11
118H
R/W
Stream12 Input Control Register, SICR12
119H
R/W
Stream12 Input Delay Register, SIDR12
11AH
R/W
Stream13 Input Control Register, SICR13
Table 14 - Address Map for Device Specific Registers
35
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
External
Address
A11 - A0
CPU
Access
11BH
R/W
Stream13 Input Delay Register, SIDR13
11CH
R/W
Stream14 Input Control Register, SICR14
11DH
R/W
Stream14 Input Delay Register, SIDR14
11EH
R/W
Stream15 Input Control Register, SICR15
11FH
R/W
Stream15 Input Delay Register, SIDR15
200H
R/W
Stream0 Output Control Register, SOCR0
Register
201H
R/W
Stream0 Output Delay Register, SOOR0
202H
R/W
Stream1 Output Control Register, SOCR1
203H
R/W
Stream1 Output Delay Register, SOOR1
204H
R/W
Stream2 Output Control Register, SOCR2
205H
R/W
Stream2 Output Delay Register, SOOR2
206H
R/W
Stream3 Output Control Register, SOCR3
207H
R/W
Stream3 Output Delay Register, SOOR3
208H
R/W
Stream4 Output Control Register, SOCR4
209H
R/W
Stream4 Output Delay Register, SOOR4
20AH
R/W
Stream5 Output Control Register, SOCR5
20BH
R/W
Stream5 Output Delay Register, SOOR5
20CH
R/W
Stream6 Output Control Register, SOCR6
20DH
R/W
Stream6 Output Delay Register, SOOR6
20EH
R/W
Stream7 Output Control Register, SOCR7
20FH
R/W
Stream7 Output Delay Register, SOOR7
210H
R/W
Stream8 Output Control Register, SOCR8
211H
R/W
Stream8 Output Delay Register, SOOR8
212H
R/W
Stream9 Output Control Register, SOCR9
213H
R/W
Stream9 Output Delay Register, SOOR9
214H
R/W
Stream10 Output Control Register, SOCR10
215H
R/W
Stream10 Output Delay Register, SOOR10
216H
R/W
Stream11 Output Control Register, SOCR11
217H
R/W
Stream11 Output Delay Register, SOOR11
218H
R/W
Stream12 Output Control Register, SOCR12
219H
R/W
Stream12 Output Delay Register, SOOR12
21AH
R/W
Stream13 Output Control Register, SOCR13
21BH
R/W
Stream13 Output Delay Register, SOOR13
21CH
R/W
Stream14 Output Control Register, SOCR14
21DH
R/W
Stream14 Output Delay Register, SOOR14
21EH
R/W
Stream15 Output Control Register, SOCR15
21FH
R/W
Stream15 Output Delay Register, SOOR15
Table 14 - Address Map for Device Specific Registers
36
Zarlink Semiconductor Inc.
ZL50012
6.0
Data Sheet
Detail Register Description
External Read/Write Address: 000H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FBD
MODE
0
FBD
EN
CKIN
2
CKIN
1
CKIN
0
CKFP
2
CKFP
1
CKFP
0
CBER
SBER
MBPE
OSB
MS2
MS1
MS0
Bit
Name
Description
15
FBDMODE
Frame Boundary Determination Mode Select.
When either the FBDEN or FBDMODE bit is set low, the frame boundary discriminator
(FBD) is disabled.
When both the FBDEN and FBDMODE bits are set HIGH, the frame discriminator (FBD)
is enabled. The device will have 20 ns of input clock jitter tolerance (on CKi and FPi)
when the FBD is enabled.
By default, the FBDEN and FBDMODE bits are Low. Both the FBDEN and FBDMODE
bits should be set HIGH during normal operation.
14
Unused
Reserved. In normal functional mode, this bit MUST be set to zero.
13
FBDEN
Frame Boundary Determinator Enable.
When either the FBDEN or FBDMODE bit is set low, the frame boundary discriminator
(FBD) is disabled.
When both the FBDEN and FBDMODE bits are set HIGH, the frame discriminator (FBD)
is enabled. The device will have 20 ns of input clock jitter tolerance (on CKi and FPi)
when the FBD is enabled.
By default, the FBDEN and FBDMODE bits are Low. Both the FBDEN and FBDMODE
bits should be set HIGH during normal operation.
12 - 10
CKIN2-0
Input ST Bus Clock (CKi) and Frame Pulse (FPi) Selection.
CKIN2 - 0
FPi Low Cycle
CKi
000
61 ns
16.384 MHz
001
122 ns
8.192 MHz
010
244 ns
4.096 MHz
011 - 111
Reserved
9
CKFP2
Output ST Bus clock CKo2 and frame pulse FPo2 Selection.
When this bit is low, CKo2 is 32.768 MHz clock and FPo2 is 30 ns wide frame pulse
When this bit is high, CKo2 is 16.384 MHz clock and FPo2 is 61 ns wide frame pulse
8
CKFP1
Output ST Bus clock CKo1 and frame pulse FPo1 Selection.
When this bit is low, CKo1 is 16.384 MHz clock and FPo1 is 61 ns wide frame pulse
When this bit is high, CKo1 is 8.192 MHz clock and FPo1 is 122 ns wide frame pulse
7
CKFP0
Output ST Bus clock CKo0 and frame pulse FPo0 Selection.
When this bit is low, CKo0 is 4.096 MHz clock and FPo0 is 244 ns wide frame pulse
When this bit is high, CKo0 is 8.192 MHz clock and FPo0 is 122 ns wide frame pulse
Table 15 - Control Register (CR) Bits
37
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
External Read/Write Address: 000H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FBD
MODE
0
FBD
EN
CKIN
2
CKIN
1
CKIN
0
CKFP
2
CKFP
1
CKFP
0
CBER
SBER
MBPE
OSB
MS2
MS1
MS0
Bit
Name
Description
6
CBER
Bit Error Rate Counter Clear: When this bit is high, it resets the internal bit error
counter and the content of the bit error count register (BCR) to zero. Upon completion of
the reset, set this bit to zero.
5
SBER
Bit Error Rate Test Start: When this bit is high, it enables the BER transmitter and
receiver; starts the bit error rate test. The bit error test result is kept in the bit error count
(BCR) register. Upon the completion of the BER test, set this bit to zero.
4
MBPE
Memory Block Programming Enable: When this bit is high, the connection memory
block programming mode is enabled to program Bit 0 to Bit 2 of the connection memory.
When it is low, the memory block programming mode is disabled.
3
OSB
2-0
MS2-0
Output Stand By Bit: This bit enables the STo0 - 15 and the STOHZ 0 -15 serial outputs. The following table describes the HiZ control of the serial data outputs:
RESET
Pin
ODE
Pin
OSB
Bit
0
X
X
HiZ
Driven High
1
0
X
HiZ
Driven High
1
1
0
HiZ
Driven High
1
1
1
Active
Active
STo0-15
STOHZ 0-15
Memory Select Bit. These bits are used to select connection memory or data memory:
MS2 - 0
Memory Selection
000
Connection Memory Read/Write
001
Data memory Read
010 - 111
Reserved
Table 15 - Control Register (CR) Bits (continued)
38
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
External Read/Write Address: 001H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
CKINP
FPINP
CK2P
FP2P
CK1P
FP1P
CK0P
FP0P
BPD
2
BPD
1
BPD
0
MBPS
Bit
Name
Description
15 - 12
Unused
Reserved. In normal functional mode, these bits MUST be set to zero.
11
CKINP
ST Bus Clock Input (CKi) Polarity.
When this bit is low, the CKi falling edge aligns with the frame boundary.
When this bit is high, the CKi rising edge aligns with the frame boundary.
10
FPINP
Frame Pulse Input (FPi) Polarity.
When this bit is low, the input frame pulse FPi should have the negative frame pulse
format. When this bit is high, the input frame pulse FPi should have the positive frame
pulse format.
9
CK2P
ST Bus Clock Output (CKo2) Polarity.
When this bit is low, the output clock CKo2 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo2 rising edge aligns with the
frame boundary.
8
FP2P
Frame Pulse Output (FPo2) Polarity.
When this bit is low, the output frame pulse FPo2 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo2 has the positive frame pulse format.
7
CK1P
ST Bus Clock Output (CKo1) Polarity.
When this bit is low, the output clock CKo1 falling edge aligns with the frame boundary. When this bit is high, the output clock CKo1 rising edge aligns with the frame
boundary.
6
FP1P
Frame Pulse Output (FPo1) Polarity.
When this bit is low, the output frame pulse FPo1 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo1 has the positive frame pulse format.
5
CK0P
ST Bus Clock Output (CKo0) Polarity.
When this bit is low, the output clock CKo0 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo0 rising edge aligns with the
frame boundary.
4
FP0P
Frame Pulse Output (FPo0) Polarity.
When this bit is low, the output frame pulse FPo0 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo0 has the positive frame pulse format.
3-1
BPD2 - 0
Block Programming Data: These bits refer to the value to be loaded into the connection memory. Whenever the memory block programming feature is activated. After the
MBPE bit in the control register is set to high and the MBPS bit is set to high, the contents of the bits BPD0 to BPD2 are loaded into Bit 0 to Bit 2 of the connection memory.
Bit 3 to Bit 11 of the connection memory are zeroed.
Table 16 - Internal Mode Selection (IMS) Register Bits
39
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
External Read/Write Address: 001H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
CKINP
FPINP
CK2P
FP2P
CK1P
FP1P
CK0P
FP0P
BPD
2
BPD
1
BPD
0
MBPS
Bit
Name
Description
0
MBPS
Memory Block Programming Start: A zero to one transition of this bit starts the
memory block programming function. The MBPS, BPD0 to BPD2 bits in this register
must be defined in the same write operation. Once the MBPE bit in the control register
is set to high, the device requires 50 µs to complete the block programming. After the
programming function has finished, the MBPS bit returns to low indicating the operation is completed. When the MBPS is high, the MBPS or MBPE can be set to low to
abort the programming operation.
To ensure proper block programming operation, when MBPS is high the BPD0 to
BPD2 bits in this register must not be changed.
Whenever the microprocessor writes a one to the MBPS bit, the block programming
function is started, the user must maintain the same logical value to the other bits in
this register to avoid any change in the device setting.
Table 16 - Internal Mode Selection (IMS) Register Bits (continued)
External Read/Write Address: 010H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
BR
SA3
BR
SA2
BR
SA1
BR
SA0
0
0
BR
CA6
BR
CA5
BR
CA4
BR
CA3
BR
CA2
BR
CA1
BR
CA0
Bit
Name
Description
15 - 13
8-7
Unused
12 - 9
BRSA3 - 0
BER Receive Stream Address Bits: The binary value of these bits refers to the input
stream which receives the BER data.
6-0
BRCA6 - 0
BER Receive Channel Address Bits: The binary value of these bits refers to the
input channel in which the BER data starts to be compared.
Reserved. In normal functional mode, these bits MUST be set to zero.
Table 17 - BER Start Receiving Register (BSRR) Bits
40
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
External Read/Write Address: 011H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
BL7
BL6
BL5
BL4
BL3
BL2
BL1
BL0
Bit
Name
Description
15 - 8
Unused
Reserved. In normal functional mode, these bits MUST be set to zero.
7-0
BL7 - 0
BER Length Bits: The binary value of these bits refers to the number of channels.
The maximum numbers of BER channels are 32, 64 and 128 for the data rate of
2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s modes respectively. The minimum number of
BER channel is 1. If these bits are set to zero, no BER test will be performed.
Table 18 - BER Length Register (BLR) Bits
External Read Address: 012H
Reset Value: 0000H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BC
15
BC
14
BC
13
BC
12
BC
11
BC
10
BC
9
BC
8
BC
7
BC
6
BC
5
BC
4
BC
3
BC
2
BC
1
BC
0
Bit
Name
Description
15 - 0
BC15 - 0
BER Count Bits: The binary value of these bits refers to the bit error counts. When it
reaches its maximum value of Hex FFFF, the value will not be changed any more
Table 19 - BER Count Register (BCR) Bits
41
Zarlink Semiconductor Inc.
ZL50012
External Read/Write Address: 100H,
Reset Value: 0000H
102H,
104H,
106H,
108H,
10AH,
Data Sheet
10CH,
10EH,
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SICR0
0
0
0
0
0
0
0
STIN0
QEN3
STIN0
QEN2
STIN0
QEN1
STIN0
QEN0
STIN0
SMP1
STIN0
SMP0
STIN0
DR2
STIN0
DR1
STIN0
DR0
SICR1
0
0
0
0
0
0
0
STIN1
QEN3
STIN1
QEN2
STIN1
QEN1
STIN1
QEN0
STIN1
SMP1
STIN1
SMP0
STIN1
DR2
STIN1
DR1
STIN1
DR0
SICR2
0
0
0
0
0
0
0
STIN2
QEN3
STIN2
QEN2
STIN2
QEN1
STIN2
QEN0
STIN2
SMP1
STIN2
SMP0
STIN2
DR2
STIN2
DR1
STIN2
DR0
SICR3
0
0
0
0
0
0
0
STIN3
QEN3
STIN3
QEN2
STIN3
QEN1
STIN3
QEN0
STIN3
SMP1
STIN3
SMP0
STIN3
DR2
STIN3
DR1
STIN3
DR0
SICR4
0
0
0
0
0
0
0
STIN4
QEN3
STIN4
QEN2
STIN4
QEN1
STIN4
QEN0
STIN4
SMP1
STIN4
SMP0
STIN4
DR2
STIN4
DR1
STIN4
DR0
SICR5
0
0
0
0
0
0
0
STIN5
QEN3
STIN5
QEN2
STIN5
QEN1
STIN5
QEN0
STIN5
SMP1
STIN5
SMP0
STIN5
DR2
STIN5
DR1
STIN5
DR0
SICR6
0
0
0
0
0
0
0
STIN6
QEN3
STIN6
QEN2
STIN6
QEN1
STIN6
QEN0
STIN6
SMP1
STIN6
SMP0
STIN6
DR2
STIN6
DR1
STIN6
DR0
SICR7
0
0
0
0
0
0
0
STIN7
QEN3
STIN7
QEN2
STIN7
QEN1
STIN7
QEN0
STIN7
SMP1
STIN7
SMP0
STIN7
DR2
STIN7
DR1
STIN7
DR0
Bit
Name
Description
15 - 9
Unused
8
STIN#QEN3
Quadrant Frame 3 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch24 to
31, Ch48 to 63 and Ch96 to 127 for the 2.048 Mb/s, 4.096 Mb/s and
8.192 Mb/s mode respectively.
7
STIN#QEN2
Quadrant Frame 2 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch16 to
23, Ch32 to 47 and Ch64 to 95 for the 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s
mode respectively.
6
STIN#QEN1
Quadrant Frame 1 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch8 to 15,
Ch16 to 31 and Ch32 to 63 for the 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s
mode respectively.
5
STIN#QEN0
Quadrant Frame 0 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch0 to 7,
Ch0 to 15 and Ch0 to 31 for 2.048 Mb/s, the 4.096 Mb/s and 8.192 Mb/s mode
respectively.
Reserved. In normal functional mode, these bits MUST be set to zero.
Table 20 - Stream Input Control Register 0 to 7 (SICR0 to SICR7)
42
Zarlink Semiconductor Inc.
ZL50012
External Read/Write Address: 100H,
Reset Value: 0000H
102H,
104H,
106H,
108H,
10AH,
Data Sheet
10CH,
10EH,
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SICR0
0
0
0
0
0
0
0
STIN0
QEN3
STIN0
QEN2
STIN0
QEN1
STIN0
QEN0
STIN0
SMP1
STIN0
SMP0
STIN0
DR2
STIN0
DR1
STIN0
DR0
SICR1
0
0
0
0
0
0
0
STIN1
QEN3
STIN1
QEN2
STIN1
QEN1
STIN1
QEN0
STIN1
SMP1
STIN1
SMP0
STIN1
DR2
STIN1
DR1
STIN1
DR0
SICR2
0
0
0
0
0
0
0
STIN2
QEN3
STIN2
QEN2
STIN2
QEN1
STIN2
QEN0
STIN2
SMP1
STIN2
SMP0
STIN2
DR2
STIN2
DR1
STIN2
DR0
SICR3
0
0
0
0
0
0
0
STIN3
QEN3
STIN3
QEN2
STIN3
QEN1
STIN3
QEN0
STIN3
SMP1
STIN3
SMP0
STIN3
DR2
STIN3
DR1
STIN3
DR0
SICR4
0
0
0
0
0
0
0
STIN4
QEN3
STIN4
QEN2
STIN4
QEN1
STIN4
QEN0
STIN4
SMP1
STIN4
SMP0
STIN4
DR2
STIN4
DR1
STIN4
DR0
SICR5
0
0
0
0
0
0
0
STIN5
QEN3
STIN5
QEN2
STIN5
QEN1
STIN5
QEN0
STIN5
SMP1
STIN5
SMP0
STIN5
DR2
STIN5
DR1
STIN5
DR0
SICR6
0
0
0
0
0
0
0
STIN6
QEN3
STIN6
QEN2
STIN6
QEN1
STIN6
QEN0
STIN6
SMP1
STIN6
SMP0
STIN6
DR2
STIN6
DR1
STIN6
DR0
SICR7
0
0
0
0
0
0
0
STIN7
QEN3
STIN7
QEN2
STIN7
QEN1
STIN7
QEN0
STIN7
SMP1
STIN7
SMP0
STIN7
DR2
STIN7
DR1
STIN7
DR0
Bit
Name
4-3
STIN#SMP1 - 0
2-0
STIN#DR2 - 0
Description
Input Data Sampling Point Selection Bits:
STIN#SMP1-0
Sampling Point
00
3/4 point
01
4/4 point
10
1/4 point
11
2/4 point
Input Data Rate Selection Bits:
STIN#DR2-0
Data Rate
000
Disabled - External pull-up or pull-down
is required for ST-BUS input
001
2.048 Mb/s
010
4.096 Mb/s
011
8.192 Mb/s
100 - 111
Reserved
Note: # denotes input stream from 0 to 7
Table 20 - Stream Input Control Register 0 to 7 (SICR0 to SICR7) (continued)
43
Zarlink Semiconductor Inc.
ZL50012
External Read/Write Address: 110H,
Reset Value: 0000H
112H,
114H,
116H,
118H,
11AH,
Data Sheet
11CH,
11EH,
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SICR8
0
0
0
0
0
0
0
STIN8
QEN3
STIN8
QEN2
STIN8
QEN1
STIN8
QEN0
STIN8
SMP1
STIN8
SMP0
STIN8
DR2
STIN8
DR1
STIN8
DR0
SICR9
0
0
0
0
0
0
0
STIN9
QEN3
STIN9
QEN2
STIN9
QEN1
STIN9
QEN0
STIN9
SMP1
STIN9
SMP0
STIN9
DR2
STIN9
DR1
STIN9
DR0
SICR10
0
0
0
0
0
0
0
STIN10
QEN3
STIN10
QEN2
STIN10
QEN1
STIN10
QEN0
STIN10
SMP1
STIN10
SMP0
STIN10
DR2
STIN10
DR1
STIN10
DR0
SICR11
0
0
0
0
0
0
0
STIN11
QEN3
STIN11
QEN2
STIN11
QEN1
STIN11
QEN0
STIN11
SMP1
STIN11
SMP0
STIN11
DR2
STIN11
DR1
STIN11
DR0
SICR12
0
0
0
0
0
0
0
STIN12
QEN3
STIN12
QEN2
STIN12
QEN1
STIN12
QEN0
STIN12
SMP1
STIN12
SMP0
STIN12
DR2
STIN12
DR1
STIN12
DR0
SICR13
0
0
0
0
0
0
0
STIN13
QEN3
STIN13
QEN2
STIN13
QEN1
STIN13
QEN0
STIN13
SMP1
STIN13
SMP0
STIN13
DR2
STIN13
DR1
STIN13
DR0
SICR14
0
0
0
0
0
0
0
STIN14
QEN3
STIN14
QEN2
STIN14
QEN1
STIN14
QEN0
STIN14
SMP1
STIN14
SMP0
STIN14
DR2
STIN14
DR1
STIN14
DR0
SICR15
0
0
0
0
0
0
0
STIN15
QEN3
STIN15
QEN2
STIN15
QEN1
STIN15
QEN0
STIN15
SMP1
STIN15
SMP0
STIN15
DR2
STIN15
DR1
STIN15
DR0
Bit
Name
Description
15 - 9
Unused
8
STIN#QEN3
Quadrant Frame 3 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch24 to
31, Ch48 to 63 and Ch96 to 127 for the 2.048 Mb/s, 4.096 Mb/s and
8.192 Mb/s mode respectively.
7
STIN#QEN2
Quadrant Frame 2 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch16 to
23, Ch32 to 47 and Ch64 to 95 for the 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s
mode respectively.
6
STIN#QEN1
Quadrant Frame 1 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch8 to 15,
Ch16 to 31 and Ch32 to 63 for the 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s
mode respectively.
5
STIN#QEN0
Quadrant Frame 0 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch0 to 7,
Ch0 to 15 and Ch0 to 31 for 2.048 Mb/s, the 4.096 Mb/s and 8.192 Mb/s mode
respectively.
Reserved. In normal functional mode, these bits MUST be set to zero.
Table 21 - Stream Input Control Register 8 to 15 (SICR8 to SICR15)
44
Zarlink Semiconductor Inc.
ZL50012
External Read/Write Address: 110H,
Reset Value: 0000H
112H,
114H,
116H,
118H,
11AH,
Data Sheet
11CH,
11EH,
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SICR8
0
0
0
0
0
0
0
STIN8
QEN3
STIN8
QEN2
STIN8
QEN1
STIN8
QEN0
STIN8
SMP1
STIN8
SMP0
STIN8
DR2
STIN8
DR1
STIN8
DR0
SICR9
0
0
0
0
0
0
0
STIN9
QEN3
STIN9
QEN2
STIN9
QEN1
STIN9
QEN0
STIN9
SMP1
STIN9
SMP0
STIN9
DR2
STIN9
DR1
STIN9
DR0
SICR10
0
0
0
0
0
0
0
STIN10
QEN3
STIN10
QEN2
STIN10
QEN1
STIN10
QEN0
STIN10
SMP1
STIN10
SMP0
STIN10
DR2
STIN10
DR1
STIN10
DR0
SICR11
0
0
0
0
0
0
0
STIN11
QEN3
STIN11
QEN2
STIN11
QEN1
STIN11
QEN0
STIN11
SMP1
STIN11
SMP0
STIN11
DR2
STIN11
DR1
STIN11
DR0
SICR12
0
0
0
0
0
0
0
STIN12
QEN3
STIN12
QEN2
STIN12
QEN1
STIN12
QEN0
STIN12
SMP1
STIN12
SMP0
STIN12
DR2
STIN12
DR1
STIN12
DR0
SICR13
0
0
0
0
0
0
0
STIN13
QEN3
STIN13
QEN2
STIN13
QEN1
STIN13
QEN0
STIN13
SMP1
STIN13
SMP0
STIN13
DR2
STIN13
DR1
STIN13
DR0
SICR14
0
0
0
0
0
0
0
STIN14
QEN3
STIN14
QEN2
STIN14
QEN1
STIN14
QEN0
STIN14
SMP1
STIN14
SMP0
STIN14
DR2
STIN14
DR1
STIN14
DR0
SICR15
0
0
0
0
0
0
0
STIN15
QEN3
STIN15
QEN2
STIN15
QEN1
STIN15
QEN0
STIN15
SMP1
STIN15
SMP0
STIN15
DR2
STIN15
DR1
STIN15
DR0
Bit
Name
4-3
STIN#SMP1 - 0
2-0
STIN#DR2 - 0
Description
Input Data Sampling Point Selection Bits:
STIN#SMP1-0
Sampling Point
00
3/4 point
01
4/4 point
10
1/4 point
11
2/4 point
Input Data Rate Selection Bits:
STIN#DR2-0
Data Rate
000
Disabled - External pull-up or pull-down
is required for ST-BUS input
001
2.048 Mb/s
010
4.096 Mb/s
011
8.192 Mb/s
100 - 111
Reserved
Note: # denotes input stream from 8 to 15
Table 21 - Stream Input Control Register 8 to 15 (SICR8 to SICR15) (continued)
45
Zarlink Semiconductor Inc.
ZL50012
External Read/Write Address: 101H,
Reset Value: 0000H
103H,
105H,
107H,
109H,
10BH,
Data Sheet
10DH,
10FH,
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIDR0
0
0
0
0
0
0
STIN0
CD6
STIN0
CD5
STIN0
CD4
STIN0
CD3
STIN0
CD2
STIN0
CD1
STIN0
CD0
STIN0
BD2
STIN0
BD1
STIN0
BD0
SIDR1
0
0
0
0
0
0
STIN1
CD6
STIN1
CD5
STIN1
CD4
STIN1
CD3
STIN1
CD2
STIN1
CD1
STIN1
CD0
STIN1
BD2
STIN1
BD1
STIN1
BD0
SIDR2
0
0
0
0
0
0
STIN2
CD6
STIN2
CD5
STIN2
CD4
STIN2
CD3
STIN2
CD2
STIN2
CD1
STIN2
CD0
STIN2
BD2
STIN2
BD1
STIN2
BD0
SIDR3
0
0
0
0
0
0
STIN3
CD6
STIN3
CD5
STIN3
CD4
STIN3
CD3
STIN3
CD2
STIN3
CD1
STIN3
CD0
STIN3
BD2
STIN3
BD1
STIN3
BD0
SIDR4
0
0
0
0
0
0
STIN4
CD6
STIN4
CD5
STIN4
CD4
STIN4
CD3
STIN4
CD2
STIN4
CD1
STIN4
CD0
STIN4
BD2
STIN4
BD1
STIN4
BD0
SIDR5
0
0
0
0
0
0
STIN5
CD6
STIN5
CD5
STIN5
CD4
STIN5
CD3
STIN5
CD2
STIN5
CD1
STIN5
CD0
STIN5
BD2
STIN5
BD1
STIN5
BD0
SIDR6
0
0
0
0
0
0
STIN6
CD6
STIN6
CD5
STIN6
CD4
STIN6
CD3
STIN6
CD2
STIN6
CD1
STIN6
CD0
STIN6
BD2
STIN6
BD1
STIN6
BD0
SIDR7
0
0
0
0
0
0
STIN7
CD6
STIN7
CD5
STIN7
CD4
STIN7
CD3
STIN7
CD2
STIN7
CD1
STIN7
CD0
STIN7
BD2
STIN7
BD1
STIN7
BD0
Bit
Name
Description
15 - 10
Unused
9-3
STIN#CD6 - 0
Input Stream# Channel Delay Bits:
The binary value of these bits refers to the number of channels that the input
stream will be delayed. This value should not exceed the maximum channel
number of the stream. Zero means no delay.
2-0
STIN#BD2 - 0
Input Stream# Bit Delay Bits:
The binary value of these bits refers to the number of bits that the input stream
will be delayed. This maximum value is 7. Zero means no delay.
Reserved. In normal functional mode, these bits MUST be set to zero.
Note: # denotes input stream from 0 to 7
Table 22 - Stream Input Delay Register 0 to 7 (SIDR0 to SIDR7)
46
Zarlink Semiconductor Inc.
ZL50012
External Read/Write Address: 111H,
Reset Value: 0000H
113H,
115H,
117H,
119H,
11BH,
Data Sheet
11DH,
11FH,
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SIDR8
0
0
0
0
0
0
STIN8
CD6
STIN8
CD5
STIN8
CD4
STIN8
CD3
STIN8
CD2
STIN8
CD1
STIN8
CD0
STIN8B
BD2
STIN8B
BD1
STIN8B
BD0
SIDR9
0
0
0
0
0
0
STIN9
CD6
STIN9
CD5
STIN9
CD4
STIN9
CD3
STIN9
CD2
STIN9
CD1
STIN9
CD0
STIN9B
BD2
STIN9B
BD1
STIN9B
BD0
SIDR10
0
0
0
0
0
0
STIN10
CD6
STIN10
CD5
STIN10
CD4
STIN10
CD3
STIN10
CD2
STIN10
CD1
STIN10
CD0
STIN10
BD2
STIN10
BD1
STIN10
BD0
SIDR11
0
0
0
0
0
0
STIN11
CD6
STIN11
CD5
STIN11
CD4
STIN11
CD3
STIN11
CD2
STIN11
CD1
STIN11
CD0
STIN11
BD2
STIN11
BD1
STIN11
BD0
SIDR12
0
0
0
0
0
0
STIN12
CD6
STIN12
CD5
STIN12
CD4
STIN12
CD3
STIN12
CD2
STIN12
CD1
STIN12
CD0
STIN12
BD2
STIN12
BD1
STIN12
BD0
SIDR13
0
0
0
0
0
0
STIN13
CD6
STIN13
CD5
STIN13
CD4
STIN13
CD3
STIN13
CD2
STIN13
CD1
STIN13
CD0
STIN13
BD2
STIN13
BD1
STIN13
BD0
SIDR14
0
0
0
0
0
0
STIN14
CD6
STIN14
CD5
STIN14
CD4
STIN14
CD3
STIN14
CD2
STIN14
CD1
STIN14
CD0
STIN14
BD2
STIN14
BD1
STIN14
BD0
SIDR15
0
0
0
0
0
0
STIN15
CD6
STIN15
CD5
STIN15
CD4
STIN15
CD3
STIN15
CD2
STIN15
CD1
STIN15
CD0
STIN15
BD2
STIN15
BD1
STIN15
BD0
Bit
Name
Description
15 - 10
Unused
9-3
STIN#CD6 - 0
Input Stream# Channel Delay Bits:
The binary value of these bits refers to the number of channels that the input
stream will be delayed. This value should not exceed the maximum channel
number of the stream. Zero means no delay.
2-0
STIN#BD2 - 0
Input Stream# Bit Delay Bits:
The binary value of these bits refers to the number of bits that the input stream
will be delayed. This maximum value is 7. Zero means no delay.
Reserved. In normal functional mode, these bits MUST be set to zero.
Note: # denotes input stream from 8 to 15
Table 23 - Stream Input Delay Register 8 to 15 (SIDR8 to SIDR15)
47
Zarlink Semiconductor Inc.
ZL50012
External Read/Write Address: 200H,
Reset Value: 0000H
202H,
204H,
206H,
208H,
20AH,
Data Sheet
20CH,
20EH,
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOCR0
0
0
0
0
0
0
0
0
0
STOHZ0
AC
STOHZ0
A2
STOHZ0
A1
STOHZ0
A0
STO0
DR2
STO0
DR1
STO0
DR0
SOCR1
0
0
0
0
0
0
0
0
0
STOHZ1
AC
STOHZ1
A2
STOHZ1
A1
STOHZ1
A0
STO1
DR2
STO1
DR1
STO1
DR0
SOCR2
0
0
0
0
0
0
0
0
0
STOHZ2
AC
STOHZ2
A2
STOHZ2
A1
STOHZ2
A0
STO2
DR2
STO2
DR1
STO2
DR0
SOCR3
0
0
0
0
0
0
0
0
0
STOHZ3
AC
STOHZ3
A2
STOHZ3
A1
STOHZ3
A0
STO3
DR2
STO3
DR1
STO3
DR0
SOCR4
0
0
0
0
0
0
0
0
0
STOHZ4
AC
STOHZ4
A2
STOHZ4
A1
STOHZ4
A0
STO4
DR2
STO4
DR1
STO4
DR0
SOCR5
0
0
0
0
0
0
0
0
0
STOHZ5
AC
STOHZ5
A2
STOHZ5
A1
STOHZ5
A0
STO5
DR2
STO5
DR1
STO5
DR0
SOCR6
0
0
0
0
0
0
0
0
0
STOHZ6
AC
STOHZ6
A2
STOHZ6
A1
STOHZ6
A0
STO6
DR2
STO6
DR1
STO6
DR0
SOCR7
0
0
0
0
0
0
0
0
0
STOHZ7
AC
STOHZ7
A2
STOHZ7
A1
STOHZ7
A0
STO7
DR2
STO7
DR1
STO7
DR0
Bit
Name
15 - 7
Unused
6
STOHZ#AC
5-3
STOHZ#A2 - 0
Description
Reserved. In normal functional mode, these bits MUST be set to zero.
STOHZ Advancement Control. When this bit is low, the advancement unit is
15.2ns. When this bit is high, the advancement unit is 1/4 bit.
STOHZ Additional Advancement Bits:
Additional Advancement
(STOHZ#AC = 0)
STOHZ#A2-0
2-0
STO#DR2 - 0
Additional Advancement
(STOHZ#AC = 1)
000
0.0 ns
0 bit
001
15.2 ns
1/4 bit
010
30.5 ns
1/2 bit
011
45.7 ns
3/4 bit
100
61.0 ns
4/4 bit
101-111
Reserved
Reserved
Output Data Rate Selection Bits:
STO#DR2-0
Output Data Rate
000
STo HiZ
STOHZ driven high
001
2.048 Mb/s
010
4.096 Mb/s
011
8.192 Mb/s
100 - 111
Reserved
Note: # denotes input stream from 0 to 7
Table 24 - Stream Output Control Register 0 to 7 (SOCR0 to SOCR7)
48
Zarlink Semiconductor Inc.
ZL50012
External Read/Write Address: 210H,
Reset Value: 0000H
212H,
214H,
216H,
218H,
21AH,
Data Sheet
21CH,
21EH,
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOCR8
0
0
0
0
0
0
0
0
0
STOHZ8
AC
STOHZ8
A2
STOHZ8
A1
STOHZ8
A0
STO8
DR2
STO8
DR1
STO8
DR0
SOCR9
0
0
0
0
0
0
0
0
0
STOHZ9
AC
STOHZ9
A2
STOHZ9
A1
STOHZ9
A0
STO9
DR2
STO9
DR1
STO9
DR0
SOCR10
0
0
0
0
0
0
0
0
0
STOHZ10
AC
STOHZ10
A2
STOHZ10
A1
STOHZ10
A0
STO10
DR2
STO10
DR1
STO10
DR0
SOCR11
0
0
0
0
0
0
0
0
0
STOHZ11
AC
STOHZ11
A2
STOHZ11
A1
STOHZ11
A0
STO11
DR2
STO11
DR1
STO11
DR0
SOCR12
0
0
0
0
0
0
0
0
0
STOHZ12
AC
STOHZ12
A2
STOHZ12
A1
STOHZ12
A0
STO12
DR2
STO12
DR1
STO12
DR0
SOCR13
0
0
0
0
0
0
0
0
0
STOHZ13
AC
STOHZ13
A2
STOHZ13
A1
STOHZ13
A0
STO13
DR2
STO13
DR1
STO13
DR0
SOCR14
0
0
0
0
0
0
0
0
0
STOHZ14
AC
STOHZ14
A2
STOHZ14
A1
STOHZ14
A0
STO14
DR2
STO14
DR1
STO14
DR0
SOCR15
0
0
0
0
0
0
0
0
0
STOHZ15
AC
STOHZ15
A2
STOHZ15
A1
STOHZ15
A0
STO15
DR2
STO15
DR1
STO15
DR0
Bit
Name
15 - 7
Unused
6
STOHZ#AC
5-3
STOHZ#A2 - 0
Description
Reserved. In normal functional mode, these bits MUST be set to zero.
STOHZ Advancement Control. When this bit is low, the advancement unit is
15.2 ns. When this bit is high, the advancement unit is 1/4 bit.
STOHZ Additional Advancement Bits:
Additional Advancement
(STOHZ#AC = 0)
STOHZ#A2-0
2-0
STO#DR2 - 0
Additional Advancement
(STOHZ#AC = 1)
000
0.0 ns
0 bit
001
15.2 ns
1/4 bit
010
30.5 ns
1/2 bit
011
45.7 ns
3/4 bit
100
61.0 ns
4/4 bit
101-111
Reserved
Reserved
Output Data Rate Selection Bits:
STO#DR2-0
Output Data Rate
000
STo HiZ
STOHZ driven high
001
2.048 Mb/s
010
4.096 Mb/s
011
8.192 Mb/s
100 - 111
Reserved
Note: # denotes input stream from 8 to 15
Table 25 - Stream Output Control Register 8 to 15 (SOCR8 to SOCR15)
49
Zarlink Semiconductor Inc.
ZL50012
External Read/Write Address: 201H,
Reset Value: 0000H
203H,
205H,
207H,
209H,
20BH,
Data Sheet
20DH,
20FH,
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOOR0
0
0
0
0
STO0
CD6
STO0
CD5
STO0
CD4
STO0
CD3
STO0
CD2
STO0
CD1
STO0
CD0
STO0
BD2
STO0
BD1
STO0
BD0
STO0
FA1
STO0
FA0
SOOR1
0
0
0
0
STO1
CD6
STO1
CD5
STO1
CD4
STO1
CD3
STO1
CD2
STO1
CD1
STO1
CD0
STO1
BD2
STO1
BD1
STO1
BD0
STO1
FA1
STO1
FA0
SOOR2
0
0
0
0
STO2
CD6
STO2
CD5
STO2
CD4
STO2
CD3
STO2
CD2
STO2
CD1
STO2
CD0
STO2
BD2
STO2
BD1
STO2
BD0
STO2
FA1
STO2
FA0
SOOR3
0
0
0
0
STO3
CD6
STO3
CD5
STO3
CD4
STO3
CD3
STO3
CD2
STO3
CD1
STO3
CD0
STO3
BD2
STO3
BD1
STO3
BD0
STO3
FA1
STO3
FA0
SOOR4
0
0
0
0
STO4
CD6
STO4
CD5
STO4
CD4
STO4
CD3
STO4
CD2
STO4
CD1
STO4
CD0
STO4
BD2
STO4
BD1
STO4
BD0
STO4
FA1
STO4
FA0
SOOR5
0
0
0
0
STO5
CD6
STO5
CD5
STO5
CD4
STO5
CD3
STO5
CD2
STO5
CD1
STO5
CD0
STO5
BD2
STO5
BD1
STO5
BD0
STO5
FA1
STO5
FA0
SOOR6
0
0
0
0
STO6
CD6
STO6
CD5
STO6
CD4
STO6
CD3
STO6
CD2
STO6
CD1
STO6
CD0
STO6
BD2
STO6
BD1
STO6
BD0
STO6
FA1
STO6
FA0
SOOR7
0
0
0
0
STO7
CD6
STO7
CD5
STO7
CD4
STO7
CD3
STO7
CD2
STO7
CD1
STO7
CD0
STO7
BD2
STO7
BD1
STO7
BD0
STO7
FA1
STO7
FA0
Bit
Name
15 - 12
Unused
11 - 5
STO#CD6-0
Description
Reserved.
Output Stream# Channel Delay Bits:
The binary value of these bits refers to the number of channels that the output
stream is to be delayed. This value should not exceed the maximum channel
number of the stream. Zero means no delay.
4-2
STO#BD2-0
Output Stream# Bit Delay Selection Bits:
The binary value of these bits refers to the number of bits that the output stream
is to be delayed. The maximum value is 7. Zero means no delay.
1-0
STO#FA1-0
Output Stream# Fractional Advancement Bits
STO#FA1-0
Advanced By
00
0
01
1/4 bit
10
2/4 bit
11
3/4 bit
Note: # denotes input stream from 0 to 7
Table 26 - Stream Output Offset Register 0 to 7 (SOOR0 to SOOR7)
50
Zarlink Semiconductor Inc.
ZL50012
External Read/Write Address: 211H,
Reset Value: 0000H
213H,
215H,
217H,
219H,
21BH,
Data Sheet
21DH,
21FH,
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SOOR8
0
0
0
0
STO8C
D6
STO8
CD5
STO8
CD4
STO8
CD3
STO8
CD2
STO8
CD1
STO8
CD0
STO8B
BD2
STO8
BD1
STO8
BD0
STO8
FA1
STO8
FA0
SOOR9
0
0
0
0
STO9C
D6
STO9
CD5
STO9
CD4
STO9
CD3
STO9
CD2
STO9
CD1
STO9
CD0
STO9
BD2
STO9
BD1
STO9
BD0
STO9
FA1
STO9
FA0
SOOR10
0
0
0
0
STO10
CD6
STO10
CD5
STO10
CD4
STO10
CD3
STO10
CD2
STO10
CD1
STO10
CD0
STO10
BD2
STO10
BD1
STO10
BD0
STO10
FA1
STO10
FA0
SOOR11
0
0
0
0
STO11
CD6
STO11
CD5
STO11
CD4
STO11
CD3
STO11
CD2
STO11
CD1
STO11
CD0
STO11
BD2
STO11
BD1
STO11
BD0
STO11
FA1
STO11
FA0
SOOR12
0
0
0
0
STO12
CD6
STO12
CD5
STO12
CD4
STO12
CD3
STO12
CD2
STO12
CD1
STO12
CD0
STO12
BD2
STO12
BD1
STO12
BD0
STO12
FA1
STO12
FA0
SOOR13
0
0
0
0
STO13
CD6
STO13
CD5
STO13
CD4
STO13
CD3
STO13
CD2
STO13
CD1
STO13
CD0
STO13
BD2
STO13
BD1
STO13
BD0
STO13
FA1
STO13
FA0
SOOR14
0
0
0
0
STO14
CD6
STO14
CD5
STO14
CD4
STO14
CD3
STO14
CD2
STO14
CD1
STO14
CD0
STO14
BD2
STO14
BD1
STO14
BD0
STO14
FA1
STO14
FA0
SOOR15
0
0
0
0
STO15
CD6
STO15
CD5
STO1
CD4
STO15
CD3
STO15
CD2
STO15
CD1
STO15
CD0
STO15
BD2
STO15
BD1
STO15
BD0
STO15
FA1
STO15
FA0
Bit
Name
15 - 12
Unused
11 - 5
STO#CD6-0
Description
Reserved.
Output Stream# Channel Delay Bits:
The binary value of these bits refers to the number of channels that the output
stream is to be delayed. This value should not exceed the maximum channel
number of the stream. Zero means no delay.
4-2
STO#BD2-0
Output Stream# Bit Delay Selection Bits:
The binary value of these bits refers to the number of bits that the output stream
is to be delayed. The maximum value is 7. Zero means no delay.
1-0
STO#FA1-0
Output Stream# Fractional Advancement Bits
STO#FA1-0
Advanced By
00
0
01
1/4 bit
10
2/4 bit
11
3/4 bit
Note: # denotes input stream from 8 to 15
Table 27 - Stream Output Offset Register 8 to 15 (SOOR8 to SOOR15)
51
Zarlink Semiconductor Inc.
ZL50012
7.0
Data Sheet
Memory Address Mappings
When A11 is high, the data or the connection memory can be accessed by the microprocessor port. The Bit 0 to Bit
2 in the control register determine the access to the data or connection memory
MSB
(Note 1)
Stream Address
(ST. 0-15)
External
Address
(A11)
A10
A9
A8
A7
1
1
1
1
1
1
1
1
1
.
.
.
.
.
1
1
0
0
0
0
0
0
0
0
0
.
.
.
.
.
1
1
0
0
0
0
1
1
1
1
1
.
.
.
.
.
1
1
0
0
1
1
0
0
1
1
0
.
.
.
.
.
1
1
0
1
0
1
0
1
0
1
0
.
.
.
.
.
0
1
Channel Address
(Ch 0-127)
Stream #
Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Stream 8
.
.
.
.
.
Stream 14
Stream 15
A6
A5
A4
A3
A2
A1
A0
0
0
.
.
0
0
0
0
.
.
0
0
.
.
1
1
0
0
.
.
0
0
1
1
.
.
1
1
.
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
.
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
.
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
.
.
1
1
0
0
.
.
1
1
0
0
.
.
1
1
.
.
1
1
0
1
.
.
0
1
0
1
.
.
0
1
.
.
0
1
Channel #
Ch 0
Ch 1
.
.
Ch 30
Ch 31 (Note 2)
Ch 32
Ch 33
.
.
Ch 62
Ch 63 (Note 3)
.
.
Ch 126
Ch 127 (Note 4)
Notes:
1. MSB of address must be high for access to data and connection memory positions. MSB must be low for access to registers.
2. Channels 0 to 31 are used when serial stream is at 2.048 Mb/s.
3. Channels 0 to 63 are used when serial stream is at 4.096 Mb/s.
4. Channels 0 to 127 are used when serial stream is at 8.192 Mb/s.
Table 28 - Address Map for Memory Locations (512 x 512 DX, MSB of address = 1)
52
Zarlink Semiconductor Inc.
ZL50012
8.0
Data Sheet
Connection Memory Bit Assignment
When the CMM bit (Bit0) is zero, the connection is in normal switching mode. When the CMM bit is one, the
connection memory is in special transmission mode.
11
10
9
8
7
6
5
4
3
2
1
0
SSA3
SSA2
SSA1
SSA0
SCA6
SCA5
SCA4
SCA3
SCA2
SCA1
SCA0
CMM
=0
Bit
Name
Description
11 - 8
SSA3-0
Source Stream Address.
The binary value of these 4 bits represents the input stream number.
7-1
SCA6-0
Source Channel Address.
The binary value of these 7 bits represents the input channel number.
0
CMM=0
Connection Memory Mode = 0.
If this bit is set low, the connection memory is in normal switching mode. Bit 1
to 11 represent the source stream number and channel number.
Table 29 - Connection Memory Bit Assignment when the CMM bit = 0
11
10
9
8
7
6
5
4
3
2
1
0
0
MSG7
MSG6
MSG5
MSG4
MSG3
MSG2
MSG1
MSG0
PCC1
PCC0
CMM
=1
Bit
Name
11
Unused
Reserved.
10 - 3
MSG7-0
Message Data Bits: 8-bit data for the message mode.
2-1
PCC1-0
Per-Channel Control Bits: These two bits control outputs.
0
CMM=1
Description
PCC
PCC0
Output
0
0
Per Channel Tristate
0
1
Message Mode
1
0
BER Test Mode
1
1
Reserved
Connection Memory Mode = 1. If this bit is set high, the connection memory
is in the per-channel control mode which is per-channel tristate, per-channel
message mode or per-channel BER mode.
Table 30 - Connection Memory Bits Assignment when the CMM bit = 1
53
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max
Units
1
I/O Supply Voltage
VDD
-0.5
5.0
V
2
Input Voltage
VI_3V
-0.5
VDD + 0.5
V
3
Input Voltage (5 V tolerant inputs)
VI_5V
-0.5
7.0
V
4
Continuous Current at digital outputs
Io
15
mA
5
Package power dissipation
PD
0.75
W
6
Storage temperature
TS
- 55
+125
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
°C
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡
Max
Units
1
Operating Temperature
TOP
-40
25
+85
°C
2
Positive Supply
VDD
3.0
3.3
3.6
V
3
Input Voltage
VI
0
VDD
V
4
Input Voltage on 5 V Tolerant Inputs
VI_5V
0
5.5
V
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics† - Voltages are with respect to ground (Vss) unless otherwise stated.
Characteristics
Sym.
Min.
Typ‡
Max
Units
250
mA
Test Conditions
Output unloaded
1
Supply Current
IDD
2
Input High Voltage
VIH
3
Input Low Voltage
VIL
0.8
V
4
Input Leakage (input pins)
Input Leakage (bi-directional pins)
IIL
IBL
5
5
µA
µA
0≤<VIN≤VDD_IO
See Note 1
5
Weak Pullup Current
IPU
-33
µA
Input at 0 V
6
Weak Pulldown Current
IPD
33
µA
Input at VDD_IO
7
Input Pin Capacitance
CI
3
pF
8
Output High Voltage
VOH
9
Output Low Voltage
2.0
V
2.4
V
IOH = 10mA
VOL
0.4
V
IOL = 10mA
10 Output High Impedance Leakage
IOZ
5
µA
0 < V < VDD
11 Output Pin Capacitance
CO
10
pF
5
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
* Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (VIN).
54
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
AC Electrical Characteristics† - Timing Parameter Measurement Voltage Levels
Characteristics
Sym.
Level
Units
1
CMOS Threshold
VCT
0.5VDD_IO
V
2
Rise/Fall Threshold Voltage High
VHM
0.7VDD_IO
V
3
Rise/Fall Threshold Voltage Low
VLM
0.3VDD_IO
V
Conditions
† Characteristics are over recommended operating conditions unless otherwise stated.
AC Electrical Characteristics† - FPi and CKi Timing when CKIN2 to 0 bits = 000
Characteristic
Sym.
Min.
Typ.‡
61
1
FPi Input Frame Pulse Width
tFPIW
40
2
FPi Input Frame Pulse Setup Time
tFPIS
3
FPi Input Frame Pulse Hold Time
4
Max. Units Notes
115
ns
20
40
ns
tFPIH
20
40
ns
CKi Input Clock Period
tCKIP
55
67
ns
5
CKi Input Clock High Time
tCKIH
27
33
ns
6
CKi Input Clock Low Time
tCKIL
27
33
ns
61
trCKi, tfCKi
0
3
7 CKi Input Clock Rise/Fall Time
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
ns
AC Electrical Characteristics† - FPi and CKi Timing when CKIN2 to 0 bits = 001
Characteristic
Sym.
Min.
Typ.‡
122
1
FPi Input Frame Pulse Width
tFPIW
90
2
FPi Input Frame Pulse Setup Time
tFPIS
3
FPi Input Frame Pulse Hold Time
4
Max. Units Notes
220
ns
45
90
ns
tFPIH
45
90
ns
CKi Input Clock Period
tCKIP
110
135
ns
5
CKi Input Clock High Time
tCKIH
63
69
ns
6
CKi Input Clock Low Time
tCKIL
63
69
ns
122
trCKi, tfCKi
0
3
7 CKi Input Clock Rise/Fall Time
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD at 3.3 V and3 are for design aid only: not guaranteed and not subject to production testing.
ns
AC Electrical Characteristics - FPi and CKi Timing when CKIN2 to 0 bits = 010
Characteristic
Sym.
Min.
Typ.‡
244
1
FPi Input Frame Pulse Width
tFPIW
90
2
FPi Input Frame Pulse Setup Time
tFPIS
3
FPi Input Frame Pulse Hold Time
4
Max. Units Notes
420
ns
110
135
ns
tFPIH
120
145
ns
CKi Input Clock Period
tCKIP
220
270
ns
5
CKi Input Clock High Time
tCKIH
110
135
ns
6
CKi Input Clock Low Time
tCKIL
110
135
ns
7
CKi Input Clock Rise/Fall Time
trCKi, tfCKi
0
3
ns
244
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
55
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
tFPIW
FPi
tFPIS
tFPH
tCKIP
tCKIL
tCKIH
CKi
Input Frame Boundary
Figure 25 - Frame Pulse Input and Clock Input Timing Diagram
AC Electrical Characteristics† - Frame Boundary Timing with Input Clock Cycle-to-cycle Variation
Characteristic
Sym.
Min.
Typ‡
Max.
Units
Notes
1 CKi Input Clock cycle-to-cycle variation
tCKV
0
50
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
Input Frame Boundary
N+1
Input Frame Boundary
N
FPi
CKi
tCKV
tCKV
Figure 26 - Frame Boundary Timing with Input Clock (cycle-to-cycle) Variation
56
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
AC Electrical Characteristics† - Frame Boundary Timing with Input Frame Pulse Cycle-to-cycle Variation
Characteristic
Sym.
Typ.‡
Min.
Max.
Units
FPi Input Frame Pulse cycle-to-cycle variation
tFPV
0
50
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
1
Notes
ns
Input Frame Boundary
N+1
Input Frame Boundary
N
FPi
CKi
tFPV
tFPV
Figure 27 - Frame Boundary Timing with Input Frame Pulse (cycle-to-cycle) Variation
AC Electrical Characteristics - Input and Output Frame Boundary Alignment
Characteristic
2
Input and Output Frame Offset
Sym.
Min.
tFBOS
1
Typ.
57
Zarlink Semiconductor Inc.
Max.
Units
18
ns
Notes
Measured when there is
no jitter on the CKi and
FPi inputs.
ZL50012
FPi
CKi
(16.384 MHz)
FPi
CKi
(8.192 MHz)
FPi
CKi
(4.096 MHz)
Input Frame Boundary
tFBOS
Output Frame Boundary
FPo2
CKo2
(32.768 MHz)
FPo2 or FPo1
CKo2 or FPo1
(16.384 MHz)
FPo1 or FPo0
CKo1 or CKo0
(8.192 MHz)
FPo0
CKo0
(4.096 MHz)
Figure 28 - Input and Output Frame Boundary Offset
58
Zarlink Semiconductor Inc.
Data Sheet
ZL50012
Data Sheet
AC Electrical Characteristics† - FPo0 and CKo0 Timing when CKFP0 = 0
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
244
270
ns
1
FPo0 Output Pulse Width
tFPW0
220
2
FPo0 Output Delay from the CKo0 falling edge
to the output frame boundary
tFODF0
115
130
ns
3
FPo0 Output Delay from the output frame
boundary to the CKo0 Rising edge
tFODR0
115
130
ns
4
CKo0 Output Clock Period
tCKP0
220
270
ns
5
CKo0 Output High Time
tCKH0
115
130
ns
6
CKo0 Output Low Time
tCKL0
115
130
ns
244
Notes
CL=30pF
CL=30pF
7 CKo0 Output Rise/Fall Time
trCK0, tfCK0
10
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPo0 and CKo0 Timing when CKFP0 = 1
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
122
140
ns
1
FPo0 Output Pulse Width
tFPW0
108
2
FPo0 Output Delay from the CKo0 falling edge
to the output frame boundary
tFODF0
54
68
ns
3
FPo0 Output Delay from the output frame
boundary to the CKo0 Rising edge
tFODR0
54
68
ns
4
CKo0 Output Clock Period
tCKP0
108
140
ns
5
CKo0 Output High Time
tCKH0
54
69
ns
6
CKo0 Output Low Time
tCKL0
54
69
ns
122
Notes
CL=30pF
CL=30pF
7 CKo0 Output Rise/Fall Time
trCK0, tfCK0
10
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tFPW0
VTT
FPo0
tFODF0
tFODR0
tCKP0
tCKH0
tCKL0
VTT
CKo0
tfCK0
Output Frame Boundary
Figure 29 - FPo0 and CKo0 Timing Diagram
59
Zarlink Semiconductor Inc.
trCK0
ZL50012
Data Sheet
AC Electrical Characteristics† - FPo1 and CKo1 Timing when CKFP1 = 0
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
61
75
ns
1
FPo1 Output Pulse Width
tFPW1
47
2
FPo1 Output Delay from the CKo1 falling edge
to the output frame boundary
tFODF1
20
40
ns
3
FPo1 Output Delay from the output frame
boundary to the CKo1 Rising edge
tFODR1
20
40
ns
4
CKo1 Output Clock Period
tCKP1
47
75
ns
5
CKo1 Output High Time
tCKH1
20
40
ns
6
CKo1 Output Low Time
tCKL1
20
40
ns
61
Notes
CL=30pF
CL=30pF
7 CKo1 Output Rise/Fall Time
trCK1, tfCK1
10
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPo1 and CKo1 Timing when CKFP1 = 1
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
122
140
ns
1
FPo1 Output Pulse Width
tFPW1
108
2
FPo1 Output Delay from the CKo1 falling edge
to the output frame boundary
tFODF1
54
68
ns
3
FPo1 Output Delay from the output frame
boundary to the CKo1 Rising edge
tFODR1
54
68
ns
4
CKo1 Output Clock Period
tCKP1
108
140
ns
5
CKo1 Output High Time
tCKH1
54
69
ns
6
CKo1 Output Low Time
tCKL1
54
69
ns
122
Notes
CL=30pF
CL=30pF
7 CKo1 Output Rise/Fall Time
trCK1, tfCK1
10
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tFPW1
FPo1
VTT
tFODF1
tFODR1
tCKP1
tCKH1
tCKL1
VTT
CKo1
tfCK1
Output Frame Boundary
Figure 30 - FPo1 and CKo1 Timing Diagram
60
Zarlink Semiconductor Inc.
trCK1
ZL50012
Data Sheet
AC Electrical Characteristics† - FPo2 and CKo2 Timing when CKFP2 = 0
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
30
45
ns
1
FPo2 Output Pulse Width
tFPW2
15
2
FPo2 Output Delay from the CKo2 falling edge
to the output frame boundary
tFODF2
8
22
ns
3
FPo2 Output Delay from the output frame
boundary to the CKo2 Rising edge
tFODR2
8
22
ns
4
CKo2 Output Clock Period
tCKP2
15
45
ns
5
CKo2 Output High Time
tCKH2
8
22
ns
6
CKo2 Output Low Time
tCKL2
8
22
ns
30
Notes
CL=30pF
CL=30pF
7 CKo2 Output Rise/Fall Time
trCK2, tfCK2
7
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics† - FPo2 and CKo2 Timing when CKFP2 = 1
Characteristic
Sym.
Min.
Typ.‡
Max.
Units
61
75
ns
1
FPo2 Output Pulse Width
tFPW2
47
2
FPo2 Output Delay from the CKo2 falling edge
to the output frame boundary
tFODF2
20
40
ns
3
FPo2 Output Delay from the output frame
boundary to the CKo2 Rising edge
tFODR2
20
40
ns
4
CKo2 Output Clock Period
tCKP2
47
75
ns
5
CKo2 Output High Time
tCKH2
20
40
ns
6
CKo2 Output Low Time
tCKL2
20
40
ns
61
Notes
CL=30pF
CL=30pF
7 CKo2 Output Rise/Fall Time
trCK2, tfCK2
10
ns
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
tFPW2
FPo2
VTT
tFODF2
tFODR2
tCKP2
tCKH2
tCKL2
VTT
CKo2
tfCK2
Output Frame Boundary
Figure 31 - FPo2 and CKo2 Timing Diagram
61
Zarlink Semiconductor Inc.
trCK2
ZL50012
Data Sheet
AC Electrical Characteristics† - ST-BUS Input Timing
Characteristic
1
2
Typ.‡
Sym.
Min.
STi Setup Time
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
tSIS2
tSIS4
tSIS8
3
3
3
ns
ns
ns
STi Hold Time
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
tSIH2
tSIH4
tSIH8
3
3
3
ns
ns
ns
Max.
Units
Test Conditions
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
FPi
CKi
(16.384 MHz)
FPi
CKi
(8.192 MHz)
FPi
CKi
(4.096 MHz)
tSIS2
tSIH2
STi0 - 15
2.048 Mb/s
Bit0
Ch31
Bit7
Ch0
Bit6
Ch0
VTT
tSIS4
tSIH4
STi0 - 15
4.096 Mb/s
Bit0
Ch63
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
VTT
tSIS8
tSIH8
STi0 - 15
8.192 Mb/s
Bit1
Ch127
Bit0
Ch127
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
Bit3
Ch0
Bit2
Ch0
Bit1
Ch0
Input Frame Boundary
Figure 32 - ST-BUS Inputs (STi0 - 15) Timing Diagram
62
Zarlink Semiconductor Inc.
Bit0
Ch0
VTT
V
TT
ZL50012
Data Sheet
AC Electrical Characteristics† - ST-BUS Output Timing
Characteristic
1
Sym.
STo Delay - Active to Active
@2.048 Mb/s
@4.096 Mb/s
@8.192 Mb/s
Typ.‡
Min.
Max.
Units
10
10
10
ns
ns
ns
tSOD2
tSOD4
tSOD8
Test Conditions
CL = 30pF
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD at 3.3 V and are for design aid only: not guaranteed and not subject to production testing.
FPo2
CKo2
(32.768 MHz)
FPo2 or FPo1
CKo2 or FPo1
(16.384 MHz)
FPo1 or FPo0
CKo1 or CKo0
(8.192 MHz)
FPo0
CKo0
(4.096 MHz)
tSOD2
STo0 - 15
2.048 Mb/s
Bit7
Ch0
Bit7
Ch31
Bit7
Ch0
VTT
tSOD4
STo0 - 15
4.096 Mb/s
Bit7
Ch63
Bit7
Ch0
Bit7
Ch0
Bit7
Ch0
Bit7
Ch0
VTT
tSOD8
STo0 - 15
8.192 Mb/s
Bit0
Ch127
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
Bit3
Ch0
Bit2
Ch0
Bit1
Ch0
Output Frame Boundary
Figure 33 - ST-BUS Outputs (STo0 - 15) Timing Diagram
63
Zarlink Semiconductor Inc.
Bit0
Ch0
VTT
ZL50012
Data Sheet
AC Electrical Characteristics† - ST-BUS Output Tristate Timing
Characteristic
1
2
2
Sym.
Typ.‡
Min.
Max.
Units
15
15
15
ns
ns
ns
45
45
45
ns
ns
ns
30
30
30
ns
ns
ns
Test
Conditions
tDZ, tZD
STo Delay - Active to High-Z
STo Delay - High-Z to Active
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Output Driver Enable (ODE) Delay
- High-Z to Active
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
tZD_ODE
Output Driver Disable (ODE) Delay
- Active to High-Z
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
tDZ_ODE
RL=1K,
CL=30pF,
See Note 1.
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Note 1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel the time taken to discharge C L.
VTT
CKo0-2
tDZ
Tri-state
VTT
Valid Data
VTT
Valid Data
STo
tZD
Tri-state
STo
Figure 34 - Serial Output and External Control
VTT
ODE
tDZ_ODE
tZD_ODE
STo
HiZ
Valid Data
HiZ
VTT
Figure 35 - Output Driver Enable (ODE)
64
Zarlink Semiconductor Inc.
ZL50012
Data Sheet
AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode
Characteristics
Sym.
Min.
Typ.
Max.
Test Conditions2
Units
1
CS setup from DS falling
tCSS
0
ns
2
R/W setup from DS falling
tRWS
10
ns
3
Address setup from DS falling
tADS
5
ns
4
DS delay from the rising edge of DTA to
the falling edge of the DS
tDSD
50
ns
5
CS delay from the rising edge of DTA to
the falling edge of the CS
tCSD
50
ns
6
CS hold after DS rising
tCSH
0
ns
7
R/W hold after DS rising
tRWH
0
ns
8
Address hold after DS rising
tADH
0
ns
9
Data setup from DTA Low on Read
tDDR
20
ns
CL=30pF
10
Data hold on read
tDHR
3
ns
CL=30pF, RL=1K (Note
1)
11
Data setup from DS falling on write
tWDS
10
ns
12
Data hold on write
tDHW
0
ns
13
Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory
tAKD
Acknowledgment Hold Time
tAKH
14
9
120/105
200/150
ns
ns
CL=30pF
CL=30pF
20
ns
CL=30pF, RL=1K (Note
1)
Note 1: High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L.
Note 2: A delay of 600 microseconds must be applied before the first microprocessor access is performed after the RESET pin is set high.
tDSD
VTT
DS
tCSD
tCSH
tCSS
VTT
CS
tRWH
tRWS
VTT
R/W
tADH
tADS
VTT
VALID ADDRESS
A0-A11
tDHR
D0-D15
READ
VTT
VALID READ DATA
tWDS
tDHW
VTT
VALID WRITE DATA
D0-D15
WRITE
tDDR
VTT
DTA
tAKD
Figure 36 - Motorola Non-Multiplexed Bus Timing
65
Zarlink Semiconductor Inc.
tAKH
ZL50012
Data Sheet
AC Electrical Characteristics† - JTAG Test Port and Reset Pin Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
1
TCK Clock Period
tTCKP
100
ns
2
TCK Clock Pulse Width High
tTCKH
80
ns
3
TCK Clock Pulse Width Low
tTCKL
80
ns
4
TMS Set-up Time
tTMSS
10
ns
5
TMS Hold Time
tTMSH
10
ns
6
TDi Input Set-up Time
tTDIS
20
ns
7
TDi Input Hold Time
tTDIH
60
ns
8
TDo Output Delay
tTDOD
9
TRST pulse width
tTRSTW
200
ns
10 Reset pulse width
tRSTW
1.0
ms
25
ns
†Characteristics are over recommended operating conditions unless otherwise stated.
tTCKL
tTCKH
tTCKP
TCK
tTMSS
tTMSH
TMS
tTDIS
tTDIH
TDi
tTDOD
TDo
tTRSTW
TRST
Figure 37 - JTAG Test Port Timing Diagram
tRSTW
Reset
Figure 38 - Reset Pin Timing Diagram
66
Zarlink Semiconductor Inc.
Notes
CL=30pF
Package Code
c Zarlink Semiconductor 2002 All rights reserved.
ISSUE
ACN
DATE
APPRD.
Previous package codes
Package Code
c Zarlink Semiconductor 2002 All rights reserved.
1
2
ACN
213740
213834
DATE
15Nov02
11Dec02
ISSUE
APPRD.
Previous package codes
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