ZARLINK ZL50061GAG2

ZL50060/1
16 K-Channel Digital Switch with High Jitter
Tolerance, Per Stream Rate Conversion (2, 4, 8,
16, or 32 Mbps), and 64 Inputs and 64 Outputs
Data Sheet
Features
•
February 2006
16,384-channel x 16,384-channel non-blocking
unidirectional switching.The Backplane and Local
inputs and outputs can be combined to form a
non-blocking switching matrix with 64 input
streams and 64 output streams
Ordering Information
ZL50060GAC
256 Ball PBGA
ZL50060GAG2
256 Ball PBGA**
ZL50061GAG
272 Ball PBGA
ZL50061GAG2
272 Ball PBGA**
**Pb Free Tin/Silver/Copper
Trays
Trays
Trays
Trays
•
8,192-channel x 8,192-channel non-blocking
Backplane input to Local output stream switch
•
8,192-channel x 8,192-channel non-blocking
Local input to Backplane output stream switch
•
8,192-channel x 8,192-channel non-blocking
Backplane input to Backplane output switch
•
8,192-channel x 8,192-channel non-blocking
Local input to Local output stream switch
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Exceptional input clock jitter tolerance (17 ns for
16 Mbps or lower data rates, 14 ns for 32 Mbps)
•
Rate conversion on all data paths, Backplane-toLocal, Local-to-Backplane, Backplane-toBackplane and Local-to-Local streams
•
Per-stream channel and bit delay for Local and
Backplane input streams
•
Per-stream advancement for Local and Backplane
output streams
•
Constant 2-frame throughput delay for frame
integrity
•
Per-channel high impedance output control for
Local and Backplane streams
•
•
-40°C to +85°C
4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any
combination, or a fixed allocation of 16 input and
16 output streams at 32.768 Mbps
Backplane port accepts 32 input and 32 output
ST-BUS streams with data rates of 2.048 Mbps,
4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any
combination, or a fixed allocation of 16 input and
16 output streams at 32.768 Mbps
Local port accepts 32 input and 32 output STBUS streams with data rates of 2.048 Mbps,
VDD_IO VDD_CORE
VSS (GND)
RESET
ODE
Backplane Data Memories
(8,192 channels)
BSTi0-31
Backplane
Connection Memory
(8,192 locations)
Backplane
Interface
BSTo0-31
Local
Interface
Local
Connection Memory
(8,192 locations)
Local
Interface
LSTo0-31
BCST0-3
LCST0-3
Local Data Memories
(8,192 channels)
BORS
FP8i
C8i
LSTi0-31
LORS
Input
Timing Unit
PLL
VDD_PLL
Output
Timing
Unit
Microprocessor Interface
and Internal Registers
DS CS R/W
A14-0
DTA
Test Port
D15-0
TMS TDi TDo TCK TRST
Figure 1 - ZL50060/1 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.
FP8o
FP16o
C8o
C16o
ZL50060/1
•
Per-channel driven-high output control for Local and Backplane streams
•
High impedance control outputs for external drivers on Local and Backplane ports
•
Per-channel message mode for Local and Backplane output streams
•
Connection memory block programming for fast device initialization
•
BER testing for Local and Backplane ports
•
Automatic selection between ST-BUS and GCI-Bus operation
•
Non-multiplexed Motorola microprocessor interface
•
Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard
•
Memory Built-In-Self-Test (BIST), controlled via microprocessor register
•
1.8 V core supply voltage
•
3.3 V I/O supply voltage
•
5 V tolerant inputs, outputs and I/Os
•
ZL50061 is pin-to-pin compatible with Zarlink’s MT90869 device 1
Note 1: For software compatibility between ZL50061 and MT90869, please refer to Section 2.6.
Applications
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Central Office Switches (Class 5)
•
Media Gateways
•
Class-independent switches
•
Access Concentrators
•
Scalable TDM-Based Architectures
•
Digital Loop Carriers
2
Zarlink Semiconductor Inc.
Data Sheet
ZL50060/1
Data Sheet
Device Overview
The ZL50060 and ZL50061 are two different packages of the same device. The ZL50060/1 has two data ports, the
Backplane and the Local port. Both the Backplane and Local ports have two independent modes of operation,
either 32 input and 32 output streams operated at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps, in any
combination, or 16 input and 16 output streams operated at 32.768 Mbps.
The ZL50060/1 contains two data memory blocks (Backplane and Local) to provide the following switching path
configurations:
•
Input-to-Output Unidirectional, supporting 16 K x 16 K switching
•
Backplane-to-Local Bi-directional, supporting 8 K x 8 K data switching,
•
Local-to-Backplane Bi-directional, supporting 8 K x 8 K data switching,
•
Backplane-to-Backplane Bi-directional, supporting 8 K x 8 K data switching.
•
Local-to-Local Bi-directional, supporting 8 K x 8 K data switching.
The device contains two connection memory blocks, one for the Backplane output and one for the Local output.
Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly
from the connection memory contents (Message Mode).
In Connection Mode, the contents of the connection memory define, for each output stream and channel, the
source stream and channel (stored in data memory) to be switched.
In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output
streams on a per channel basis. This feature is useful for transferring control and status information to external
circuits or other ST-BUS devices.
The device uses a master frame pulse (FP8i) and master clock (C8i) to define the input frame boundary and timing
for both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCIBus style frame pulse is being used. There is a two-frame delay from the time RESET is de-asserted to the
establishment of full switch functionality. During this period, the input frame pulse format is determined before
switching begins.
The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the outputs of
the Backplane and Local ports.
A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and
switching configurations. The microprocessor port provides access for Register read/write, Connection Memory
read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and 4 control
signals. The microprocessor may monitor channel data in the Backplane and Local data memories.
The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port.
The ZL50060 and ZL50061 are each available in one package:
•
ZL50060: a 17 mm x 17 mm body, 1 mm ball-pitch, 256-PBGA.
•
ZL50061: a 27 mm x 27 mm body, 1.27 mm ball-pitch, 272-PBGA.
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Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Table of Contents
1.0 Unidirectional and Bi-directional Switching Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.1 Flexible Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.1.1 Non-Blocking Unidirectional Configuration (Typical System Configuration) . . . . . . . . . . . . . . . . . . 22
1.1.2 Non-Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.1.3 Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1 Switching Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1.1 Unidirectional Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1.2 Backplane-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1.3 Local-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1.4 Backplane-to-Backplane Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1.5 Local-to-Local Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1.6 Port Data Rate Modes and Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1.7 Local Port Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.1.7.1 Local Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.1.7.2 Local Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.1.8 Backplane Port Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.1.8.1 Backplane Input Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.1.8.2 Backplane Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2 Frame Pulse Input and Master Input Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3 Input Frame Pulse and Generated Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.4 Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator. . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.5 Input Clock Jitter Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.6 Backward Compatibility with MT90869 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.0 Input and Output Offset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1 Input Offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1.1 Input Channel Delay Programming (Backplane and Local Input Streams) . . . . . . . . . . . . . . . . . . . 30
3.1.2 Input Bit Delay Programming (Backplane and Local Input Streams) . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 Output Advancement Programming (Backplane and Local Output Streams) . . . . . . . . . . . . . . . . . . . . . . 32
4.0 Port high impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1 LORS/BORS Asserted LOW, Non-32Mbps Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.2 LORS/BORS Asserted LOW, 32Mbps Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.3 LORS/BORS Asserted HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.0 Bit Error Rate Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.0 Device Power-up, Initialization and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.1 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.0 Connection Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1 Local Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2 Backplane Connection Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.3 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.3.1 Memory Block Programming Procedure: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.0 Memory Built-In-Self-Test (BIST) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
11.2 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.2.1 Test Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.2.2 Test Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Table of Contents
11.2.2.3 The Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.3 Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12.0 Memory Address Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.1 Local Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.2 Backplane Data Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.3 Local Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.4 Backplane Connection Memory Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13.0 Internal Register Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
14.0 Detailed Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14.1 Control Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14.2 Block Programming Register (BPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
14.3 Bit Error Rate Test Control Register (BERCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
14.4 Local Input Channel Delay Registers (LCDR0 to LCDR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
14.4.1 Local Channel Delay Bits 8-0 (LCD8 - LCD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
14.5 Local Input Bit Delay Registers (LIDR0 to LIDR31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
14.5.1 Local Input Delay Bits 4-0 (LID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
14.6 Backplane Input Channel Delay Registers (BCDR0 to BCDR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
14.6.1 Backplane Channel Delay Bits 8-0 (BCD8 - BCD0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
14.7 Backplane Input Bit Delay Registers (BIDR0 to BIDR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
14.7.1 Backplane Input Delay Bits 4-0 (BID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
14.8 Local Output Advancement Registers (LOAR0 to LOAR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.8.1 Local Output Advancement Bits 1-0 (LOA1-LOA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
14.9 Backplane Output Advancement Registers (BOAR0 - BOAR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14.9.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
14.10 Local Bit Error Rate (BER) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
14.10.1 Local BER Start Send Register (LBSSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
14.10.2 Local Transmit BER Length Register (LTXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.10.3 Local Receive BER Length Register (LRXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
14.10.4 Local BER Start Receive Register (LBSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
14.10.5 Local BER Count Register (LBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
14.11 Backplane Bit Error Rate (BER) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
14.11.1 Backplane BER Start Send Register (BBSSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
14.11.2 Backplane Transmit BER Length Register (BTXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
14.11.3 Backplane Receive BER Length Register (BRXBLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
14.11.4 Backplane BER Start Receive Register (BBSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
14.11.5 Backplane BER Count Register (BBCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.12 Local Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.12.1 Local Input Bit Rate Registers (LIBRR0 - LIBRR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
14.12.2 Local Output Bit Rate Registers (LOBRR0 - LOBRR31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.13 Backplane Bit Rate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.13.1 Backplane Input Bit Rate Registers (BIBRR0 - BIBRR31). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
14.13.2 Backplane Output Bit Rate Registers (BOBRR0 - BOBRR31) . . . . . . . . . . . . . . . . . . . . . . . . . . 78
14.14 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
14.15 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
15.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
16.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
List of Figures
Figure 1 - ZL50060/1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL50061 PBGA Connections (272 PBGA, 27 mm x 27 mm) Pin Diagram
(as viewed through top of package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3 - ZL50060 PBGA Connections (256 PBGA, 17 mm x 17 mm) Pin Diagram
(as viewed through top of package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4 - 16,384 x 16,384 Channels (16 Mbps), Unidirectional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5 - 8,192 x 8,192 Channels (16 Mbps), Bi-directional Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 6 - 12,288 by 4,096 Channels Blocking Bi-directional Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7 - ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 8 - Input and Output Frame Pulse Alignment for Different Data Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 9 - Backplane and Local Input Channel Delay Timing Diagram (assuming 8 Mbps operation) . . . . . . . . . 30
Figure 10 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mbps . . . . . . . . . . . . . . . . 31
Figure 11 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for Data Rate of
8 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 12 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 16 Mbps . . . . . . . . . . . 33
Figure 13 - Local/Backplane Port External High Impedance Control Timing (Non-32 Mbps Mode) . . . . . . . . . . . 37
Figure 14 - Local and Backplane Port External High Impedance Control Timing (32Mbps Mode) . . . . . . . . . . . . 41
Figure 15 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch0 Switched to Output Ch0 . . . . 43
Figure 16 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch0 Switched to Output Ch13 . . . 43
Figure 17 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch13 Switched to Output Ch0 . . . 43
Figure 18 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch0 Switched to Output Ch0 . . . . 44
Figure 19 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch0 Switched to Output Ch13 . . . 44
Figure 20 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch13 Switched to Output Ch0 . . . 44
Figure 21 - Examples of BER Transmission Channels on a 16Mbps Output Stream . . . . . . . . . . . . . . . . . . . . . . 45
Figure 22 - Hardware RESET de-assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 23 - Frame Boundary Conditions, ST-BUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 24 - Frame Boundary Conditions, GCI-Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 25 - Input and Output Clock Timing Diagram for ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 26 - Input and Output Clock Timing Diagram for GCI-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 27 - ST-BUS Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps) . . . . . . . . . . . . . . . . . . . . 88
Figure 28 - ST-BUS Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps). . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 29 - GCI-Bus Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps) . . . . . . . . . . . . . . . . . . . 90
Figure 30 - GCI-Bus Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 31 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 32 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 33 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 34 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
List of Tables
Table 1 - Per-stream Input and Output Data Rate Selection: Backplane and Local . . . . . . . . . . . . . . . . . . . . . . . 24
Table 2 - Local and Backplane Output Enable Control Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 3 - L/BCSTo Allocation of Channel Control Bits to Output Streams (Non-32 Mbps Mode). . . . . . . . . . . . . . 35
Table 4 - L/BCSTo Allocation of Channel Control Bits to Output Streams (32 Mbps Mode) . . . . . . . . . . . . . . . . . 39
Table 5 - Variable Range for Input Streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 6 - Variable Range for Output Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 7 - Data Throughput Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 8 - Local and Backplane Connection Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 9 - Local Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 10 - Backplane Connection Memory in Block Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 11 - Address Map for Data and Connection Memory Locations (A14 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 12 - Local Data Memory (LDM) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 13 - Backplane Data Memory (BDM) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 14 - LCM Bits for Non-32Mbps Source-to-Local Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 15 - LCM Bits for 32Mbps Source-to-Local Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 16 - BCM Bits for Non-32Mbps Source-to-Backplane Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 17 - BCM Bits for 32Mbps Source-to-Backplane Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 18 - Address Map for Registers (A14 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 19 - Control Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 20 - Block Programming Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 21 - Bit Error Rate Test Control Register (BERCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 22 - Local Input Channel Delay Register (LCDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 23 - Local Input Channel Delay (LCD) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 24 - Local Input Bit Delay Register (LIDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 25 - Local Input Bit Delay and Sampling Point Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 26 - Backplane Input Channel Delay Register (BCDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 27 - Backplane Input Channel Delay (BCD) Programming Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 28 - Backplane Input Bit Delay Register (BIDRn) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 29 - Backplane Input Bit Delay and Sampling Point Programming Table. . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 30 - Local Output Advancement Register (LOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 31 - Local Output Advancement (LOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 32 - Backplane Output Advancement Register (BOAR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 33 - Backplane Output Advancement (BOAR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 34 - Local BER Start Send Register (LBSSR) Bits in Non-32 Mbps Mode. . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 35 - Local BER Start Send Register (LBSSR) Bits in 32 Mbps Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 36 - Local BER Length Register (LTXBLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 37 - Local Receive BER Length Register (LRXBLR) Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 38 - Local BER Start Receive Register (LBSRR) Bits for Non-32 Mbps Mode . . . . . . . . . . . . . . . . . . . . . . 73
Table 39 - Local BER Start Receive Register (LBSRR) Bits for 32 Mbps Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 40 - Local BER Count Register (LBCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 41 - Backplane BER Start Send Register (BBSSR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 42 - Backplane Transmit BER Length (BTXBLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 43 - Backplane Receive BER Length (BRXBLR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 44 - Backplane BER Start Receive Register (BBSRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 45 - Backplane BER Count Register (BBCR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 46 - Local Input Bit Rate Register (LIBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 47 - Local Input Bit Rate (LIBR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 48 - Local Output Bit Rate Register (LOBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
7
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
List of Tables
Table 49 - Local Output Bit Rate (LOBR) Programming Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 50 - Backplane Input Bit Rate Register (BIBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 52 - Backplane Output Bit Rate Register (BOBRR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 53 - Backplane Output Bit Rate (BOBRR) Programming Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 54 - Memory BIST Register (MBISTR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 55 - Device Identification Register (DIR) Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
8
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Pinout Diagram: (as viewed through top of package)
A1 corner identified by metallized marking
1
2
3
IC_GND BSTo5
4
5
6
7
8
9
10
11
12
13
14
BSTo4
BSTo2
A2
VDD_
CORE
A8
A11
A14
DS
ODE
DTA
TCK
TRST
15
16
17
18
19
20
LSTo0
LSTo1
LSTo2
NC
BCSTo2 LCSTo2 IC_GND LSTo3
LSTo4
LSTo5
LSTo6
LSTo7
LSTo8
LSTo9
LSTo10 LSTo11
BCSTo1 LCSTo3
A
GND
B
BSTo6
BSTo7
VDD_
CORE
BSTo1
NC
A5
A7
A10
NC
CS
VDD_
CORE
TDi
C
BSTo9
BSTo10 IC_GND BSTo3
BSTo0
A1
A4
A6
NC
A13
R/W
RESET
TDo
D
BSTo11 BSTo12 BSTo13
A0
VDD_IO
A3
GND
A9
A12
VDD_IO
TMS
GND
E
BSTo14 BSTo15 BSTo16 BSTo17
LSTo12 LSTo13 LSTo14 LSTo15
F
BSTo18 BSTo19 BSTo20 VDD_IO
VDD_IO LSTo16 LSTo17 LSTo18
G
BSTo21 BSTo22 BSTo23 BSTo24
LSTo19 LSTo20 LSTo21 LSTo22
H
BSTo25 BSTo26 BSTo27
J
BSTo28 BSTo29 BSTo30 BSTo31
BSTo8
GND
BCSTo0 BCSTo3 LCSTo1 LCSTo0
VDD_
CORE
VDD_IO IC_GND
GND
GND
GND
LSTo23 LSTo24 LSTo25
GND
GND
GND
GND
LSTo26 LSTo27 LSTo28 LSTo29
K
VDD_
CORE
BORS
BSTi0
VDD_IO
GND
GND
GND
GND
LSTo30 LSTo31
LORS
VDD_
CORE
L
BSTi1
BSTi2
BSTi3
BSTi4
GND
GND
GND
GND
VDD_IO
LSTi0
LSTi1
LSTi2
M
BSTi5
BSTi6
BSTi7
BSTi8
GND
GND
GND
GND
LSTi3
LSTi4
LSTi5
LSTi6
N
BSTi9
BSTi10
VDD_
CORE
GND
GND
LSTi7
LSTi8
LSTi9
P
BSTi11
BSTi12
BSTi13
BSTi14
LSTi10
VDD_
CORE
LSTi11
LSTi12
R
BSTi15
BSTI16
BSTi17 VDD_IO
VDD_IO LSTi13
LSTi14
LSTi15
T
BSTi18
BSTi19
BSTi20
BSTi21
U
BSTi22
NC
NC
GND
V
VDD_
CORE
NC
NC
W
BSTi23
BSTi24
Y
BSTi26
BSTi27
VDD_
CORE
LSTi16
LSTi17
LSTi18
BSTi28 VDD_IO
D10
GND
D4
VDD_IO
GND
VDD_
PLL
GND
FP8i
VDD_IO
VDD_
CORE
GND
LSTi19
LSTi20
LSTi21
BSTi29
VDD_
CORE
D13
D9
D7
D3
D0
IC_GND
NC
C8o
FP8o
NC
NC
LSTi22
LSTi23
LSTi24
LSTi25
BSTi25
BSTi30
D15
D12
D8
D6
D2
IC_GND IC_GND
C8i
C16o
FP16o
NC
NC
NC
LSTi26
LSTi27
NC
NC
BSTi31
D14
D11
VDD_
CORE
D5
D1
IC_GND
IC_
OPEN
IC_
OPEN
VDD_
CORE
NC
NC
LSTi29
LSTi30
LSTi31
LSTi28
VDD_
CORE
Figure 2 - ZL50061 PBGA Connections (272 PBGA, 27 mm x 27 mm) Pin Diagram
(as viewed through top of package)
9
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Pinout Diagram: (as viewed through top of package)
A1 corner identified by metallized marking
1
2
3
4
5
6
7
8
A
A0
A1
A2
A3
A4
DS
R/W
CS
B
BSTo0
BSTo1
BSTo2
BSTo3
A5
A6
A7
A8
A9
ODE
RESET
TMS
LSTo0
LSTo1
LSTo2
LSTo3
C
BSTo4
BSTo5
BSTo6
BSTo7
A10
A11
A12
A13
A14
DTA
TDi
TDo
LSTo4
LSTo5
LSTo6
LSTo7
D
BSTo8
BSTo9
BSTo10 BSTo11
TCK
TRST
LORS
LSTo8
LSTo9
LSTo10
LSTo11
E
BSTo12 BSTo13 BSTo14 BSTo15 VDD_IO VDD_IO
F
BSTo16 BSTo17 BSTo18 BSTo19 VDD_IO
G
BORS
9
10
11
12
13
14
15
16
BCSTo0 BCSTo1 BCSTo2 BCSTo3 LCSTo3 LCSTo2 LCSTo1 LCSTo0
IC_GND IC_GND IC_GND IC_GND
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_
CORE
VDD_IO VDD_IO LSTo12 LSTo13 LSTo14 LSTo15
VDD_
CORE
GND
GND
GND
GND
VDD_
CORE
VDD_IO LSTo16 LSTo17 LSTo18 LSTo19
BSTo20 BSTo21 BSTo22 BSTo23 VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO LSTo20 LSTo21 LSTo22 LSTo23
H
BSTo24 BSTo25 BSTo26 BSTo27 VDD_IO
GND
GND
GND
GND
GND
GND
VDD_IO LSTo24
J
BSTo28 BSTo29 BSTo30 BSTo31
VDD_
CORE
GND
GND
GND
GND
GND
GND
VDD_
CORE
LST25
LSTo26 LSTo27
LSTo28 LSTo29 LSTo30 LSTo31
K
BSTi0
BSTi1
BSTi2
BSTi3
VDD_
CORE
GND
GND
GND
GND
GND
GND
VDD_
CORE
LSTi0
LSTi1
LSTi2
LSTi3
L
BSTi4
BSTi5
BSTi6
BSTi7
VDD_IO
VDD_
CORE
VDD_
CORE
GND
GND
VDD_
CORE
VDD_
CORE
VDD_IO
LSTi4
LSTi5
LSTi6
LSTi7
M
BSTi8
BSTi9
BSTi10
BSTi11 VDD_IO
D3
D2
D1
D0
VDD_
PLL
NC
VDD_IO
LSTi8
LSTi9
LSTi10
LSTi11
N
BSTi12
BSTi13
BSTi14
BSTi15
BSTi16
D7
D6
D5
D4
IC_
OPEN
IC_
OPEN
LSTi12
LSTi13
LSTi14
LSTi15
LSTi16
P
BSTi17
BSTi18
BSTi19
BSTi20
BSTi21
D11
D10
D9
D8
C16o
FP16o
LSTi17
LSTi18
LSTi19
LSTi20
LSTi21
R
BSTi22
BSTi23
BSTi24
BSTi25
BSTi26
D15
D14
D13
D12
FP8o
FP8i
LSTi22
LSTi23
LSTi24
LSTi25
LSTi26
T
BSTi27
BSTi28
BSTi29
BSTi30
BSTi31 IC_GND IC_GND IC_GND IC_GND
C8i
C8o
LSTi27
LSTi28
LSTi29
LSTi30
LSTi31
Figure 3 - ZL50060 PBGA Connections (256 PBGA, 17 mm x 17 mm) Pin Diagram
(as viewed through top of package)
10
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Pin Description
ZL50061
Package
Coordinates
(272-ball
PBGA)
ZL50060
Package
Coordinates
(256-ball
PBGA)
C8i
W12
T10
Master Clock (5 V Tolerant Schmitt-Triggered Input). This
pin accepts an 8.192 MHz clock. The internal frame boundary
is aligned with the clock falling or rising edge, as controlled by
the C8IPOL bit in the Control Register. Input data on both the
Backplane and Local sides (BSTi0-31 and LSTi0-31) must be
aligned to this clock and the accompanying input frame pulse,
FP8i.
FP8i
U14
R11
Frame Pulse Input (5 V Tolerant Schmitt-Triggered Input).
When the Frame Pulse Width bit (FPW) of the Control
Register is LOW (default), this pin accepts a 122 ns-wide
frame pulse. When the FPW bit is HIGH, this pin accepts a
244 ns-wide frame pulse. The device will automatically detect
whether an ST-BUS or GCI-Bus style frame pulse is applied.
Input data on both the Backplane and Local sides (BSTi0-31
and LSTi0-31) must be aligned to this frame pulse and the
accompanying input clock, C8i.
C8o
V13
T11
C8o Output Clock (5 V Tolerant Three-state Output). This
pin outputs an 8.192 MHz clock generated within the device.
The clock falling edge or rising edge is aligned with the output
frame boundary presented on FP8o; this edge polarity
alignment is controlled by the COPOL bit of the Control
Register. Output data on both the Backplane and Local sides
(BSTo0-31 and LSTo0-31) will be aligned to this clock and the
accompanying output frame pulse, FP8o.
FP8o
V14
R10
Frame Pulse Output (5 V Tolerant Three-state Output).
When the Frame Pulse Width bit (FPW) of the Control
Register is LOW (default), this pin outputs a 122 ns-wide
frame pulse. When the FPW bit is HIGH, this pin outputs a
244 ns-wide frame pulse. The frame pulse, running at 8 kHz
rate, will have the same format (ST-BUS or GCI-Bus) as the
input frame pulse (FP8i). Output data on both the Backplane
and Local sides (BSTo0-31 and LSTo0-31) will be aligned to
this frame pulse and the accompanying output clock, C8o.
C16o
W13
P10
C16o Output Clock (5 V Tolerant Three-state Output). This
pin outputs a 16.384 MHz clock generated within the device.
The clock falling edge or rising edge is aligned with the output
frame boundary presented on FP16o; this edge polarity
alignment is controlled by the COPOL bit of the Control
Register. Output data on both the Backplane and Local sides
(BSTo0-31 and LSTo0-31) will be aligned to this clock and the
accompanying output frame pulse, FP16o.
Pin Name
Description
Device Timing
11
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Pin Description (continued)
Pin Name
ZL50061
Package
Coordinates
(272-ball
PBGA)
ZL50060
Package
Coordinates
(256-ball
PBGA)
FP16o
W14
P11
Description
Frame Pulse Output (5 V Tolerant Three-state Output).
When the Frame Pulse Width bit (FPW) of the Control
Register is LOW (default), this pin outputs a 61 ns-wide frame
pulse. When the FPW bit is HIGH, this pin outputs a
122 ns-wide frame pulse. The frame pulse, running at 8 kHz
rate, will have the same format (ST-BUS or GCI-Bus) as the
input frame pulse (FP8i). Output data on both the Backplane
and Local sides (BSTo0-31 and LSTo0-31) will be aligned to
this frame pulse and the accompanying output clock, C16o.
Backplane and Local Inputs
BSTi0-15
K3, L1, L2,
L3, L4, M1,
M2, M3, M4,
N1, N2, P1,
P2, P3, P4,
R1
K1, K2, K3,
K4, L1, L2,
L3, L4, M1,
M2, M3, M4,
N1, N2, N3,
N4
Backplane Serial Input Streams 0 to 15 (5 V Tolerant
Inputs with Internal Pull-downs).
In Backplane Non-32 Mbps Mode, these pins accept serial
TDM data streams at a data rate of:
16.384 Mbps (with 256 channels per stream),
8.192 Mbps (with 128 channels per stream),
4.096 Mbps (with 64 channels per stream) or
2.048 Mbps (with 32 channels per stream).
The data rate is independently programmable for each input
stream.
In Backplane 32 Mbps Mode, these pins accept serial TDM
data streams at a fixed data rate of 32.768 Mbps (with 512
channels per stream).
BSTi16-31
R2, R3, T1,
T2, T3, T4,
U1, W1, W2,
W3, Y1, Y2,
U5, V4, W4,
Y4
N5, P1, P2,
P3, P4, P5,
R1, R2, R3,
R4, R5, T1,
T2, T3, T4, T5
Backplane Serial Input Streams 16 to 31 (5 V Tolerant
Inputs with Internal Pull-downs).
In Backplane Non-32 Mbps Mode, these pins accept serial
TDM data streams at a data rate of:
16.384 Mbps (with 256 channels per stream),
8.192 Mbps (with 128 channels per stream),
4.096 Mbps (with 64 channels per stream) or
2.048 Mbps (with 32 channels per stream).
The data rate is independently programmable for each input
stream.
In Backplane 32 Mbps Mode, these pins are unused and
should be externally connected to a defined logic level.
12
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Pin Description (continued)
Pin Name
LSTi0-15
ZL50061
Package
Coordinates
(272-ball
PBGA)
ZL50060
Package
Coordinates
(256-ball
PBGA)
L18, L19,
L20, M17,
M18, M19,
M20, N18,
N19, N20,
P17, P19,
P20, R18,
R19, R20
K13, K14,
K15, K16,
L13, L14,
L15, L16,
M13, M14,
M15, M16,
N12, N13,
N14, N15
Description
Local Serial Input Streams 0 to 15 (5 V Tolerant Inputs
with Internal Pull-downs).
In Local Non-32 Mbps Mode, these pins accept serial TDM
data streams at a data rate of:
16.384 Mbps (with 256 channels per stream),
8.192 Mbps (with 128 channels per stream),
4.096 Mbps (with 64 channels per stream) or
2.048 Mbps (with 32 channels per stream).
The data rate is independently programmable for each input
stream.
In Local 32 Mbps Mode, these pins accept serial TDM data
streams at a fixed data rate of 32.768 Mbps (with 512
channels per stream).
LSTi16-31
T18, T19,
T20, U18,
U19, U20,
V17, V18,
V19, V20,
W18, W19,
Y20, Y17,
Y18, Y19
N16, P12,
P13, P14,
P15, P16,
R12, R13,
R14, R15,
R16, T12,
T13, T14,
T15, T16
Local Serial Input Streams 16 to 31 (5 V Tolerant Inputs
with Internal Pull-downs).
In Local Non-32 Mbps Mode, these pins accept serial TDM
data streams at a data rate of:
16.384 Mbps (with 256 channels per stream),
8.192 Mbps (with 128 channels per stream),
4.096 Mbps (with 64 channels per stream) or
2.048 Mbps (with 32 channels per stream).
The data rate is independently programmable for each input
stream.
In Local 32 Mbps Mode, these pins are unused and should be
externally connected to a defined logic level.
Backplane and Local Outputs and Control
ODE
A12
B10
Output Drive Enable (5 V Tolerant Input with Internal
Pull-up).
An asynchronous input providing Output Enable control to the
BSTo0-31, LSTo0-31, BCSTo0-3, and LCSTo0-3 outputs.
When LOW, the BSTo0-31 and LSTo0-31 outputs are driven
HIGH or high impedance (dependent on the BORS and LORS
pin settings respectively) and the outputs BCSTo0-3 and
LCSTo0-3 are driven low.
When HIGH, the outputs BSTo0-31, LSTo0-31, BCSTo0-3,
and LCSTo0-3 are enabled.
13
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Pin Description (continued)
Pin Name
ZL50061
Package
Coordinates
(272-ball
PBGA)
ZL50060
Package
Coordinates
(256-ball
PBGA)
BORS
K2
D5
Description
Backplane Output Reset State (5 V Tolerant Input with
Internal Pull-down).
When this input is LOW, the device will initialize with the
BSTo0-31 outputs driven high, and the BCSTo0-3 outputs
driven low. Following initialization, the Backplane stream
outputs are always active and a high impedance state, if
required on a per-channel basis, may be implemented with
external buffers controlled by outputs BCSTo0-3.
When this input is HIGH, the device will initialize with the
BSTo0-31 outputs at high impedance and the BCSTo0-3
outputs driven low. Following initialization, the Backplane
stream outputs may be set active or high impedance using the
ODE pin or on a per-channel basis with the BE bit in the
Backplane Connection Memory.
BSTo0-15
C5, B5, A5,
C4, A4, A3,
B1, B2, B3,
C1, C2, D1,
D2, D3, E1,
E2
B1, B2, B3,
B4, C1, C2,
C3, C4, D1,
D2, D3, D4,
E1, E2, E3,
E4
Backplane Serial Output Streams 0 to 15 (5 V Tolerant,
Three-state Outputs with Slew-Rate Control).
In Backplane Non-32 Mbps Mode, these pins output serial
TDM data streams at a data rate of:
16.384 Mbps (with 256 channels per stream),
8.192 Mbps (with 128 channels per stream),
4.096 Mbps (with 64 channels per stream) or
2.048 Mbps (with 32 channels per stream).
The data rate is independently programmable for each output
stream.
In Backplane 32 Mbps Mode, these pins output serial TDM
data streams at a fixed data rate of 32.768 Mbps (with 512
channels per stream).
Refer to the descriptions of the BORS and ODE pins for
control of the output HIGH or high impedance state.
14
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Pin Description (continued)
Pin Name
BSTo16-31
ZL50061
Package
Coordinates
(272-ball
PBGA)
ZL50060
Package
Coordinates
(256-ball
PBGA)
E3, E4, F1,
F2, F3, G1,
G2, G3, G4,
H1, H2, H3,
J1, J2, J3, J4
F1, F2, F3,
F4, G1, G2,
G3, G4, H1,
H2, H3, H4,
J1, J2, J3, J4
Description
Backplane Serial Output Streams 16 to 31 (5 V Tolerant,
Three-state Outputs with Slew-Rate Control).
In Backplane Non-32 Mbps Mode, these pins output serial
TDM data streams at a data rate of:
16.384 Mbps (with 256 channels per stream),
8.192 Mbps (with 128 channels per stream),
4.096 Mbps (with 64 channels per stream) or
2.048 Mbps (with 32 channels per stream).
The data rate is independently programmable for each output
stream.
These pins are unused when the Backplane 32 Mbps Mode is
selected. Therefore, the value output on these pins during
Backplane 32 Mbps Mode (either driven-HIGH or high
impedance) is dependent on the configuration of the BORS
pin.
Refer to the descriptions of the BORS and ODE pins for
control of the output HIGH or high impedance state.
BCSTo0-3
C14, A15,
B15, C15
A9, A10, A11,
A12
Backplane Output Channel high impedance Control (5 V
Tolerant, Three-state Outputs). These pins control external
buffering individually for a set of Backplane output streams on
a per-channel basis.
When LOW, the external output buffer will be tri-stated.
When HIGH, the external output buffer will be enabled.
In Backplane Non-32 Mbps Mode (stream rates 2 Mbps to
16Mbps):
BCSTo0 is the output enable for BSTo0,4,8,12,16,20,24,28
BCSTo1 is the output enable for BSTo1,5,9,13,17,21,25,29
BCSTo2 is the output enable for BSTo2,6,10,14,18,22,26,30
BCSTo3 is the output enable for BSTo3,7,11,15,19,23,27,31.
In Backplane 32Mbps Mode (stream rate 32Mbps):
BCSTo0 is the output enable for BSTo0,4,8,12
BCSTo1 is the output enable for BSTo1,5,9,13
BCSTo2 is the output enable for BSTo2,6,10,14
BCSTo3 is the output enable for BSTo3,7,11,15.
Refer to the descriptions of the BORS and ODE pins for
control of the output LOW or active state.
15
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Pin Description (continued)
Pin Name
ZL50061
Package
Coordinates
(272-ball
PBGA)
ZL50060
Package
Coordinates
(256-ball
PBGA)
LORS
K19
D12
Description
Local Output Reset State (5 V Tolerant Input with Internal
Pull-down).
When this input is LOW, the device will initialize with the
LSTo0-31 outputs driven high, and the LCSTo0-3 outputs
driven low. Following initialization, the Local stream outputs
are always active and a high impedance state, if required on a
per-channel basis, may be implemented with external buffers
controlled by outputs LCSTo0-3.
When this input is HIGH, the device will initialize with the
LSTo0-31 outputs at high impedance and the LCSTo0-3
outputs driven low. Following initialization, the Local stream
outputs may be set active or high impedance using the ODE
pin or on a per-channel basis with the LE bit in the Local
Connection Memory.
LSTo0-15
A17, A18,
A19, B18,
B19, B20,
C18, C19,
C20, D18,
D19, D20,
E17, E18,
E19, E20
B13, B14,
B15, B16,
C13, C14,
C15, C16,
D13, D14,
D15, D16,
E13, E14,
E15, E16
Local Serial Output Streams 0 to 15 (5 V Tolerant
Three-state Outputs with Slew-Rate Control).
In Local Non-32 Mbps Mode, these pins output serial TDM
data streams at a data rate of:
16.384 Mbps (with 256 channels per stream),
8.192 Mbps (with 128 channels per stream),
4.096 Mbps (with 64 channels per stream) or
2.048 Mbps (with 32 channels per stream).
The data rate is independently programmable for each output
stream.
In Local 32 Mbps Mode, these pins output serial TDM data
streams at a fixed data rate of 32.768 Mbps (with 512
channels per stream).
Refer to the descriptions of the LORS and ODE pins for
control of the output HIGH or high impedance state.
16
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Pin Description (continued)
Pin Name
LSTo16-31
ZL50061
Package
Coordinates
(272-ball
PBGA)
ZL50060
Package
Coordinates
(256-ball
PBGA)
F18, F19,
F20, G17,
G18, G19,
G20, H18,
H19, H20,
J17, J18, J19,
J20, K17, K18
F13, F14,
F15, F16,
G13, G14,
G15, G16,
H13, H14,
H15, H16,
J13, J14, J15,
J16
Description
Local Serial Output Streams 16 to 31 (5 V Tolerant
Three-state Outputs with Slew-Rate Control).
In Local Non-32 Mbps Mode, these pins output serial TDM
data streams at a data rate of:
16.384 Mbps (with 256 channels per stream),
8.192 Mbps (with 128 channels per stream),
4.096 Mbps (with 64 channels per stream) or
2.048 Mbps (with 32 channels per stream).
The data rate is independently programmable for each output
stream.
These pins are unused when the Local 32 Mbps Mode is
selected. Therefore, the value output on these pins during
Local 32 Mbps Mode (either driven-HIGH or high impedance)
is dependent on the configuration of the LORS pin.
Refer to the descriptions of the LORS and ODE pins for
control of the output HIGH or high impedance state.
LCSTo0-3
C17, C16,
B16, A16
A16, A15,
A14, A13
Local Output Channel high impedance Control (5 V
Tolerant Three-state Outputs). These pins control external
buffering individually for a set of Local output streams on a
per-channel basis.
When LOW, the external output buffer will be tri-stated.
When HIGH, the external output buffer will be enabled.
In Local Non-32 Mbps Mode (stream rate 2 Mbps to 16 Mbps):
LCSTo0 is the output enable for LSTo0,4,8,12,16,20,24,28
LCSTo1 is the output enable for LSTo1,5,9,13,17,21,25,29
LCSTo2 is the output enable for LSTo2,6,10,14,18,22,26,30
LCSTo3 is the output enable for LSTo3,7,11,15,19,23,27,31.
In Local 32 Mbps Mode (stream rate 32 Mbps):
LCSTo0 is the output enable for LSTo0,4,8,12
LCSTo1 is the output enable for LSTo1,5,9,13
LCSTo2 is the output enable for LSTo2,6,10,14
LCSTo3 is the output enable for LSTo3,7,11,15.
Refer to descriptions of the LORS and ODE pins for control of
the output LOW or active state.
17
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Pin Description (continued)
Pin Name
ZL50061
Package
Coordinates
(272-ball
PBGA)
ZL50060
Package
Coordinates
(256-ball
PBGA)
Description
Microprocessor Port Signals
A0 - A14
D5, C6, A6,
D7, C7, B7,
C8, B8, A8,
D9, B9, A9,
D10, C10,
A10
A1, A2, A3,
A4, A5, B5,
B6, B7, B8,
B9, C5, C6,
C7, C8, C9
Address 0 - 14 (5 V Tolerant Inputs). These pins form the
15-bit address bus to the internal memories and registers.
A0 = LSB
D0 - D15
V10, Y9, W9,
V9, U9, Y8,
W8, V8, W7,
V7, U7, Y6,
W6, V6, Y5,
W5
M9, M8, M7,
M6, N9, N8,
N7, N6, P9,
P8, P7, P6,
R9, R8, R7,
R6
Data Bus 0 - 15 (5 V Tolerant Inputs/Outputs with
Slew-Rate Control). These pins form the 16-bit data bus of
the microprocessor port.
D0 = LSB
CS
B11
A8
Chip Select (5 V Tolerant Input). Active LOW input used by
the microprocessor to enable the microprocessor port access.
Note that a minimum of 30 ns must separate the
de-assertion of DTA (to high) and the assertion of CS
and/or DS to initiate the next access.
DS
A11
A6
Data Strobe (5 V Tolerant Input). This active LOW input
works in conjunction with CS to enable the microprocessor
port read and write operations. Note that a minimum of
30 ns must separate the de-assertion of DTA (to high) and
the assertion of CS and/or DS to initiate the next access.
R/W
C11
A7
Read/Write (5 V Tolerant Input). This input controls the
direction of the data bus lines (D0-D15) during a
microprocessor access.
DTA
A13
C10
Data Transfer Acknowledgment (5 V Tolerant Three-state
Output). This active LOW output indicates that a data bus
transfer is complete. A pull-up resistor is required to hold a
HIGH level. Note that a minimum of 30 ns must separate
the de-assertion of DTA (to high) and the assertion of CS
and/or DS to initiate the next access.
18
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Pin Description (continued)
Pin Name
ZL50061
Package
Coordinates
(272-ball
PBGA)
ZL50060
Package
Coordinates
(256-ball
PBGA)
RESET
C12
B11
Device Reset (5 V Tolerant Input with Internal Pull-up).
This input (active LOW) asynchronously applies reset and
synchronously releases reset to the device. In the reset state,
the outputs LSTo0-31 and BSTo0-31 are set to a HIGH or high
impedance state, depending on the state of the LORS and
BORS external control pins, respectively. The assertion of
RESET causes the LCSTo0-3 and BCSTo0-3 pins to be driven
LOW (refer to Table 2). The assertion of this pin also clears
the device registers and internal counters. Refer to
Section 8.3 on page 47 for the timing requirements
regarding this reset signal.
Description
JTAG Control Signals
TCK
A14
D10
Test Clock (5 V Tolerant Input).
Provides the clock to the JTAG test logic.
TMS
D12
B12
Test Mode Select (5 V Tolerant Input with Internal Pull-up).
JTAG signal that controls the state transitions of the TAP
controller.
TDi
B13
C11
Test Serial Data In (5 V Tolerant Input with Internal
Pull-up).
JTAG serial test instructions and data are shifted in on this pin.
TDo
C13
C12
Test Serial Data Out (5 V Tolerant Three-state Output).
JTAG serial data is output on this pin on the falling edge of
TCK. This pin is held in a high impedance state when JTAG is
not enabled.
TRST
B14
D11
Test Reset (5 V Tolerant Input with Internal Pull-up).
Asynchronously initializes the JTAG TAP controller to the
Test-Logic-Reset state. This pin must be pulsed LOW during
power-up for JTAG testing. This pin must be held LOW for
normal functional operation of the device.
Power and Ground Pins
VDD_IO
D6, D11, D15,
F4, F17, K4,
L17, R4, R17,
U6, U10, U15
E5, E6, E11,
E12, F5, F12,
G5, G12, H5,
H12, L5, L12,
M5, M12
Power Supply for Periphery Circuits: +3.3 V
VDD_CORE
A7, B4, B12,
D14, K1, K20,
N3, P18, T17,
U16, V1, V5,
Y7, Y11, Y14
E7, E8, E9,
E10, F6, F11,
J5, J12, K5,
K12, L6, L7,
L10, L11
Power Supply for Core Circuits: +1.8 V
19
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Pin Description (continued)
Pin Name
ZL50061
Package
Coordinates
(272-ball
PBGA)
ZL50060
Package
Coordinates
(256-ball
PBGA)
VDD_PLL
U12
M10
VSS (GND)
A1, D4, D8,
D13, D17,
H4, H17, J9,
J10, J11, J12,
K9, K10, K11,
K12, L9, L10,
L11, L12, M9,
M10, M11,
M12, N4,
N17, U4, U8,
U11, U13,
U17
F7, F8, F9,
F10, G6, G7,
G8, G9, G10,
G11, H6, H7,
H8, H9, H10,
H11, J6, J7,
J8, J9, J10,
J11, K6, K7,
K8, K9, K10,
K11, L8, L9
NC
A20, B6, B10,
C9, U2, U3,
V2, V3, V12,
V15, V16,
W15, W16,
W17, W20,
Y3, Y15, Y16
M11
IC_OPEN
Y12, Y13
N10, N11
IC_GND
A2, B17, C3,
D16, V11,
W10, W11,
Y10
D6, D7, D8,
D9, T6, T7,
T8, T9
Description
Power Supply for Analog PLL: +1.8 V
Ground.
Unused Pins
No Connects. These pins are not used and can be tied HIGH,
LOW, or left unconnected.
Internal Connections - OPEN. These pins must be left
unconnected.
Internal Connections - GND. These pins must be tied LOW.
20
Zarlink Semiconductor Inc.
ZL50060/1
1.0
Data Sheet
Unidirectional and Bi-directional Switching Applications
The ZL50060/1 has a maximum capacity of 16,384 input channels and 16,384 output channels. This is calculated
from the maximum number of streams and channels: 64 input streams (32 Backplane, 32 Local) at 16.384 Mbps
and 64 output streams (32 Backplane, 32 Local) at 16.384 Mbps.
A typical mode of operation is to separate the input and output streams to form a unidirectional switch, as shown in
Figure 4 below.
BSTi0-31
BSTo0-31
32 streams
32 streams
INPUT
OUTPUT
LSTi0-31
32 streams
LSTo0-31
32 streams
ZL50060/1
Figure 4 - 16,384 x 16,384 Channels (16 Mbps), Unidirectional Switching
In this system, the Backplane and Local input streams are combined, and the Backplane and Local output streams
are combined, so that the switch appears as a 64 input stream by 64 output stream switch. This gives the maximum
16,384 x 16,384 channel capacity.
Often a system design needs to differentiate between a Backplane and a Local side, or it needs to put the switch in
a bi-directional configuration. In this case, the ZL50060/1 can be used as shown in Figure 5 to give 8,192 x 8,192
channel bi-directional capacity.
BSTi0-31
LSTo0-31
32 streams
32 streams
BACKPLANE
LOCAL
BSTo0-31
32 streams
LSTi0-31
32 streams
ZL50060/1
Figure 5 - 8,192 x 8,192 Channels (16 Mbps), Bi-directional Switching
In this system setup, the chip has a capacity of 8,192 input channels and 8,192 output channels on the Backplane
side, as well as 8,192 input channels and 8,192 output channels on the Local side. Note that some or all of the
output channels on one side can come from the other side, e.g., Backplane input to Local output switching.
Note that in either configuration, the Backplane port can be operated in the Backplane 32Mbps Mode, providing
512 channels on each of the 16 available input and output streams (BSTi0-15 and BSTo0-15) operating at a data
rate of 32.768 Mbps, in conjunction with the Local streams (LSTi0-31 and LSTo0-31) operating at 16.384 Mbps
(Local Non-32 Mbps Mode) or in conjunction with the Local streams (LSTi0-15 and LSTo0-15) operating at
32.768 Mbps (Local 32 Mbps Mode). Similarly, the Local port can be operated in the Local 32 Mbps Mode,
providing 512 channels on each of the 16 available input and output streams (LSTi0-15 and LSTo0-15) operating at
a data rate of 32.768 Mbps, in conjunction with the Backplane streams (BSTi0-31 and BSTo0-31) operating at
16.384 Mbps (Backplane Non-32 Mbps Mode) or in conjunction with the Backplane streams (BSTi0-15 and
BSTo0-15) operating at 32.768 Mbps (Backplane 32 Mbps Mode).
21
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
The modes in which one port operates in 32Mbps Mode while the other port operates in Non-32 Mbps Mode allow
data rate conversion between 32.768 Mbps and 16.384 Mbps without loss to the switching capacity.
1.1
Flexible Configuration
The ZL50060/1 can be configured as a 16 K by 16 K non-blocking unidirectional digital switch, an 8 K by 8 K
non-blocking bi-directional digital switch, or as a blocking switch with various switching capacities.
1.1.1
Non-Blocking Unidirectional Configuration (Typical System Configuration)
Because the input and output drivers are synchronous, the user can combine input Backplane streams and input
Local streams as well as output Backplane streams and output Local streams to increase the total number of input
and output streams of the switch in a unidirectional configuration, as shown in Figure 4.
•
16,384-channel x 16,384-channel non-blocking switching from input to output streams
1.1.2
Non-Blocking Bi-directional Configuration
Another typical application is to configure the ZL50060/1 as a non-blocking 8 K by 8 K bi-directional switch, as
shown in Figure 5:
•
8,192-channel x 8,192-channel non-blocking switching from Backplane input to Local output streams
•
8,192-channel x 8,192-channel non-blocking switching from Local input to Backplane output streams
•
8,192-channel x 8,192-channel non-blocking switching from Backplane input to Backplane output streams
•
8,192-channel x 8,192-channel non-blocking switching from Local input to Local output streams
1.1.3
Blocking Bi-directional Configuration
The ZL50060/1 can be configured as a blocking bi-directional switch if it is an application requirement. For
example, it can be configured as a 12 K by 4 K bi-directional blocking switch, as shown in Figure 6:
•
12,288-channel x 4,096-channel blocking switching from Backplane input to Local output streams
•
4,096-channel x 12,288-channel blocking switching from Local input to Backplane output streams
•
12,288-channel x 12,288-channel non-blocking switching from Backplane input to Backplane output streams
•
4,096-channel x 4,096-channel non-blocking switching from Local input to Local output streams
ZL50060/1
BSTi0-31
12K by 4K
LSTi0-15
BSTo0-31
12K by 12K
LSTo0-15
LSTi16-31
4K by 4K
LSTo16-31
4K by 12K
Total 48 streams input and 48 streams output
Total 16 streams input and 16 streams output
Figure 6 - 12,288 by 4,096 Channels Blocking Bi-directional Configuration
22
Zarlink Semiconductor Inc.
ZL50060/1
2.0
Functional Description
2.1
Switching Configuration
Data Sheet
The device supports five switching configurations: (1) Unidirectional switch, (2) Backplane-to-Local, (3)
Local-to-Backplane, (4) Backplane-to-Backplane, and (5) Local-to-Local. The following sections describe the
switching paths in detail. Configurations (2) - (5) enable a non-blocking bi-directional switch with 8,192 Backplane
input/output channels at Backplane stream data rates of 16.384 Mbps or 32.768 Mbps, and 8,192 Local
input/output channels at Local stream data rates of 16.384 Mbps or 32.768 Mbps. The switching paths of
configurations (2) to (5) may be operated simultaneously. When the lower data-rates of 8.192, 4.096 and
2.048 Mbps are included, there will be a corresponding reduction in switch capacity although conversion between
differing rates will be maintained.
2.1.1
Unidirectional Switch
The device can be configured as a 16,384 x 16,384 unidirectional switch by grouping together all input streams and
all output streams. All streams can be operated at a data rate of 16.384 Mbps or 32.768 Mbps, or a combination of
16.384 Mbps and 32.768 Mbps (i.e., one rate on the Local streams and the other rate on the Backplane streams).
Lower data rates may be used with a corresponding reduction in switch capacity.
2.1.2
Backplane-to-Local Path
The device can provide data switching between the Backplane input port and the Local output port. The Local
Connection Memory determines the switching configurations.
2.1.3
Local-to-Backplane Path
The device can provide data switching between the Local input port and the Backplane output port. The Backplane
Connection Memory determines the switching configurations.
2.1.4
Backplane-to-Backplane Path
The device can provide data switching between the Backplane input and output ports. The Backplane Connection
Memory determines the switching configurations.
2.1.5
Local-to-Local Path
The device can provide data switching between the Local input and output ports. The Local Connection Memory
determines the switching configurations.
2.1.6
Port Data Rate Modes and Selection
The bit rate for each input stream is selected by writing to dedicated input bit rate registers, BIBRR0 to BIBRR31 for
Backplane Input Bit Rate Registers (see Table 50) and LIBRR0 to LIBRR31 for Local Input Bit Rate Registers (see
Table 46).
The bit rate for each output stream is selected by writing to dedicated output bit rate registers, BOBRR0 to
BOBRR31 for Backplane Output Bit Rate Registers (see Table 52) and LOBRR0 to LOBRR31 for Local Output Bit
Rate Registers (see Table 48).
If the Backplane 32 Mbps Mode is selected by setting the Control Register bit MODE32B HIGH, the settings in
BIBRRn and BOBRRn are ignored. Similarly, if the Local 32 Mbps Mode is selected by setting the Control Register
bit MODE32L HIGH, the settings in LIBRRn and LOBRRn are ignored.
23
Zarlink Semiconductor Inc.
ZL50060/1
Stream Numbers
Data Sheet
Rate Selection Capability (for each individual stream)
Local Input streams - LSTi0-15
2.048, 4.096, 8.192 or 16.384 Mbps in Local Non-32 Mbps Mode.
All streams at 32.768 Mbps in Local 32 Mbps Mode.
Local Input streams - LSTi16-31
2.048, 4.096, 8.192 or 16.384 Mbps in Local Non-32 Mbps Mode.
Unused in Local 32 Mbps Mode.
Backplane Input streams - BSTi0-15
2.048, 4.096, 8.192 or 16.384 Mbps in Backplane Non-32 Mbps
Mode.
All streams at 32.768 Mbps in Backplane 32 Mbps Mode.
Backplane Input streams - BSTi16-31
2.048, 4.096, 8.192 or 16.384 Mbps in Backplane Non-32 Mbps
Mode.
Unused in Backplane 32 Mbps Mode.
Local Output streams - LSTo0-15
2.048, 4.096, 8.192 or 16.384 Mbps in Local Non-32 Mbps Mode.
All streams at 32.768 Mbps in Local 32 Mbps Mode.
Local Output streams - LSTo16-31
2.048, 4.096, 8.192 or 16.384 Mbps in Local Non-32 Mbps Mode.
Unused in Local 32 Mbps Mode.
Backplane Output streams - BSTo0-15
2.048, 4.096, 8.192 or 16.384 Mbps in Backplane Non-32 Mbps
Mode.
All streams at 32.768 Mbps in Backplane 32Mbps Mode.
Backplane Output streams - BSTo16-31
2.048, 4.096, 8.192 or 16.384 Mbps in Backplane Non-32 Mbps
Mode.
Unused in Backplane 32 Mbps Mode.
Table 1 - Per-stream Input and Output Data Rate Selection: Backplane and Local
2.1.7
Local Port Rate Selection
The Local port has 32 input (LSTi0-31) and 32 output (LSTo0-31) data streams.
The Local streams can be operated in one of two modes, Local Non-32 Mbps Mode and Local 32 Mbps Mode. The
Local stream data rates are not affected by the operating mode of the Backplane port. The operating mode of the
Local side is determined by the state of the Control Register bit MODE32L. Setting this bit HIGH will invoke the
Local 32 Mbps Mode. Setting the bit LOW will invoke the Non-32 Mbps Mode. The default value of this bit on device
reset is LOW. The timing of the input and output clocks and frame pulses is shown in Figure 8, “Input and Output
Frame Pulse Alignment for Different Data Rates” on page 28.
Local Non-32 Mbps Mode: Each of the Local streams (LSTi0-31 and LSTo0-31) can be independently programmed
for a data rate of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps.
Local 32 Mbps Mode: 16 of the Local input streams (LSTi0-15) and 16 of the Local output streams (LSTo0-15)
operate at a fixed rate of 32.768 Mbps. In this mode, the remaining input and output streams are unused.
2.1.7.1
Local Input Port
The input traffic on the Local streams are aligned based on the FP8i and C8i input timing signals. Each input
stream, LSTi0-31, can be individually set to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps by
programming the LIBR1-0 bits in the Local Input Bit Rate Register (LIBRR0-31). The Local streams can also be set
to operate at 32.768 Mbps. When the MODE32L bit in the Control Register is set high, the first 16 input streams,
LSTi0-15, operate at 32.768 Mbps and the remaining 16 streams, LSTi16-31, will not be used and must be
connected to a defined logic level.
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Zarlink Semiconductor Inc.
ZL50060/1
2.1.7.2
Data Sheet
Local Output Port
The output traffic on the Local streams are aligned based on the FP8o and C8o output timing signals. Operation of
stream data in Connection Mode or Message Mode is determined by the state of the LMM bit of the Local
Connection Memory. The channel high impedance state is controlled by the LE bit of the Local Connection Memory.
The data source (i.e. from the Local or Backplane Data Memory) is determined by the LSRC bit of the Local
Connection Memory. Refer to Section 9.1, Local Connection Memory, and Section 12.3, Local Connection Memory
Bit Definition for more details. Each output stream, LSTo0-31, can be individually set to operate at 2.048 Mbps,
4.096 Mbps, 8.192 Mbps or 16.384 Mbps by programming the LOBR1-0 bits in the Local Output Bit Rate Register
(LOBRR0-31). The Local streams can also be set to operate at 32.768 Mbps. When the MODE32L bit in the
Control Register is set high, the first 16 output streams, LSTo0-15, operate at 32.768 Mbps and the remaining 16
streams, LSTo16-31, will not be used and must be connected to a defined logic level.
2.1.8
Backplane Port Rate Selection
The Backplane port has 32 input (BSTi0-31) and 32 output (BSTo0-31) data streams.
The Backplane streams can be operated in one of two modes, Backplane Non-32 Mbps Mode and Backplane
32 Mbps Mode. The Backplane stream data rates are not affected by the operating mode of the Local port. The
operating mode of the Backplane side is determined by the state of the Control Register bit MODE32B. Setting this
bit HIGH will invoke the Backplane 32 Mbps Mode. Setting the bit LOW will invoke the Non-32 Mbps Mode. The
default value of this bit on device reset is LOW. The timing of the input and output clocks and frame pulses is shown
in Figure 8, “Input and Output Frame Pulse Alignment for Different Data Rates” on page 28.
Backplane Non-32 Mbps Mode: Each of the Backplane streams (BSTi0-31 and BSTo0-31) can be independently
programmed for a data rate of 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps.
Backplane 32 Mbps Mode: 16 of the Backplane input streams (BSTi0-15) and 16 of the Backplane output streams
(BSTo0-15) operate at a fixed rate of 32.768 Mbps. In this mode, the remaining input and output streams are
unused.
2.1.8.1
Backplane Input Port
The input traffic on the Backplane streams are aligned based on the FP8i and C8i input timing signals. Each input
stream, BSTi0-31, can be individually set to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps by
programming the BIBR1-0 bits in the Backplane Input Bit Rate Register (BIBRR0-31). The Backplane streams can
also be set to operate at 32.768 Mbps. When the MODE32B bit in the Control Register is set high, the first 16 input
streams, BSTi0-15, operate at 32.768 Mbps and the remaining 16 streams, BSTi16-31, will not be used and must
be connected to a defined logic level.
2.1.8.2
Backplane Output Port
The output traffic on the Backplane streams are aligned based on the FP8o and C8o output timing signals.
Operation of stream data in Connection Mode or Message Mode is determined by the state of the BMM bit of the
Backplane Connection Memory and the channel high impedance state is controlled by the BE bit of the Backplane
Connection Memory. The data source (i.e. from the Local or Backplane Data Memory) is determined by the BSRC
bit of the Backplane Connection Memory. Refer to Section 9.2, Backplane Connection Memory and Section 12.4,
Backplane Connection Memory Bit Definition for more details. Each output stream, BSTo0-31, can be individually
set to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps by programming the BOBR1-0 bits in the
Backplane Output Bit Rate Register (BOBRR0-31). The Backplane streams can also be set to operate at
32.768 Mbps. When the MODE32B bit in the Control Register is set high, the first 16 output streams, BSTo0-15,
operate at 32.768 Mbps and the remaining 16 streams, BSTo16-31, will not be used and must be connected to a
defined logic level.
25
Zarlink Semiconductor Inc.
ZL50060/1
2.2
Data Sheet
Frame Pulse Input and Master Input Clock Timing
The input frame pulse (FP8i) is an 8 kHz input signal active for 122 ns or 244 ns at the frame boundary. The FPW
bit in the Control Register must be set according to the applied pulse width. See Pin Description and Table 19,
“Control Register Bits” on page 56, for details.
The active state and timing of FP8i can conform either to the ST-BUS or to the GCI-Bus as shown in Figure 7,
ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates. The ZL50060/1 device will automatically
detect whether an ST-BUS or a GCI-Bus style frame pulse is being used for the master frame pulse (FP8i). The
output frame pulses (FP8o and FP16o) are always of the same style (ST-BUS or GCI-Bus) as the input frame
pulse. The active edge of the input clock (C8i) shall be selected by the state of the Control Register bit C8IPOL.
Note that the active edge of ST-BUS is falling edge, which is the default mode of the device, while GCI-Bus uses
rising edge as the active edge. Although GCI frame pulse will be automatically detected, to fully conform to
GCI-Bus operation, the device should be set to use C8i rising edge as the active edge (by setting bit C8IPOL HIGH)
when GCI-Bus is used.
For the purposes of describing the device operation, the remaining part of this document assumes the ST-BUS
frame pulse format with a single width frame pulse of 122ns and a falling active clock-edge, unless explicitly stated
otherwise.
In addition, the device provides FP8o, FP16o, C8o and C16o outputs to support external devices which connect to
the output ports. The generated frame pulses (FP8o, FP16o) will be provided in the same format as the master
frame pulse (FP8i). The polarity of C8o and C16o, at the frame boundary, can be controlled by the Control Register
bit, COPOL. An analog phase lock loop (APLL) is used to multiply the input clock frequency on C8i to generate an
internal clock signal operating at 131.072MHz.
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Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
FP8i (ST-BUS)
(8kHz)
C8i (ST-BUS)
(8.192MHz)
FP8i (GCI-Bus)
(8kHz)
C8i (GCI-Bus)
(8.192MHz)
Channel 0
Channel 510
Channel 1
BSTi/LSTi0-15
(32Mbps) ST-BUS
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
BSTi/LSTi0-15
(32Mbps) GCI-Bus
4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
Channel 0
Channel 510
Channel 1
1
0
7
6
5
Channel 255
3
4
2
1
0
6
5
Channel 0
BSTi/LSTi0-31
(16Mbps) GCI-Bus
6
7
0
1
2
5
6
7
1
2
Channel 0
BSTi/LSTi0-31
(8Mbps) ST-BUS
0
6
7
7
5
1
0
4
3
3
4
7
5
6
7
0
0
7
6
7
0
0
7
7
0
Channel 63
6
1
Channel 31
0
7
7
Channel 31
Channel 0
BSTi/LSTi0-31
(2Mbps) GCI-Bus 7
0
Channel 63
Channel 0
BSTi/LSTi0-31
(2Mbps) ST-BUS 0
1
1
1
6
0
4
5
Channel 0
BSTi/LSTi0-31
(4Mbps) GCI-Bus 7
2
Channel 127
2
7
3
2
Channel 0
BSTi/LSTi0-31
(4Mbps) ST-BUS 0
3
Channel 127
Channel 0
BSTi/LSTi0-31
(8Mbps) GCI-Bus
4
Channel 255
4
3
Channel 511
1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1
Channel 0
BSTi/LSTi0-31
(16Mbps) ST-BUS
Channel 511
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
7
0
Figure 7 - ST-BUS and GCI-Bus Input Timing Diagram for Different Data Rates
27
Zarlink Semiconductor Inc.
0
ZL50060/1
2.3
Data Sheet
Input Frame Pulse and Generated Frame Pulse Alignment
The ZL50060/1 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are
aligned to the master frame pulse. There is a constant throughput delay for data being switched from the input to
the output of the device such that data which is input during Frame N is output during Frame N+2.
For further details of frame pulse conditions and options, see Section 14.1, Control Register (CR), Figure 23, Frame
Boundary Conditions, ST-BUS Operation, and Figure 24, Frame Boundary Conditions, GCI-Bus Operation.
FP8i
C8i
BSTi/LSTi0-31
(2Mbps)
BSTi/LSTi0-31
(4Mbps)
BSTi/LSTi0-31
(8Mbps)
BSTi/LSTi0-31
(16Mbps)
BSTi/LSTi0-15
(32Mbps)
CH0
CH1
CH0
CH0
CH
0
CH
0 1
CH1
CH1
CH
1
2
CH
CH
3
2
3
4
CH2
5
6
CH
4
7
8
CH
5
CH3
CH2
CH3
CH
6
CH4
CH
7
CH
8
CH5
CH
9
CH
10
9 10 11 12 13 14 15 16 17 18 19 20
CH2
CH7
CH6
CH
11
CH
12
CH4
CH
13
CH
14
CH9
CH8
CH
15
CH
16
CH5
CH
17
CH
18
CH10
CH
19
CH
20
CH11
CH
21
CH
22
CH
23
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
tFBOS
FP8o
C8o
BSTo/LSTo0-31
(2Mbps)
BSTo/LSTo0-31
(4Mbps)
BSTo/LSTo0-31
(8Mbps)
BSTo/LSTo0-31
(16Mbps)
BSTo/LSTo0-15
(32Mbps)
CH0
CH1
CH0
CH0
CH
0
CH
0 1
CH1
CH
1
2
CH1
3
CH2
CH
2
CH
3
CH
4
4
6
8
5
7
CH
5
CH
6
CH3
CH2
CH3
CH4
CH
7
CH
8
CH5
CH
9
CH
10
9 10 11 12 13 14 15 16 17 18 19 20
CH2
CH7
CH6
CH
11
CH
12
CH
13
CH5
CH4
CH
14
CH8
CH
15
CH
16
CH9
CH CH
17 18
CH
19
CH10
CH
20
CH11
CH CH
21 22
CH
23
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Figure 8 - Input and Output Frame Pulse Alignment for Different Data Rates
The tFBOS is the offset between the input frame pulse, FP8i, and the generated output frame pulse, FP8o. Refer to
the “AC Electrical Characteristics,” on page 83. Note that although the figure above shows the traditional setups of
the frame pulses and clocks for both ST-BUS and GCI-Bus configurations, the devices can be configured to
accept/generate double-width frame pulses (if the FPW bit in the Control Register is set) as well as to use the
opposite clock edge for frame-boundary determination (using the C8IPOL and COPOL bits in the Control Register).
See the timing diagrams in “AC Electrical Characteristics,” on page 83 for all of the available configurations.
2.4
Jitter Tolerance Improvement Circuit - Frame Boundary Discriminator
To improve the jitter tolerance of the ZL50060/1, a Frame Boundary Discriminator (FBD) circuit was added to the
device. This circuit is enabled by setting the Control Register bit FBDEN to HIGH. By default the FBD is disabled.
The FBD can operate in two modes, as controlled by the FBD_MODE[2:0] bits of the Control Register. When bits
FBD_MODE[2:0] are set to 000B, the FBD is set to handle lower frequency jitter only (<8kHz). When bits
FBD_MODE[2:0] are set to 111B, the FBD can handle both low frequency and high frequency jitter. All other values
are reserved. These bits are ignored when bit FBDEN is LOW. It is strongly recommended that if bit FBDEN is set
HIGH, bits FBD_MODE[2:0] should be set to 111B to improve the high frequency jitter handling capability.
To achieve the best jitter tolerance performance, it is also recommended that the input data sampling point be
optimized. In most applications, the optimum sampling point is 1/2 instead of the default 3/4 (it can be changed by
programming all the LIDR and BIDR registers). This will give more allowance for sampling point variations caused
28
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
by jitter. There are, however, some cases where data experience more delay than the timing signals. A common
example is when multiple data lines are tied together to form bidirectional buses. The large bus loading may cause
data to be delayed. If this is the case, the optimum sampling point may be 3/4 or 4/4 instead of 1/2. The optimum
sampling point is dependent on the application. The user should optimize the sampling point to achieve the best
jitter tolerance performance.
2.5
Input Clock Jitter Tolerance
Input clock jitter tolerance depends on the data rate. In general, the higher the data rate, the smaller the jitter
tolerance is, because the period of a bit cell is shorter, and the sampling point variation allowance is smaller.
Jitter tolerance can not be accurately represented by just one number. Jitter of the same amplitude but different
frequency spectrum can have different effect on the operation of a device. For example, a device that can tolerate
20 ns of jitter of 10 kHz frequency may only be able to tolerate 10 ns of jitter of 1 MHz frequency. Therefore, jitter
tolerance should be represented as a spectrum over frequency. The highest possible jitter frequency is half of the
carrier frequency. In the case of the ZL50060/1, the input clock is 8.192 MHz, and the jitter associated with this
clock can have the highest frequency component at 4.096 MHz.
For the above reasons, jitter tolerance of the ZL50060/1 has been characterized at two data rates, 16.384 Mbps
and 32.768 Mbps. The lower data rates (2.048 Mbps, 4.096 Mbps, 8.192 Mbps) will have the same or better
tolerance than that of the 16.384 Mbps operation. Tolerance of jitter of different frequencies are shown in the “AC
Electrical Characteristics“ section, table “Input Clock Jitter Tolerance“ on page 93. The Jitter Tolerance
Improvement Circuit was enabled (Control Register, bit FBDEN set HIGH, and bits FBD_MODE[2:0] set to 111B),
and the sampling point was optimized.
2.6
Backward Compatibility with MT90869
The ZL50061 is pin-to-pin compatible with Zarlink’s MT90869 device. To ensure software compatibility between the
two devices, the user must consider the following items:
1. The ZL50061 has enhanced input clock jitter tolerance. To maximize the jitter tolerance, the Frame Boundary
Discriminator (FBD) circuit has to be enabled by setting bits FBDEN and FBD_MODE[2:0] in the Control Register HIGH. In MT90869, these bits are un-used. The input data sampling point also needs to be optimized by programming all the LIDR and BIDR registers. These are described in details in Section 2.4.
2. When Bit Error Rate (BER) transmission is enabled, all the channels on all same side (Local/Backplane) as the
target BER transmission channel(s) will be unable to switch traffic. Also, the BER Counters (LBCR and BBCR)
will not rollover. They will saturate when they reach their maximum value. These are described in more details in
Section 6.0.
3. The hardware reset signal (RESET) must be de-asserted less than 12 µs after the frame boundary or more than
13 µs after the frame boundary, as described in Section 8.3. This can be achieved, for example, by synchronizing the de-assertion of the reset signal with the input frame pulse.
3.0
Input and Output Offset Programming
Various registers are used to control the input sampling point (delay) and the output advancement for the Local and
Backplane streams. The following sections explain the details of these offset programming features.
3.1
Input Offsets
Control of the Input Channel Delay and the Input Bit Delay allows each input stream to have a different frame
boundary with respect to the master frame pulse, FP8i.
The use of Input Channel Delay in combination with Input Bit Delay enables the Ch0 position to be placed
anywhere within a frame to a resolution of 1/4 of the bit period.
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Zarlink Semiconductor Inc.
ZL50060/1
3.1.1
Data Sheet
Input Channel Delay Programming (Backplane and Local Input Streams)
By programming the Backplane or Local Input Channel Delay Registers (BCDR0 - BCDR31 and LCDR0 LCDR31), users can individually assign the Ch0 position of each input stream to be located at any Of the channel
boundaries in a frame. For delays within channel boundaries, the input bit delay programming can be used.
By default, all input streams have a channel delay of zero such that Ch0 is the first channel that appears after the
frame boundary.
FP8i
C8i
BSTi/LSTi0-31
Channel Delay = 2
Ch125
Ch 0
Channel Delay, 2
Ch127
Ch126
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Ch126
Ch127
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Channel Delay,1
Ch127
BSTi/LSTi0-31
Channel Delay = 1
Ch126
Ch 1
Ch 0
BSTi/LSTi0-31
Channel Delay = 0
(Default)
Ch0
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Ch125
7 6 5 4 3 2 1 0 7 6
Figure 9 - Backplane and Local Input Channel Delay Timing Diagram (assuming 8 Mbps
operation)
3.1.2
Input Bit Delay Programming (Backplane and Local Input Streams)
In addition to the Input Channel Delay programming, Input Bit Delay Registers LIDR0-31 and BIDR0-31 work in
conjunction with the SMPL_MODE bit in the Control Register to allow users to control input bit fractional delay as
well as input bit sample point selection for greater flexibility when designing switch matrices for high speed
operation.
When SMPL_MODE = LOW (input bit fractional delay mode), bits LID[4:0] and BID[4:0] in the LIDR0-31 and
BIDR0-31 registers respectively define the input bit fractional delay of the corresponding local and backplane
stream. The total delay can be up to 7 3/4 bits with a resolution of 1/4 bit at the selected data rate. When
SMPL_MODE = HIGH (sampling point select mode), bits LID[1:0] and BID[1:0] define the input bit sampling point of
the stream. The sampling point can be programmed at the 3/4, 4/4, 1/4 or 2/4 bit location to allow better tolerance
for input jitter. Bits LID[4:2] and BID[4:2] define the integer input bit delay, with a maximum value of 7 bits at a
resolution of 1 bit.
Refer to Figure 10 and Figure 11 for Input Bit Delay Timing at 16 Mbps and 8 Mbps data rates, respectively.
Refer to Figure 11 for Input Sampling Point Selection Timing at 8 Mbps data rates.
30
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
SMPL_MODE = LOW
FP8i
C8i
Ch255
BSTi/LSTi0-31
Bit Delay = 0
(Default)
3
2
Ch1
Ch0
1
0
7
6
5
4
3
2
1
7
0
6
5
4
Bit Delay, 1/4
BSTi/LSTi0-31
Bit Delay = 1/4
Ch0
Ch255
3
2
1
7
0
6
5
Ch1
4
3
2
1
0
7
6
5
4
Bit Delay, 1/2
BSTi/LSTi0-31
Bit Delay = 1/2
Ch255
3
Ch0
2
1
0
7
6
5
Ch1
4
3
2
1
7
0
6
5
4
Bit Delay, 3/4
BSTi/LSTi0-31
Bit Delay = 3/4
Ch255
3
Ch0
2
1
7
0
6
5
Ch1
4
3
2
1
7
0
6
5
4
Bit Delay, 1
Ch0
Ch255
BSTi/LSTi0-31
Bit Delay = 1
BSTi/LSTi0-31
Bit Delay = 7 1/2
BSTi/LSTi0-31
Bit Delay = 7 3/4
3
2
1
7
0
6
Ch254
2
Ch1
4
3
2
1
7
0
6
5
4
Ch254
0
7
6
5
3
4
6
5
Bit Delay, 7 1/2
Ch0
2
1
0
7
6
5
4
Bit Delay, 7 3/4
Ch0
Ch255
1
7
0
Ch255
1
2
5
3
2
1
0
7
6
5
4
Please refer to Control Register (Section 14.1) for SMPL_MODE definition.
Figure 10 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mbps
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Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
SMPL_MODE = LOW
FP8i
C8i
Ch127
BSTi/LSTi0-31
BID[4:0]/LID[4:0] = 00000B
Bit delay = 0 bit (Default)
Ch0
0
1
6
7
5
3
4
2
sample at 3/4 point
Ch127
BSTi/LSTi0-31
BID[4:0]/LID[4:0] = 00011B
Bit Delay = 3/4 bit
Ch0
0
1
6
7
5
3
4
2
sample at 3/4 point
SMPL_MODE = HIGH
FP8i
C8i
Ch127
BSTi/LSTi0-31
BID[4:0]/LID[4:0] = 00000B
3/4 sampling (Default)
Ch0
0
1
6
7
5
4
3
2
5
4
3
2
sample at 3/4 point
Ch127
BSTi/LSTi0-31
BID[4:0]/LID[4:0] = 00011B
2/4 sampling
1
Ch0
0
6
7
sample at 2/4 point
Please refer to Control Register (Section 14.1) for SMPL_MODE definition.
Figure 11 - Backplane and Local Input Bit Delay or Sampling Point Selection Timing Diagram for
Data Rate of 8 Mbps
3.2
Output Advancement Programming (Backplane and Local Output Streams)
This feature is used to advance the output channel alignment of individual Local or Backplane output streams with
respect to the frame boundary FP8o. Each output stream has its own advancement value that can be programmed
by the Output Advancement Registers. The output advancement selection is useful in compensating for various
parasitic loading on the serial data output pins.
The Local and Backplane Output Advancement Registers, LOAR0 - LOAR31 and BOAR0 - BOAR31, are used to
control the Local and Backplane output advancement respectively. The advancement is determined with reference
to the internal system clock rate (131.072 MHz). For 2 Mbps, 4 Mbps, 8 Mbps or 16 Mbps streams, the
advancement can be 0, -2 cycles, -4 cycles or -6 cycles, which converts to approximately 0 ns, -15 ns, -31 ns or
-46 ns as shown in Figure 12. For 32 Mbps streams, the advancement can be 0, -1 cycle, -2 cycles or -3 cycles,
which converts to approximately 0ns, -7.6 ns, -15 ns or -23 ns.
32
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
FP8o
System Clock
131.072 MHz
Bit Advancement, 0
Ch255
BSTo/LSTo0-31
Bit Advancement = 0
(Default)
Bit 1
Bit 0
Bit 7
Bit 1
Bit 0
Bit 6
Bit 5
Ch0
Bit 0
Bit 1
Bit 1
Ch0
Bit 7
Bit 7
Bit 6
Bit Advancement, -6
Ch255
BSTo/LSTo0-31
Bit Advancement = -6
Bit 5
Bit Advancement, -4
Ch255
BSTo/LSTo0-31
Bit Advancement = -4
Bit 6
Bit Advancement, -2
Ch255
BSTo/LSTo0-31
Bit Advancement = -2
Ch0
Bit 0
Bit 7
Bit 4
Bit 5
Ch0
Bit 6
Bit 5
Bit 4
Figure 12 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 16 Mbps
4.0
Port high impedance Control
The input pins, LORS and BORS, select whether the Local (LSTo0-31) and Backplane (BSTo0-31) output streams,
respectively, are set to high impedance at the output of the device itself, or are always driven (active HIGH or active
LOW). In the latter case (i.e., always driven), a high impedance state, if required on a per-channel basis, is invoked
through an external interface circuit controlled by the LCSTo0-3/BCSTo0-3 signals.
Setting LORS/BORS to a LOW state will configure the output streams, LSTo0-31/BSTo0-31, to transmit bi-state
channel data with per-channel high impedance determined by external circuits under the control of the
LCSTo0-3/BCSTo0-3 outputs.
Setting LORS/BORS to a HIGH state will configure the output streams, LSTo0-31/BSTo0-31, of the device to
invoke a high impedance output on a per-channel basis when required as controlled by the LE/BE bit.
The state of the LORS/BORS pin is detected and the device configured accordingly during a RESET operation,
e.g. following power-up. The LORS/BORS pin is an asynchronous input and is expected to be hard-wired for a
particular system application, although it may be driven under logic control if preferred.
The Local/Backplane output enable control in order of highest priority is: RESET, ODE, OSB, LE/BE.
LE/BE
(Local /
OSB
LORS/BORS
Backplane
(Control
(input pin)
Register bit) Connection
Memory bit)
LSTo0-31/
BSTo0-31
LCSTo0-3/
BCSTo0-3
0
HIGH
LOW
X
1
HI-Z
LOW
X
X
0
HIGH
LOW
0
X
X
1
HI-Z
LOW
1
1
0
X
0
HIGH
LOW
1
1
0
X
1
HI-Z
LOW
1
1
1
0
0
HIGH
LOW
RESET
(input pin)
ODE
(input pin)
0
X
X
X
0
X
X
1
0
1
Table 2 - Local and Backplane Output Enable Control Priority
33
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
LE/BE
OSB
(Local /
LORS/BORS
(Control
Backplane
(input pin)
Register bit) Connection
Memory bit)
RESET
(input pin)
ODE
(input pin)
1
1
1
0
1
1
1
1
LSTo0-31/
BSTo0-31
LCSTo0-3/
BCSTo0-3
1
HI-Z
LOW
X
ACTIVE
(HIGH or LOW)
ACTIVE
(HIGH or LOW)
Table 2 - Local and Backplane Output Enable Control Priority (continued)
4.1
LORS/BORS Asserted LOW, Non-32Mbps Mode
The data (channel control bit) transmitted by L/BCSTo0-3 replicates the Local/Backplane Output Enable (LE/BE)
bit of the Local/Backplane Connection Memory, with a LOW state indicating the channel to be set to high
impedance. Refer to “Local Connection Memory Bit Definition,” on page 52 and “Backplane Connection Memory Bit
Definition,” on page 53 for more details.
The L/BCSTo0-3 pins transmit serial data (channel control bits) at 16.384 Mbps, with each bit representing the
per-channel high impedance state for a specific stream. Eight output streams are allocated to each control line as
follows:
•
L/BCSTo0 outputs the channel control bits for streams L/BSTo0, 4, 8, 12, 16, 20, 24, and 28
•
L/BCSTo1 outputs the channel control bits for streams L/BSTo1, 5, 9, 13, 17, 21, 25, and 29
•
L/BCSTo2 outputs the channel control bits for streams L/BSTo2, 6, 10, 14, 18, 22, 26 and 30
•
L/BCSTo3 outputs the channel control bits for streams L/BSTo3, 7, 11, 15, 19, 23, 27 and 31
The channel control bit location, within a frame period, for each channel of the Local/Backplane output streams is
presented in Table 3, L/BCSTo Allocation of Channel Control Bits to Output Streams (Non-32 Mbps Mode).
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 3:
1. The channel control bit corresponding to Stream 0, Channel 0, L/BSTo0_Ch0, is transmitted on L/BCSTo0 and
is advanced, relative to the frame boundary, by 10 periods of C16o.
2. The channel control bit corresponding to Stream 28, Channel 0, L/BSTo28_Ch0, is transmitted on L/BCSTo0 in
advance of the frame boundary by three periods of output clock, C16o. Similarly, the channel control bits for
L/BSTo29_Ch0, L/BSTo30_Ch0 and L/BSTo31_Ch0 are advanced relative to the frame boundary by three
periods of C16o, on L/BCSTo1, L/BCSTo2 and L/BCSTo3, respectively.
The L/BCSTo0-3 pins output data at a constant data rate of 16.384Mbps, independent of the data rate selected for
the individual output streams, L/BSTo0-31. Streams at data rates lower than 16.384 Mbps will have the value of
their respective channel control bit repeated for the duration of the channel. The bit will be repeated twice for
8.192 Mbps streams, four times for 4.096 Mbps streams and eight times for 2.048 Mbps streams. The channel
control bit is not repeated for 16.384 Mbps streams.
Examples are presented, with reference to Table 3:
3. With stream L/BSTo4 selected to operate at a data rate of 2.048Mbps, the value of the channel control bit for
Channel 0 will be transmitted during the C16o clock period numbers 2040, 2048, 8, 16, 24, 32, 40 and 48.
4. With stream L/BSTo8 operated at a data rate of 8.192 Mbps, the value of the channel control bit for Channel 1
will be transmitted during the C16o clock period numbers 9 and 17.
34
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Channel No. 2
Allocated Stream No.
C16o
L/BCSTo0
Period1
L/BCSTo1
L/BCSTo2
L/BCSTo3 16 Mbps 8 Mbps 4 Mbps 2 Mbps
2039
0 3-1
1
2
3
Ch 0
Ch 0
Ch 0
Ch 0
2040
3-3
5
6
7
Ch 0
Ch 0
Ch 0
Ch 0
2041
8
9
10
11
Ch 0
Ch 0
Ch 0
Ch 0
2042
12
13
14
15
Ch 0
Ch 0
Ch 0
Ch 0
2043
16
17
18
19
Ch 0
Ch 0
Ch 0
Ch 0
2044
20
21
22
23
Ch 0
Ch 0
Ch 0
Ch 0
2045
24
25
26
27
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
2046
4
28
3-2
29
3-2
30
3-2
31
3-2
2047
0
1
2
3
Ch 1
Ch 0
Ch 0
Ch 0
2048
3-3
5
6
7
Ch 1
Ch 0
Ch 0
Ch 0
Frame
1
8
9
10
11
Ch 1
Ch 0
Ch 0
Ch 0
Boundary
2
12
13
14
15
Ch 1
Ch 0
Ch 0
Ch 0
3
16
17
18
19
Ch 1
Ch 0
Ch 0
Ch 0
4
20
21
22
23
Ch 1
Ch 0
Ch 0
Ch 0
5
24
25
26
27
Ch 1
Ch 0
Ch 0
Ch 0
6
28
29
30
31
Ch 1
Ch 0
Ch 0
Ch 0
7
0
1
2
3
Ch 2
Ch 1
Ch 0
Ch 0
8
4
3-3
5
6
7
Ch 2
Ch 1
Ch 0
Ch 0
8
3-4
9
10
11
Ch 2
Ch 1
Ch 0
Ch 0
9
4
10
12
13
14
15
Ch 2
Ch 1
Ch 0
Ch 0
11
16
17
18
19
Ch 2
Ch 1
Ch 0
Ch 0
12
20
21
22
23
Ch 2
Ch 1
Ch 0
Ch 0
13
24
25
26
27
Ch 2
Ch 1
Ch 0
Ch 0
14
28
29
30
31
Ch 2
Ch 1
Ch 0
Ch 0
15
0
1
2
3
Ch 3
Ch 1
Ch 0
Ch 0
16
4
3-3
5
6
7
Ch 3
Ch 1
Ch 0
Ch 0
3-4
17
8
9
10
11
Ch 3
Ch 1
Ch 0
Ch 0
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
2029
etc.
etc.
etc.
etc.
Ch 254
Ch 127
Ch 63
Ch 31
2030
28
29
30
31
Ch 254
Ch 127
Ch 63
Ch 31
2031
0
1
2
3
Ch 255
Ch 127
Ch 63
Ch 31
2032
4
5
6
7
Ch 255
Ch 127
Ch 63
Ch 31
2033
8
9
10
11
Ch 255
Ch 127
Ch 63
Ch 31
2034
12
13
14
15
Ch 255
Ch 127
Ch 63
Ch 31
Table 3 - L/BCSTo Allocation of Channel Control Bits to Output Streams (Non-32 Mbps Mode)
35
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Channel No. 2
Allocated Stream No.
C16o
Period1 L/BCSTo0
L/BCSTo1
L/BCSTo2
L/BCSTo3 16 Mbps 8 Mbps 4 Mbps 2 Mbps
2035
16
17
18
19
Ch 255
Ch 127
Ch 63
Ch 31
2036
20
21
22
23
Ch 255
Ch 127
Ch 63
Ch 31
2037
24
25
26
27
Ch 255
Ch 127
Ch 63
Ch 31
2038
28
29
30
31
Ch 255
Ch 127
Ch 63
Ch 31
1
2
3
Ch 0
Ch 0
Ch 0
Ch 0
0
3-1
4
3-3
5
6
7
Ch 0
Ch 0
Ch 0
Ch 0
2041
8
9
10
11
Ch 0
Ch 0
Ch 0
Ch 0
2042
12
13
14
15
Ch 0
Ch 0
Ch 0
Ch 0
2043
16
17
18
19
Ch 0
Ch 0
Ch 0
Ch 0
2044
20
21
22
23
Ch 0
Ch 0
Ch 0
Ch 0
2045
24
25
26
27
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
2039
2040
2046
28
3-2
29
3-2
30
3-2
31
3-2
2047
0
1
2
3
Ch 1
Ch 0
Ch 0
Ch 0
2048
3-3
5
6
7
Ch 1
Ch 0
Ch 0
Ch 0
Frame
Boundary
4
1
8
9
10
11
Ch 1
Ch 0
Ch 0
Ch 0
2
12
13
14
15
Ch 1
Ch 0
Ch 0
Ch 0
3
16
17
18
19
Ch 1
Ch 0
Ch 0
Ch 0
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
Table 3 - L/BCSTo Allocation of Channel Control Bits to Output Streams (Non-32 Mbps Mode)
(continued)
Note 1:
Clock period count is referenced to frame boundary.
Note 2:
The channel numbers presented relate to the data rate selected for a specific stream.
Note 3:
3-1 to 3-4: See above for examples of channel control bits for streams of different data rates.
36
Zarlink Semiconductor Inc.
37
Zarlink Semiconductor Inc.
CH 1
L/BSTo10
CH 1
L/BSTo14
CH 1
L/BSTo15
Chan 63 Bit 0
Channel 31 Bit 0
CH 1
L/BSTo12
Chan 127 Chan 127 Chan 127 Chan 127
Bit 3
Bit 2
Bit 1
Bit 0
7
CH 1
L/BSTo13
0
CH 1
L/BSTo8
CH 1
L/BSTo4
1
CH 1
L/BSTo9
CH 1
L/BSTo5
2
CH 1
L/BSTo0
3
CH 0
L/BSTo1
CH 0
L/BSTo28
Chan 63 Bit 1
CH 0
L/BSTo29
4
CH 0
L/BSTo24
CH 0
L/BSTo20
5
CH 0
L/BSTo25
CH 0
L/BSTo21
Channel 0 Bit 7
CH 0
L/BSTo16
6
CH 0
L/BSTo17
Chan 0 Bit 6
CH 0
L/BSTo12
Chan 0
Bit 4
CH 0
L/BSTo13
CH 0
L/BSTo8
7
CH 1
L/BSTo11
CH 0
L/BSTo14
CH 0
L/BSTo15
CH 0
L/BSTo9
CH 2
L/BST04
0
CH 0
L/BSTo6
CH 0
L/BSTo10
CH 0
L/BSTo11
CH 2
L/BSTo5
1
CH 0
L/BSTo7
CH 0
L/BSTo6
CH 0
L/BSTo7
CH 2
L/BSTo0
Chan 0
Bit 5
CH 1
L/BSTo1
2
CH 1
L/BSTo2
CH 2
L/BSTo2
CH 2
L/BSTo3
CH 1
L/BSTo28
Chan 0 Bit 7
CH 1
L/BSTo29
3
CH 1
L/BSTo3
CH 1
L/BSTo30
CH 1
L/BSTo31
CH 1
L/BSTo24
Chan 0
Bit 6
CH 1
L/BSTo25
CH 1
L/BSTo20
4
CH 0
L/BSTo30
CH 1
L/BSTo26
CH 1
L/BSTo27
CH 1
L/BSTo21
5
CH 0
L/BSTo31
CH 1
L/BSTo22
CH 1
L/BSTo23
Chan 31
Bit 0
CH 1
L/BSTo16
Chan 0
Bit 7
CH 1
L/BSTo17
6
CH 0
L/BSTo26
CH 1
L/BSTo18
CH 1
L/BSTo19
CH 1
L/BSTo12
CH 1
L/BSTo8
Chan 63
Bit 0
CH 1
L/BSTo13
CH 1
L/BSTo9
CH 1
L/BSTo4
Chan 127
Bit 0
7
CH 0
L/BSTo27
CH 1
L/BSTo14
CH 1
L/BSTo15
L/BCSTo1
0
CH 0
L/BSTo22
CH 1
L/BSTo10
CH 1
L/BSTo11
L/BCSTo0
CH 1
L/BSTo5
L/BSTo7
(2Mbps)
1
CH 0
L/BSTo23
CH 0
L/BSTo6
L/BCSTo3
CH 0
L/BSTo7
L/BSTo6
(4Mbps)
CH 1
L/BSTo0
L/BSTo1
(8Mbps)
CH 0
L/BSTo1
Channel 0
CH 0
L/BSTo18
CH 1
L/BSTo2
L/BSTo0
(16Mbps)
CH 0
L/BSTo19
L/BCSTo2
CH 1
L/BSTo3
ZL50060/1
Data Sheet
Figure 13, Local/Backplane Port External High Impedance Control Timing (Non-32 Mbps Mode) shows the channel
control bits for L/BCSTo0, L/BCSTo1, L/BCSTo2 and L/BCSTo3 in one possible scenario which includes stream
L/BSTo0 at a data rate of 16.384 Mbps, L/BSTo1 at 8.192 Mbps, L/BSTo6 at 4.096 Mbps and L/BSTo7 at
2.048 Mbps. All remaining streams are operated at a data rate of 16.384 Mbps.
FP8o
C8o
Channel 255
6
Chan 0
Bit 7
Chan 0
Bit 7
Chan 0
Bit 7
One C16o period
Figure 13 - Local/Backplane Port External High Impedance Control Timing (Non-32 Mbps Mode)
ZL50060/1
4.2
Data Sheet
LORS/BORS Asserted LOW, 32Mbps Mode
Note that when the devices are operating in Local or Backplane 32 Mbps mode, some of the output streams (the
upper half of the available streams) are unused. The LE/BE bits of the channels on those output streams will
always be low. Therefore, the upper LSTo/BSTo pins are either driven HIGH or high impedance, in accordance with
the value of the LORS/BORS input signals, as shown in Table 2 on page 33.
The data (channel control bit) transmitted by L/BCSTo0-3 replicates the Local/Backplane Output Enable (LE/BE)
bit of the Local/Backplane Connection Memory, with a LOW state indicating the channel to be set to high
impedance. Refer to “Local Connection Memory Bit Definition,” on page 52 and “Backplane Connection Memory Bit
Definition,” on page 53 for more details.
The L/BCSTo0-3 pins transmit serial data (channel control bits) at 16.384 Mbps, with each bit representing the
per-channel high impedance state for a specific stream. Four output streams are allocated to each control line as
follows:
•
L/BCSTo0 outputs the channel control bits for streams L/BSTo0, 4, 8, and 12
•
L/BCSTo1 outputs the channel control bits for streams L/BSTo1, 5, 9, and 13
•
L/BCSTo2 outputs the channel control bits for streams L/BSTo2, 6, 10, and 14
•
L/BCSTo3 outputs the channel control bits for streams L/BSTo3, 7, 11, and 15
The channel control bit location, within a frame period, for each channel of the Local/Backplane output streams is
presented in Table 4, L/BCSTo Allocation of Channel Control Bits to Output Streams (32 Mbps Mode)
The L/BCSTo0-3 pins output data at a constant data rate of 16.384 Mbps and all output streams, L/BSTo0-15,
operate at a data rate of 32.768 Mbps.
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 4:
1. The channel control bit corresponding to Stream 0, Channel 0, L/BSTo0_Ch0, is transmitted on L/BCSTo0 and
is advanced, relative to the frame boundary, by ten periods (clock period number 2039) of C16o.
2. The channel control bit corresponding to Stream 12, Channel 0, L/BSTo12_Ch0, is transmitted on L/BCSTo0 in
advance of the frame boundary by seven periods (clock period number2042) of output clock, C16o. Similarly,
the channel control bits for L/BSTo13_Ch0, L/BSTo14_Ch0 and L/BSTo15_Ch0 are advanced relative to the
frame boundary by seven periods of C16o, on L/BCSTo1, L/BCSTo2 and L/BCSTo3, respectively.
3. For stream L/BSTo4, the value of the channel control bit for Channel 511 will be transmitted during the C16o
clock period number 2036 on L/BCSTo0.
4. For stream L/BSTo5, the value of the channel control bit for Channel 5 will be transmitted during the C16o clock
period number 12 on L/BCSTo1.
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Data Sheet
Channel No. 2
Allocated Stream No.
C16o
Period1
L/BCSTo0
L/BCSTo1
L/BCSTo2
L/BCSTo3
32 Mbps
2039
0 3-1
1
2
3
Ch 0
2040
4
5
6
7
Ch 0
2041
8
9
10
11
Ch 0
2042
12
3-2
13
3-2
14
3-2
2
15
3-2
3
Ch 0
2043
0
1
Ch 1
2044
4
5
6
7
Ch 1
2045
8
9
10
11
Ch 1
2046
12
13
14
15
Ch 1
2047
0
1
2
3
Ch 2
2048
4
5
6
7
Ch 2
Frame
1
8
9
10
11
Ch 2
Boundary
2
12
13
14
15
Ch 2
3
0
1
2
3
Ch 3
4
4
5
6
7
Ch 3
5
8
9
10
11
Ch 3
6
12
13
14
15
Ch 3
7
0
1
2
3
Ch 4
8
4
5
6
7
Ch 4
9
8
9
10
11
Ch 4
10
12
13
14
15
Ch 4
11
0
1
2
3
Ch 5
12
4
3-4
6
7
Ch 5
13
8
9
10
11
Ch 5
14
12
13
14
15
Ch 5
15
0
1
2
3
Ch 6
16
4
5
6
7
Ch 6
17
8
9
10
11
Ch 6
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
etc.
2029
etc.
etc.
etc.
etc.
Ch 509
2030
12
13
14
15
Ch 509
2031
0
1
2
3
Ch 510
2032
4
5
6
7
Ch 510
2033
8
9
10
11
Ch 510
2034
12
13
14
15
Ch 510
5
Table 4 - L/BCSTo Allocation of Channel Control Bits to Output Streams (32 Mbps Mode)
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Data Sheet
Channel No. 2
Allocated Stream No.
C16o
Period1
L/BCSTo0
L/BCSTo1
L/BCSTo2
L/BCSTo3
32 Mbps
2035
0
1
2
3
Ch 511
2036
3-3
5
6
7
Ch 511
2037
8
9
10
11
Ch 511
2038
12
13
14
15
Ch 511
2039
0
1
2
3
Ch 0
2040
4
5
6
7
Ch 0
2041
8
9
10
11
Ch 0
2042
12
13
14
15
Ch 0
2043
0
1
2
3
Ch 1
2044
4
5
6
7
Ch 1
2045
8
9
10
11
Ch 1
2046
12
13
14
15
Ch 1
2047
0
1
2
3
Ch 2
2048
4
5
6
7
Ch 2
Frame
Boundary
4
1
8
9
10
11
Ch 2
2
12
13
14
15
Ch 2
3
0
1
2
3
Ch 3
etc.
etc.
etc.
etc.
etc.
etc.
Table 4 - L/BCSTo Allocation of Channel Control Bits to Output Streams (32 Mbps Mode)
(continued)
Note 1:
Clock period count is referenced to frame boundary.
Note 2:
The channel numbers presented relate to the specific stream operating at a data rate of 32.768 Mbps.
Note 3:
3-1 to 3-4: See above for examples of channel control bits.
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Data Sheet
Figure 14, Local and Backplane Port External High Impedance Control Timing (32Mbps Mode) shows the channel
control bits for L/BCSTo0, L/BCSTo1, L/BCSTo2 and L/BCSTo3.
FP8o
CH 2
L/BSTo12
CH 2
L/BSTo10
CH 2
L/BSTo14
CH 2
L/BSTo11
CH 2
L/BSTo15
CH 2
L/BSTo5
CH 2
L/BSTo6
CH 2
L/BSTo7
CH 2
L/BSTo1
CH 2
L/BSTo2
CH 2
L/BSTo3
CH 1
L/BSTo13
CH 1
L/BSTo14
CH 1
L/BSTo15
CH 1
L/BSTo9
CH 1
L/BSTo10
CH 1
L/BSTo11
CH 1
L/BSTo5
CH 1
L/BSTo6
CH 1
L/BSTo7
CH 1
L/BSTo1
CH 1
L/BSTo2
CH 1
L/BSTo3
CH 0
L/BSTo13
CH 0
L/BSTo14
CH 0
L/BSTo15
CH 0
L/BSTo9
CH 0
L/BSTo10
CH 0
L/BSTo11
CH 4
L/BSTo5
CH 4
L/BSTo6
CH 4
L/BSTo7
CH 4
L/BSTo1
CH 4
L/BSTo2
CH 4
L/BSTo3
CH 3
L/BSTo13
CH 3
L/BSTo14
CH 3
L/BSTo15
CH 3
L/BSTo9
CH 3
L/BSTo10
CH 3
L/BSTo11
CH 3
L/BSTo5
CH 3
L/BSTo6
CH 3
L/BSTo7
CH 3
L/BSTo1
CH 3
L/BSTo2
CH 3
L/BSTo3
CH 2
L/BSTo13
CH 2
L/BSTo14
CH 2
L/BSTo15
CH 2
L/BSTo9
CH 2
L/BSTo10
CH 2
L/BSTo11
CH 2
L/BSTo5
CH 2
L/BSTo6
CH 2
L/BSTo1
CH 2
L/BSTo7
L/BCSTo2
CH 2
L/BSTo2
L/BCSTo1
CH 2
L/BSTo3
L/BCSTo0
CH 2
L/BSTo13
Channel 511
bits 7-0
CH 2
L/BSTo4
Channel 510
bits 7-0
CH 2
L/BSTo0
Channel 1
bits 7-0
CH 1
L/BSTo12
Channel 0
bits 7-0
CH 1
L/BSTo8
L/BSTo3
(32Mbps)
CH 1
L/BSTo4
Channel 511
bits 7-0
CH 1
L/BSTo0
Channel 510
bits 7-0
CH 0
L/BSTo12
Channel 1
bits 7-0
CH 0
L/BSTo8
Channel 0
bits 7-0
CH 4
L/BSTo4
L/BSTo2
(32Mbs)
CH 4
L/BSTo0
Channel 511
bits 7-0
CH 3
L/BSTo12
Channel 510
bits 7-0
CH 3
L/BSTo8
Channel 1
bits 7-0
CH 3
L/BSTo4
Channel 0
bits 7-0
CH 3
L/BSTo0
L/BSTo1
(32Mbps)
CH 2
L/BSTo12
Channel 511
bits 7-0
CH 2
L/BSTo8
Channel 510
bits 7-0
CH 2
L/BSTo4
Channel 1
bits 7-0
CH 2
L/BSTo0
Channel 0
bits 7-0
CH 2
L/BSTo9
L/BSTo0
(32Mbps)
CH 2
L/BSTo8
C8o
L/BCSTo3
One C16o cycle
Figure 14 - Local and Backplane Port External High Impedance Control Timing (32Mbps Mode)
4.3
LORS/BORS Asserted HIGH
When the LORS/BORS input pin is HIGH, the Local/Backplane Output Enable Bit (LE/BE) of the Local/Backplane
Connection Memory has direct per-channel control on the high impedance state of the Local/Backplane output
streams, L/BSTo0-31. Programming a LOW state in the connection memory LE/BE bit will set the stream output of
the device to high impedance for the duration of the channel period. See “Local Connection Memory Bit Definition,”
on page 52 and “Backplane Connection Memory Bit Definition,” on page 53 for programming details.
When the LORS/BORS signal is asserted HIGH, the L/BCSTo0-3 outputs directly the values given in LE/BE.
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5.0
Data Sheet
Data Delay Through the Switching Paths
Serial data which goes into the device is converted into parallel format and written to consecutive locations in the
data memory. Each data memory location corresponds to the input stream and channel number. With the input
channel delay feature disabled, channels written to any of the buffers during Frame N will be read out during Frame
N+2. With the input channel delay feature enabled, channels written to any of the buffers during Frame N will be
read out during Frame N+3.
The input channel offsets affect the overall throughput delay; however the input bit delay and output bit
advancement have no impact on the overall data throughput delay.
In the following paragraphs, the data throughput delay (T) is represented as a function of ST-BUS frames, input
channel number, (m), output channel number (n), and input channel delay (α). Table 5 describes the variable range
for input streams and Table 6 describes the variable range for output streams. Table 7 summarizes the data
throughput delay under various input channel and output channel delay conditions.
Input Stream
Data Rate
Input Channel
Number (m)
Possible Input channel delay (α)
2 Mbps
0 to 31
0 to 31
4 Mbps
0 to 63
0 to 63
8 Mbps
0 to 127
0 to 127
16 Mbps
0 to 255
0 to 255
32 Mbps
0 to 511
0 to 511
Table 5 - Variable Range for Input Streams
Output Stream
Data Rate
Output Channel
Number (n)
2 Mbps
0 to 31
4 Mbps
0 to 63
8 Mbps
0 to 127
16 Mbps
0 to 255
32 Mbps
0 to 511
Table 6 - Variable Range for Output Streams
Input Channel Delay OFF
Input Channel Delay ON
T = 2 frames + (n - m)
T = 3 frames - α + (n - m)
Table 7 - Data Throughput Delay
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Data Sheet
By default, when the input channel delay, α, is set to zero, the data throughput delay (T) is: T = 2 frames + (n - m).
Assuming that m (input channel) and n (output channel) are equal, we have the figure below, in which the delay
between the input data being written and the output data being read is exactly 2 frames.
Frame
Serial Input Data
(No Delay)
Frame N
Frame N Data
Frame N+1
Frame N+2
Frame N+1Data
Frame N+3
Frame N+4
Frame N+5
Frame N+2 Data
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
2 Frames + 0
Serial Output Data
(No Delay)
Frame N-2 Data
Frame N-1 Data
Figure 15 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch0 Switched to
Output Ch0
Assuming that n (output channel) is greater than m (input channel), we have the figure below, in which the delay
time between the input channel being written and the output channel being read exceeds 2 frames.
Frame
Serial Input Data
(No Delay)
Frame N
Frame N Data
Frame N+1
Frame N+2
Frame N+1Data
Frame N+2 Data
Frame N+3
Frame N+4
Frame N+5
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
2 Frames + (n - m)
Serial Output Data
(No Delay)
Frame N-2 Data
Frame N-1 Data
Frame N Data
Figure 16 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch0 Switched to
Output Ch13
Assuming that n (output channel) is less than m (input channel), we have the figure below, in which the delay time
between the input channel being written and the output channel being read is less than 2 frames.
Frame
Serial Input Data
(No Delay)
Frame N
Frame N Data
Frame N+1
Frame N+2
Frame N+1Data
Frame N+2 Data
Frame N+3
Frame N+4
Frame N+5
Frame N+3 Data
Frame N+4 Data
Frame N+5 Data
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
2 Frames + (n - m)
Serial Output Data
(No Delay)
Frame N-2 Data
Frame N-1 Data
Frame N Data
Figure 17 - Data Throughput Delay with Input Channel Delay Disabled, Input Ch13 Switched to
Output Ch0
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Data Sheet
When the input channel delay, α, is enabled, the data throughput delay is: T = 3 frames - α + (m - n). Assuming that
m (input channel) and n (output channel) are equal, we have the figure below, in which the delay between the input
data being written and the output data being read is less than 3 frames.
Frame
Frame N
Frame N+1
Frame N+2
Frame N+3
Frame N+4
Frame N+5
Frame N+3 Data
Frame N+4 Data
Frame N+1 Data
Frame N+2 Data
Input Channel Delay (from 1 to max # of channels)
Serial Input Data
(α > 0)
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
3 Frames - α + 0
Serial Output Data
Frame N-3 Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Figure 18 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch0 Switched to
Output Ch0
Assuming that n (output channel) is greater than m (input channel), we have the figure below, in which the delay
time between the input channel being written and the output channel being read could exceed 3 frames, if the
distance between n and m is greater than the input channel delay.
Frame
Frame N
Frame N+1
Frame N+2
Frame N+3
Frame N+4
Frame N+5
Frame N+3 Data
Frame N+4 Data
Input Channel Delay (from 1 to max # of channels)
Serial Input Data
(α > 0)
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
3 Frames - α + (n - m)
Serial Output Data
Frame N-3 Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Figure 19 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch0 Switched to
Output Ch13
Assuming that n (output channel) is less than m (input channel), we have the figure below, in which the delay time
between the input channel being written and the output channel being read will be less than 3 frames.
Frame
Frame N
Frame N+1
Frame N+2
Frame N+3
Frame N+4
Frame N+5
Frame N+3 Data
Frame N+4 Data
Input Channel Delay (from 1 to max # of channels)
Serial Input Data
(α > 0)
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
3 Frames - α + (n - m)
Serial Output Data
Frame N-3 Data
Frame N-2 Data
Frame N-1 Data
Frame N Data
Frame N+1 Data
Frame N+2 Data
Figure 20 - Data Throughput Delay with Input Channel Delay Enabled, Input Ch13 Switched to
Output Ch0
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6.0
Data Sheet
Bit Error Rate Test
Independent Bit Error Rate (BER) testers are provided for the Local and Backplane ports. In both ports there is a
BER transmitter and a BER receiver. The transmitter and receiver are each independently controlled to allow
Backplane-to-Backplane, Local-to-Local, Backplane-to-Local or Local-to-Backplane testing. The transmitter
generates a 215-1 or 223-1 Pseudo Random Binary Sequence (PRBS), which may be allocated to a specific stream
and number of channels. This is defined by a stream number, a start channel number, and the number of
consecutive channels following the start channel. The stream, channel number and the number of consecutive
channels following the start channel are similarly allocated for the receiver and detection of the PRBS. Examples of
a channel sequence are presented in Figure 21.
frame boundary
FP8i
Start Ch=0
L/BTXB8-0=111111111B
Total Length = 256 Channels
0
1
2
3
......
.....
.....
.....
254
255
0
1
2
Start Ch=0
L/BXTR8-0=000000001B
Total Length = 3 Channels
0
1
2
3
......
.....
.....
.....
254
255
0
1
2
Start Ch=254
L/BXTR8-0=000000011B
Total Length = 4 Channels
0
1
2
3
......
.....
.....
.....
254
255
0
1
2
Channels containing PRBS sequence
Channels containing unknown data
Note: Total Length = Number of Consecutive Channels Desired Programmed in L/BTXR8-0 - 1 Channel
Once started, BER transmission continues until stopped by the BER Control Register.
Figure 21 - Examples of BER Transmission Channels on a 16Mbps Output Stream
When enabled, the receiver attempts to lock to the PRBS on the incoming bit stream. Once lock is achieved, by
detection of a seed value, a bit-by-bit comparison takes place and each error will increment a 16-bit counter. A
counter saturation to FFFFH occurs in the event of an error count in excess of 65,535.
The BER operations are controlled by registers as follows (refer to Section 14.3, Bit Error Rate Test Control
Register (BERCR) for overall control, Section 14.10, Local Bit Error Rate (BER) Registers and Section 14.11,
Backplane Bit Error Rate (BER) Registers for register programming details):
•
BER Control Register (BERCR) - Independently enables BER transmission and receive testing for
Backplane and Local ports.
•
Local and Backplane BER Start Send Registers (LBSSR and BBSSR) - Define the output stream and start
channel for BER transmission.
•
Local and Backplane Transmit BER Length Registers (LTXBLR and BTXBLR) - Define, for transmit stream,
how many consecutive channels to follow the start channel.
•
Local and Backplane BER Start Receive Registers (LBSR and BBSR) - Define the input stream and channel
from which the BER sequence will start to be compared.
•
Local and Backplane Receive BER Length Registers (LRXBLR and BRXBLR) - Define, for the receive
stream, how many consecutive channels to follow the start channel.
•
Local and Backplane BER Count Registers (LBCR and BBCR) - Contain the number of counted errors.
The registers listed completely define the transmit and receive stream and channels. When BER transmission is
enabled for these channels, the source bits and the Message Mode bits, LSRC and LMM in the Local Connection
Memory, and BSRC and BMM in the Backplane Connection Memory, are ignored. The per-channel enable bits (LE
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Zarlink Semiconductor Inc.
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Data Sheet
and BE) of the respective connection memories should be set to HIGH to enable the outputs for the selected
channels.
The BER receive channel numbering is not affected by the input channel delay value. It means that the BER
receive circuitry always assume there is no input channel delay, regardless of the values of the BCDR and LCDR
registers. For example, if BER data is received on local input stream 0 channel 3, without input channel delay, the
LBSRR (Local BER Start Receive Register) should be programmed to 3. With input channel delay of 5, however,
the LBSRR should be programmed to 8 (3 + 5) instead.
Note that when BER transmission is enabled, the target channels will carry PRBS data, and the rest of the channels
on all streams of the same side (Local/Backplane) will carry unknown data, which renders that side of the switch
unable to switch traffic during BER test.
7.0
Microprocessor Port
The 16 K switch family supports non-multiplexed Motorola type microprocessor buses. The microprocessor port
consists of a 16-bit parallel data bus (D0-15), a 15-bit address bus (A0-14) and four control signals (CS, DS, R/W
and DTA). The data bus provides access to the internal registers, the Backplane Connection and Data Memories,
and the Local Connection and Data Memories. Each memory has 8,192 locations. See Table 11, Address Map for
Data and Connection Memory Locations (A14 = 1), for the address mapping.
Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can only
be read (but not written) from the microprocessor port.
To prevent the bus ’hanging’, in the event of the switch not receiving a master clock, the microprocessor port shall
complete the DTA handshake when accessed, but any data read from the bus will be invalid.
8.0
Device Power-up, Initialization and Reset
8.1
Power-Up Sequence
The recommended power-up sequence is for the VDD_IO supply (nominally +3.3 V) to be established before the
power-up of the VDD_PLL and VDD_CORE supplies (nominally +1.8 V). The VDD_PLL and VDD_CORE supplies may be
powered up simultaneously, but neither should 'lead' the VDD_IO supply by more than 0.3 V.
All supplies may be powered-down simultaneously.
8.2
Initialization
Upon power up, the device should be initialized by applying the following sequence:
1
Ensure the TRST pin is permanently LOW to disable the JTAG TAP controller.
2
Set ODE pin to LOW. This configures the LCSTo0-3 output signals to LOW (i.e., setting optional external
output buffers to high impedance), and sets the LSTo0-31 outputs to HIGH or high impedance,
dependent on the LORS input value, and sets the BCSTo0-3 output signals to LOW (i.e., setting optional
external output buffers to high impedance), and sets the BSTo0-31 outputs to HIGH or high impedance,
dependent on BORS input value. Refer to Pin Description for details of the LORS and BORS pins.
3
Reset the device by asserting the RESET pin to zero for at least two cycles of the input clock, C8i. A
delay of an additional 250 µs must also be applied before the first microprocessor access is
performed following the de-assertion of the RESET pin; this delay is required for determination of the
input frame pulse format.
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Data Sheet
4
Use the Block Programming Mode to initialize the Local and the Backplane Connection Memories. Refer
to Section 9.3, Connection Memory Block Programming.
5
Set ODE pin to HIGH after the connection memories are programmed to ensure that bus contention will
not occur at the serial stream outputs.
8.3
Reset
The RESET pin is used to reset the device. When set LOW, an asynchronous reset is applied to the device. It is
then synchronized to the internal clock. During the reset period, depending on the state of input pins LORS and
BORS, the output streams LSTo0-31 and BSTo0-31 are set to HIGH or high impedance, and all internal registers
and counters are reset to the default state.
The RESET pin must remain LOW for two input clock cycles (C8i) to guarantee a synchronized reset release. A
delay of an additional 250 µs must also be waited before the first microprocessor access is performed following
the de-assertion of the RESET pin; this delay is required for determination of the frame pulse format.
In addition, the reset signal must be de-asserted less than 12µs after the frame boundary or more than 13 µs after
the frame boundary, as illustrated in Figure 22. This can be achieved, for example, by synchronizing the
de-assertion of the reset signal with the input frame pulse FP8i.
FP8i
RESET
(case 1)
RESET
(case 2)
12µs
RESET assertion
13µs
RESET de-assertion
De-assertion of RESET must not fall within this window
Figure 22 - Hardware RESET de-assertion
9.0
Connection Memory
The device includes two connection memories, the Local Connection Memory and the Backplane Connection
Memory.
9.1
Local Connection Memory
The Local Connection Memory (LCM) is a 16-bit wide memory with 8,192 memory locations to support the Local
output port. The most significant bit of each word, bit[15], selects the source stream from either the Backplane
(LSRC = LOW) or the Local (LSRC = HIGH) port and determines the Backplane-to-Local or Local-to-Local data
routing. Bits[14:13] select the control modes of the Local output streams, the per-channel Message Mode and the
per-channel high impedance output control modes. In Connection Mode (bit[14] = LOW), bits[12:0] select the
source stream and channel number as detailed in Table 8. In Message Mode (bit[14] = HIGH), bits[12:8] are unused
and bits[7:0] contain the message byte to be transmitted. Bit[13] must be HIGH for Message Mode to ensure that
the output channel is not tri-stated.
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9.2
Data Sheet
Backplane Connection Memory
The Backplane Connection Memory (BCM) is a 16-bit wide memory with 8,192 memory locations to support the
Backplane output port. The most significant bit of each word, bit[15], selects the source stream from either the
Backplane (BSRC = HIGH) or the Local (BSRC = LOW) port and determines the Local-to-Backplane or
Backplane-to-Backplane data routing. Bit[14:13] select the control modes of the Backplane output streams, namely
the per-channel Message Mode and the per-channel high impedance output control mode. In Connection Mode
(bit[14] = LOW), bits[12:0] select the source stream and channel number as detailed in Table 8. In Message Mode
(bit[14] = HIGH), bits[12:8] are unused and bits[7:0] contain the message byte to be transmitted. Bit[13] must be
HIGH for Message Mode to ensure that the output channel is not tri-stated.
The Control Register bits MS[2:0] must be set to 000 to select the Local Connection Memory for the write and read
operations via the microprocessor port. The Control Register bits MS[2:0] must be set to 001 to select the
Backplane Connection Memory for the write and read operations via the microprocessor port. See Section 7.0,
Microprocessor Port, and Section 14.1, Control Register (CR) for details on microprocessor port access.
Source Stream Bit Rate
Source Stream No.
Source Channel No.
2 Mbps
Bits[12:8]
legal values 0:31
Bits[7:0]
legal values 0:31
4 Mbps
Bits[12:8]
legal values 0:31
Bits[7:0]
legal values 0:63
8 Mbps
Bits[12:8]
legal values 0:31
Bits[7:0]
legal values 0:127
16 Mbps
Bits[12:8]
legal values 0:31
Bits[7:0]
legal values 0:255
32 Mbps
Bits[12:9]
legal values 0:15
Bits[8:0]
legal values 0:511
Table 8 - Local and Backplane Connection Memory Configuration
9.3
Connection Memory Block Programming
This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after
power-up. When the Memory Block Programming mode is enabled, the contents of the Block Programming
Register (BPR) will be loaded into the connection memories. See Table 19 and Table 20 for details of the Control
Register and Block Programming Register values, respectively.
9.3.1
Memory Block Programming Procedure:
•
Set the MBP bit in the Control Register from LOW to HIGH.
•
Set the BPE bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,
LBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] of the Local Connection
Memory. The remaining bit positions are loaded with zeros as shown in Table 9.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LBPD2
LBPD1
LBPD0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 9 - Local Connection Memory in Block Programming Mode
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Data Sheet
The Backplane Block Programming data bits, BBPD[2:0], of the Block Programming Register, will be loaded into
bits[15:13] respectively, of the Backplane Connection Memory. The remaining bit positions are loaded with zeros as
shown in Table 10.
15
14
BBPD2
BBPD1
13
BBPD0
12
11
10
0
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Table 10 - Backplane Connection Memory in Block Programming Mode
The Block Programming Register bit, BPE will be automatically reset LOW within 125 µs, to indicate completion of
memory programming.
The Block Programming Mode can be terminated at any time prior to completion by clearing the BPE bit of the
Block Programming Register or the MBP bit of the Control Register.
Note that the default values (LOW) of LBPD[2:0] and BBPD[2:0] of the Block Programming Register, following a
device reset, can be used.
During reset, all output channels go HIGH or high impedance, depending on the value of the LORS and BORS
pins, irrespective of the values in bits[14:13] of the connection memory.
10.0
Memory Built-In-Self-Test (BIST) Mode
As operation of the memory BIST will corrupt existing data, this test must only be initiated when the device is placed
“out-of-service” or isolated from live traffic.
The memory BIST mode is enabled through the microprocessor port (Section 14.14, Memory BIST Register).
Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The
memory test result is monitored through the Memory BIST Register.
11.0
JTAG Port
The ZL50060/1 JTAG interface conforms to the IEEE 1149.1 standard. The operation of the boundary-scan circuit
shall be controlled by an external Test Access Port (TAP) Controller.
11.1
Test Access Port (TAP)
The Test Access Port (TAP) consists of four input pins and one output pin described as follows:
•
Test Clock Input (TCK)
TCK provides the clock for the TAP Controller and is independent of any on-chip clock. TCK permits the
shifting of test data into or out of the Boundary-Scan register cells under the control of the TAP Controller in
Boundary-Scan Mode.
•
Test Mode Select Input (TMS)
The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS
signals are sampled at the rising edge of the TCK pulse. This pin in internally pulled to VDD_IO when not
driven from an external source.
•
Test Data Input (TDi)
Depending on the previously applied data to the TMS input, the serial input data applied to the TDi port is
connected either to the Instruction Register or to a Test Data Register. Both registers are described in
Section 11.2, TAP Registers. The applied input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to VDD_IO when not driven from an external source.
•
Test Data Output (TDo)
Depending on the previously applied sequence to the TMS input, the contents of either the instruction
register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked on the
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Data Sheet
falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDo output is
set to a high impedance state.
•
Test Reset (TRST)
TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled high when
not driven from an external source. This pin MUST be pulled low for normal operation.
11.2
TAP Registers
The ZL50060/1 implements the public instructions defined in the IEEE-1149.1 standard with the provision of an
Instruction Register and three Test Data Registers.
11.2.1
Test Instruction Register
The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the Instruction
Register from the TDi pin when the TAP Controller is in the shift-IR state. Instructions are subsequently decoded to
achieve two basic functions: to select the Test Data Register to operate while the instruction is current, and to
define the serial Test Data Register path to shift data between TDi and TDo during data register scanning. Please
refer to Figure 34 for JTAG test port timing.
11.2.2
Test Data Registers
11.2.2.1
The Boundary-Scan Register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the
boundary of the ZL50060/1 core logic.
11.2.2.2
The Bypass Register
The Bypass register is a single stage shift register to provide a one-bit path from TDi to TDo.
11.2.2.3
The Device Identification Register
The JTAG device ID for the ZL50060/1 is 0C38D14BH.
Version, Bits <31:28>:0000
Part No., Bits <27:12>:1100 0011 1000 1101
Manufacturer ID, Bits <11:1>:0001 0100 101
Header, Bit <0> (LSB):1
11.3
Boundary Scan Description Language (BSDL) File
A Boundary Scan Description Language (BSDL) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149.1 test interface.
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12.0
Data Sheet
Memory Address Mappings
When the most significant bit, A14, of the address bus is set to ’1’, the microprocessor performs an access to one of
the device’s internal memories. The Control Register bits MS[2:0] indicate which memory (Local Connection, Local
Data, Backplane Connection, or Backplane Data) is being accessed. Address bits A0-A13 indicate which location
within the particular memory is being accessed.
Address Bit
A14
Description
Selects memory or register access (0 = register, 1 = memory).
Note that which memory (Local Connection, Local Data, Backplane Connection, Backplane
Data) is accessed depends on the MS[2:0] bits in the Control Register.
A13-A9
Stream address (0 - 31)
Only streams 0 to 15 are used when the target side (Local/Backplane) is operating at
32.768Mbps.
A8-A0
Channel address (0 - 511)
Channels 0 to 31 are used when serial stream is at 2.048 Mbps
Channels 0 to 63 are used when serial stream is at 4.096 Mbps
Channels 0 to 127 are used when serial stream is at 8.192 Mbps
Channels 0 to 255 are used when serial stream is at 16.384 Mbps
Channels 0 to 511 are used when serial stream is at 32.768 Mbps
Table 11 - Address Map for Data and Connection Memory Locations (A14 = 1)
The device contains two data memory blocks, one for received Backplane data and one for received Local data. For
all data rates, the received data is converted to parallel format by internal serial-to-parallel converters and stored
sequentially in the relevant data memory.
12.1
Local Data Memory Bit Definition
The 8-bit Local Data Memory (LDM) has 8,192 positions. The locations are associated with the Local input streams
and channels. As explained in the section above, address bits A13-A0 of the microprocessor define the addresses
of the streams and the channels. The LDM is read-only and configured as follows:
Bit
Name
15:8
Reserved
7:0
LDM
Description
Set to a default value of 8’h00.
Local Data Memory - Local Input Channel Data.
The LDM[7:0] bits contain the timeslot data from the Local side input TDM
stream. LDM[7] corresponds to the first bit received, i.e., bit 7 in ST-BUS mode,
bit 0 in GCI-Bus mode. See Figure 7, ST-BUS and GCI-Bus Input Timing
Diagram for Different Data Rates for the arrival order of the bits.
Table 12 - Local Data Memory (LDM) Bits
Note that the Local Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the
table above are presented to provide 16-bit microprocessor read accesses.
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12.2
Data Sheet
Backplane Data Memory Bit Definition
The 8-bit Backplane Data Memory (BDM) has 8,192 positions. The locations are associated with the Backplane
input streams and channels. As explained previously, address bits A13-A0 of the microprocessor define the
addresses of the streams and the channels. The BDM is read-only and configured as follows:
Bit
Name
15:8
Reserved
7:0
BDM
Description
Set to a default value of 8’h00.
Backplane Data Memory - Backplane Input Channel Data.
The BDM[7:0] bits contain the timeslot data from the Backplane side input TDM
stream. BDM[7] corresponds to the first bit received, i.e., bit 7 in ST-BUS mode,
bit 0 in GCI-Bus mode. See Figure 7, ST-BUS and GCI-Bus Input Timing
Diagram for Different Data Rates for the arrival order of the bits
Table 13 - Backplane Data Memory (BDM) Bits
Note that the Backplane Data Memory is actually an 8-bit wide memory. The most significant 8 bits expressed in the
table above are presented to provide 16-bit microprocessor read accesses.
12.3
Local Connection Memory Bit Definition
The Local Connection Memory (LCM) has 8,192 addresses of 16-bit words. Each address, accessed through bits
A13-A0 of the microprocessor port, is allocated to an individual Local output stream and channel. The bit definition
for each 16-bit word is presented in Table 14 for Non-32 Mbps Source-to-Local Mode connections, and in Table 15
for 32Mbps Source-to-Local Mode connections.
The most-significant bit in the memory location, LSRC, selects the switch configuration for Backplane-to-Local or
Local-to-Local. When the per-channel Message Mode is selected (LMM memory bit = HIGH), the lower byte of the
LCM word (LCAB[7:0]) will be transmitted as data on the output stream (LSTo0-31) in place of data defined by the
Source Control, Stream and Channel Address bits.
.
Bit
Name
Description
15
LSRC
Local Source Control Bit
When LOW, the source is from the Backplane input port (Backplane Data Memory).
When HIGH, the source is from the Local input port (Local Data Memory).
Ignored when LMM is set HIGH.
14
LMM
Local Message Mode Bit
When LOW, the channel is in Connection Mode (data to be output on channel originated in
Local or Backplane Data Memory).
When HIGH, the channel is in Message Mode (data to be output on channel originated in
Local Connection Memory).
13
LE
Local Output Enable Bit
When LOW, the channel may be high impedance, either at the device output, or set by an
external buffer dependent upon the LORS pin.
When HIGH, the channel is active.
12:8
LSAB[4:0]
Source Stream Address Bits
The binary value of these 5 bits represents the input stream number.
Ignored when LMM is set HIGH.
Table 14 - LCM Bits for Non-32Mbps Source-to-Local Switching
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Data Sheet
Bit
Name
Description
7:0
LCAB[7:0]
Source Channel Address Bits / Message Mode Data
The binary value of these 8 bits represents the input channel number when LMM is set
LOW.
Transmitted as data when LMM is set HIGH.
Note: When LMM is set HIGH, in both ST-BUS and GCI-Bus modes, the LCAB[7:0] bits are
output sequentially to the timeslot with LCAB[7] being output first.
Table 14 - LCM Bits for Non-32Mbps Source-to-Local Switching (continued)
Bit
Name
Description
15
LSRC
Local Source Control Bit
When LOW, the source is from the Backplane input port (Backplane Data Memory).
When HIGH, the source is from the Local input port (Local Data Memory).
Ignored when LMM is set HIGH.
14
LMM
Local Message Mode Bit
When LOW, the channel is in Connection Mode (data to be output on channel originated in
Local or Backplane Data Memory).
When HIGH, the channel is in Message Mode (data to be output on channel originated in
Local Connection Memory).
13
LE
Local Output Enable Bit
When LOW, the channel may be high impedance, either at the device output, or set by an
external buffer dependent upon the LORS pin.
When HIGH, the channel is active.
12:9
LSAB[3:0]
Source Stream Address Bits
The binary value of these 4 bits represents the input stream number.
Ignored when LMM is set HIGH.
8:0
LCAB[8:0]
Source Channel Address Bits / Message Mode Data
The binary value of these 9 bits represents the input channel number, when LMM is LOW.
Bits LCAB[7:0] transmitted as data when LMM is set HIGH.
Note: When LMM is set HIGH, in both ST-BUS and GCI-Bus modes, the LCAB[7:0] bits are
output sequentially to the timeslot with LCAB[7] being output first.
Table 15 - LCM Bits for 32Mbps Source-to-Local Switching
12.4
Backplane Connection Memory Bit Definition
The Backplane Connection Memory (BCM) has 8,192 addresses of 16-bit words. Each address, accessed through
bits A13-A0 of the microprocessor port, is allocated to an individual Backplane output stream and channel. The bit
definition for each 16-bit word is presented in Table 16 for Non-32 Mbps Source-to-Backplane Mode connections,
and in Table 17 for 32 Mbps Source-to-Backplane Mode connections.
The most-significant bit in the memory location, BSRC, selects the switch configuration for Local-to-Backplane or
Backplane-to-Backplane. When the per-channel Message Mode is selected (BMM memory bit = HIGH), the lower
byte of the BCM word (BCAB[7:0]) will be transmitted as data on the output stream (BSTo0-31) in place of data
defined by the Source Control, Stream and Channel Address bits.
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Data Sheet
.
Bit
Name
Description
15
BSRC
Backplane Source Control Bit
When LOW, the source is from the Local input port (Local Data Memory).
When HIGH, the source is from the Backplane input port (Backplane Data Memory).
Ignored when BMM is set HIGH.
14
BMM
Backplane Message Mode Bit
When LOW, the channel is in Connection Mode (data to be output on channel originated in
Backplane or Local Data Memory).
When HIGH, the channel is in Message Mode (data to be output on channel originated in
Backplane Connection Memory).
13
BE
Backplane Output Enable Bit
When LOW, the channel may be high impedance, either at the device output, or set by an
external buffer dependent upon the BORS pin.
When HIGH, the channel is active.
12:8
BSAB[4:0]
Source Stream Address Bits
The binary value of these 5 bits represents the input stream number.
Ignored when BMM is set HIGH.
7:0
BCAB[7:0]
Source Channel Address Bits / Message Mode Data
The binary value of these 8 bits represents the input channel number when BMM is set
LOW.
Transmitted as data when BMM is set HIGH.
Note: When BMM is set HIGH, in both ST-BUS and GCI-Bus modes, the BCAB[7:0] bits
are output sequentially to the timeslot with BCAB[7] being output first.
Table 16 - BCM Bits for Non-32Mbps Source-to-Backplane Switching
Bit
Name
Description
15
BSRC
Backplane Source Control Bit
When LOW, the source is from the Local input port (Local Data Memory).
When HIGH, the source is from the Backplane input port (Backplane Data Memory).
Ignored when BMM is set HIGH.
14
BMM
Backplane Message Mode Bit
When LOW, the channel is in Connection Mode (data to be output on channel originated in
Backplane or Local Data Memory).
When HIGH, the channel is in Message Mode (data to be output on channel originated in
Backplane Connection Memory).
13
BE
Backplane Output Enable Bit
When LOW, the channel may be high impedance, either at the device output, or set by an
external buffer dependent upon the BORS pin.
When HIGH, the channel is active.
12:9
BSAB[3:0]
Source Stream Address Bits
The binary value of these 4 bits represents the input stream number.
Ignored when BMM is set HIGH.
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Data Sheet
Bit
Name
Description
8:0
BCAB[8:0]
Source Channel Address Bits / Message Mode Data
The binary value of these 9 bits represents the input channel number, when BMM is LOW.
Bits BCAB[7:0] transmitted as data when BMM is set HIGH.
Note: When BMM is set HIGH, in both ST-BUS and GCI-Bus modes, the BCAB[7:0] bits
are output sequentially to the timeslot with BCAB[7] being output first.
Table 17 - BCM Bits for 32Mbps Source-to-Backplane Switching
13.0
Internal Register Mappings
When the most significant bit, A14, of the address bus is set to ’0’, the microprocessor is performing an access to
one of the device’s internal registers. Address bits A13-A0 indicate which particular register is being accessed.
A14-A0
Register
0000H
Control Register, CR
0001H
Block Programming Register, BPR
0002H
BER Control Register, BERCR
0003H - 0022H
Local Input Channel Delay Register 0 - 31, LCDR0 - 31
0023H - 0042H
Local Input Bit Delay Register 0 - 31, LIDR0 - 31
0043H - 0062H
Backplane Input Channel Delay Register 0 - 31, BCDR0 - 31
0063H - 0082H
Backplane Input Bit Delay Register 0 - 31, BIDR0 - 31
0083H - 00A2H
Local Output Advancement Register 0 - 31, LOAR0 - 31
00A3H - 00C2H
Backplane Output Advancement Register 0 - 31, BOAR0 - 31
00C3H
Local BER Start Send Register, LBSSR
00C4H
Local Transmit BER Length Register, LTXBLR
00C5H
Local Receive BER Length Register, LRXBLR
00C6H
Local BER Start Receive Register, LBSRR
00C7H
Local BER Count Register, LBCR
00C8H
Backplane BER Start Send Register, BBSSR
00C9H
Backplane Transmit BER Length Register, BTXBLR
00CAH
Backplane Receive BER Length Register, BRXBLR
00CBH
Backplane BER Start Receive Register, BBSRR
00CCH
Backplane BER Count Register, BBCR
00CDH - 00ECH
Local Input Bit Rate Register 0 - 31, LIBRR0 - 31
00EDH - 010CH
Local Output Bit Rate Register 0 - 31, LOBRR0 - 31
010DH - 012CH
Backplane Input Bit Rate Register 0 - 31, BIBRR0 - 31
Table 18 - Address Map for Registers (A14 = 0)
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A14-A0
012DH - 014CH
Data Sheet
Register
Backplane Output Bit Rate Register 0 - 31, BOBRR0 - 31
014DH
Memory BIST Register, MBISTR
3FFFH
Device Identification Register, DIR
Table 18 - Address Map for Registers (A14 = 0) (continued)
14.0
Detailed Register Descriptions
This section describes the registers that are used in the device.
14.1
Control Register (CR)
Address 0000H.
The Control Register defines which memory is to be accessed. It initiates the memory block programming mode
and selects the Backplane and Local data rate modes. The Control Register (CR) is configured as follows:
Reset
Value
Bit
Name
15:13
FBD_
MODE[2:0]
0
12
SMPL_
MODE
0
11
Reserved
0
10
FBDEN
0
9
MODE32L
0
Description
Frame Boundary Discriminator Mode
When set to 111B, the Frame Boundary Discriminator can handle both low
frequency and high frequency jitter.
When set to 000B, the Frame Boundary Discriminator is set to handle lower
frequency jitter only.
All other values are reserved.
These bits are ignored when FBDEN bit is LOW.
Sample Point Mode
When LOW the input bit sampling point is always at the 3/4 bit location. The input bit
fractional delay is programmed in 1/4 bit increments from 0 to 7 3/4 as per the value
of the LIDR0 to LIDR31 and BIDR0 to BIDR31 registers.
When HIGH, the input bit sampling point is programmed to the 3/4, 4/4, 1/4, 2/4 bit
location as per the value of the LIDR0 to LIDR31 and BIDR0 to BIDR31 registers. In
addition, the incoming data can be delayed by 0 to 7 bits in 1 bit increments.
See Table 24, Table 25, Table 28 and Table 29 for details.
Reserved
Must be set to 0 for normal operation
Frame Boundary Discriminator Enable
When LOW, the frame boundary discriminator function is disabled.
When HIGH, enables frame boundary discriminator function which allows the
device to tolerate inconsistent frame boundaries, hence improving the tolerance to
cycle-to-cycle variation on the input clock.
Local 32MHz Mode
When LOW, Local streams LSTi0-31 and LSTo0-31 can be individually programmed
for data rates of 2, 4, 8, or 16 Mbps.
When HIGH, Local streams LSTi0-15 and LSTo0-15 operate at 32.768 Mbps only
and LSTi16-31 and LSTo16-31 are unused.
Table 19 - Control Register Bits
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Bit
Name
Reset
Value
8
FPW
0
7
MODE32B
0
6
C8IPOL
0
5
COPOL
0
4
MBP
0
3
OSB
0
Data Sheet
Description
Frame Pulse Width
When LOW, the user must apply a 122 ns frame pulse on FP8i; the FP8o pin will
output a 122 ns wide frame pulse; FP16o will output a 61 ns wide frame pulse.
When HIGH, the user must apply a 244 ns frame pulse on FP8i; the FP8o pin will
output a 244 ns wide frame pulse; FP16o will output a 122 ns wide frame pulse.
Backplane 32 MHz Mode
When LOW, Backplane streams BSTi0-31 and BSTo0-31 may be individually
programmed for data rates of 2, 4, 8, or 16 Mbps.
When HIGH, Backplane streams BSTi0-15 and BSTo0-15 operate at 32.768 Mbps
only and BSTi16-31 and BSTo16-31 are unused.
8 MHz Input Clock Polarity
The frame boundary is aligned to the falling or rising edge of the input clock.
When LOW, the frame boundary is aligned to the clock falling edge.
When HIGH, the frame boundary is aligned to the clock rising edge.
Output Clock Polarity
When LOW, the output clock has the same polarity as the input clock.
When HIGH, the output clock is inverted.
This applies to both the 8 MHz (C8o) and 16 MHz (C16o) output clocks.
Memory Block Programming
When LOW, the memory block programming mode is disabled.
When HIGH, the connection memory block programming mode is ready to program
the Local Connection Memory (LCM) and the Backplane Connection Memory
(BCM).
Output Stand By
This bit enables the BSTo0-31 and LSTo0-31 serial outputs.
ODE Pin
OSB bit
BSTo0-31, LSTo0-31
0
1
1
X
0
1
Disabled
Disabled
Enabled
Output Control with ODE pin and OSB bit
2
Reserved
0
1:0
MS[1:0]
0
When LOW, BSTo0-31 and LSTo0-31 are driven HIGH or high impedance,
dependent on the BORS and LORS pin settings respectively, and BCSTo0-3 and
LCSTo0-3 are driven low.
When HIGH, BSTo0-31, LSTo0-31, BCSTo0-3 and LCSTo0-3 are enabled.
Reserved
Must be set to 0 for normal operation
Memory Select Bits
These three bits select the connection or data memory for subsequent microport
memory access operations:
00 selects Local Connection Memory (LCM) for read or write operations.
01 selects Backplane Connection Memory (BCM) for read or write operations.
10 selects Local Data Memory (LDM) for read-only operation.
11 selects Backplane Data Memory (BDM) for read-only operation.
Table 19 - Control Register Bits (continued)
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Frame Boundary
(a) Frame Pulse Width = 122ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 0
C8i
FP8i
(b) Frame Pulse Width = 122ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 1
C8i
FP8i
(c) Frame Pulse Width = 244ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 0
C8i
FP8i
(d) Frame Pulse Width = 244ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 1
C8i
FP8i
Figure 23 - Frame Boundary Conditions, ST-BUS Operation
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Data Sheet
ZL50060/1
Frame Boundary
(e) Pulse Width = 122ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 0
C8i
FP8i
(f) Pulse Width = 122ns,
Control Register Bit8 (FPW) = 0
Control Register Bit6 (C8IPOL) = 1
C8i
FP8i
(g) Pulse Width = 244ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 0
C8i
FP8i
(h) Pulse Width = 244ns,
Control Register Bit8 (FPW) = 1
Control Register Bit6 (C8IPOL) = 1
C8i
FP8i
Figure 24 - Frame Boundary Conditions, GCI-Bus Operation
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Data Sheet
ZL50060/1
14.2
Data Sheet
Block Programming Register (BPR)
Address 0001H.
The Block Programming Register stores the bit patterns to be loaded into the connection memories when the
Memory Block Programming feature is enabled. The BPE, LBPD[2:0] and BBPD[2:0] bits in the BPR register must
be defined in the same write operation.
The BPE bit is set HIGH to commence the block programming operation. Programming is completed in one frame
period and may be initiated at any time within a frame. The BPE bit returns to LOW to indicate that the block
programming function has completed.
When BPE is HIGH, no other bits of the BPR register may be changed for at least a single frame period, except to
abort the programming operation. The programming operation may be aborted by setting either BPE to LOW, or the
Control Register bit, MBP, to LOW.
The BPR register is configured as follows.
.
Bit
Name
Reset
Value
15:7
Reserved
0
Reserved
Must be set to 0 for normal operation
6:4
BBPD[2:0]
0
Backplane Block Programming Data
These bits refer to the value loaded into the Backplane Connection Memory
(BCM) when the Memory Block Programming feature is activated.
When the MBP bit in the Control Register (CR) is set HIGH and BPE (in this
register) is set HIGH, the contents of bits BBPD[2:0] are loaded into bits 15-13,
respectively, of the BCM. Bits 12-0 of the BCM are set LOW.
3:1
LBPD[2:0]
0
Local Block Programming Data
These bits refer to the value loaded into the Local Connection Memory (LCM),
when the Memory Block Programming feature is activated.
When the MBP bit in the Control Register is set HIGH and BPE (in this register)
is set HIGH, the contents of bits LBPD[2:0] are loaded into bits 15-13,
respectively, of the LCM. Bits 12-0 of the LCM are set LOW.
0
BPE
0
Block Programming Enable
A LOW to HIGH transition of this bit enables the Memory Block Programming
function. A LOW will be returned after 125 µs, upon completion of programming.
Set LOW to abort the programming operation.
Description
Table 20 - Block Programming Register Bits
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14.3
Data Sheet
Bit Error Rate Test Control Register (BERCR)
Address 0002H.
The BER Test Control Register controls Backplane and Local port BER testing. It independently enables and
disables transmission and reception. It is configured as follows:
Bit
Name
Reset
Value
15:12
Reserved
0
Reserved
Must be set to 0 for normal operation
11
LOCKB
0
Backplane Lock (READ ONLY)
This bit is automatically set HIGH when the receiver has locked to the incoming
data sequence. The bit is reset by a LOW to HIGH transition on SBERRXB.
10
PRSTB
0
PBER Reset for Backplane
A LOW to HIGH transition initializes the Backplane BER generator to the seed
value.
9
CBERB
0
Clear Bit Error Rate Register for Backplane
A LOW to HIGH transition in this bit resets the Backplane internal bit error
counter and the Backplane Bit Error Register (BBERR) to zero.
8
SBERRXB
0
Start Bit Error Rate Receiver for Backplane
A LOW to HIGH transition enables the Backplane BER receiver. The receiver
monitors incoming data for reception of the seed value. When detected, the
LOCK state is indicated (LOCKB), the receiver compares the incoming bits with
the reference generator for bit equality, and increments the Backplane Bit Error
Register (BBCR) on each failure.
When LOW, bit comparison is disabled and the error count is frozen.
7
SBERTXB
0
Start Bit Error Rate Transmitter for Backplane
A LOW to HIGH transition starts the BER transmission on the Backplane.
When LOW, Backplane transmission is disabled.
6
PRBSB
0
BER Mode Select for Backplane
When HIGH, a PRBS sequence of length 223-1 is selected for the Backplane
port.
When LOW, a PRBS sequence of length 215-1 is selected for the Backplane
port.
5
LOCKL
0
Local Lock (READ ONLY)
This bit is automatically set HIGH when the receiver has locked to the incoming
data sequence. The bit is reset by a LOW to HIGH transition on SBERRXL
4
PRSTL
0
PBER Reset for Local
A LOW to HIGH transition initializes the Local BER generator to the seed value.
3
CBERL
0
Clear Bit Error Rate Register for Local
A LOW to HIGH transition resets the Local internal bit error counter and the
Local Bit Error Register (LBERR) to zero.
Description
Table 21 - Bit Error Rate Test Control Register (BERCR) Bits
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Data Sheet
Bit
Name
Reset
Value
2
SBERRXL
0
Start Bit Error Rate Receiver for Local
A LOW to HIGH transition enables the Local BER receiver. The receiver
monitors incoming data for reception of the seed value. When detected, the
LOCK state is indicated (LOCKL), the receiver compares the incoming bits with
the reference generator for bit equality, and increments the Local Bit Error
Register (LBCR) on each failure.
When LOW, bit comparison is disabled and the error count is frozen.
1
SBERTXL
0
Start Bit Error Rate Transmitter for Local
A LOW to HIGH transition enables the Local BER transmission.
When LOW, Local transmission is disabled.
0
PRBSL
0
BER Mode Select for Local
When HIGH, a PRBS sequence of length 223-1 is selected for the Local port.
When LOW, a PRBS sequence of length 215-1 is selected for the Local port.
Description
Table 21 - Bit Error Rate Test Control Register (BERCR) Bits (continued)
14.4
Local Input Channel Delay Registers (LCDR0 to LCDR31)
Addresses 0003h to 0022H.
Thirty-two Local Input Channel Delay Registers (LCDR0 to LCDR31) allow users to program the input channel
delay for the Local input data streams LSTi0-31. The maximum possible adjustment is 511 channels and the
LCDR0 to LCDR31 registers are configured as follows:
:
LCDRn Bit
(where n = 0 to 31 for Local
Non-32Mbps Mode, n = 0 to 15
for Local 32Mbps Mode)
Name
Reset
Value
15:9
Reserved
0
Reserved
Must be set to 0 for normal operation
8:0
LCD[8:0]
0
Local Channel Delay Register
The binary value of these bits refers to the channel
delay value for the Local input stream.
Description
Table 22 - Local Input Channel Delay Register (LCDRn) Bits
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14.4.1
Data Sheet
Local Channel Delay Bits 8-0 (LCD8 - LCD0)
These nine bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data
from the Local input pins. The input channel delay can be selected to be up to 511 (32 Mbps streams), 255
(16 Mbps streams), 127 (8 Mbps streams), 63 (4 Mbps streams) or 31 (2 Mbps streams) channels from the frame
boundary.
Input Stream
Channel Delay
Corresponding Delay Bits
LCD8-LCD0
0 Channel (Default)
0 0000 0000
1 Channel
0 0000 0001
2 Channels
0 0000 0010
3 Channels
0 0000 0011
4 Channels
0 0000 0100
5 Channels
0 0000 0101
...
...
509 Channels
1 1111 1101
510 Channels
1 1111 1110
511 Channels
1 1111 1111
Table 23 - Local Input Channel Delay (LCD) Programming Table
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14.5
Data Sheet
Local Input Bit Delay Registers (LIDR0 to LIDR31)
Addresses 0023H to 0042H.
There are thirty-two Local Input Delay Registers (LIDR0 to LIDR31).
When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit
location and LIDR0 to LIDR31 define the input bit and fractional bit delay of each Local stream. The possible bit
delay adjustment is up to 73/4 bits, in steps of 1/4 bit.
When the SMPL_MODE bit is HIGH, LIDR0 to LIDR31 define the input bit sampling point as well as the integer bit
delay of each Local stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay can be
adjusted in 1-bit increments from 0 to 7 bits.
The LIDR0 to LIDR31 registers are configured as follows:
LIDRn Bit
(where n = 0 to 31 for Local
Non-32 Mbps Mode, n = 0 to 15
for Local 32Mbps Mode)
Name
Reset
Value
15:5
Reserved
0
Reserved
Must be set to 0 for normal operation
4:0
LID[4:0]
0
Local Input Bit Delay Register
When SMPL_MODE = LOW, the binary value of these
bits refers to the input bit and fractional bit delay value (0
to 73/4).
When SMPL_MODE = HIGH, the binary value of LID[1:0]
refers to the input bit sampling point (1/4 to 4/4). LID[4:2]
refer to the integer bit delay value (0 to 7 bits).
Description
Table 24 - Local Input Bit Delay Register (LIDRn) Bits
14.5.1
Local Input Delay Bits 4-0 (LID[4:0])
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to
sample each input. Input bit delay adjustment can range up to 73/4 bit periods forward, with resolution of 1/4 bit
period. The default sampling point is at the 3/4 bit location.
This can be described as: no. of bits delay = LID[4:0] / 4
For example, if LID[4:0] is set to 10011 (19), the input bit delay = 19 * 1/4 = 43/4.
When SMPL_MODE = HIGH, the binary value of LID[1:0] refers to the input bit sampling point (1/4 to 4/4). LID[4:2]
refer to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from 1/4 to 4/4 in 1/4-bit increments.
Table 25 illustrates the bit delay and sampling point selection.
SMPL_MODE
= LOW
LIDn
SMPL_MODE
= HIGH
LID4
LID3
LID2
LID1
LID0
Input Data
Bit Delay
Input Data
Bit Delay
Input Data
Sampling
Point
0
0
0
0
0
0
0
0
0
1
0 (Default)
1/4
0 (Default)
0
3/4
4/4
Table 25 - Local Input Bit Delay and Sampling Point Programming Table
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Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
SMPL_MODE
= LOW
LIDn
SMPL_MODE
= HIGH
LID4
LID3
LID2
LID1
LID0
Input Data
Bit Delay
Input Data
Bit Delay
Input Data
Sampling
Point
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1/2
3/4
1
1 1/4
1 1/2
1 3/4
2
2 1/4
2 1/2
2 3/4
3
3 1/4
3 1/2
3 3/4
4
4 1/4
4 1/2
4 3/4
5
5 1/4
5 1/2
5 3/4
6
6 1/4
6 1/2
6 3/4
7
7 1/4
7 1/2
7 3/4
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
Table 25 - Local Input Bit Delay and Sampling Point Programming Table (continued)
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14.6
Data Sheet
Backplane Input Channel Delay Registers (BCDR0 to BCDR31)
Addresses 0043H to 0062H
Thirty-two Backplane Input Channel Delay Registers (BCDR0 to BCDR31) allow users to program the input
channel delay for the Backplane input data streams BSTi0-31. The maximum possible adjustment is 511 channels
and the BCDR0 to BCDR31 registers are configured as follows:
BCDRn Bit
(where n = 0 to 31 for
Backplane Non-32 Mbps
Mode, n = 0 to 15 for
Backplane 32 Mbps Mode)
15:9
Name
Reset
Value
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
8:0
BCD[8:0]
Backplane Channel Delay Register
0
The binary value of these bits refers to the channel
delay value for the Backplane input stream.
Table 26 - Backplane Input Channel Delay Register (BCDRn) Bits
14.6.1
Backplane Channel Delay Bits 8-0 (BCD8 - BCD0)
These nine bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data
from the Backplane input pins. The input channel delay can be selected to be up to 511 (32 Mbps streams), 255
(16 Mbps streams), 127 (8 Mbps streams), 63 (4 Mbps streams) or 31 (2 Mbps streams) channels from the frame
boundary.
Input Stream
Channel Delay
Corresponding Delay Bits
BCD8-BCD0
0 Channel (Default)
0 0000 0000
1 Channel
0 0000 0001
2 Channels
0 0000 0010
3 Channels
0 0000 0011
4 Channels
0 0000 0100
5 Channels
0 0000 0101
...
...
509 Channels
1 1111 1101
510 Channels
1 1111 1110
511 Channels
1 1111 1111
Table 27 - Backplane Input Channel Delay (BCD) Programming Table
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14.7
Data Sheet
Backplane Input Bit Delay Registers (BIDR0 to BIDR31)
Addresses 0063H to 0082H
There are thirty-two Backplane Input Delay Registers (BIDR0 to BIDR31).
When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit
location and BIDR0 to BIDR31 define the input bit and fractional bit delay of each Backplane stream. The possible
bit delay adjustment is up to 73/4 bits, in steps of 1/4 bit.
When the SMPL_MODE bit is HIGH, BIDR0 to BIDR31 define the input bit sampling point as well as the integer bit
delay of each Backplane stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay
can be adjusted in 1-bit increments from 0 to 7 bits.
The BIDR0 to BIDR31 registers are configured as follows:
BIDRn Bit
(where n = 0 to 31 for
Backplane Non-32 Mbps Mode,
n = 0 to 15 for Backplane
32 Mbps Mode)
Name
Reset
Value
15:5
Reserved
0
Reserved
Must be set to 0 for normal operation
4:0
BID[4:0]
0
Backplane Input Bit Delay Register
When SMPL_MODE = LOW, the binary value of these
bits refers to the input bit and fractional bit delay value (0
to 73/4).
When SMPL_MODE = HIGH, the binary value of BID[1:0]
refers to the input bit sampling point (1/4 to 4/4). BID[4:2]
refer to the integer bit delay value (0 to 7 bits).
Description
Table 28 - Backplane Input Bit Delay Register (BIDRn) Bits
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14.7.1
Data Sheet
Backplane Input Delay Bits 4-0 (BID[4:0])
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to
sample each input. Input bit delay adjustment can range up to 73/4 bit periods forward, with resolution of 1/4 bit
period. The default sampling point is at the 3/4 bit location.
This can be described as: no. of bits delay = BID[4:0] / 4
For example, if BID[4:0] is set to 10011 (19), the input bit delay = 19 * 1/4 = 43/4.
When SMPL_MODE = HIGH, the binary value of BID[1:0] refers to the input bit sampling point (1/4 to 4/4). BID[4:2]
refer to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from 1/4 to 4/4 in 1/4-bit increments.
Table 29 illustrates the bit delay and sampling point selection.
SMPL_MODE
= LOW
BIDn
SMPL_MODE
= HIGH
BID4
BID3
BID2
BID1
BID0
Input Data
Bit Delay
Input Data
Bit Delay
Input Data
Sampling
Point
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 (Default)
1/4
1/2
3/4
1
1 1/4
1 1/2
1 3/4
2
2 1/4
2 1/2
2 3/4
3
3 1/4
3 1/2
3 3/4
4
4 1/4
4 1/2
4 3/4
5
5 1/4
5 1/2
5 3/4
6
6 1/4
6 1/2
6 3/4
0 (Default)
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
Table 29 - Backplane Input Bit Delay and Sampling Point Programming Table
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Data Sheet
SMPL_MODE
= LOW
BIDn
SMPL_MODE
= HIGH
BID4
BID3
BID2
BID1
BID0
Input Data
Bit Delay
Input Data
Bit Delay
Input Data
Sampling
Point
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
7
7 1/4
7 1/2
7 3/4
7
7
7
7
3/4
4/4
1/4
2/4
Table 29 - Backplane Input Bit Delay and Sampling Point Programming Table (continued)
14.8
Local Output Advancement Registers (LOAR0 to LOAR31)
Addresses 0083H to 00A2H.
Thirty-two Local Output Advancement Registers (LOAR0 to LOAR31) allow users to program the output
advancement for output data streams LSTo0 to LSTo31.
For 2 Mbps, 4 Mbps, 8 Mbps and 16 Mbps stream operation, the possible adjustment is -2 (15 ns), -4 (31 ns) or -6
(46 ns) cycles of the internal system clock (131.072 MHz).
For 32 Mbps stream operation, the possible adjustment is -1 (7.6 ns), -2 (15 ns) or -3 (23 ns) cycles of the internal
system clock (131.072 MHz).
The LOAR0 to LOAR31 registers are configured as follows:
LOARn Bit
(where n = 0 to 31 for Local
Non-32 Mbps Mode, n = 0 to 15
for Local 32 Mbps Mode)
Name
Reset
Value
15:2
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
1:0
LOA[1:0]
0
Local Output Advancement Value
Table 30 - Local Output Advancement Register (LOAR) Bits
14.8.1
Local Output Advancement Bits 1-0 (LOA1-LOA0)
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.
Local Output Advancement For
2 Mbps, 4 Mbps, 8 Mbps & 16 Mbps
Local Output
Advancement For 32 Mbps
Corresponding
Advancement Bits
Clock Rate 131.072 MHz
Clock Rate 131.072 MHz
LOA1
LOA0
0 (Default)
0 (Default)
0
0
-2 cycles (~15 ns)
-1 cycle (~7.6 ns)
0
1
Table 31 - Local Output Advancement (LOAR) Programming Table
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ZL50060/1
Data Sheet
Local Output Advancement For
2 Mbps, 4 Mbps, 8 Mbps & 16 Mbps
Local Output
Advancement For 32 Mbps
Corresponding
Advancement Bits
Clock Rate 131.072 MHz
Clock Rate 131.072 MHz
LOA1
LOA0
-4 cycles (~31 ns)
-2 cycles (~15 ns)
1
0
-6 cycles (~46 ns)
-3 cycles (~23 ns)
1
1
Table 31 - Local Output Advancement (LOAR) Programming Table (continued)
14.9
Backplane Output Advancement Registers (BOAR0 - BOAR31)
Addresses 00A3H to 00C2H
Thirty-two Backplane Output Advancement Registers (BOAR0 to BOAR31) allow users to program the output
advancement for output data streams BSTo0 to BSTo31.
For 2 Mbps, 4 Mbps, 8 Mbps and 16 Mbps stream operation, the possible adjustment is -2 (15 ns), -4 (31 ns) or -6
(46 ns) cycles of the internal system clock (131.072 MHz).
For 32 Mbps stream operation, the possible adjustment is -1 (7.6 ns), -2 (15 ns) or -3 (23 ns) cycles of the internal
system clock (131.072 MHz).
The BOAR0 to BOAR31 registers are configured as follows:
BOARn Bit
(where n = 0 to 31 for Backplane
Non-32 Mbps Mode, n = 0 to 15
for Backplane 32 Mbps Mode)
Name
Reset
Value
15:2
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
1:0
BOA[1:0]
0
Backplane Output Advancement Value
Table 32 - Backplane Output Advancement Register (BOAR) Bits
14.9.1
Backplane Output Advancement Bits 1-0 (BOA1-BOA0)
The binary value of these two bits indicates the amount of offset that a particular stream output can be advanced
with respect to the output frame boundary. When the advancement is 0, the serial output stream has the normal
alignment with the generated frame pulse FP8o.
Backplane Output Advancement For
2 Mbps, 4 Mbps, 8 Mbps & 16 Mbps
Backplane Output
Advancement For 32 Mbps
Corresponding
Advancement Bits
Clock Rate 131.072 MHz
Clock Rate 131.072 MHz
BOA1
BOA0
0 (Default)
0 (Default)
0
0
-2 cycles (~15 ns)
-1 cycle (~7.6 ns)
0
1
-4 cycles (~31 ns)
-2 cycles (~15 ns)
1
0
-6 cycles (~46 ns)
-3 cycles (~23 ns)
1
1
Table 33 - Backplane Output Advancement (BOAR) Programming Table
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14.10
Data Sheet
Local Bit Error Rate (BER) Registers
14.10.1
Local BER Start Send Register (LBSSR)
Address 00C3H.
The Local BER Start Send Register defines the output channel and the stream on which the BER sequence starts
to be transmitted. The LBSSR register is configured differently for Non-32 Mbps and 32 Mbps Modes:
Bit
Name
Reset
Value
15:13
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
12:8
LBSSA[4:0]
0
Local BER Send Stream Address Bits
The binary value of these bits refers to the Local output stream
which carries the BER data.
7:0
LBSCA[7:0]
0
Local BER Send Channel Address Bits
The binary value of these bits refers to the Local output channel at
which the BER data starts to be sent.
Table 34 - Local BER Start Send Register (LBSSR) Bits in Non-32 Mbps Mode
Bit
Name
Reset
Value
15:13
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
12:9
LBSSA[3:0]
0
Local BER Send Stream Address Bits
The binary value of these bits refers to the Local output stream
which carries the BER data.
8:0
LBSCA[8:0]
0
Local BER Send Channel Address Bits
The binary value of these bits refers to the Local output channel at
which the BER data starts to be sent.
Table 35 - Local BER Start Send Register (LBSSR) Bits in 32 Mbps Mode
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14.10.2
Data Sheet
Local Transmit BER Length Register (LTXBLR)
Address 00C4H.
Local BER Transmit Length Register (LTXBLR) defines how many channels of the BER sequence will be
transmitted during each frame. The minimum length of the BER transmitter is 1 channel. To set a desired BER
length, set LTXBL8-0 bits for the desired length - 1 channel. For example, to run a BER test for 32 consecutive
channels, program LTXBL to 000011111B. The LTXBLR register is configured as follows:
Bit
Name
Reset
Value
15:9
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
8:0
LTXBL[8:0]
Local Transmit BER Length Bits
0
The binary value of these bits defines the number of channels in addition to the
Start Channel allocated for the BER Transmitter. (i.e. Total Channels = LTXBL
value + 1)
Table 36 - Local BER Length Register (LTXBLR) Bits
14.10.3
Local Receive BER Length Register (LRXBLR)
Address 00C5H.
Local BER Receive Length Register (LRXBLR) defines how many channels of the BER sequence will be received
during each frame. The minimum length of the BER receiver is 1 channel. To set a desired BER length, set
LRXBL8-0 bits for the desired length - 1 channel. For example, to receive a BER test for 32 consecutive channels,
program LRXBL to 000011111B. The LRXBLR register is configured as follows:
Bit
Name
Reset
Value
15:9
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
8:0
LRXBL[8:0]
0
Local Receive BER Length Bits
The binary value of these bits defines the number of channels in addition
to the Start Channel allocated for the BER Receiver. (i.e., Total Channels
= LRXBL value + 1)
Table 37 - Local Receive BER Length Register (LRXBLR) Bits
72
Zarlink Semiconductor Inc.
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14.10.4
Data Sheet
Local BER Start Receive Register (LBSRR)
Address 00C6H.
Local BER Start Receive Register defines the input stream and start channel at which the BER sequence shall start
to be received. The LBSRR register is configured differently for Non-32 Mbps and 32 Mbps Modes:
Bit
Name
Reset
Value
15:13
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
12:8
LBRSA[4:0]
0
Local BER Receive Stream Address Bits
The binary value of these bits refers to the Local input stream
configured to receive the BER data.
7:0
LBRCA[7:0]
0
Local BER Receive Channel Address Bits
The binary value of these bits refers to the Local input channel at which
the BER data starts to be compared.
Table 38 - Local BER Start Receive Register (LBSRR) Bits for Non-32 Mbps Mode
Bit
Name
Reset
Value
15:13
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
12:9
LBRSA[3:0]
0
Local BER Receive Stream Address Bits
The binary value of these bits refers to the Local input stream
configured to receive the BER data.
8:0
LBRCA[8:0]
0
Local BER Receive Channel Address Bits
The binary value of these bits refers to the Local input channel at which
the BER data starts to be compared.
Table 39 - Local BER Start Receive Register (LBSRR) Bits for 32 Mbps Mode
14.10.5
Local BER Count Register (LBCR)
Address 00C7H.
Local BER Count Register contains the number of counted errors. This register is read-only. The LBCR register is
configured as follows:
Bit
Name
Reset
Value
15:0
LBC[15:0]
0
Description
Local Bit Error Rate Count
The binary value of the bits defines the Local Bit Error count.
If the number of errors exceeds the maximum counter value, this counter
will stay at FFFFH until the CBERL bit in the BERCR register clears it.
Table 40 - Local BER Count Register (LBCR) Bits
73
Zarlink Semiconductor Inc.
ZL50060/1
14.11
14.11.1
Data Sheet
Backplane Bit Error Rate (BER) Registers
Backplane BER Start Send Register (BBSSR)
Address 00C8H.
Backplane BER Start Send Register defines the output channel and the stream on which the BER sequence is
transmitted.
The BBSSR register is configured as follows:
Bit
Name
Reset
Value
15:14
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
13:9
BBSSA[4:0]
0
Backplane BER Send Stream Address Bits
The binary value of these bits refers to the Backplane output stream
which carries the BER data.
8:0
BBSCA[8:0]
0
Backplane BER Send Channel Address Bits
The binary value of these bits refers to the Backplane output channel at
which the BER data starts to be sent.
Table 41 - Backplane BER Start Send Register (BBSSR) Bits
14.11.2
Backplane Transmit BER Length Register (BTXBLR)
Address 00C9H.
Backplane Transmit BER Length Register (BTXBLR) defines how many channels of the BER sequence will be
transmitted in each frame. The minimum length of the BER transmitter is 1 channel. To set a desired BER length,
set BTXBL8-0 bits for the desired length - 1 channel. For example, to run a BER test for 32 consecutive channels,
program BTXBL to 000011111B. The BTXBLR register is configured as follows:
Bit
Name
Reset
Value
15:9
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
8:0
BTXBL[8:0]
0
Backplane Transmit BER Length Bits
The binary value of these bits defines the number of channels in addition to the
Start Channel allocated for the BER Transmitter. (i.e., Total Channels = BTXBL
value + 1)
Table 42 - Backplane Transmit BER Length (BTXBLR) Bits
74
Zarlink Semiconductor Inc.
ZL50060/1
14.11.3
Data Sheet
Backplane Receive BER Length Register (BRXBLR)
Address 00CAH.
Backplane Receive BER Length Register (BRXBLR) defines how many channels of the BER sequence will be
received in each frame. The minimum length of the BER receiver is 1 channel. To set a desired BER length, set
BRXBL8-0 bits for the desired length - 1 channel. For example, to receive a BER test for 32 consecutive channels,
program BRXBL to 000011111B. The BRXBLR register is configured as follows:
Bit
Name
Reset
Value
15:9
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
8:0
BRXBL[8:0]
0
Backplane Receive BER Length Bits
The binary value of these bits defines the number of channels in addition to
the Start Channel allocated for the BER Receiver. (i.e. Total Channels =
BRXBL value + 1)
Table 43 - Backplane Receive BER Length (BRXBLR) Bits
14.11.4
Backplane BER Start Receive Register (BBSRR)
Address 00CBH.
Backplane BER Start Receive Register defines the input stream and the start channel at which the BER sequence
shall start to be received. The BBSRR register is configured as follows:
Bit
Name
Reset
Value
15:14
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
13:9
BBRSA[4:0]
0
Backplane BER Receive Stream Address Bits
The binary value of these bits refers to the Backplane input stream configured
to receive the BER data.
8:0
BBRCA[8:0]
0
Backplane BER Receive Channel Address Bits
The binary value of these bits refers to the Backplane input channel at which
the BER data starts to be compared.
Table 44 - Backplane BER Start Receive Register (BBSRR) Bits
75
Zarlink Semiconductor Inc.
ZL50060/1
14.11.5
Data Sheet
Backplane BER Count Register (BBCR)
Address 00CCH.
Backplane BER Count Register contains the number of counted errors. This register is read-only.
The BBCR register is configured as follows:
Bit
Name
Reset
Value
15:0
BBC[15:0]
0
Description
Backplane Bit Error Rate Count
The binary value of these bits defines the Backplane Bit Error count.
If the number of errors exceeds the maximum counter value, this counter will
stay at FFFFH until the CBERB bit in the BERCR register clears it.
Table 45 - Backplane BER Count Register (BBCR) Bits
14.12
Local Bit Rate Registers
14.12.1
Local Input Bit Rate Registers (LIBRR0 - LIBRR31)
Addresses 00CDH to 00ECH.
Thirty-two Local Input Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or 16 Mbps.
These registers may be overridden by setting Local 32 Mbps Mode in the Control Register (via the MODE32L bit),
in which case, Local input streams 0-15 will operate at 32 Mbps and Local input streams 16-31 will be unused.
The LIBRR registers are configured as follows:
LIBRn
(for n=0 to
31)
Name
Reset
Value
15:2
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
1:0
LIBR[1:0]
Local Input Bit Rate
0
Table 46 - Local Input Bit Rate Register (LIBRR) Bits
MODE32L
LIBR1
LIBR0
Bit rate for stream n
0
0
0
2 Mbps
0
0
1
4 Mbps
0
1
0
8 Mbps
0
1
1
16 Mbps
1
X
X
32 Mbps
Table 47 - Local Input Bit Rate (LIBR) Programming Table
76
Zarlink Semiconductor Inc.
ZL50060/1
14.12.2
Data Sheet
Local Output Bit Rate Registers (LOBRR0 - LOBRR31)
Addresses 00EDH to 010CH.
Thirty-two Local Output Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or
16 Mbps. These registers may be overridden by setting Local 32 Mbps Mode in the Control Register (via the
MODE32L bit), in which case, Local output streams 0-15 will operate at 32 Mbps and Local output streams 16-31
will be unused. The LOBRR registers are configured as follows:
LOBRn Bit
(where n = 0 to
31)
Name
Reset
Value
15:2
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
1:0
LOBR[1:0]
0
Local Output Bit Rate
Table 48 - Local Output Bit Rate Register (LOBRR) Bits
MODE32L
LOBR1
LOBR0
Bit rate for stream n
0
0
0
2 Mbps
0
0
1
4 Mbps
0
1
0
8 Mbps
0
1
1
16 Mbps
1
X
X
32 Mbps
Table 49 - Local Output Bit Rate (LOBR) Programming Table
14.13
Backplane Bit Rate Registers
14.13.1
Backplane Input Bit Rate Registers (BIBRR0 - BIBRR31)
Addresses 010DH to 012CH.
Thirty-two Backplane Input Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or
16 Mbps. These registers may be overridden by setting Backplane 32 Mbps Mode in the Control Register (via the
MODE32B bit), in which case, Backplane input streams 0-15 will operate at 32 Mbps and Backplane input streams
16-31 will be unused.
The BIBRR registers are configured as follows:
BIBRn Bit
(for n = 0 to 31)
15:2
Name
Reset
Value
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
1:0
BIBR[1:0]
0
Backplane Input Bit Rate
Table 50 - Backplane Input Bit Rate Register (BIBRR) Bits
77
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
MODE32B
BIBR1
BIBR0
Bit rate for stream n
0
0
0
2 Mbps
0
0
1
4 Mbps
0
1
0
8 Mbps
0
1
1
16 Mbps
1
X
X
32 Mbps
Table 51 - Backplane Input Bit Rate (BIBR) Programming Table
14.13.2
Backplane Output Bit Rate Registers (BOBRR0 - BOBRR31)
Addresses 012DH to 014CH.
Thirty-two Backplane Output Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or
16 Mbps. These registers may be overridden by setting Backplane 32 Mbps Mode in the Control Register (via the
MODE32B bit), in which case, Backplane output streams 0-15 will operate at 32 Mbps and Backplane output
streams 16-31 will be unused. The BOBRR registers are configured as follows:
BOBRn Bit
(for n = 0 to 31)
15:2
Name
Reset
Value
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
1:0
BOBR[1:0]
Backplane Output Bit Rate
0
Table 52 - Backplane Output Bit Rate Register (BOBRR) Bits
MODE32B
BOBR1
BOBR0
Bit rate for stream n
0
0
0
2 Mbps
0
0
1
4 Mbps
0
1
0
8 Mbps
0
1
1
16 Mbps
1
X
X
32 Mbps
Table 53 - Backplane Output Bit Rate (BOBRR) Programming Table
78
Zarlink Semiconductor Inc.
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14.14
Data Sheet
Memory BIST Register
Address 014DH.
The Memory BIST Register enables the self-test of chip memory. Two consecutive write operations are required to
start MBIST: the first with only Bit 12 (LV_TM) set HIGH (i.e., 1000h); the second with Bit 12 maintained HIGH but
with the required start bit(s) also set HIGH.
The MBISTR register is configured as follows:
Bit
Name
Reset
Value
15:13
Reserved
0
Description
Reserved
Must be set to 0 for normal operation
12
LV_TM
0
MBIST Test Enable
Set HIGH to enable MBIST mode.
Set LOW for normal operation.
11
BISTSDB
0
Backplane Data Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
10
BISTCDB
0
Backplane Data Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Backplane Data
Memory BIST sequence.
9
BISTPDB
0
Backplane Data Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Backplane
Data Memory BIST sequence (indicated by assertion of BISTCDB).
A HIGH indicates Pass, a LOW indicates Fail.
8
BISTSDL
0
Local Data Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
7
BISTCDL
0
Local Data Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Local Data
Memory BIST sequence.
6
BISTPDL
0
Local Data Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Local Data
Memory BIST sequence (indicated by assertion of BISTCDL).
A HIGH indicates Pass, a LOW indicates Fail.
5
BISTSCB
0
Backplane Connection Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
4
BISTCCB
0
Backplane Connection Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Backplane
Connection Memory BIST sequence.
3
BISTPCB
0
Backplane Connection Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Backplane
Connection Memory BIST sequence (indicated by assertion of BISTCCB).
A HIGH indicates Pass, a LOW indicates Fail.
2
BISTSCL
0
Local Connection Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
Table 54 - Memory BIST Register (MBISTR) Bits
79
Zarlink Semiconductor Inc.
ZL50060/1
Bit
Name
Reset
Value
1
BISTCCL
0
Data Sheet
Description
Local Connection Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Local Connection
Memory BIST sequence.
0
BISTPCL
0
Local Connection Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Local
Connection Memory BIST sequence (indicated by assertion of BISTCCL).
A HIGH indicates Pass, a LOW indicates Fail.
Table 54 - Memory BIST Register (MBISTR) Bits (continued)
14.15
Device Identification Register
Address 3FFFH.
The Device Identification Register stores the binary value of the silicon revision number and the Device ID. This
register is read-only. The DIR register is configured as follows:
Bit
Name
Reset Value
15:8
Reserved
0
Description
Reserved
Will read 0 in normal operation
7:4
RC[3:0]
0000
3
Reserved
0
Revision Control Bits
Reserved
Will read 0 in normal operation
2:0
DID[2:0]
000
Device ID
Table 55 - Device Identification Register (DIR) Bits
80
Zarlink Semiconductor Inc.
ZL50060/1
15.0
Data Sheet
DC Electrical Characteristics
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
VDD_CORE
-0.5
2.5
V
1
Core Supply Voltage
2
I/O Supply Voltage
VDD_IO
-0.5
5.0
V
3
PLL Supply Voltage
VDD_PLL
-0.5
2.5
V
4
Input Voltage (non-5 V tolerant inputs)
VI
-0.5
VDD_IO +0.5
V
5
Input Voltage (5 V tolerant inputs)
VI_5V
-0.5
7.0
V
6
Continuous Current at digital outputs
Io
15
mA
7
Package power dissipation
PD
1.5
W
8
Storage temperature
TS
- 55
+125
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
°C
Recommended Operating Conditions
Characteristics
Sym.
Min.
Typ.
Max.
Units
TOP
-40
25
+85
°C
1
Operating Temperature
2
Positive Supply
VDD_IO
3.0
3.3
3.6
V
3
Positive Supply
VDD_CORE
1.71
1.8
1.89
V
4
Positive Supply
VDD_PLL
1.71
1.8
1.89
V
5
Input Voltage
VI
0
VDD_IO
V
0
5.5
V
6
Input Voltage on 5 V Tolerant Inputs
VI_5V
Voltages are with respect to ground (VSS) unless otherwise stated.
81
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
DC Electrical Parameters
Characteristics
1a
Sym.
Min.
Supply Current
IDD_Core
Supply Current
IDD_Core
Supply Current
IDD_IO
Supply Current
IDD_IO
Typ.
Max.
Units
Test Conditions
4
mA
Static IDD_Core and
PLL current
290
mA
Applied clock
C8i = 8.192 MHz
100
µA
Static IDD_IO
18
mA
IAV with all output
streams at max.
data rate unloaded
I
1b
1c
1d
N
P
U
240
14
T
2
Input High Voltage
VIH
Input Low Voltage
VIL
0.8
V
Input Leakage (input pins)
Input Leakage (bi-directional pins)
IIL
IBL
5
5
µA
µA
0 < V < VDD_IO
Note 1
Weak Pullup Current
IPU
200
µA
Input at 0V
5
Weak Pulldown Current
IPD
200
µA
Input at VDD_IO
6
Input Pin Capacitance
CI
5
pF
3
S
4
7
8
9
10
O
U
T
P
U
T
S
Output High Voltage
VOH
Output Low Voltage
VOL
High impedance Leakage
Output Pin Capacitance
2.0
V
2.4
V
IOH = 8mA
0.4
V
IOL = 8mA
IOZ
5
µA
0 < V0 < VDD_IO
Note 1
CO
5
pF
Voltages are with respect to ground (Vss) unless otherwise stated.
Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage (V)
82
Zarlink Semiconductor Inc.
ZL50060/1
16.0
Data Sheet
AC Electrical Characteristics
AC Electrical Characteristics Timing Parameter Measurement: Voltage Levels
Characteristics
Sym.
Level
Units
Conditions
1
CMOS Threshold
VCT
0.5VDD_IO
V
3.0V < VDD_IO < 3.6V
2
Rise/Fall Threshold Voltage High
VHM
0.7VDD_IO
V
3.0V < VDD_IO < 3.6V
3
Rise/Fall Threshold Voltage Low
VLM
0.3VDD_IO
V
3.0V < VDD_IO < 3.6V
Input and Output Clock Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
244
122
350
220
ns
Notes
1
FP8i, Input Frame Pulse Width
tIFPW244
tIFPW122
210
10
2
Input Frame Pulse Setup Time
(before C8i clock falling/rising edge)
tIFPS244
tIfPS122
5
5
110
60
ns
3
Input Frame Pulse Hold Time
(from C8i clock falling/rising edge)
tIFPH244
tIFPH122
0
0
110
60
ns
4
C8i Clock Period (Average value, does not
consider the effects of jitter)
tICP
120
122
124
ns
5
C8i Clock Pulse Width High
tICH
50
61
70
ns
6
C8i Clock Pulse Width Low
tICL
50
61
70
ns
7
C8i Clock Rise/Fall Time
trIC, tfIC
0
2
3
ns
8
C8i Cycle to Cycle Variation
(This values is with respect to the typical C8i
Clock Period, and using mid-bit sampling)
tCCVIC
-7.0
7.0
ns
32Mbps
-8.5
8.5
ns
16Mbps
or lower.
9
Output Frame Boundary Offset
tOFBOS
7
9.5
ns
10
FP8o Frame Pulse Width
tOFPW8_244
tOFPW8_122
224
117
244
122
264
127
ns
FPW =1
FPW=0
CL=60pF
11
FP8o Output Delay
(from frame pulse edge to output frame
boundary)
tFPFBF8_244
tFPFBF8_122
117
58
122
61
127
64
ns
FPW =1
FPW=0
CL=60pF
12
FP8o Output Delay
(from output frame boundary to frame pulse
edge)
tFBFPF8_244
tFBFPF8_122
117
58
122
61
127
64
ns
FPW =1
FPW=0
CL=60pF
13
C8o Clock Period
tOCP8
117
122
127
ns
14
C8o Clock Pulse Width High
tOCH8
58
61
64
ns
15
C8o Clock Pulse Width Low
tOCL8
58
61
64
ns
16
C8o Clock Rise/Fall Time
trOC8, tfOC8
3
7
ns
83
Zarlink Semiconductor Inc.
CL=60pF
ZL50060/1
Data Sheet
Input and Output Clock Timing (continued)
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
17
FP16o Frame Pulse Width
tOFPW16_122
tOFPW16_61
117
58
122
61
127
64
ns
FPW =1
FPW=0
CL=60pF
18
FP16o Output Delay
(from frame pulse edge to output frame
boundary)
tFPFBF16_122
tFPFBF16_61
58
29
61
31
64
33
ns
FPW =1
FPW=0
19
FP16o Output Delay
(from output frame boundary to frame pulse
edge)
tFBFPF16_122
tFBFPF16_61
58
29
61
31
64
33
ns
FPW =1
FPW=0
20
C16o Clock Period
tOCP16
58
61
64
ns
21
C16o Clock Pulse Width High
tOCH16
29
31
33
ns
22
C16o Clock Pulse Width Low
tOCL16
29
31
33
ns
23
C16o Clock Rise/Fall Time
trOC16,
tfOC16
3
7
ns
84
Zarlink Semiconductor Inc.
CL=60pF
ZL50060/1
Data Sheet
tIFPW244
FP8i
(244ns)
tIFPS244
tIFPH244
tIFPW122
FP8i
(122ns)
tIFPS122
tICL
tIFPH122
tICP
tICH
C8i
trIC
tfIC
CK_int *
tOFBOS
tOFPW8_244
FP8o
(244ns)
tFPFBF8_244
tFBFPF8_244
tOFPW8_122
FP8o
(122ns)
tFBFPF8_122
tFPFBF8_122
tOCL8
tOCP8
tOCH8
C8o
trOC8
tfOC8
tOFPW16_122
FP16o
(122ns)
tFPFBF16_122
tFBFPF16_122
tOFPW16_61
FP16o
(61ns)
tFPFB16_61
tOCL16
tFBFP16_61
tOCH16
tOCP16
C16o
trOC16
tfOC16
Note *: CK_int is the internal clock signal of 131.072MHz
Note **: Although the figures above show the frame boundary as measured from the falling edge of C8i/C8o/C16o, the
frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the
Control Register.
Figure 25 - Input and Output Clock Timing Diagram for ST-BUS
85
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
tIFPW244
FP8i
(244ns)
tIFPS244
tIFPH244
tIFPW122
FP8i
(122ns)
tIFPS122
tICL
tIFPH122
tICP
tICH
C8i
trIC
tfIC
CK_int *
tOFBOS
tOFPW8_244
FP8o
(244ns)
tFPFBF8_244
tFBFPF8_244
tOFPW8_122
FP8o
(122ns)
tFBFPF8_122
tFPFBF8_122
C8o
tOCL8
tOCP8
tOCH8
trOC8
tfOC8
tOFPW16_122
FP16o
(122ns)
tFPFBF16_122
tFBFPF16_122
tOFPW16_61
FP16o
(61ns)
tFPFB16_61
tOCH16
tFBFP16_61
tOCL16
tOCP16
C16o
tfOC16
trOC16
Note *: CK_int is the internal clock signal of 131.072MHz
Note **: Although the figures above show the frame boundary as measured from the rising edge of C8i/C8o/C16o, the
frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the
Control Register.
Figure 26 - Input and Output Clock Timing Diagram for GCI-Bus
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Data Sheet
Local and Backplane Data Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
Local/Backplane Input Data Sampling Point
tIDS32
tIDS16
tIDS8
tIDS4
tIDS2
20
43
87
178
357
23
46
92
183
366
26
49
97
188
375
ns
With
SMPL_MODE =
0 (3/4-bit
sampling) and
zero offset.
2
Local/Backplane Serial Input Set-up Time
tSIS32
tSIS16
tSIS8
tSIS4
tSIS2
2
2
2
2
2
ns
With respect to
Min. Input Data
Sampling Point
3
Local/Backplane Serial Input Hold Time
tSIH32
tSIH16
tSIH8
tSIH4
tSIH2
2
2
2
2
2
ns
With respect to
Max. Input Data
Sampling Point
4
Output Frame Boundary Offset
tOFBOS
5
Local/Backplane Serial Output Delay
tSOD32
tSOD16
tSOD8
tSOD4
tSOD2
87
Zarlink Semiconductor Inc.
7
9.5
ns
4.5
4.5
4.5
4.5
4.5
ns
CL=50pF
These numbers
are referencing
output frame
boundary.
ZL50060/1
Data Sheet
FP8i
C8i
CK_int *
tIDS8
tSIS8
tSIH8
L/BSTi0-31
8.192Mbps
0
1
7
6
tIDS4
4
5
2
3
1
tSIS4
tSIH4
L/BSTi0-31
4.096Mbps
Bit7
Ch0
Bit0
Ch63
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
tIDS2
tSIS2
tSIH2
L/BSTi0-31
2.048Mbps
Bit0
Ch31
Bit6
Ch0
Bit7
Ch0
tOFBOS
FP8o
C8o
CK_int *
tSOD8
L/BSTo0-31
8.192Mbps
Bit1
Ch127
Bit0
Ch127
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
Bit2
Ch0
Bit3
Ch0
Bit1
Ch0
tSOD4
L/BSTo0-31
4.096Mbps
Bit0
Ch63
Bit6
Ch0
Bit7
Ch0
Bit5
Ch0
Bit4
Ch0
tSOD2
L/BSTo0-31
2.048Mbps
Bit0
Ch31
Bit7
Ch0
Bit6
Ch0
Note *: CK_int is the internal clock signal of 131.072MHz
Figure 27 - ST-BUS Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps)
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ZL50060/1
Data Sheet
FP8i
C8i
CK_int *
tIDS32
tSIS32
tSIH32
L/BSTi0-15
32.768Mbps
2
6
7
0
1
tIDS16
4
5
2
3
tSIS16
tSIH16
L/BSTi0-31
16.384Mbps
Bit7
Ch0
Bit0
Ch255
Bit1
Ch255
Bit6
Ch0
Bit5
Ch0
tOFBOS
FP8o
C8o
CK_int *
tSOD32
L/BSTo0-15
32.768Mbps
Bit1
Ch511
Bit1
Ch511
Bit7
Ch0
Bit0
Ch511
Bit6
Ch0
Bit5
Ch0
Bit4
Ch0
Bit2
Ch0
Bit3
Ch0
tSOD16
L/BSTo0-31
16.384Mbps
Bit0
Ch255
Bit7
Ch0
Bit6
Ch0
Bit5
Ch0
Note *: CK_int is the internal clock signal of 131.072MHz
Figure 28 - ST-BUS Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps)
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Zarlink Semiconductor Inc.
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Data Sheet
FP8i
C8i
CK_int *
tIDS8
tSIS8
tSIH8
L/BSTi0-31
8.192Mbps
7
6
1
0
tIDS4
3
2
5
4
6
tSIS4
tSIH4
L/BSTi0-31
4.096Mbps
Bit0
Ch0
Bit7
Ch63
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
tIDS2
tSIS2
tSIH2
Bit7
Ch31
L/BSTi0-31
2.048Mbps
Bit1
Ch0
Bit0
Ch0
tOFBOS
FP8o
C8o
CK_int *
tSOD8
L/BSTo0-31
8.192Mbps
Bit6
Ch127
Bit7
Ch127
Bit0
Ch0
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
Bit5
Ch0
Bit4
Ch0
Bit6
Ch0
tSOD4
Bit7
Ch63
L/BSTo0-31
4.096Mbps
Bit1
Ch0
Bit0
Ch0
Bit2
Ch0
Bit3
Ch0
tSOD2
L/BSTo0-31
2.048Mbps
Bit7
Ch31
Bit0
Ch0
Bit1
Ch0
Note *: CK_int is the internal clock signal of 131.072MHz
Figure 29 - GCI-Bus Local/Backplane Data Timing Diagram (8 Mbps, 4 Mbps, 2 Mbps)
90
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
FP8i
C8i
CK_int *
tIDS32
tSIS32
tSIH32
L/BSTi0-15
32.768Mbps
2
7
0
1
6
tIDS16
4
5
2
3
tSIS16
tSIH16
L/BSTi0-31
16.384Mbps
Bit6
Ch255
Bit0
Ch0
Bit7
Ch255
Bit1
Ch0
Bit2
Ch0
tOFBOS
FP8o
C8o
CK_int *
tSOD32
L/BSTo0-15
32.768Mbps
Bit5
Ch511
Bit6
Ch511
Bit0
Ch0
Bit7
Ch511
Bit1
Ch0
Bit2
Ch0
Bit3
Ch0
Bit5
Ch0
Bit4
Ch0
tSOD16
L/BSTo0-31
16.384Mbps
Bit7
Ch255
Bit0
Ch0
Bit1
Ch0
Bit2
Ch0
Note *: CK_int is the internal clock signal of 131.072MHz
Figure 30 - GCI-Bus Local/Backplane Data Timing Diagram (32 Mbps, 16 Mbps)
91
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Local and Backplane Output High Impedance Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
4
4
6
6
ns
ns
RL=1k, CL=50pF, See Note 1
1
STo delay - Active to High-Z
- High-Z to Active
tDZ
tZD
2
Output Driver Enable (ODE)
Delay to Active Data
Output Driver Enable (ODE)
Delay to high impedance
tODE
14
ns
RL=1k, CL=50pF, See Note 1
tODZ
14
ns
RL=1k, CL=50pF, See Note 1
Note 1: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
VTT
CLK
tDZ
STo
Valid Data
HiZ
VTT
Valid Data
VTT
tZD
HiZ
STo
Figure 31 - Serial Output and External Control
VTT
ODE
tODE
STo
Hi-Z
tODZ
Valid Data
Hi-Z
VTT
Figure 32 - Output Driver Enable (ODE)
92
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Input Clock Jitter Tolerance
Jitter Frequency
16.384 Mbps Data Rate
Jitter Tolerance
32.768 Mbps Data Rate
Jitter Tolerance
Units
1
1 kHz
1200
600
ns
2
10 kHz
1200
600
ns
3
50 kHz
150
80
ns
4
66 kHz
110
50
ns
5
83 kHz
80
35
ns
6
95 kHz
70
30
ns
7
100 kHz
25
20
ns
8
200 kHz
17
14
ns
9
300 kHz
17
14
ns
10
400 kHz
17
14
ns
11
500 kHz
17
14
ns
12
1 MHz
17
14
ns
13
2 MHz
17
14
ns
14
4 MHz
17
14
ns
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Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
Non-Multiplexed Microprocessor Port Timing
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
CS setup from DS falling
tCSS
0
ns
2
R/W setup from DS falling
tRWS
9
ns
3
Address setup from DS falling
tADS
9
ns
4
CS hold after DS rising
tCSH
0
ns
5
R/W hold after DS rising
tRWH
9
ns
6
Address hold after DS rising
tADH
9
ns
7
Data setup from DTA Low on Read
tRDS
5
12
ns
ns
Memory Read
Register Read
CL=60pF
8
Data hold on read
tRDH
ns
CL=60pF, RL=1k
Note 1
9
Data setup on write
tWDS
9
ns
10
Data hold on write
tWDH
9
ns
11
Acknowledgment Delay:
Reading/Writing Registers
Reading/Writing Memory
tAKD
Acknowledgment Hold Time
tAKH
12
4.5
88
80
ns
ns
CL=60pF
CL=60pF
11
ns
CL=60pF, RL=1k,
Note 1
Note 1:
High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge
CL.
Note 2:
There must be a minimum of 30 ns between CPU accesses, to allow the device to recognize the accesses as separate (i.e., a
minimum of 30 ns must separate the de-assertion of DTA (to high) and the assertion of CS and/or DS to initiate the next
access).
94
Zarlink Semiconductor Inc.
ZL50060/1
Data Sheet
DS
VTT
tCSH
tCSS
VTT
CS
tRWH
tRWS
VTT
R/W
tADS
tADH
VTT
VALID ADDRESS
A0-A14
tRDH
VTT
VALID READ DATA
D0-D15
READ
tWDH
tWDS
D0-D15
WRITE
VTT
VALID WRITE DATA
tRDS
VTT
DTA
tAKD
Figure 33 - Motorola Non-Multiplexed Bus Timing
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Zarlink Semiconductor Inc.
tAKH
ZL50060/1
Data Sheet
AC Electrical Characteristics† - JTAG Test Port Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
1
TCK Clock Period
tTCKP
100
ns
2
TCK Clock Pulse Width High
tTCKH
80
ns
3
TCK Clock Pulse Width Low
tTCKL
80
ns
4
TMS Set-up Time
tTMSS
10
ns
5
TMS Hold Time
tTMSH
10
ns
6
TDi Input Set-up Time
tTDIS
20
ns
7
TDi Input Hold Time
tTDIH
60
ns
8
TDo Output Delay
tTDOD
9
TRST pulse width
tTRSTW
30
ns
200
ns
†Characteristics are over recommended operating conditions unless otherwise stated.
tTCKL
tTCKH
tTCKP
TCK
tTMSS
tTMSH
TMS
tTDIS
tTDIH
TDi
tTDOD
TDo
tTRSTW
TRST
Figure 34 - JTAG Test Port Timing Diagram
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Zarlink Semiconductor Inc.
Notes
CL=30pF
b
Package Code
c Zarlink Semiconductor 2003 All rights reserved.
ISSUE
1
ACN
214440
DATE
26June03
APPRD.
Previous package codes
Package Code
c Zarlink Semiconductor 2003 All rights reserved.
ISSUE
ACN
DATE
APPRD.
Previous package codes:
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