ZARLINK ZL38010

ZL38010
Low Power Quad ADPCM Transcoder
Data Sheet
Features
January 2007
•
Full duplex transcoder with four encode channels
and four decode channels
•
32 kbps, 24 kbps and 16 kbps ADPCM coding
complying with ITU-T (previously CCITT) G.726
(without 40 kbps), and ANSI T1.303-1989
•
Low power operation, 6.5 mW typical
•
Asynchronous 4.096 MHz master clock operation
•
SSI and ST-BUS interface options
•
Transparent PCM bypass
•
Transparent ADPCM bypass
•
Linear PCM code
•
No microprocessor control required
•
Simple interface to Codec devices
•
Pin selectable µ−Law or A-Law operation
•
Pin selectable ITU-T or signed magnitude PCM
coding
•
Single 3.3 Volts power supply
ADPCMi
Ordering Information
ZL38010DCE
28 Pin SOIC
ZL38010DCF
28 Pin SOIC
ZL38010DCE1 28 Pin SOIC**
ZL38010DCF1 28 Pin SOIC**
**Pb Free Matte Tin
-40°C to +85°C
Applications
•
Pair gain
•
Voice mail systems
•
Wireless telephony systems
Description
ADPCM
I/O
ADPCMo
The Quad ADPCM Transcoder is a low power, CMOS
device capable of four encode and four decode
functions per frame. Four 64 kbps PCM octets are
compressed into four 32, 24 or 16 kbps ADPCM words,
and four 32, 24 or 16 kbps ADPCM words are
expanded into four 64 kbps PCM octets. The 32, 24
and 16 kbps ADPCM transcoding algorithms utilized
conform to ITU-T Recommendation G.726 (excluding
40 kbps), and ANSI T1.303 - 1989.
Full Duplex
Quad
Transcoder
PCM
I/O
BCLK
F0i
C2o
PCMo1
PCMi1
PCMo2
PCMi2
ENB1
ENB2/F0od
MCLK
Tubes
Tape & Reel
Tubes
Tape & Reel
Timing
Control Decode
EN1
EN2
VDD VSS PWRDN IC
MS1 MS2 MS3 A/µ FORMAT MS4 MS5 MS6 LINEAR SEL
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2005-2007, Zarlink Semiconductor Inc. All Rights Reserved.
ZL38010
Data Sheet
Switching, on-the-fly, between 32 kbps and 24 kbps ADPCM, is possible by controlling the appropriate mode select
(MS1 - MS6) control pins. All optional functions of the device are pin selectable allowing a simple interface to
industry standard codecs, digital phone devices and Layer 1 transceivers. Linear coded PCM is provided to
facilitate external DSP functions.
Change Summary
Changes from October 2005 Issue to January 2007 Issue.
Page
Item
Change
1
Ordering Information Box
Added Pb Free part numbers.
EN1
MCLK
F0i
C2o
BCLK
PCMo1
PCMi1
VSS
LINEAR
ENB2/F0od
ENB1
PCMo2
PCMi2
SEL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
EN2
MS6
MS5
MS4
ADPCMo
ADPCMi
VDD
MS3
MS2
MS1
IC
PWRDN
FORMAT
A/µ
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
EN1
Enable Strobe 1 (Output). This 8 bit wide, active high strobe is active during the B1
PCM channel in ST-BUS mode. Becomes a single bit, high true pulse when LINEAR=1.
In SSI mode this output is high impedance.
2
MCLK
Master Clock (input). This is a 4.096 MHz (minimum) input clock utilized by the
transcoder function; it must be supplied in both ST-BUS and SSI modes of operation.
In ST-BUS mode the C4 ST-BUS clock is applied to this pin. This synchronous clock is
also used to control the data I/O flow on the PCM and ADPCM input/output pins
according to ST-BUS requirements.
In SSI mode this master clock input is derived from an external source and may be
asynchronous with respect to the 8 kHz frame. MCLK rates greater than 4.096 MHz are
acceptable in this mode since the data I/O rate is governed by BCLK.
3
F0i
Frame Pulse (Input). Frame synchronization pulse input for ST-BUS operation. SSI
operation is enabled by connecting this pin to VSS.
4
C2o
2.048 MHz Clock (Output). This ST-BUS mode bit clock output is the MCLK (C4) input
divided by two, inverted, and synchronized to F0i. This output is high-impedance during
SSI operation.
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Zarlink Semiconductor Inc.
ZL38010
Data Sheet
Pin #
Name
Description
5
BCLK
Bit Clock (Input). 128 kHz to 4096 kHz bit clock input for both PCM and ADPCM ports;
used in SSI mode only. The falling edge of this clock latches data into ADPCMi, PCMi1
and PCMi2. The rising edge clocks data out on ADPCMo, PCMo1 and PCMo2. This input
must be tied to VSS for ST-BUS operation.
6
PCMo1
Serial PCM Stream 1 (Output). 128 kbps to 4096 kbps serial companded/linear PCM output stream. Data are clocked out by rising edge of BCLK in SSI mode. Clocked out by
MCLK divided by two in ST-BUS mode. See Figure 14.
7
PCMi1
Serial PCM Stream 1 (Input). 128 kbps to 4096 kbps serial companded/linear PCM
input stream. Data are clocked in on falling edge of BCLK in SSI mode. Clocked in at the
3/4 bit position of MCLK in ST-BUS mode. See Figure 14.
8
VSS
9
LINEAR
10
ENB2/F0od
Digital Ground. Nominally 0 volts
Linear PCM Select (Input). When tied to VDD the PCM I/O ports (PCM1,PCM2) are 16bit linear PCM. Linear PCM operates only at a bit rate of 2048 kbps. Companded PCM is
selected when this pin is tied to VSS. See Figure 5 & Figure 8.
PCM B-Channel Enable Strobe 2 (Input) / Delayed Frame Pulse (Output).
SSI operation: ENB2 (Input). An 8-bit wide enable strobe input defining B2 channel
(AD)PCM data. A valid 8-bit strobe must be present at this input for SSI operation. See
Figure 4 & Figure 6.
ST-BUS operation: F0od (Output). This pin is a delayed frame strobe output. When LINEAR=0, this becomes a delayed frame pulse output occurring 64 C4 clock cycles after
F0i and when LINEAR = 1 at 128 C4 clock cycles after F0i. See Figures 7, 8, 9 & 14.
11
ENB1
PCM B-Channel Enable Strobe 1 (Input).
SSI operation: An 8-bit wide enable strobe input defining B1 channel (AD)PCM data. A
valid 8-bit strobe must be present at this input for SSI operation.
ST-BUS operation: When tied to VSS transparent bypass of the ST-BUS D- and C- channels is enabled. When tied to VDD the ST-BUS D-channel and C-channel output timeslots
are forced to a high-impedance state.
12
PCMo2
Serial PCM Stream 2 (Output). 128 kbps to 4096 kbps serial companded/linear PCM output stream. Clocked out by rising edge of BCLK in SSI mode. Clocked out by MCLK divided by two in ST-BUS mode. See Figure 14.
13
PCMi2
Serial PCM Stream 2 (Input). 128 kbps to 4096 kbps serial companded/linear PCM input
stream. Data bits are clocked in on falling edge of BCLK in SSI mode. Clocked in at the
3/4 bit position of MCLK in ST-BUS mode. See Figure 14.
14
SEL
SELECT (Input).
PCM bypass mode: When SEL=0 the PCM1 port is selected for PCM bypass operation
and when SEL=1 the PCM2 port is selected for PCM bypass operation.
See Figure 6 & Figure 9.
16 kbps transcoding mode:
SSI Operation - in 16 kbps transcoding mode, the ADPCM words are assigned to the I/O
timeslot defined by ENB2 when SEL=1 and by ENB1 when SEL=0. See Figure 4.
ST-BUS operation- in 16 kbps transcoding mode, the ADPCM words are assigned to the
B2 timeslot when SEL=1 and to the B1 timeslot when SEL=0. See Figure 9.
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Zarlink Semiconductor Inc.
ZL38010
Data Sheet
Pin #
Name
Description
15
A/µ
16
FORMAT
FORMAT Select (Input). Selects ITU-T PCM coding when high and Sign-Magnitude
PCM coding when low. This control is for all channels.This input is ignored in Linear
mode during which it may be tied to VSS or VDD.
17
PWRDN
Power-down (Input). An active low reset forcing the device into a low power mode
where all outputs are high-impedance and device operation is halted.
18
IC
19
20
21
MS1
MS2
MS3
Mode Selects 1, 2 and 3 (Inputs). Mode selects for all four encoders.
MODE
MS3 MS2 MS1
0
0
0
32 kbps ADPCM
0
0
1
24 kbps ADPCM
0
1
0
16 kbps ADPCM in EN1/ENB1 when SEL=0
in EN2/ENB2 when SEL=1
0
1
1
ADPCM Bypass for 32 kbps and 24 kbps
1
0
0
ADPCM Bypass for 16 kbps
1
0
1
PCM Bypass (64 kbps) to PCM1 if SEL=0, PCM2 if SEL=1
1
1
0
Algorithm reset (ITU-T optional reset)
1
1
1
ADPCMo disable
22
VDD
Positive Power Supply. Nominally 3.3 Volts +/-10%
23
ADPCMi
Serial ADPCM Stream (Input). 128 kbps to 4096 kbps serial ADPCM word input stream.
Data bits are clocked in on falling edge of BCLK in SSI mode and clocked in on the 3/4 bit
edge of MCLK in ST-BUS mode.
24
ADPCMo
Serial ADPCM Stream (Output). 128 kbps to 4096 kbps serial ADPCM word output
stream. Data bits are clocked out by rising edge of BCLK in SSI mode and clocked out by
MCLK divided by two in ST-BUS mode.
25
26
27
MS4
MS5
MS6
Mode Selects 4, 5 and 6 (Inputs). Mode selects for all four decoders.
MODE
MS6 MS5 MS4
0
0
0
32 kbps ADPCM
0
0
1
24 kbps ADPCM
0
1
0
16 kbps ADPCM in EN1/ENB1 when SEL=0
in EN2/ENB2 when SEL=1
0
1
1
ADPCM Bypass for 32 kbps and 24 kbps
1
0
0
ADPCM Bypass for 16 kbps
1
0
1
PCM Bypass (64 kbps) to PCM1 if SEL=0, PCM2 if SEL=1
1
1
0
Algorithm reset (ITU-T optional reset)
1
1
1
PCMo1/2 disable
28
EN2
Enable Strobe 2 (Output). This 8 bit wide, active high strobe is active during the B2
PCM channel in ST-BUS mode. Forced to high impedance when LINEAR=1.
A-Law/µ−Law Select (Input). This input pin selects µ−Law companding when set to
logic 0, and A-Law companding when set to logic 1. This control is for all channels.This
input is ignored in Linear mode during which it may be tied to VSS or VDD.
Internal Connection (Input). Tie to VSS for normal operation.
Note:
All unused inputs should be connected to logic low or high unless otherwise stated. All outputs should be left open circuit when not used.
All inputs have TTL compatible logic levels except for MCLK which has CMOS compatible logic levels and PWRDN which has Schmitt trigger
compatible logic levels.
All outputs are CMOS with CMOS logic levels (See DC Electrical Characteristics).
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Zarlink Semiconductor Inc.
ZL38010
Data Sheet
Functional Description
The Quad-channel ADPCM Transcoder is a low power, CMOS device capable of four encode and four decode
operations per frame. Four 64 kbps channels (PCM octets) are compressed into four 32, 24 or 16 kbps ADPCM
channels (ADPCM words), and four 32, 24 or 16 kbps ADPCM channels (ADPCM words) are expanded into four
64 kbps PCM channels (PCM octets). The ADPCM transcoding algorithm utilized conforms to ITU-T
recommendation G.726 (excluding 40 kbps), and ANSI T1.303 - 1989. Switching on-the-fly between 32 and
24 kbps transcoding is possible by toggling the appropriate mode select pins (supports T1 robbed-bit signalling).
All functions supported by the device are pin selectable. The four encode functions comprise a common group
controlled via Mode Select pins MS1, MS2 and MS3. Similarly, the four decode functions form a second group
commonly controlled via Mode Select pins MS4, MS5 and MS6. All other pin controls are common to the entire
transcoder.
The device requires 6.5 mWatts (MCLK= 4.096 MHz) typically for four channel transcode operation. A minimum
master clock frequency of 4.096 MHz is required for the circuit to complete four encode channels and four decode
channels per frame. For SSI operation a master clock frequency greater than 4.096 MHz and asynchronous,
relative to the 8 kHz frame, is allowed.
The PCM and ADPCM serial busses support both ST-BUS and Synchronous Serial Interface (SSI) operation. This
allows serial data clock rates from 128 kHz to 4096 kHz, as well as compatibility with Zarlink’s standard Serial
Telecom BUS (ST-BUS). For ST-BUS operation, on chip channel counters provide channel enable outputs as well
as a 2048 kHz bit clock output which may be used by down-stream devices utilizing the SSI bus interface.
Linear coded PCM is also supported. In this mode the encoders compress, four 14-bit, two’s complement
(S,S,S,12,...,1,0), uniform PCM channels into four 4, 3 or 2 bit ADPCM channels. Similarly, the decoder expands
four 4, 3 or 2 bit ADPCM channels into four 16-bit, two’s complement (S,14,...,1,0), uniform PCM channels. The
data rate for both ST-BUS and SSI operation in this mode is 2048 kbps.
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Zarlink Semiconductor Inc.
ZL38010
Data Sheet
Serial (AD)PCM Data I/O
Serial data transfer to/from the Quad ADPCM transcoder is provided through one ADPCM and two PCM ports
(ADPCMi, ADPCMo, PCMi1, PCMo1, PCMi2, PCMo2). Data is transferred through these ports according to either
ST-BUS or SSI requirements. The device determines the mode of operation by monitoring the signal applied to the
F0i pin. When a valid ST-BUS frame pulse (244nSec low going pulse) is applied to the F0i pin the transcoder will
assume ST-BUS operation. If F0i is tied continuously to VSS the transcoder will assume SSI operation. Pin
functionality in each of these modes is described in the following sub-sections.
ST-BUS Mode
During ST-BUS operation the C2o, EN1, EN2 and F0od outputs become active and all serial timing is derived from
the MCLK (C4) and F0i inputs while the BCLK input is tied to VSS. (See Figures 7, 8 & 9.)
Basic Rate “D” and “C” Channels
In ST-BUS mode, when ENB1 is brought low, transparent transport of the ST-BUS "Basic Rate D- and C-channels"
is supported through the PCMi1 and PCMo1 pins. This allows a microprocessor controlled device, connected to the
PCMi/o1 pins, to access the "D" and "C" channels of a transmission device connected to the ADPCMi/o pins. When
ENB1 is brought high, the “D” and “C” channel outputs are tristated. Basic Rate “D” and “C” channels are not
supported in LINEAR mode.(See Figure 7.)
SSI Mode
During SSI operation the BCLK, ENB1 and ENB2/F0od inputs become active. The C2o, EN1, and EN2 outputs are
forced to a high-impedance state except during LINEAR operation during which the EN1 output remains active.
(See Figures 4, 5 & 6.)
The SSI port is a serial data interface, including data input and data output pins, a variable rate bit clock input and
two input strobes providing enables for data transfers. There are three SSI I/O ports on the Quad ADPCM; the
PCMi/o1 PCM port, the PCMi/o2 PCM port, and the ADPCMi/o port. The two PCM ports may transport 8-bit
companded PCM or 16-bit linear PCM. The alignment of the channels is determined by the two input strobe signals
ENB1 and ENB2/F0od. The bit clock (BCLK) and input strobes (ENB1 and ENB2/F0od) are common for all three of
the serial I/O ports. BCLK can be any frequency between 128 kHz and 4096 kHz synchronized to the input strobes.
BCLK may be discontinuous outside of the strobe boundaries except when LINEAR=1. In LINEAR mode, BCLK
must be 2048 kHz and continuous for 64 cycles after the ENB1 rising edge and for the duration of ENB2/F0od.
Mode Select Operation (MS1, MS2, MS3, MS4, MS5, MS6)
Mode Select pins MS1, MS2 and MS3 program different bit rate ADPCM coding, bypass, algorithmic reset and
disable modes for all four encoder functions simultaneously. When 24 kbps ADPCM mode is selected bit 4 is
unused while in 16 kbps ADPCM mode all ADPCM channels are packed contiguously into one 8-bit octet. Mode
Select pins MS4, MS5 and MS6 operate in the same manner for the four decode functions. The mode selects must
be set up according to the timing constraints illustrated in Figures 16 and 17.
32 kbps ADPCM Mode
In 32 kbps ADPCM mode, the 8-bit PCM octets of the B1, B2, B3 and B4 channels (PCMi1 and PCMi2) are
compressed into four 4-bit ADPCM words on ADPCMo. Conversely, the 4-bit ADPCM words of the B1, B2, B3 and
B4 channels from ADPCMi are expanded into four 8-bit PCM octets on PCMo1 and PCMo2. The 8-bit PCM octets
(A-Law or µ-Law) are transferred most significant bit first starting with b7 and ending with b0. ADPCM words are
transferred most significant bit first starting with I1 and ending with I4 (See Figures 4 & 7). Reference ITU-T G.726
for I-bit definitions.
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Zarlink Semiconductor Inc.
ZL38010
Data Sheet
24 kbps ADPCM Mode
In 24 kbps mode PCM octets are transcoded into 3-bit words rather than the 4-bit words utilized in 32 kbps
ADPCM. This is useful in situations where lower bandwidth transmission is required. Dynamic operation of the
mode select control pins will allow switching from 32 kbps mode to 24 kbps mode on a frame by frame basis. The 8
bit PCM octets (A-Law or µ-Law) are transferred most significant bit first starting with b7 and ending with b0.
ADPCM words are transferred most significant bit first starting with I1 and ending with I3 (I4 becomes don’t care).
(See Figures 4 & 7.)
16 kbps ADPCM Mode
When SEL is set to 0, the 8-bit PCM octets of the B1, B2, B3 and B4 channels (PCMi1 and PCMi2) are compressed
into four 2-bit ADPCM words on ADPCMo during the ENB1 timeslot in SSI mode and during the B1 timeslot in STBUS mode. Similarly, the four 2-bit ADPCM words on ADPCMi are expanded into four 8-bit PCM octets (on PCMo1
and PCMo2) during the ENB1/B1 timeslot. (See Figures 4 & 7.)
When SEL is set to 1, The same conversion takes place as described when SEL = 0 except that the ENB2/B2
timeslots are utilized.
A-Law or µ-Law 8-bit PCM are received and transmitted most significant bit first starting with b7 and ending with b0.
ADPCM data are most significant bit first starting with I1 and ending with I2.
ADPCM BYPASS (32 and 24 kbps)
In ADPCM bypass mode the B1 and B2 channel ADPCM words are bypassed (with a two-frame delay) to/from the
ADPCM port and placed into the most significant nibbles of the PCM1/2 port octets. Note that the SEL pin performs
no function for these two modes (See Figures 6 & 9). LINEAR, FORMAT and A/µ pins are ignored in bypass mode.
In 32 kbps ADPCM bypass mode, Bits 1 to 4 of the B1, B2, B3 and B4 channels from PCMi1 and PCMi2 are
transparently passed, with a two frame delay, to the same channels on ADPCMo. In the same manner, the B1, B2,
B3 and B4 channels from ADPCMi are transparently passed, with a two frame delay, to the same channels on
PCMo1 and PCMo2 pins. Bits 5 to 8 are don’t care. This feature allows two voice terminals, which utilize ADPCM
transcoding, to communicate through a system without incurring unnecessary transcode conversions. This
arrangement allows byte-wide or nibble-wide transport through a switching matrix.
24 kbps ADPCM bypass mode is the same as 32 kbps mode bypass excepting that only bits 1 to 3 are bypassed
and bits 4 to 8 are don’t care.
ADPCM BYPASS (16 kbps)
When SEL is set to 0, only bits 1 and 2 of the B1, B2, B3 and B4 PCM octets (on PCMi1 and PCMi2) are bypassed,
with a two frame delay, to the same channels on ADPCMo during the ENB1 timeslot in SSI mode and during the B1
timeslot in ST-BUS mode. Similarly, the four 2-bit ADPCM words on ADPCMi are transparently bypassed, with a
two frame delay, to PCMo1 and PCMo2 during the ENB1 or B1 timeslot. Bits 3-8 are don’t care. (See Figures 6 &
9.)
When SEL is set to 1, the same bypass occurs as described when SEL = 0 except that the ENB2 or B2 timeslots
are utilized.
LINEAR, FORMAT and A/µ pins are ignored in bypass mode.
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Zarlink Semiconductor Inc.
ZL38010
Data Sheet
PCM BYPASS
When SEL is set to 0, the B1 and B2 PCM channels on PCMi1 are transparently passed, with a two-frame delay, to
the same channels on the ADPCMo. Summarily, the two 8-bit words which are on ADPCMi are transparently
passed, with a two-frame delay, to channels B1 and B2 of PCMo1 while PCMo2 is set to a high-impedance
state.(See Figures 6 & 9.)
When SEL is set to 1, the B3 and B4 channels on PCMi2 are transparently passed, with a two frame delay, to the
same channels on ADPCMo. Similarly, the two 8-bit words which are on ADPCMi are transparently passed, with a
two-frame delay, to channels B3 and B4 of PCMo2. In this case PCMo1 is always high-impedance if ENB1 = 0. If
ENB1 = 1 during ST-BUS operation then the D and C channels are active on PCMo1.
LINEAR, FORMAT and A/µ pins are ignored in bypass mode.
Algorithm Reset Mode
While an algorithmic reset is asserted the device will incrementally converge its internal variables to the 'Optional
reset values' stated in G.726. Algorithmic reset requires that the master clock (MCLK) and frame pulse (ENB1/2 or
F0i) remain active and that the reset condition be valid for at least four frames. Note that this is not a power down
mode; see PWRDN for this function.
ADPCMo & PCMo1/2 Disable
When the encoders are programmed for ADPCMo disable (MS1 to MS3 set to 1) the ADPCMo output is set to a
high impedance state and the internal encode function remains active. Therefore convergence is maintained. The
decode processing function and data I/O remain active.
When the decoders are programmed for PCMo1/2 disable (MS4 to MS6 set to 1) the PCMo1/2 outputs are high
impedance during the B Channel timeslots and also, during ST-BUS operation, the D and C channel timeslots
according to the state of ENB1. Therefore convergence is maintained. The encode processing function and data
I/O remain active.
Whenever any combination of the encoders or decoders are set to the disable mode the following outputs remain
active. A) ST-BUS mode: ENB2/F0od, EN1, EN2 and C2o. Also the “D” and “C” channels from PCMo1 and
ADPCMo remain active if ENB1 is set to 0. If ENB1 is brought high then PCMo1 and ADPCMo are fully tri-stated. B)
SSI mode: When used in the 16-bit linear mode, only the EN1 output remains active. For complete chip power
down see PWRDN.
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Zarlink Semiconductor Inc.
ZL38010
Data Sheet
Other Pin Controls
16 Bit Linear PCM
Setting the LINEAR pin to logic one causes the device to change to 16-bit linear (uniform) PCM transmission on the
PCMi/o1 and PCMi/o2 ports. The data rate for both ST-BUS and SSI operation in this mode is 2048 kbps and all
decode and encode functions are affected by this pin. In SSI mode, the input channel strobes ENB1 and
ENB2/F0od remain active for 8 cycles of BCLK for an ADPCM transfer. The EN1 output is high for one BCLK period
at the end of the frame (i.e., during the 256th BCLK period). In ST-BUS mode, the output strobes EN1 and
ENB2/F0od are adjusted to accommodate the required PCM I/O streams. The EN1 output becomes a single bit
high true pulse during the last clock period of the frame (i.e., the 256th bit period) while ENB2/F0od becomes a
delayed, low true frame-pulse (F0od) output occurring during the 64th bit period after the EN1 rising edge.
Linear PCM on PCMi1 and PCMi2, are received as 14-bit, two’s complement data with three bits of sign extension
in the most significant positions (i.e., S,S,S,12,...1,0) for a total of 16 bits. The linear PCM data transmitted from
PCMo1 and PCmo2 are 16-bit, two’s complement data with one sign bit in the most significant position (i.e.,
S,14,13,...1,0)
32 and 24 kbps ADPCM mode
In 32 kbps and 24 kbps linear mode, the 16-bit uniform PCM dual-octets of the B1, B2, B3 and B4 channels (from
PCMi1 and PCMi2) are compressed into four 4-bit words on ADPCMo. The four 4-bit ADPCM words of the B1, B2,
B3 and B4 channels from ADPCMi are expanded into four 16-bit uniform PCM dual-octets on PCMo1 and PCMo2.
16-bit uniform PCM are received and transmitted most significant bit first starting with b15 and ending with b0.
ADPCM data are transferred most significant bit first starting with I1 and ending with I4 for 32 kbps and ending with
I3 for 24 kbps operation (i.e., I4 is don’t care).(See Figures 5 & 8.)
16 kbps ADPCM mode
When SEL is set to 0, the four, 2-bit ADPCM words are transmitted/received on ADPCMo/i during the ENB1 timeslot in SSI mode and during the B1 timeslot in ST-BUS mode. When SEL is set to 1, the four, 2-bit ADPCM words
are transmitted/received on ADPCMo/i during the ENB2 timeslot in SSI mode and during the B2 timeslot in ST-BUS
mode. (See Figures 5 & 8.)
PCM Law Control (A/µ, FORMAT)
The PCM companding/coding law invoked by the transcoder is controlled via the A/µ and FORMAT pins. ITU-T
G.711 companding curves, µ-Law and A-Law, are selected by the A/µ pin (0=µ-Law; 1=A-Law). Per sample,
digital code assignment can conform to ITU-T G.711 (when FORMAT=1) or to Sign-Magnitude coding (when
FORMAT=0). Table 1 illustrates these choices.
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Zarlink Semiconductor Inc.
ZL38010
Data Sheet
FORMAT
PCM Code
0
1
SignMagnitude
ITU-T (G.711)
A/µ = 0 or 1
(A/µ = 0)
(A/µ = 1)
+ Full Scale
1111 1111
1000 0000 1010 1010
+ Zero
1000 0000
1111 1111 1101 0101
- Zero
0000 0000
0111 1111 0101 0101
- Full Scale
0111 1111
0000 0000 0010 1010
Table 1 - Companded PCM
Power Down
Setting the PWRDN pin low will asynchronously cause all internal operation to halt and the device to go to a power
down condition where no internal clocks are running. Output pins C2o, EN1, EN2, PCMo1, PCMo2 and ADPCMo
and I/O pin F0od/ENB2 are forced to a high-impedance state. Following the reset (i.e., PWRDN pin brought high)
and assuming that clocks are applied to the MCLK and BCLK pins, the internal clocks will still not begin to operate
until the first frame alignment is detected on the ENB1 pin for SSI mode or on the F0i pin for ST-BUS mode. The
C2o clock and EN1, EN2 pins will not start operation until a valid frame pulse is applied to the F0i pin. If the F0i pin
remains low for longer than 2 cycles of MCLK then the C2o pin will top toggling and will stay low. If the F0i pin is
held high then the C2o pin will continue to operate. In ST-BUS mode the EN1 and EN2 pins will stop toggling if the
frame pulse (F0i) is not applied every frame.
Master Clock (MCLK)
A minimum 4096 kHz master clock is required for execution of the transcoding algorithm. The algorithm requires
512 cycles of MCLK during one frame for proper operation. For SSI operation this input, at the MCLK pin, may be
asynchronous with the 8 kHz frame provided that the lowest frequency and deviation due to clock jitter still meets
the strobe period requirement of a minimum of 512 tC4P - 25%tC4P (see Figure 3). For example, a system producing
large jitter values can be accommodated by running an over-speed MCLK that will ensure a minimum 512 MCLK
cycles per frame is obtained. The minimum MCLK period is 61 nSec, which translates to a maximum frequency of
16.384 MHz. Extra MCLK cycles (>512/frame) are acceptable since the transcoder is aligned by the appropriate
strobe signals each frame.
ENB1
MCLK
512 tC4P - 25%tC4P Minimum
Figure 3 - MCLK Minimum Requirement
10
Zarlink Semiconductor Inc.
ZL38010
Data Sheet
Bit Clock (BCLK)
For SSI operation the bit rate, for both ADPCM and PCM ports, is determined by the clock input at BCLK. BCLK
must be eight periods in duration and synchronous with the 8 kHz frame inputs at ENB1 and ENB2. Data is
sampled at PCMi1/2 and at ADPCMi concurrent with the falling edge of BCLK. Data is available at PCMo1/2 and
ADPCMo concurrent with the rising edge of BCLK. BCLK may be any rate between 128 kHz and 4096 kHz. For STBUS operation BCLK is ignored (tie to VSS) and the bit rate is internally set to 2048 kbps.
BCLK
ENB1
ENB2/F0od
B1
PCMi/o1
B2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
B3
PCMi/o2
B4
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
32 kbps
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
B1
ADPCM i/o
24 kbps
ADPCM i/o
16 kbps
B3
B4
1 2 3 x 1 2 3 x 1 2 3 x 1 2 3 x
B1
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel strobe boundaries
Two frame delay from data input to data output
B2
B2
B3
1 2 1 2 1 2
B4
B1
B2
B3
B4
1 2 1 2 1 2 1 2 1 2
SEL = 0
SEL = 1
SEL for 16 kbps only
Figure 4 - SSI 8-Bit Companded PCM Relative Timing
11
Zarlink Semiconductor Inc.
ZL38010
Data Sheet
Notes: S = 3 bits sign extension
BCLK
µ−Law is 13 bit 2’s complement data (bits 0 -12)
A-Law is 12 bit 2’s complement data (shifted left once and utilizing
bits 1 - 12, bit 0 not defined)
... (2.048 MHz only)
EN1
ENB1
ENB2/F0od
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
B1
PCMi/o1
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
B2
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
ADPCM i/o
24 kbps
ADPCMi/o
16 kbps
B4
B3
PCMi/o2
32 kbps
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
1234 1234 1234 1234
B1
B2
B3
1234 1234
B3
B4
B4
123x 123x 123x 123x
123x 123x
12 12 12 12 12 12 12 12
12 12 12 12
B B B B B B B B
B B B B
1 2 3 4 1 2 3 4
1 2 3 4
SEL = 0
SEL = 1
SEL = 1
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel strobe boundaries
Two frame delay from data input to data output
Figure 5 - SSI 16-Bit Linear PCM Relative Timing
12
Zarlink Semiconductor Inc.
SEL for 16 kbps only
ZL38010
Data Sheet
BCLK
ENB1
ENB2/F0od
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
B1
PCMi/o1
B2
SEL = 0
ADPCMo/i
SSI PCM
Bypass
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SEL = 1
B3
PCMi/o2
B4
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1 2 3 4 x x x x
1 2 3 4 x x x x
B2
B1
PCMi/o1
32 kbps using bits 1 2 3 4
ADPCMo/i
1 2 3 4 1 2 3 4 1 2 3 4 1 2 34
B3
PCMi/o2
24 kbps where bit 4 = x
B4
1 2 3 4 x x x x 1 2 3 4 x x x x
1 2 x x x x x x
PCMi/o1
1 2 x x x x x x
B2
B1
SEL = 0
ADPCM o/i
SEL = 1
1 2 1 2 1 2 1 2 1 2 1 2
B1
PCMi/o2
SSI ADPCM
Bypass
B2 B3
B4
1 2 1 2
B1 B2 B3
16 kbps
B4
B3
B4
1 2 x x x x x x
1 2 x x x x x x
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel strobe boundaries
Two frame delay from data input to data output
Figure 6 - SSI PCM and ADPCM Bypass Relative Timing
13
Zarlink Semiconductor Inc.
ZL38010
Data Sheet
MCLK (C4)
F0i
ENB2/F0od
C2o (output)
EN1 (output)
EN2 (output)
PCMi1
0 1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
D
PCMo1
0 1
C
B1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
PCMi2
transparent relay of D- and C- channels
when ENB1=0
0 1
B4
7 6 5 4 3 2 1 0 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
D
ADPCMo
B3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
PCMo2
ADPCMi
B2
C
B1
B2
B3
B4
7 6 5 4 3 2 1 0 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
0 1
SEL=0
32 kbps is shown
In 24 kbps, bit 4 becomes “X”
SEL=1
B1 B2 B3 B4 B1 B2 B3 B4
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
B1 B2 B3 B4 B1 B2 B3 B4
16 kbps
SEL operates for
16 kbps only
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
outputs = High impedance
inputs = don’t care
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel boundaries
Two frame delay from data input to data output
Figure 7 - ST-BUS 8-Bit Companded PCM Relative Timing
14
Zarlink Semiconductor Inc.
ZL38010
Data Sheet
MCLK (C4i)
F0i
C2o
EN1 (output)
F0od/ENB2
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
B1
PCMi/o1
B2
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
SSS 12 11 10 9 8 7 6 5 4 3 2 1 0
B3
B4
PCMi/o2
1234 1234 1234 1234
ADPCMi/o
B1
B2
B3
B4
(32/24 kbps)
bit 4 = x at 24 kbps
12 12 12 12 12 12 12 12
B B B B B B B B
ADPCMi/o
1 2 3 4 1 2 3 4
(16 kbps)
SEL = 0
SEL = 1
SEL operated for
16 kbps only
outputs = High impedance
inputs = don’t care
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel boundaries
Two frame delay from data input to data output
Note: D &C channels not supported in this mode.
Figure 8 - ST-BUS 16-Bit Linear PCM Relative Timing
15
Zarlink Semiconductor Inc.
ZL38010
Data Sheet
MCLK
F0i
ENB2/F0od
C2o
EN1 (output)
EN2 (output)
PCMi1
P
C
M
B
y
p
a
s
0 1
7 6 5 4 3 2 1 0
D
PCMo1
0 1
7 6 5 4 3 2 1 0
C
B1
7 6 5 4 3 2 1 0
B2
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
SEL=0
PCMi2
SEL=1
B3
PCMo2
ADPCMi
0 1
7 6 5 4 3 2 1 0
D
ADPCMo
B4
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
C
B1/B3
0 1
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
0 1
7 6 5 4 3 2 1 0
1 2 3 4 x x x x
B1
PCMi/o1
D
A
D
P
C
M
B
y
p
a
s
7 6 5 4 3 2 1 0
C
PCMi/o2
ADPCMi/o
32 kbps
24 kbps bit 4 = X
D
7 6 5 4 3 2 1 0
B2
B3
1 2 3 4 x x x x
B4
1 2 3 4 x x x x
1 2 3 4 x x x x
1 2 3 4 1 2 3 4
1 2 3 4 1 2 3 4
7 6 5 4 3 2 1 0
0 1
B2/B4
B1
C
B2
B3
SEL=0
D
ADPCMi/o
(16 kbps)
0 1
PCMi/o1
0 1
PCMi/o2
C
B1
7 6 5 4 3 2 1 0
C
B3 B4
SEL=1
B1 B2
B3 B4
1 2 1 2 1 2 1 2
B1
B2
1 2 x x x x x x
1 2
B3
B4
1 2 x x x x x x
1 2
7 6 5 4 3 2 1 0
D
B2
1 2 1 2 1 2 1 2
B4
x x x x x x
x x x x x x
outputs = High impedance
inputs = don’t care
X = undetermined logic level output; don’t care input
Outputs high impedance outside of channel boundaries
Two frame delay from data input to data output
Figure 9 - ST-BUS PCM and ADPCM Bypass Relative Timing
16
Zarlink Semiconductor Inc.
ZL38010
Data Sheet
Processing Delay Through the Device
In order to accommodate variable rate PCM and ADPCM interfaces, the serial input and output streams require a
complete frame to load internal shift registers. Internal frame alignment of the encoding/decoding functions are
taken from either of the F0i or ENB1 & ENB2 input strobes depending upon the device operating mode (i.e., STBUS or SSI). The encoding/decoding of all channels then takes one frame to complete before the output buffers are
loaded. This results in a two frame transcoding delay. The two frame delay also applies to the D and C channels
and to the PCM and ADPCM bypass functions.(See Figure 10.)
Note: When changing the relative positions of the ENB1 and ENB2 strobes, precaution must be taken to ensure
that two conditions are met. They are:
1. There must be at least 512 master clock cycles between consecutive rising edges of ENB1. This condition also
holds true for ENB2.
2. The ENB1 strobe must alternate with the ENB2 strobe.
Violation of these requirements may cause noise on the output channels.
frame n-1
frame n
frame n+1
PCM Byte "X" latched into device
during frame n-1
PCM Byte "X" processed according
to MSn input states latched during
frame n
ADPCM Word "X" output from
device during frame n+1
Byte "x"
PCMi1/2
ADPCMo
Word "x"
ENB1 or ENB2
F0i
MS1 or 4
32 kbps
24 kbps
32 kbps
Where MS2, 3, 5, 6 = 0
This diagram shows the conversion sequence from PCM to ADPCM. The same pipelining occurs in the
reverse ADPCM to PCM direction.
Total delay from data input to data output = 2 frames.
Figure 10 - Data Throughput
Applications
Figure 11 depicts an ISDN line card utilizing a ’U’ interface transceiver and ZL38010 ADPCM transcoder. This
central office application implements the network end of a Pair-Gain system. Figure 12 shows Zarlink devices used
to construct the remote Pair-Gain loop terminator.
17
Zarlink Semiconductor Inc.
ZL38010
Data Sheet
F0i
ISDN ’U’
Interface LIN+
ZL38010
PCMi1
PCMo1
PCMi2
PCMo2
ADPCMi
ADPCMo
T
2
R
LINLOUTLOUT+
F0b
C4b
F0i
MCLK
DSTo
DSTi
F0od
C4i
F0od
1
T R
1
F0i
F0od
PCMi1
PCMo1
PCMi2
PCMo2
C4i
C4i
F0od
C4i
F0i
PCMi1
PCMo1
PCMi2
PCMo2
F0od
C4i
PCMi1
PCMo1
PCMi2
PCMo2
F0i
8
T R
8
2
F0i
F0i
MT89L80
DX
ST1i
ST1o
C4i
ST2i
ST2o
Figure 11 - ISDN Line Card with 32 kbps ADPCM
Figure 13 depicts an ADPCM to linear PCM converter for applications where further, value added, functions are
being performed via digital signal processor. Access to linear coded PCM reduces the overhead of the DSP by
removing the need for a companded to linear conversion. The linear PCM capability of the ADPCM transcoder in
conjunction with the frame alignment signal EN1 allows direct connection to the serial port of both Motorola and
Texas Instruments Digital Signal Processors. Daisy-chaining via the delayed frame strobe output ensures that the
ADPCM array is distributed over the complete 2048 kbit bandwidth. If the DSP has a second serial port then access
to the processed PCM can be had directly. For processors with only one serial port the MT8920 connected to the
DSP parallel port will provide serial access by parallel to serial conversion. The same daisy-chained arrangement of
Quad ADPCM transcoders will provide a general system resource for PCM-ADPCM conversion by setting the
device to non-linear operation.
18
Zarlink Semiconductor Inc.
GND
GND
VBAT
VBAT
VEE
VEE
VDD
19
Zarlink Semiconductor Inc.
13
11
18
Figure 12 - Pair Gain Remote Terminal Utilizing Zarlink Components
16
25
3
38
5V
-5V
-24VDC
15
26
39
40
14
27
4
37
22
7
34
21
28
30
20
16
DCRI
DCRI
ESI2
ESTi
RG2
RG1
VX2
VR2
RF3
RF2
RF1
VX1
VR1
Pair Gain
SLIC 2 19
1
2
5,8,9,17,23,32,33,36
-24VDC
-5V
5V
VDD
RING2
TIP2
RING1
TIP1
Pair Gain
SLIC 1
120VDC ring
voltage
meter signal
I/P
120VDC ring
voltage
meter signal
I/P
1
2 MT91L60
3
4
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
20
2 MT91L60 19
3
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
1
20
2 MT91L60 19
3
2
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
MVSSA
HSPKR+
HSPKRVDD
CLOCKin
STB/F0i
Din
Dout
MT91L60
M+
1
VBias
VRef
PWRST
IC
A/µ/IRQ
VSSD
CS
SCLK
DATA1
DATA2
3.3V
3.3V
3.3V
3.3V
EN1
EN2 28
8
Reset
A/µ 15
FORMAT 16
PWRDN 17
IC 18
MS1 19
MS2 20
10.24 MHz
ISND ’U’ \
Interface
or
MT9172
C4b
DSTi
DSTo
F0b
MicroController
Optional QADPCM
functional control
SLIC Functions
Static Control:
3
3
3.3V
3
9 control lines for QADPCM, some optional
D-Channel access through CODEC1 Microport
8 signals for microport are:
DATA1, DATA2, SCLK, IRQ, CS1, CS2, CS3, CS4
8
3
16 control/status lines are:
LR1/2, ESE1/2, SHK1/2, RC1/2 - 8 x 2 SLIC’s
Serial Micro-port
Intel MCS-51
Motorola SPI
Nat Semi Microwire
SEL
PCMi2
PCMo2
ENB1
ENB2/F0od
16
14
13
12
11
10
LINEAR
MS3 21
9
VDD 22
VSS
6
8
ADPCMi 23
PCMo1
5
PCMi1
ADPCMo 24
BCLK
4
7
MS5 26
MS6 27
MS4 25
1
ZL38010
C2o
MCLK
F0i
3
2
1
ZL38010
Data Sheet
ZL38010
Data Sheet
System Frame pulse
System 4.096 MHz
ZL38010
C2o
F0i
MCLK (C4i)
PCMo1
PCMo2
ADPCMo
ADPCMi
PCMi1
PCMi2
LINEAR
ENB2/F0od
EN1
FSR
FSX
IRQ0
MT8920
ZL38010
CLKR
C2o
CLKX
PCMo1
PCMo2
S
T
+3.3V
TI DSP
F0i
MCLK (C4i)
ADPCMo
ADPCMi
PCMi1
PCmi2
DR
P
LINEAR
ENB2/F0od
EN1
A
DX
+3.3V
ZL38010
C2o
F0i
MCLK (C4i)
PCMo1
PCmo2
ADPCMo
ADPCMi
PCMi1
PCMi2
STPA
ST-BUS
port
2nd serial port
if available
EN1
LINEAR
ENB2/F0od
+3.3V
ZL38010
C2o
PCMo1
PCMo2
F0i
MCLK (C4i)
ADPCMo
ADPCMi
PCMi1
PCMi2
EN1
LINEAR
ENB2/F0od
+3.3V
ADPCM BUS
Figure 13 - ST-BUS to DSP Platform
20
Zarlink Semiconductor Inc.
ZL38010
Data Sheet
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
VDD-VSS
-0.3
7.0
V
Vi | Vo
VSS-0.3
VDD+ 0.3
V
±20
mA
150
°C
500
mW
1
Supply Voltage
2
Voltage on any I/O pin
3
Continuous Current on any I/O pin
Ii | Io
4
Storage Temperature
TST
-65
5 Package Power Dissipation
PD
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
VDD
3.0
3.3
3.6
V
1
Supply Voltage
2
CMOS Input High Voltage
3.0
VDD
V
3
CMOS Input Low Voltage
VSS
0.5
V
Test Conditions
-40
+85
°C
Operating Temperature
TA
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
4
‡
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.‡
Max.
Units
Test Conditions
100
4.5
µA
mA
PWRDN = 0
PWRDN = 1, clocks active
1
Supply Current
ICC
IDD
2
Input HIGH voltage (CMOS)
VIH
3
Input LOW voltage (CMOS)
VIL
4
Input leakage current
IIH/IIL
5
High level output voltage
VOH
6
Low level output voltage
VOL
7
High impedance leakage
IOZ
1
8
Output capacitance
Co
10
pF
9
Input capacitance
Ci
8
pF
Positive Threshold Voltage
Hysteresis
Negative Threshold Voltage
V+
VH
V-
1.0
V
V
V
10
P
W
R
D
N
2.0
V
0.1
0.8
V
10
µA
VIN=VSS to VDD
V
IOL=2.5 mA Typically
0.4
V
IOL=5.0 mA Typically
10
µA
VIN=VSS to VDD
2.4
1.8
1.4
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* DC Electrical Characteristics are over recommended temperature and supply voltage.
21
Zarlink Semiconductor Inc.
ZL38010
Data Sheet
AC Electrical Characteristics† - Serial PCM/ADPCM Interfaces (see Figure 14)
Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym.
Min.
Typ.†
Max.
Units
1
BCLK Clock High
tBCH
80
ns
2
BCLK Clock Low
tBCL
80
ns
3
BCLK Period
tBCP
200
4
Data Output Delay (excluding first
bit)
tDD
5
Output Active to High Z
tAHZ
6
Strobe Signal Setup
tSSS
7
Strobe Signal Hold
8
7900
ns
95
ns
95
ns
80
tBCL80
ns
tSSH
80
tBCL80
ns
Data Input Setup
tDIS
50
ns
9
Data Input Hold
tDIH
50
ns
10
Strobe to Data Delay (first bit)
tSD
11
F0i Setup
tF0iS
50
12
F0i Hold
tF0iH
13
MCLK (C4i) duty cycle
tH/tL
x100
14
F0od Delay
tDFD
60
ns
15
F0od Pulse Width
tDFW
244
ns
16
MCLK (C4i) period
tC4P
17
Data Output delay
tDSD
18
Data in Hold time
tDSH
50
ns
19
Data in Setup time
tDSS
50
ns
95
ns
122
150
ns
50
122
150
ns
40
50
60
%
61
80
244.2
ns
120
ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
22
Zarlink Semiconductor Inc.
Test Conditions
ZL38010
tBCH
tBCP
Data Sheet
tBCL
VIH
BCLK
S
S
I
VIL
tSSH
tSSS
ENB1
or
ENB2
tDIS
VIH
VIL
tDIH
VIH
PCMi/ADPCMi
VIL
tDSS
tSD
tDSH
tAHZ
tDD
VOH
PCMo/ADPCMo
VOL
tDSD
tH
S
T
B
U
S
VIHC
MCLK
VILC
tF0iH
tC4P
tL
F0i
tF0iS
tDFD
F0od
tDFD
VIH
VIL
VOH
VOL
Figure 14 - Serial Port Timing
23
Zarlink Semiconductor Inc.
ZL38010
Data Sheet
AC Electrical Characteristics† - ST-BUS C2o Conversion
Voltages are with respect to ground (VSS) unless otherwise stated.
Min.
Typ.†
Characteristics
Sym.
Max.
Units
Test Conditions
1
Delay MCLK falling to C2o rising
tD1
100
ns
150 pF//1 K Load
2
Delay MCLK falling to Enable
tD2
100
ns
150 pF//1 K Load
VIH
VIL
F0i
VIHC
MCLK
(C4i)
VILC
tD1
C2o
VOH
VOL
EN1
EN2
VOH
VOL
tD2
tD2
Figure 15 - ST-BUS Timing for External Signal Generation
24
Zarlink Semiconductor Inc.
ZL38010
Data Sheet
AC Electrical Characteristics† - Mode Select Timing (see Figures 16 & 17)
Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
1
Mode Select Setup
Sym.
Min.
tSU
500
Typ.†
Max.
Units
ns
Test Conditions
MCLK=4096 kHz
500
ns
2 Mode Select Hold
tHOLD
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
t
SU
t
HOLD
MS1
to
MS6
VIH
VIL
VIH
ENB1 (input)
Figure 16 - SSI Mode Select Set-up and Hold Timing
t
t
HOLD
SU
VIH
VIL
MS1
to
MS6
MCLK
F0i
Refer to Figure 14 for ST-BUS F0i timing.
Figure 17 - ST-BUS Mode Select Set-up and Hold Timing
25
Zarlink Semiconductor Inc.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
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