W681360 3V SINGLE-CHANNEL 13-BIT LINEAR VOICE-BAND CODEC Data Sheet -1- Publication Release Date: September 2005 Revision A.2 W681360 1. GENERAL DESCRIPTION The W681360 is a general-purpose single channel 13–bit linear PCM CODEC with 2s complement data format. It operates from a single +3V power supply and is available in 20-pin SOG(SOP), SSOP and TSSOP package options. The primary function of the device is the digitization and reconstruction of voice signals, including the band limiting and smoothing required for PCM systems. The W681360 performance is specified over the industrial temperature range of –40°C to +85°C. The W681360 includes an on-chip precision voltage reference. The analog section is fully differential, reducing noise and improving the power supply rejection ratio. The VAG reference pin allows for decoupling of the internal circuitry that generates the reference voltage to the VSS power supply ground, minimizing clock noise on the analog circuitry when external analog signals are referenced to VSS. The data transfer protocol supports both long-frame and short-frame, synchronous and asynchronous communications for PCM applications. The W681360 accepts eight master clock rates between 256kHz and 4.800MHz, and an on-chip pre-scaler automatically determines the division ratio for the required internal clock. An additional on-chip power amplifier is capable of driving 300Ω loads differentially up to a level of 3.544V peak-to-peak. For fast evaluation a development kit (W681360DK) is available. For fast prototyping purposes a low-cost evaluation board (W681360ES) is also available. 2. FEATURES • • • • • • • • • • • • Single +3V power supply (2.7V to 5.25V) Typical power dissipation: 9.8mW Standby power dissipation: 3µW Power-Down dissipation: 0.09µW Fully-differential analog circuit design for low noise 13-bit linear A/D & D/A conversions with 2s complement data format CODEC A/D and D/A filtering compliant with ITU G.712 Eight master clock rates of 256kHz to 4.800 MHz 256KHz – 4.8MHz bit clock rates on the serial PCM port On-chip precision reference of 0.886 V for a -5 dBm TLP at 600 Ω (436mVRMS) Programmable receive gain: 0 to –21dB in 3dB steps Industrial temp. range (–40°C to +85°C) 20-pin SOG (SOP), SSOP and TSSOP as well as a QFN-32L package Pb-Free / RoHS package options available Applications • VoIP, Voice over Networks equipment • Digital telephone and communication systems • Wireless Voice devices • DECT/Digital Cordless phones • Broadband Access Equipment • Bluetooth Headsets • Fiber-to-curb equipment • Enterprise phones • Digital Voice Recorders -2- Publication Release Date: September 2005 Revision A2 W681360 3. BLOCK DIAGRAM Transmit Receive PCM PCM Interface Interface BCLKR FSR PCMR BCLKT FST PCMT PAO+ PAOPAI G.712 CODEC ROAO AI+ AIHB Voltage reference 256 kHz 8 kHz VAGREF Power Conditioning PUI Pre-scaler VDD 256 kHz 512 kHz 1536 kHz 1544 kHz 2048 kHz 2560 kHz 4096 kHz 4800 kHz VSS MCLK VAG -3- Publication Release Date: September 2005 Revision A.2 W681360 4. TABLE OF CONTENTS 1. GENERAL DESCRIPTION.................................................................................................................. 2 2. FEATURES ......................................................................................................................................... 2 3. BLOCK DIAGRAM............................................................................................................................... 3 4. TABLE OF CONTENTS ...................................................................................................................... 4 5. PIN CONFIGURATION ....................................................................................................................... 6 6. PIN DESCRIPTION ............................................................................................................................. 7 7. FUNCTIONAL DESCRIPTION............................................................................................................ 8 7.1. Transmit Path................................................................................................................................ 8 7.1.1 Input Operational Amplifier Gain ............................................................................................. 9 7.2. Receive Path............................................................................................................................... 10 7.2.1. Receive Gain Adjust Mode................................................................................................... 11 7.3. Power Management.................................................................................................................... 11 7.3.1. Analog and Digital Supply .................................................................................................... 11 7.3.2. Analog Ground Reference Bypass ...................................................................................... 11 7.3.3. Analog Ground Reference Voltage Output .......................................................................... 11 7.4. PCM Interface ............................................................................................................................. 12 7.4.1. Long Frame Sync................................................................................................................. 12 7.4.2. Short Frame Sync ................................................................................................................ 12 7.4.3. Special 16-bit Receive Modes.............................................................................................. 13 7.4.3.1. Sign-Extended Mode Timing............................................................................................. 13 7.4.3.2. Receive Gain Adjust Mode Timing.................................................................................... 13 7.4.4. System Timing ..................................................................................................................... 14 7.5. On-Chip Power Amplifier ............................................................................................................ 14 8. TIMING DIAGRAMS.......................................................................................................................... 15 9. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 20 9.1. Absolute Maximum Ratings ........................................................................................................ 20 9.2. Operating Conditions .................................................................................................................. 20 10. ELECTRICAL CHARACTERISTICS ............................................................................................... 21 10.1. General Parameters ................................................................................................................. 21 10.2. Analog Signal Level and Gain Parameters............................................................................... 22 10.3. Analog Distortion and Noise Parameters ................................................................................. 23 10.4. Analog Input and Output Amplifier Parameters ........................................................................ 24 10.5. Digital I/O .................................................................................................................................. 26 10.5.1. PCM Codes for Zero and Full Scale .................................................................................. 26 10.5.2. PCM Codes for 1kHz Digital Milliwatt ................................................................................ 26 11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 27 12. PACKAGE DRAWING AND DIMENSIONS .................................................................................... 28 12.1. 20L SOG (SOP)-300mil ............................................................................................................ 28 12.2. 20L SSOP-209 mil .................................................................................................................... 29 12.3. 20L TSSOP - 4.4X6.5mm ......................................................................................................... 30 12.3. QFN-32L ................................................................................................................................... 31 -4- Publication Release Date: September 2005 Revision A.2 W681360 13. ORDERING INFORMATION........................................................................................................... 32 14. VERSION HISTORY ....................................................................................................................... 33 -5- Publication Release Date: September 2005 Revision A.2 W681360 5. PIN CONFIGURATION VREF ROPAI PAOPAO+ VDD FSR PCMR BCLKR PUI 1 20 2 19 3 18 4 17 W681360 SINGLE CHANNEL CODEC 5 6 7 8 16 15 14 13 9 12 10 11 VAG AI+ AIAO HB VSS FST PCMT BCLKT MCLK 32 31 AI+ NC NC VAG VREF NC NC SOG, SSOP,TSSOP 30 29 28 27 26 RO- 1 25 NC PAI 2 24 AI- PAO- 3 23 AO NC 4 22 HB PAO+ 5 21 NC VDD 6 20 VSS FSR 7 19 FST 18 NC PCMR 8 17 PCMT NC BCLKT 15 16 NC NC 13 14 MCLK 11 12 PUI 10 NC BCLKR 9 QFN-32L -6- Publication Release Date: September 2005 Revision A.2 W681360 6. PIN DESCRIPTION Pin Name Pin No. nonQFN QFN VREF 1 30 RO- 2 1 PAI 3 2 PAO- 4 3 PAO+ 5 5 VDD FSR 6 7 6 7 PCMR 8 8 BCLKR 9 9 PUI 10 12 MCLK 11 13 BCLKT 12 16 PCMT 13 17 FST VSS HB 14 15 16 19 20 22 AO AIAI+ VAG 17 18 19 20 23 24 26 29 Functionality This pin is used to bypass the on–chip VDD/2 voltage reference for the VAG output pin. This pin should be bypassed to VSS with a 0.1μF ceramic capacitor using short, low inductance traces. The VREF pin is only used for generating the reference voltage for the VAG pin. Nothing is to be connected to this pin except the bypass capacitor. Inverting output of the receive smoothing filter. This pin can typically drive a 2kΩ load to 0.886VPEAK referenced to analog ground. Inverting input to the power amplifier. The non-inverting input is tied internally to VAG voltage. Inverting power amplifier output. The PAO- and PAO+ can drive a 300Ω load differentially to 1.772VPEAK. Non-inverting power amplifier output. The PAO- and PAO+ can drive a 300Ω load differentially to 1.772VPEAK. Power supply. Should be decoupled to VSS with a 0.1μF ceramic capacitor. 8kHz Frame Sync input for the PCM receive section. FSR can be asynchronous to FST in either Long Frame Sync or Short Frame Sync mode. PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins. PCM receive bit clock input pin. Can accept any bit clock frequency from 256 to 4800kHz. When not clocked it can be used to select the 16 sign-bit extended synchronous mode (BCLKR=0) or the receive gain adjust synchronous mode (BCLKR=1) Power up input signal. When this pin is tied to VDD, the part is powered up. When tied to VSS, the part is powered down. System master clock input. Possible input frequencies are 256kHz, 512kHz, 1536kHz, 1544kHz, 2048kHz, 2560kHz, 4096kHz & 4800kHz. For performance reasons, it is recommended that MCLK be synchronous and aligned to the FST signal. This is a requirement in the case of 256 and 512kHz frequencies. PCM transmit bit clock input pin. Can accept any bit clock frequency from 256 to 4800kHz. PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins. 8kHz transmit frame sync input. This pin synchronizes the transmit data bytes. This is the supply ground. This pin should be connected to 0V. High-pass Bypass. Determines if the transmit high-pass filter is used (HB=’0’) or bypassed (HB=’1’). When the high pass is bypassed the frequency response extends to DC. Analog output of the first gain stage in the transmit path. Inverting input of the first gain stage in the transmit path. Non-inverting input of the first gain stage in the transmit path. Mid-Supply analog ground pin, which supplies a VDD/2 volt reference voltage for allanalog signal processing. This pin should be decoupled to VSS with a 0.01μF capacitor. This pin becomes high impedance when the chip is powered down. -7- Publication Release Date: September 2005 Revision A.2 W681360 7. FUNCTIONAL DESCRIPTION W681360 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC complies with the specifications of the ITU-T G.712 recommendation. The CODEC block diagram in Section 3 illustrates the main components of the W681360. The chip consists of a PCM interface, which can process long and short frame sync formats. The pre-scaler of the chip provides the internal clock signals and synchronizes the CODEC sample rate with the external frame sync frequency. The power conditioning block provides the internal power supply for the digital and the analog section, while the voltage reference block provides a precision analog ground voltage for the analog signal processing. The calibration level for both the Analog to Digital Converter (ADC) and the Digital to Analog Converter (DAC) is referenced to μ-Law with the same bit voltage weighing about the zero crossing, resulting in the 0dBm0 calibration level 3.2dB below the peak sinusoidal level before clipping, Based on the reference voltage of 0.886V the calibration level is 0.436 Vrms or –5dBm at 600Ω. VAG + - PAO+ - + PAOPAI 13 DATA Receive 13 bit linear DAC fC = 3400 Hz Smoothing Filter a Buffer1 Av=1 Smoothing Filter b High Pass Bypass 13 DATA Transmit 13 bit linear ADC fC = 200 Hz High Pass Filter fC = 3400 Hz Anti-Aliasing Filter a RO- AO - AI- + AI+ Anti-Aliasing Filter b FIGURE 7.1: THE W681360 SIGNAL PATH 7.1. Transmit Path The first stage of the A-to-D path of the CODEC is an analog input operational amplifier with externally configurable gain settings. A differential analog input may be applied to the Inputs AI+ and AI-. Alternately the input amplifier may be powered down and a single-ended input signal can be applied to either the AO pin or the AIpin. The input amplifier can be powered down by connecting the AI+ pin to either VDD or VSS which also determines whether AO or AI+ is selected as input according to -8- Publication Release Date: September 2005 Revision A.2 W681360 Table 7.1. When the input operational amplifier is powered down the AO pin becomes high input impedance. TABLE 7.1: INPUT AMPLIFIER MODES OF OPERATION AI+ (Pin 19) Input Amplifier Input VDD 1.2 to VDD-1.2 VSS Powered Down Powered Up Powered Down AO (Pin 17) AI+, AI- (Pins 19, 18) AI- (Pin 18) When the input amplifier is powered down, the input signal at AO or AI- should be referenced to the analog ground voltage VAG. The output of the input operational amplifier is first fed through a low-pass filter to prevent aliasing at the switched capacitor 3.4kHz low pass filter. Subsequently the 3.4kHz switched capacitor low pass filter bandlimits the input signals well below 4kHz. Signals above 4kHz would be aliased at the sampling rate of 8kHz. A high pass filter with a 200Hz cut-off frequency prevents DC coupling. All filters are designed according to the G.712 ITU-T specification. The high-pass filter may be bypassed depending on the logic level on the HB pin. If the high pass is removed the frequency response of the device extends down to DC. After filtering the signal is digitized as a 13-bit linear PCM code and fed to the PCM interface for serial transmission at the sample rate supplied by the external frame sync FST. 7.1.1 Input Operational Amplifier Gain The gain of the input operational amplifier can be adjusted using external resistors. For single-ended input operation the gain is given by a simple resistive ratio. FIGURE 7.2: INPUT OPERATIONAL AMPLIFIER GAIN – SINGLE-ENDED INPUT Ro AO AI- Ri - Vin VAG + AI+ Gin = Ro/Ri For differential input operation the external resistor network is more complex but the gain is expressed in the same way. Of course, a differential input also has an inherent 6dB advantage over a corresponding single-ended input. -9- Publication Release Date: September 2005 Revision A.2 W681360 Ro AO AI- Ri AI+ Ri + Gin = Ro/Ri VinVin+ Ro VAG FIGURE 7.3: INPUT OPERATIONAL AMPLIFIER GAIN – DIFFERENTIAL INPUT The gain of the operational amplifier will be typically be set to 30dB for microphone interface circuits. However the gain may be used for more than 30dB but this will require a compact layout with minimal trace lengths and good isolation from noise sources. It is also recommended that the layout be as symmetrical as possible as imbalances work against the noise canceling advantages of the differential design. 7.2. Receive Path The 13-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed through the 13-bit linear DAC and converted to analog samples. The analog samples are filtered by a low-pass smoothing filter with a 3.4kHz cut-off frequency, according to the ITU-T G.712 specification. A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is buffered to provide the receive output signal RO-. The output may be also be attenuated when the device is in the receive path adjust mode. If the device is operated half–channel with the FST pin clocking and FSR pin held LOW, the receive filter input will be connected to the VAG voltage. This minimizes transients at the RO– pin when full–channel operation is resumed by clocking the FSR pin. The RO- output can be externally connected to the PAI pin to provide a differential output with high driving capability at the PAO+ and PAO- pins. By using external resistors various gain settings of this output amplifier can be achieved. If the transmit power amplifier is not in use, it can be powered down by connecting PAI to VDD. The bias voltage and signal reference of the PAO+ & PAO– outputs is the VAG pin. The VAG pin cannot source or sink as much current as these pins, and therefore low impedance loads must be placed between PAO+ and PAO–. The PAO+ and PAO– differential drivers are also capable of driving a 100Ω resistive load or a 100nF piezoelectric transducer in series with a 20Ω resister with a small increase in distortion. These drivers may be used to drive resistive loads of 32Ω when the gain of PAO– is set to 1/4 or less. - 10 - Publication Release Date: September 2005 Revision A.2 W681360 7.2.1. Receive Gain Adjust Mode The W681360 can be put in the receive path adjust mode by applying a logic “1” to the BCLKR pin while all other clocks are clocked normally. The device is then in a position to read 16-bits of data, with three additional coefficient bits an addend to the 13-bit digital voice data. These three coefficients are used to program a receive path attenuation, thereby allowing the receive signal to be attenuated according to the values in the following table. If the feature is not used the default value is 0dB. TABLE 7.2: ATTENUATION COEFFICIENT RELATIONSHIP IN RECEIVE GAIN ADJUST MODE Coefficient Attenuation (dB) 000 0 001 3 010 6 011 9 100 12 101 15 110 18 111 21 7.3. POWER MANAGEMENT 7.3.1. Analog and Digital Supply The power supply for the analog and digital parts of the W681360 must be 2.7V to 5.25V. This supply voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 μF ceramic capacitor. 7.3.2. Analog Ground Reference Bypass The system has an internal precision voltage reference which generates the VDD/2 mid-supply analog ground voltage. This voltage needs to be decoupled to VSS at the VREF pin through a 0.1 μF ceramic capacitor. 7.3.3. Analog Ground Reference Voltage Output The analog ground reference voltage is available for external reference at the VAG pin. This voltage needs to be decoupled to VSS through a 0.01 μF ceramic capacitor. The analog ground reference voltage is generated from the voltage on the VREF pin and is also used for the internal signal processing. - 11 - Publication Release Date: September 2005 Revision A.2 W681360 7.4. PCM INTERFACE The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received through the PCMR pin and the output data is transmitted through the PCMT pin. The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR or BCLKT pin to a 256kHz to 4.800 MHz clock and connecting the FSR or FST pin to the 8kHz frame sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on the positive edge of the Frame Sync signal. Long Frame Sync is recognized when the FST pin is held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. Short Frame Sync Mode is recognized when the Frame Sync signal at pin FST is HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. 7.4.1. Long Frame Sync The device recognizes a Long Frame Sync when the FST pin is held HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. The length of the Frame Sync pulse can vary from frame to frame, as long as the positive frame sync edge occurs every 125 μsec. During data transmission in the Long Frame Sync mode, the transmit data pin PCMT will become low impedance when the Frame Sync signal FST is HIGH or when the 13-bit data word is being transmitted. The transmit data pin PCMT will become high impedance when the Frame Sync signal FST becomes LOW while the data is transmitted or when half of the LSB is transmitted. The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down state. Long Frame Sync mode is illustrated below. More detailed timing information can be found in the interface timing section. BCLKT (BCLKR) FST (FSR) PCMT 1 2 3 4 5 6 7 8 9 10 11 12 13 PCMR don't care 1 2 3 4 5 6 7 8 9 10 11 12 13 don't care Long Frame Sync (Transmit and Receive Have Individual Clocking) FIGURE 7.4: LONG FRAME SYNC PCM MODE 7.4.2. Short Frame Sync The W681360 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge of the bit-clock, the W681360 starts clocking out the data on the PCMT pin, which will also change from high to low impedance state. The data transmit pin PCMT will go back to the high impedance state halfway through the LSB. The Short Frame Sync operation of the W681360 is based on a 13-bit data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down state. Short Frame Sync mode is illustrated below. More detailed timing information can be found in the interface timing section. - 12 - Publication Release Date: September 2005 Revision A.2 W681360 BCLKT (BCLKR) FST (FSR) PCMT 1 2 3 4 5 6 7 8 9 10 11 12 13 PCMR don't care 1 2 3 4 5 6 7 8 9 10 11 12 13 don't care Short Frame Sync (Transmit and Receive Have Individual Clocking) FIGURE 7.5: SHORT FRAME SYNC PCM MODE 7.4.3. Special 16-bit Receive Modes 7.4.3.1. Sign-Extended Mode Timing The Sign-bit extended mode is entered by applying a logic “0” to the BCLKR pin while all other clocks are clocked normally. In standard 13-bit mode the first bit is the sign bit. In this mode the device transmits and receives 16-bit data where the sign bit is extended to the first four data bits. The PCM timing for this mode is illustrated below. BCLKT (BCLKR) FST (FSR) SHORT OR LONG FRAME SYNC PCMT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PCMR don't care 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 16 don't care don't care Sign-Extended (BCLKR=0) Transmit and Receive both use BCLKT, and the first four data bits are the sign bit. FST may occur at a different time than FSR FIGURE 7.6: SIGN EXTENDED MODE 7.4.3.2. Receive Gain Adjust Mode Timing The Receive Path Adjust Mode is entered by applying a logic “1” to the BCLKR pin while all other clocks are clocked normally. In this mode the device receives 16-bit data where the last three bits are coefficients to program the Receive Gain Adjust Attenuation described above. The PCM timing for this mode is illustrated below. - 13 - Publication Release Date: September 2005 Revision A.2 W681360 BCLKT (BCLKR) FST (FSR) SHORT O R LONG FRAM E SYNC PCMT 1 2 3 4 5 6 7 8 9 10 11 12 13 PCMR don't care 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 don't care don't care Receive Gain Adjust (BCLKR=1) Transm it and Receive both use BCLKT. FST m ay occur at a different tim e than FSR. Bits 14, 15, and 16, clocked into PCMR, are used for attenuation control for the receive analog output. FIGURE 7.7: RECEIVE GAIN ADJUST TIMING MODE 7.4.4. System Timing The system can work at 256kHz, 512kHz, 1536kHz, 1544kHz, 2048kHz, 2560kHz, 4096kHz & 4800kHz master clock rates. The system clock is supplied through the master clock input MCLK and can be derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256kHz and 8kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency versus the Frame Sync frequency and sets the division ratio accordingly. If both Frame Syncs are LOW for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the W681360 will enter the low power standby mode. Another way to power down is to set the PUI pin to LOW. When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the transmit Frame Sync pulse needs to be present. It will take two transmit Frame Sync cycles before the pin PCMT becomes low impedance. 7.5. ON-CHIP POWER AMPLIFIER The on-chip power amplifier is typically used to drive an external loudspeaker. The inverting input to the power amplifier is available at pin PAI. The non-inverting input is tied internally to VAG. The inverting output PAO– is used to provide a feedback signal to the PAI pin to set the gain of the power amplifier outputs (PAO+ and PAO-). These push–pull outputs are capable of driving a 300Ω load to 1.772 VPEAK. Connecting PAI to VDD will power down the power driver amplifiers and the PAO+ and PAO– outputs will be high impedance. - 14 - Publication Release Date: September 2005 Revision A.2 W681360 8. TIMING DIAGRAMS TFTRHM TMCK TFTRSM TRISE TFALL MCLK TMCKH TMCKL TBCK BCLKT TFTRS TFTRH TBCKH TFTFH TBCKL TFS TFSL FST TFDTD TFDTD TBDTD THID THID PCMT MSB BCLKR (BCLKT) TFRRS TFRRH LSB TBCK TBCKH TFRFH TBCKL FSR TDRS PCMR MSB TDRH LSB FIGURE 8.1: LONG FRAME SYNC PCM TIMING NOTE: The Data is clocked out on the rising edge of BCLK. The Data is clocked in on the falling edge of BCLK. - 15 - Publication Release Date: September 2005 Revision A.2 W681360 TABLE 8.1: LONG FRAME SYNC PCM TIMING PARAMETERS SYMBOL 1/TFS TFSL 1/TBCK TBCKH TBCKL TFTRH TFTRS TFTFH TFDTD TBDTD THID TFRRH TFRRS TFRFH TDRS TDRH 1 DESCRIPTION FST, FSR Frequency FST / FSR Minimum LOW Width 1 BCLKT, BCLKR Frequency 1 BCLKT, BCLKR HIGH Pulse Width BCLKT, BCLKR LOW Pulse Width BCLKT Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT Falling edge Setup Time BCLKT Falling Edge to FST Falling Edge Hold Time The later of BCLKT rising edge, or FST rising edge to first valid PCMT Bit Delay Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from the Later of FST Falling Edge, or BCLKT Falling Edge of last PCMT Bit to PCMT Output High Impedance BCLKR Falling Edge to FSR Rising Edge Hold Time FSR Rising Edge to BCLKR Falling edge Setup Time BCLKR Falling Edge to FSR Falling Edge Hold Time Valid PCMR to BCLKR Falling Edge Setup Time PCMR Hold Time from BCLKR Falling Edge MIN --TBCK 256 50 50 20 TYP 8 MAX --- UNIT kHz sec kHz ns ns ns --------- 4800 ------- 80 --- --- ns 50 --- --- ns --- --- 60 ns --- --- 60 ns 10 --- 60 ns 20 --- --- ns 80 --- --- ns 50 --- --- ns 1 --- --- ns 50 --- --- ns TFSL must be at least ≥ TBCK - 16 - Publication Release Date: September 2005 Revision A.2 W681360 TFTRHM TMCK TFTRSM TRISE TFALL MCLK TMCKH BCLKT TFTRS TFTRH TMCKL TBCK TBCKH TFTFS TBCKL TFS TFTFH FST TBDTD TBDTD THID PCMT MSB BCLKR (BCLKT) TFRRS TFRRH LSB TBCK TBCKH TFRFS TBCKL TFRFH FSR TDRS PCMR MSB TDRH LSB FIGURE 8.2: SHORT FRAME SYNC PCM TIMING - 17 - Publication Release Date: September 2005 Revision A.2 W681360 TABLE 8.2: SHORT FRAME SYNC PCM TIMING PARAMETERS SYMBOL 1/TFS DESCRIPTION FST, FSR Frequency 1/TBCK TBCKH TBCKL TFTRH TFTRS TFTFH TFTFS TBDTD THID BCLKT, BCLKR Frequency BCLKT, BCLKR HIGH Pulse Width BCLKT, BCLKR LOW Pulse Width BCLKT Falling Edge to FST Rising Edge Hold Time FST Rising Edge to BCLKT Falling edge Setup Time BCLKT Falling Edge to FST Falling Edge Hold Time FST Falling Edge to BCLKT Falling Edge Setup Time BCLKT Rising Edge to Valid PCMT Delay Time Delay Time from BCLKT Falling Edge at last PCMT bit (LSB) to PCMT Output High Impedance BCLKR Falling Edge to FSR Rising Edge Hold Time FSR Rising Edge to BCLKR Falling edge Setup Time BCLKR Falling Edge to FSR Falling Edge Hold Time FSR Falling Edge to BCLKR Falling Edge Setup Time Valid PCMR to BCLKR Falling Edge Setup Time PCMR Hold Time from BCLKR Falling Edge TFRRH TFRRS TFRFH TFRFS TDRS TDRH MIN --- - 18 - TYP 8 MAX --- 256 50 50 20 80 50 50 10 10 ------------------- 4800 ------------60 60 20 80 50 50 1 50 ------------- ------------- UNIT kHz kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns Publication Release Date: September 2005 Revision A.2 W681360 TABLE 8.3: GENERAL PCM TIMING PARAMETERS SYMBOL 1/TMCK DESCRIPTION Master Clock Frequency TMCKH / TMCK TMCKH MCLK Duty Cycle for 256kHz Operation 45% Minimum Pulse Width HIGH for MCLK(512kHz or Higher) Minimum Pulse Width LOW for MCLK (512kHz or Higher) MCLK falling Edge to FST Rising Edge Hold Time FST Rising Edge to MCLK Falling edge Setup Time Rise Time for All Digital Signals Fall Time for All Digital Signals 50 --- --- ns 50 --- --- ns 50 --- --- ns 50 --- --- ns ----- ----- 50 50 ns ns TMCKL TFTRHM TFTRSM TRISE TFALL MIN --- - 19 - TYP 256 512 1536 1544 2048 2560 4096 4800 MAX --- UNIT kHz 55% Publication Release Date: September 2005 Revision A.2 W681360 9. ABSOLUTE MAXIMUM RATINGS 9.1. ABSOLUTE MAXIMUM RATINGS Condition Value 0 Junction temperature 150 C Storage temperature range -650C to +1500C Voltage applied to any pin (VSS - 0.3V) to (VDD + 0.3V) Voltage applied to any pin (Input current limited to +/-20 mA) (VSS – 1.0V) to (VDD + 1.0V) VDD - VSS -0.5V to +6V 1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings may affect device reliability. Functional operation is not implied at these conditions. 9.2. OPERATING CONDITIONS Condition Value Industrial operating temperature -400C to +850C Supply voltage (VDD) +2.7V to +5.25V Ground voltage (VSS) 0V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. - 20 - Publication Release Date: September 2005 Revision A.2 W681360 10. ELECTRICAL CHARACTERISTICS 10.1. GENERAL PARAMETERS VDD=2.7V – 3.6V; VSS=0V; TA=-40°C to +85°C; Symbol Parameters Conditions VIL Input LOW Voltage VIH Input HIGH Voltage VOL PCMT Output LOW Voltage IOL = 1.6 mA VOH PCMT Output HIGH Voltage IOL = -1.6 mA IDD VDD Current (Operating) - ADC + DAC No Load ISB VDD Current (Standby) FST&FSR =Vss ; PUI=VDD (3) Min (2) Typ (1) Max Units 0.6 V (2) 2.2 V 0.4 VDD–0.5 (3) V V 3.25 4.7 mA 1 100 μA 0.03 10 μA IPD VDD Current (Power Down) PUI= Vss IIL Input Leakage Current VSS<VIN<VDD -10 +10 μA IOL PCMT Output Leakage Current VSS<PCMT<VDD High Z State -10 +10 μA CIN Digital Input Capacitance 10 pF COUT PCMT Output Capacitance 15 pF 1. PCMT High Z Typical values: TA = 25°C , VDD = 3.0 V 2. All min/max limits are guaranteed by Winbond via electrical testing or characterization. Not all specifications are 100 percent tested. 3. No DC load from VREF & VAG to Vss - 21 - Publication Release Date: September 2005 Revision A.2 W681360 10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS VDD=2.7V to 3.6V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG; 0dBm0 = 0.436 Vrms = 5dBm @ 600 Ohm; FST =FSR = 8kHz;MCLK=BCLK= 2.048 MHz PARAMETER SYM. Absolute Level LABS Max. Transmit Level Absolute Gain (0 dBm0 @ 1020Hz; TA=+25°C) Absolute Gain variation with Temperature Frequency Response, Relative to 0dBm0 @ 1020Hz (HB=0) TXMAX CONDITION TYP. 0 dBm0 = -5dBm @ 600Ω 0.616 0.436 3.2 0.886 0 TRANSMIT (A/D) MIN. MAX. ----- RECEIVE (D/A) MIN. MAX. ----- --- --- --- --- -0.20 +0.20 -0.20 +0.20 UNIT VPK VRMS dBm0 VPK dB GABS 0 dBm0 @ 1020Hz; TA=+25°C GABST TA=0°C to TA=+70°C TA=-40°C to TA=+85°C 0 -0.05 -0.10 +0.05 +0.10 -0.05 -0.10 +0.05 +0.10 dB GRTV 15Hz 50Hz 60Hz 200Hz 300 to 1600Hz 1600 to 2400Hz 2400 to 3000Hz 3300Hz 3400Hz 3600Hz 4000Hz 4600Hz to 100kHz ------------------------- -------1.4 -0.2 -0.2 -0.2 -0.2 -0.7 ------- -45 -30 -26 -0.4 +0.2 +0.2 +0.2 +0.2 +0.15 0 -12.5 -32 -0.5 -0.5 -0.5 -0.5 -0.2 -0.2 -0.25 -0.4 -0.8 ------- 0 0 0 0 +0.2 +0.25 +0.2 +0.15 0 0 -12.5 -30 dB - 22 - Publication Release Date: September 2005 Revision A.2 W681360 10.3. ANALOG DISTORTION AND NOISE PARAMETERS VDD=2.7V to 3.6V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG; 0dBm0 = 0.436 Vrms = 5dBm @ 600 Ohm; FST =FSR = 8kHz;MCLK=BCLK= 2.048 MHz PARAMETER SYM. CONDITION Total Distortion vs. Level Tone (1020Hz, CMessage Weighted) DLT +3 dBm0 0 dBm0 -10 dBm0 -20 dBm0 -30 dBm0 -40 dBm0 -50 dBm0 -60 dBm0 Spurious Out-OfBand at RO(300Hz to 3400Hz @ 0dBm0) Crosstalk (1020Hz @ 0dBm0) Absolute Group Delay Group Delay Distortion (relative to group delay @ 1200Hz) DSPO 4600Hz to 7600Hz 7600Hz to 8400Hz 8400Hz to 100000Hz Idle Channel Noise NIDL DXT TRANSMIT (A/D) MIN. TYP. MAX. 55 --45 60 --50 60 --51 54 --50 44 --41 34 --32 24 --22 14 --12 ------------------- RECEIVE (D/A) MIN. TYP. MAX. 60 --50 63 --48 60 --45 55 --48 47 --45 37 --35 27 --25 17 --14 -----30 -----40 -----30 UNIT dBC dB --- --- -75 --- --- -75 dB τABS 1200Hz (HB=0) --- --- 360 --- --- 240 μsec τD 500Hz 600Hz 1000Hz 2600Hz 2800Hz C-message weighted Psophometric weighted --------------- --------------- 750 380 130 130 750 18 -72 --------------- --------------- 750 370 120 120 750 12 -74 μsec - 23 - dBrnc0 dBm0p Publication Release Date: September 2005 Revision A.2 W681360 10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS VDD=2.7V to 3.6V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG; PARAMETER AI Input Offset Voltage AI Input Current AI Input Resistance AI Input Capacitance AI Common Mode Input Voltage Range AI Common Mode Rejection Ratio AI Amp Gain Bandwidth Product SYM. VOFF,AI IIN,AI RIN,AI CIN,AI VCM,AI CONDITION AI+, AIAI+, AIAI+, AI- to VAG AI+, AIAI+, AI- MIN. ----10 --1.2 TYP. --±0.1 ------- MAX. ±25 ±1.0 --10 VDD-1.2 UNIT. mV μA MΩ pF V CMRRTI GBWTI AI+, AIAO, RLD≥10kΩ ----- ----- dB kHz ----0.4 2 ----±1.0 ----VDD/2-0.1 60 2500 95 -24 ----------1 --VDD/2 AI Amp DC Open Loop Gain AI Amp Equivalent Input Noise AO Output Voltage Range Load Resistance Load Capacitance Load Capacitance AO & RO Output Current RO- Output Resistance RO- Output Offset Voltage Analog Ground Voltage GTI NTI VTG RLDTGRO CLDTGAO CLDTGRO IOUT1 RROVOFF,ROVAG VAG Output Resistance RVAG AO, RLD≥10kΩ C-Message Weighted RLD=2kΩ to VAG AO, RO to VAG AO RO 0.5 ≤AO,RO-≤ VDD-0.5 RO-, 0 to 3400Hz RO- to VAG Relative to VSS (no load) Within ±25mV change ----VDD-0.4 --100 200 ----±25 VDD/2+0.1 dB dBrnC V kΩ pF pF mA Ω mV V --- 12.5 Ω Transmit Receive 40 40 60 60 25 ----- Power Supply Rejection Ratio (0 to 100kHz to VDD, C-message. All signals referenced to VAG) PAI Input Offset Voltage PAI Input Current PAI Input Resistance PAI Amp Gain Bandwidth Product PSRR dBC VOFF,PAI IIN,PAI RIN,PAI GBWPI PAI PAI PAI to VAG PAO- no load (@10kHz) PAO+ to PAOPAO+, PAOdifferentially or PAO+, PAO to VAG ----10 --- --±0.05 --1000 ±25 ±1.0 ----- mV μA MΩ kHz Output Offset Voltage Load Capacitance VOFF,PO CLDPO ----- ----- ±50 1000 mV pF - 24 - Publication Release Date: September 2005 Revision A.2 W681360 VDD=2.7V to 3.6V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG; PARAMETER PAO Output Current SYM. IOUTPAO PAO Output Resistance PAO Differential Gain RPAO GPAO PAO Differential Signal to Distortion C-Message weighted DPAO PAO Power Supply Rejection Ratio (0 to 25kHz to VDD, Differential out) PSRRPA O CONDITION 0.4 ≤ PAO+,PAO--≤ VDD-0.4 PAO+ to PAORLD=300Ω, +3dBm0, 1kHz, PAO+ to PAOZLD=300Ω ZLD=100nF + 20Ω ZLD=100Ω (10mA limit) 0 to 4kHz 4 to 25kHz - 25 - MIN. ±10.0 TYP. --- MAX. --- UNIT. mA ---0.2 1 0 --+0.2 Ω dB 45 ----- 60 40 40 ------- dBC 40 --- 55 40 ----- dB Publication Release Date: September 2005 Revision A.2 W681360 10.5. DIGITAL I/O 10.5.1. PCM Codes for Zero and Full Scale Level Sign bit Magnitude Bits + Full Scale + One Step Zero - One Step - Full Scale 0 0 0 1 1 1111 1111 1111 0000 0000 0001 0000 0000 0000 1111 1111 1111 0000 0000 0000 10.5.2. PCM Codes for 1kHz Digital Milliwatt Phase Sign bit Magnitude Bits π/8 0 0100 0011 1100 3π / 8 0 1010 0011 1001 5π / 8 0 1010 0011 1001 7π / 8 0 0100 0011 1100 9π / 8 1 1011 1100 0100 11π / 8 1 0101 1100 0111 13π / 8 1 0101 1100 0111 15π / 8 1 1011 1100 0100 - 26 - Publication Release Date: September 2005 Revision A.2 W681360 11. TYPICAL APPLICATION CIRCUIT VDD 1K 1.0 uF ELECTRET MICROPHONE 17 100pF 3.9K 18 100pF 62K 0.01 uF 0.1 uF 27K 1.5K 3.9K 19 20 1 27K 27K 2 3 4 5 AO FST BCLKT PCMT AIAI+ MCLK VAG VREF PCMR BCLKR FSR RO- 14 12 13 11 8 9 7 8 KHz Frame Sy nc 2.048 MHz Bit Clock PCM OUT PCM IN PAI PAOVSS 1.0 uF VDD U2 62K + 6 22 uF 0.1 uF PAO+ W681360 HB PUI 16 10 HP FILTER SELECT POWER CONTROL 15 1.5K SPEAKER FIGURE 11.1: TYPICAL HANDSET INTERFACE - 27 - Publication Release Date: September 2005 Revision A.2 W681360 12. PACKAGE DRAWING AND DIMENSIONS 12.1. 20L SOG (SOP)-300MIL SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS 11 20 c E HE L 1 10 D 0.2 O A Y SEATING e GAUGE A b SYMBOL A A1 b c E D e HE Y L 0 DIMENSION (MM) MAX. MIN. 2.35 0.10 2.65 0.30 0.33 0.51 0.23 0.32 7.40 7.60 12.60 13.00 1.27 BSC 10.00 10.65 0.10 0.40 1.27 0º 8º - 28 - DIMENSION (INCH) MIN. MAX. 0.093 0.004 0.104 0.012 0.013 0.020 0.009 0.013 0.291 0.299 0.496 0.512 0.050 BSC 0.394 0.419 0.004 0.016 0.050 0º 8º Publication Release Date: September 2005 Revision A.2 W681360 12.2. 20L SSOP-209 MIL SHRINK SMALL OUTLINE PACKAGE DIMENSIONS D 11 20 DTEAIL HE E 1 10 A b A SEATING PLANE Y e SYMBOL A A1 A2 b c D E HE e L L1 Y 0 SEATING PLANE θ L L b A DETAIL DIMENSION (MM) NOM. MAX. MIN. DIMENSION (INCH) MIN. NOM. MAX. 0.05 1.65 0.22 0.09 6.90 5.00 7.40 0.55 0º 0.002 0.065 0.009 0.004 0.272 0.197 0.291 0.021 0 1.75 7.20 5.30 7.80 0.65 0.75 1.25 - 2.00 1.85 0.38 0.25 7.50 5.60 8.20 0.95 0.10 8º - 29 - 0.069 0.283 0.209 0.307 0.0256 0.030 0.050 - 0.079 0.015 0.010 0.295 0.220 0.323 0.037 0.004 8º Publication Release Date: September 2005 Revision A.2 W681360 12.3. 20L TSSOP - 4.4X6.5MM PLASTIC THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) DIMENSIONS SYMBOL A A1 A2 E HE D L L1 b e c 0 Y MIN. 0.05 0.80 4.30 6.40 0.50 0.19 0.09 0º DIMENSION (MM) NOM. MAX. 1.20 0.15 0.90 1.05 4.40 4.50 6.40 BSC 6.50 6.60 0.60 0.75 1.00 REF 0.30 0.65 BSC 0.20 8º 0.10 BASIC - 30 - DIMENSION (INCH) MIN. NOM. MAX. 0.047 0.002 0.006 0.031 0.035 0.041 0.169 0.173 0.177 .252 BSC 0.252 0.256 0.260 0.020 0.024 0.030 0.039 REF 0.007 0.012 0.026 BSC 0.004 0.008 0º 8º 0.004 BASIC Publication Release Date: September 2005 Revision A.2 W681360 12.3. QFN-32L QUAD FLAT PACK NO LEADS PACKAGE (QFN) DIMENSIONS L - 31 - Publication Release Date: September 2005 Revision A.2 W681360 13. ORDERING INFORMATION Winbond Part Number Description W681360_ _ Product Family W681360 Package Material: Blank = Standard Package G = Pb-free (RoHS) Package Package Type: S = 20-Lead Plastic Small Outline Package (SOG/SOP) R = 20-Lead Plastic Shrink Small Outline Package (SSOP) W = 20-Lead Plastic Thin Shrink Small Outline Package (TSSOP) Y = 32-Quad Flat No leads Package (QFN) When ordering W681360 series devices, please refer to the following part numbers. Part Number W681360S W681360R W681360W W681360SG W681360RG W681360WG W681360YG* * W681360YG available in Pb-free (RoHS) package only - 32 - Publication Release Date: September 2005 Revision A.2 W681360 14. VERSION HISTORY VERSION A.1 A.15 A.16 DATE April 2004 April 2005 September, 2005 PAGE All 32 2 6, 7 9 10, 12 22 27 31 32 DESCRIPTION Preliminary Specification Add Important Note Added reference to Pb-free RoHS packaging and to VRMS Added reference to QFN-32L package Added QFN-32L Pinout Added Pin numbers to Tables Capitalized logic HIGH/LOW Added Reference to VRMS Improved Application Diagram Added QFN-32L Mechanical Dimensions Added Y and G package ordering code - 33 - Publication Release Date: September 2005 Revision A.2 W681360 Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. The information contained in this datasheet may be subject to change without notice. It is the responsibility of the customer to check the Winbond USA website (www.winbond-usa.com) periodically for the latest version of this document, and any Errata Sheets that may be generated - 34 - Publication Release Date: September 2005 Revision A.2