PANJIT PT2315A-D(L)

Tel: 886-2-66296288
Fax: 886-2-29174598
URL: http://www.princeton.com.tw
2-Channel Audio Processor IC
PT2315A
DESCRIPTION
PT2315A is a two-channel digital audio processor utilizing CMOS Technology. Volume, Bass, Treble
and Balance Controls are incorporated into a single chip. Loudness Function is also provided to build a
highly effective electronic audio processor having the highest performance and reliability with the least
external components. All functions are programmable using the I2C Bus. The pin assignments and
application circuit are optimized for easy PCB layout and cost saving advantage for audio application.
Housed in a 20-pin DIP and SOP, PT2315A is pin-to-pin compatible with TDA7315 and is very similar
in performance with the later.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
CMOS Technology
Least External Components
Treble and Bass Control
Loudness Function
Input/Output for External Noise Reduction System/Equalizer
2 Independent Speaker Controls for Balance Function
Independent Mute Function
Volume Control in 1.25dB/step
Low Distortion
Low Noise and DC Stepping
Controlled by I2C Bus Micro-Processor Interface
Pin-to-pin Compatible with TDA7315
APPLICATIONS
• Car Stereo (Audio)
• Hi-Fi Audio System
• Can be used in all I2C System Applications
Note:
Purchase of I2C Component of Princeton Technology Corporation (PTC) conveys a license under
Philips I2C Patent Right to use these components in any I2C System, provided that the system
conforms to the I2C Standard Specification defined by Philips
PT2315A V1.1
-1-
December, 2006
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URL: http://www.princeton.com.tw
2-Channel Audio Processor IC
BLOCK DIAGRAM
PT2315A
L OU D_L
9
B OU T_L B IN _L
12
13
TRE B_ L
4
RB
L IN
Vo lu me
&
L ou d ne ss
11
B ass
Tre ble
S pe ake r
ATT
17
L OU T
Mu te
S er ial B u s D eco de r & La tche s
20
CL K
19
DATA
18
DG ND
16
RO UT
S pe ake r
ATT
RIN
Vo lu me
&
L ou d ne ss
6
B ass
Tre ble
Mu te
RB
S up pl y
2
3
1
V DD A GN D RE F
PT2315A V1.1
7
L OU D_R
15
14
B OU T_R B IN _R
-2-
5
TRE B _R
December, 2006
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2-Channel Audio Processor IC
PT2315A
PIN CONFIGURATION
RE F
1
20
CLK
VD D
2
19
D ATA
AG N D
3
18
DGND
T R EB _ L
4
17
LOUT
T R EB _ R
5
16
ROUT
RIN
6
15
BO U T_ R
LOUD_R
7
14
BI N _ R
NC
8
13
BO U T_ L
LOUD_L
9
12
BI N _ L
11
L IN
PT23 15A
NC 10
PIN DESCRIPTION
Pin Name
REF
VDD
AGND
TREB_L
TREB_R
RIN
LOUD_R
NC
LOUD_L
LIN
BIN_L
BOUT_L
BIN_R
BOUT_R
ROUT
LOUT
DGND
DATA
CLK
PT2315A V1.1
I/O
I
I
I
I
I
I
I
O
I
O
O
O
I
I
Description
Analog Reference Voltage (1/2 VDD)
Supply Input Voltage
Analog Ground
Left Channel Input for Treble Controller
Right Channel Input for Treble Controller
Audio Processor Right Channel Input
Right Channel Loudness Input
No Connection
Left Channel Loudness Input
Audio Processor Left Channel Input
Left Bass Controller Input Channel
Left Bass Controller Output Channel
Right Channel Input for Bass Controller
Right Channel Output for Bass Controller
Right Speaker Output
Left Speaker Output
Digital Ground
Control Data Input
Clock Input for Serial Data Transmission
-3-
Pin No.
1
2
3
4
5
6
7
8, 10
9
11
12
13
14
15
16
17
18
19
20
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2-Channel Audio Processor IC
PT2315A
FUNCTION DESCRIPTION
I2C BUS INTERFACE
Data are transmitted to and from the microprocessor to the PT2315A via the DATA and CLK. The
DATA and CLK make up the BUS Interface.
DATA VALIDITY
A data on the DATA Line is considered valid and stable only when the CLK Signal is in HIGH State. The
HIGH and LOW State of the DATA Line can only change when the CLK signal is LOW. Please refer to
the figure below.
DATA
CLK
DATA LINE
STABLE,
DATA VALID
DATA
CHANGE
ALLOWED
START AND STOP CONDITIONS
A Start Condition is activated when
1) CLK is set to HIGH and
2) DATA shifts from HIGH to LOW State.
The Stop Condition is activated when
1) CLK is set to HIGH and
2) DATA shifts from LOW to HIGH State.
Please refer to the timing diagram below.
CLK
DATA
ST OP
START
PT2315A V1.1
-4-
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2-Channel Audio Processor IC
PT2315A
BYTE FORMAT
Every byte transmitted to the DATA Line consist of 8 bits. Each byte must be followed by an
Acknowledge Bit. The MSB is transmitted first.
ACKNOWLEDGE
During the Acknowledge Clock Pulse, the master (µP) puts a resistive HIGH level on the DATA Line.
The peripheral (audio processor) that acknowledges has to pull-down (LOW) the DATA line during the
Acknowledge Clock Pulse so that the DATA Line is in a Stable Low State during this Clock Pulse.
Please refer to the diagram below.
1
CLK
DATA
2
3
4
7
8
9
MSB
AC KNOWLED GE MENT
F ROM RECE IV ER
START
The audio processor that has been addressed has to generate an acknowledge after receiving each
byte, otherwise, the DATA Line will remain at the High Level during the ninth (9th) Clock Pulse. In this
case, the master transmitter can generate the STOP Information in order to abort the transfer.
TRANSMISSION WITHOUT ACKNOWLEDGE
If you want to avoid the acknowledge detection of the audio processor, a simpler µP transmission may
be used. Wait one clock and do not check the slave acknowledge of this same clock then send the new
data. If you use this approach, there are greater chances of faulty operation as well as decrease in
noise immunity.
INTERFACE PROTOCOL
The interface protocol consists of the following:
• A Start Condition
• A Chip Address Byte including the PT2315A address. The 8th Bit of the Byte must be “0”. PT2315A
must always acknowledge the end of each transmitted byte.
• A Data Sequence (N-Bytes + Acknowledge)
• A Stop Condition
PT2315A V1.1
-5-
December, 2006
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2-Channel Audio Processor IC
PT2315A
Please refer to the diagram below:
PT2315 ADDRESS
MSB FIRST BYTE LSB
MSB
START 1 0 0 0 0 0 0 0 ACK
LSB
MSB
ACK
DATA
LSB
ACK STOP
DATA
DATA TRANSMITTED (N-BYTES + ACKNOWLEDGE)
Notes:
1. ACK=Acknowledge
2. Max. Clock Speed=100K Bits/s
SOFTWARE SPECIFICATION
PT2315A ADDRESS
PT2315A Address is shown below.
1
MSB
0
0
0
0
0
0
0
LSB
DATA BYTES
MSB
LSB
0
0
B2
B1
B0
A2
A1
A0
1
0
0
B1
B0
A2
A1
A0
1
0
1
B1
B0
A2
A1
A0
0
1
0
*
*
L
*
*
0
1
1
0
C3
C2
C1
C0
0
1
1
1
C3
C2
C1
C0
where Ax=1.25dB steps; Bx=10dB steps; Cx=2dB steps; *=no effect
PT2315A V1.1
-6-
Function
Volume Control
Speaker ATT L
Speaker ATT R
Loudness Control
Bass Control
Treble Control
December, 2006
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2-Channel Audio Processor IC
PT2315A
I2C BUS INTERFACE START TIME
After Power is turned ON, PT2315A needs to wait for a short time in order to insure stability. This
waiting period is relative to the value of Cref. As the Cref value is 10µf, the waiting time period for
PT2315A to send I2C Bus Signal is at least 300ms. If the waiting time period is less than 300ms, I2C
Control may fail. Please refer to the diagram below.
V
POWER ON
90% VDD
VDD
at least 300 mS
SDA/SCL
PT2315A V1.1
-7-
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2-Channel Audio Processor IC
PT2315A
VOLUME
The table below gives a detailed description of the Volume Data Bytes. For example, a volume of
-37.5dB is given by 0 0 0 1 1 1 1 0.
MSB
LSB
Function
0
0
B2
B1
B0
A2
A1
A0
Volume 1.25dB steps
0
0
0
0
0
0
1
-1.25
0
1
0
-2.5
0
1
1
-3.75
1
0
0
-5
1
0
1
-6.25
1
1
0
-7.5
1
1
1
-8.75
0
0
B2
B1
B0
A2
A1
A0
Volume 10dB steps
0
0
0
0
0
0
1
-10
0
1
0
-20
0
1
1
-30
1
0
0
-40
1
0
1
-50
1
1
0
-60
1
1
1
-70
PT2315A V1.1
-8-
December, 2006
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2-Channel Audio Processor IC
PT2315A
SPEAKER ATTENUATORS
The table below gives a detailed description of the speaker attenuators data bytes. For example, an
attenuation of 30dB on the Speaker L (Left) is given by 1 0 0 1 1 0 0 0.
MSB
LSB
Function
1
0
0
B1
B0
A2
A1
A0
Speaker L
1
0
1
B1
B0
A2
A1
A0
Speaker R
0
0
0
0
0
0
1
-1.25
0
1
0
-2.5
0
1
1
-3.75
1
0
0
-5
1
0
1
-6.25
1
1
0
-7.5
1
1
1
-8.75
0
0
0
0
1
-10
1
0
-20
1
1
-30
1
1
1
1
1
Mute
LOUDNESS FUNCTION
The following table shows the detailed description of the Loudness Function. For example, when the
Loudness Function is turned ON, the code format is 0 1 0 0 0 0 0 0
MSB
LSB
Function
0
1
0
*
*
L
*
*
Loudness Control
0
Loudness ON
1
Loudness OFF
Note: *=No Effect
PT2315A V1.1
-9-
December, 2006
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2-Channel Audio Processor IC
PT2315A
BASS AND TREBLE DATA BYTES
The following table shows a detailed description of the Bass and Treble Data Byte. For example a
Treble at -12dB is given by 0 1 1 1 0 0 0 1.
MSB
LSB
Function
0
1
1
0
C3
C2
C1
C0
Bass
0
1
1
1
C3
C2
C1
C0
Treble
0
0
0
0
-14
0
0
0
1
-12
0
0
1
0
-10
0
0
1
1
-8
0
1
0
0
-6
0
1
0
1
-4
0
1
1
0
-2
0
1
1
1
0
1
1
1
1
1
1
1
1
PT2315A V1.1
- 10 -
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
2
4
6
8
10
12
14
December, 2006
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2-Channel Audio Processor IC
PT2315A
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating supply voltage
Input current, any pin except supplies
Input voltage (see Note)
Operating temperature
Symbol
VS
Iin
Vin
Min.
-10
-0.3
Max.
10.5
10
VS+0.3
Topr
-40
85
Unit
V
mA
V
℃
Storage temperature
Tstg
-65
Note: Transient Currents of up to 100mA will not cause SCR latch-up.
150
℃
QUICK REFERENCE DATA
Parameter
Supply voltage
Max. input signal handling
Total harmonic distortion
(V = 1Vrms, f = 1KHz)
Signal to noise ratio
Channel separation
(f=1KHz)
Volume control 1.25dB step
Bass & treble control 2dB step
Balance control 1.25dB step
Mute attenuation
PT2315A V1.1
Symbol
VS
VCL
Min.
6
2
Typ.
9
2.5
Max.
10
-
Unit
V
Vrms
THD
-
0.03
0.07
%
S/N
-
95
-
dB
Sc
-
85
-
dB
-75
-14
-37.5
-
95
0
+14
0
-
dB
dB
dB
dB
- 11 -
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2-Channel Audio Processor IC
PT2315A
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, Ta=25℃, VDD=9V, RL=100KΩ, Rg=600Ω, all controls flat<G=0>, f=1KHz)
Parameter
Symbol Test Condition
Min.
Typ.
Max. Unit
Supply
Supply voltage
VDD
6
9
10
V
Supply current
IS
30
40
mA
Volume Control
Input resistance
RIV
15
25
35
KΩ
Control range
CRANGE
70
75
80
dB
Min. attenuation
AVMIN
-1
0
1
dB
Max. attenuation
AVMAX
70
75
80
dB
Step resolution
ASTEP
0.5
1.25
1.75
dB
-1.25
1.25
dB
AV=0 to -20dB
Attenuation set error
EA
0
AV=-20 to -60dB
-3.0
2.0
dB
Speaker Attenuators
Control range
CRANGE
35
37.5
40
dB
Step resolution
SSTEP
0.5
1.25
1.75
dB
Attenuation set error
EA
1.5
dB
Output mute attenuation
AMUTE
90
95
dB
Bass Control (see Note)
Control range
Gb
Max. Boost/Cut
±12
±14
±16
dB
Step resolution
BSTEP
1
2
3
dB
Internal feedback resistance
RB
40
50
60
KΩ
Treble Control (see Note)
Control range
Gt
Max. Boost/Cut
±13
±14
±15
dB
Step resolution
TSTEP
1
2
3
dB
Audio Outputs
Clipping level
VOCL
AV=-8.75dB, d=0.3%
2
2.5
Vrms
Output resistance
ROUT
40
45
Ω
DC voltage level
VOUT
4.2
4.5
4.8
V
Load impedance
RL
10
KΩ
PT2315A V1.1
- 12 -
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2-Channel Audio Processor IC
Parameter
General
Output noise
Signal to noise ratio
PT2315A
Symbol
NO
S/N
Test Condition
BW=20~20KHz, flat
Output Muted
All gains=0dB
A Curve
All Gains=0dB
All Gains=0dB
VO=1Vrms
AV=0,VIN=1Vrms
AV=0dB,
VIN=0.2Vrms
Min.
Typ.
Max.
Unit
-
-100
-95
-
dB
-
-98
-
dB
-
95
-
dB
-
0.03
0.03
0.07
0.05
%
Distortion
D
Channel separation left/right
Bus Inputs
Input low voltage
Input high voltage
Input current
Output voltage SDA acknowledge
Sc
80
90
-
dB
VIL
VIH
IIN
VO
3
-5
-
-
1
+5
0.4
V
V
µA
V
IO=1.6mA
Note: For the Bass and Treble Response, please refer to the diagram below. The center frequency
and quality of the resonance behavior can be selected by the external circuitry. A standard first
order bass response can realized by a standard feedback network.
PT2315A V1.1
- 13 -
December, 2006
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2-Channel Audio Processor IC
PT2315A
(dB) RESPONSE
FREQUENCY (HZ)
Typical Tone Response
dB
Hz
Loudness vs Volume Attenuation Frequency Response (C10=C11=100nF)
PT2315A V1.1
- 14 -
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2-Channel Audio Processor IC
PT2315A
OPEN
dB
56nF
220nF
33nF
10nF
100nF
Shorted to
Hz
C10, C11 vs. Loudness Frequency Response (Volume=-40dB, All other controls are flat)
PT2315A V1.1
- 15 -
December, 2006
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2-Channel Audio Processor IC
PT2315A
ELECTRICAL CHARACTERISTICS DIAGRAMS
20
10
+20
5
+0
2
-20
1
0.5
%
0.2
d
B
0.1
0.05
0.02
-40
-60
-80
0.01
0.005
-100
0.002
0.001
1m
2m
5m 10m 20m
100m
500m 1
2
-120
20
5
V
50
100
200
500
1k
2k
5k
10k 20k
Hz
Total Harmonic Distortion and Amplitude
1Vrms Output FFT Analysis
+0
-20
-40
d
B
-60
-80
-100
-120
-140
20
50
100
200
500
1k
2k
5k
10k 20k
Hz
Left and Right Channel Crosstalk
PT2315A V1.1
- 16 -
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2-Channel Audio Processor IC
PT2315A
APPLICATION CIRCUIT
R2
5.6K
C4
100n
MCU
18
+
C2
2.2µ
+
C10
2.7n
20
9
13
12
4
LOUD_L
BOUT_L
BIN_L
TREB_L
R
11 RIN
AM/FM
Tuner
C1
2.2µ
C7
100n
CLK
19
DGND DATA
C6
100n
6
LOUT 17
C12
10µ
+
LIN
R
PT2315A
ROUT 16
+
C13
10µ
VDD
VDD
AGND
REF
LOUD_R
BOUT_R
2
3
1
7
15
C3
22µ
+
C5
100n
C8
100n
BIN_R TREB_R
5
14
C9
100n
C11
2.7n
R1
5.6K
Notes:
1. It is suggested that you use Mylar Capacitor for capacitors, C4 ~ C11.
2. Recommended Value of Resistor (R)=1K.
PT2315A V1.1
- 17 -
December, 2006
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2-Channel Audio Processor IC
PT2315A
ORDER INFORMATION
Valid Part Number
PT2315A-D
PT2315A
PT2315A-D (L)
PT2315A (L)
Package Information
20 Pins, DIP, 300mil
20 Pins, SOP, 300mil
20 Pins, DIP, 300mil
20 Pins, SOP, 300mil
Top Code
PT2315A-D
PT2315A
PT2315A-D
PT2315A
Notes:
1. (L), (C) or (S) = Lead Free.
2. The Lead Free mark is put in front of the date code.
PT2315A V1.1
- 18 -
December, 2006
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URL: http://www.princeton.com.tw
2-Channel Audio Processor IC
PT2315A
PACKAGE INFORMATION
20 PINS, DIP, 300MIL
PT2315A V1.1
- 19 -
December, 2006
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2-Channel Audio Processor IC
Symbol
A
A1
A2
b
b1
b2
b3
c
c1
D
D1
E
E1
e
eA
eB
eC
L
PT2315A
Min.
0.015
0.115
0.014
0.014
0.045
0.030
0.008
0.008
0.980
0.005
0.300
0.240
0.000
0.115
Nom.
Max.
0.210
0.130
0.018
0.018
0.060
0.039
0.010
0.010
1.030
0.195
0.022
0.020
0.070
0.045
0.014
0.011
1.060
0.310
0.250
0.100 bsc.
0.300 bsc.
0.325
0.280
0.130
0.430
0.060
0.150
Notes:
1. All dimensions are in INCHES.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension ”A”, ”A1” and ”L” are measured with the package seated in JEDEC Seating Plane Gauge
GS-3
4. “D”,”D1” and “E1” dimensions do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed 0.010 inch.
5. “E” and “eA” measured with the leads constrained to be perpendicular to datum -c- .
6. “eB” and “eC” are measured at the lead tips with the leads unconstrained.
7. N is the number of the terminal positions (N=20)
8. Pointed or rounded lead tips are preferred to ease insertion.
9. “b2” and “b3” maximum dimensions are not include dambar protrusions. Dambar protrusions shall
not exceed 0.010 inch (0.25mm)
10. Distance between leads including Dambar protrusions to be 0.005 inch minimum.
11. Datum plane -H- coincident with the bottom of lead, where lead exits body.
12. Refer to JEDEC MS-001, Variation AD.
JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.
PT2315A V1.1
- 20 -
December, 2006
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2-Channel Audio Processor IC
PT2315A
20 PINS, SOP, 300MIL
Symbol
A
A1
B
C
D
E
e
H
h
L
α
PT2315A V1.1
Min.
2.35
0.10
0.33
0.23
12.60
7.40
Nom.
Max.
2.65
0.30
0.51
0.32
13.00
7.60
1.27 bsc.
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
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December, 2006
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URL: http://www.princeton.com.tw
2-Channel Audio Processor IC
PT2315A
Notes:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold Flash, protrusion or gate
burrs shall not exceed 0.15 mm (0.006 in) per side.
3. Dimension “E” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm (0.010 in) per side.
4. The chamfer on the body is optional. It is not present, a visual index feature must be located within
the crosshatched area.
5. “L” is the length of the terminal for soldering to a substrate.
6. N is the number of the terminal positions (N=20)
7. The lead width “B” as measured 0.36 mm (0.014 in) or greater above the seating plane, shall not
exceed a maximum value of 0.61 mm (0.24 in).
8. Controlling dimension: MILLIMETER.
9. Refer to JEDEC MS-013, Variation AC.
JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.
PT2315A V1.1
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December, 2006