POWERINT DI-124

Design Idea DI-124
®
LinkSwitch-TN
Ultra-wide Input Range (57-580 VAC) Flyback Power Supply
Application
Device
Power Output
Input Voltage
Output Voltage
Topology
Metering / Industrial
LNK304
3W
57-580 VAC
12 V, 250 mA
StackFET Flyback
Design Highlights
•
A 600 V MOSFET, Q1, and U1 are arranged in the StackFET
configuration (cascode). The drain of U1 drives the source
of Q1 while the drain of Q1 drives the transformer primary.
The drain voltage of U1 is limited to 450 V by VR1-3. This
extends the maximum peak composite drain voltage of U1
and Q1 to 1050 V. The resistor chain R6-R8 provides startup
charge for the gate of Q1 and R9 dampens high-frequency
ringing. Once the converter is operating, the gate is largely
driven by the charge stored in the capacitance of VR1-3.
Zener VR4 limits the gate to source voltage of Q1. Leakage
inductance energy is clamped by VR5 and D9 with R10 added
to reduce ringing and thereby, EMI.
StackFET flyback topology delivers full load over
extremely wide input voltage range
E-ShieldTM transformer construction for reduced
common-mode EMI (>10 dBµV margin)
66 kHz switching frequency with jitter reduces
conducted EMI
Simple ON/OFF controller – no feedback compensation
required
Auto-restart function for automatic and self-resetting
open-loop, overload and short circuit protection
Built-in hysteretic thermal shutdown at 135 ºC
TM
•
•
•
•
•
The operation of U1 is unaffected by the StackFET
configuration. When the internal MOSFET turns on, Q1 is also
turned on, applying the input voltage across the transformer
primary. Once the primary current reaches the internal current
limit of U1, the MOSFET is turned off and the energy stored
is delivered to the output. Regulation is maintained using
ON/OFF control. Switching cycles are enabled/disabled based
on current into the FEEDBACK pin of U1. This is ideal as
it results in a lowering of the effective switching frequency
Operation
The AC input is rectified and filtered and the resultant DC
applied to one end of the transformer primary winding. The
450 V input capacitors are stacked with parallel balancing
resistors to meet the required voltage rating. Resistors R1 to
R4 provide fusing in case of a catastrophic failure. Inductor
L1, C1 and transformer E-Shield windings allow the design
to meet EN55022 B conducted limits with good margin.
C1
2.2 nF
250 VAC
D1
1N4007
D2
1N4007
D3
1N4007
D4
1N4007
C5
15 µF
450 V
J1
R1
J2
10 Ω 1 W
R2
10 Ω 1 W
J3
J4
C7
15 µF
450 V
R3
10 Ω 1 W
R4
10 Ω 1 W
D5
1N4007
R13
475 kΩ
1%
0.5 W
R15
475 kΩ
1%
0.5 W
C6
15 µF
450 V
C9
5.6 nF
1 kV
C8
15 µF
450 V
R14
475 kΩ
1%
0.5 W
R16
475 kΩ
1%
0.5 W
R5
1k
D6
1N4007
D7
1N4007
D8
1N4007
L1
1 mH
VR1
P6KE150A
R6
680 kΩ
0.5 W
R7
680 kΩ
0.5 W
VR5
P6KE150A
D9
UF4007
EEL16
NC
4
L2
J5
Ferrite Bead
5
C2
470 µF
16 V
7
9
R10
R8 200 Ω
680 kΩ 1%
0.5 W
D10
UF4004
C3
100 µF
16 V
J6
1
10
T1
R9
10 Ω
Q1
IRFBC20
VR4
1N5245B
15 V
R11
330 Ω
D
U1
LNK304P
VR2
P6KE150A
VR3
P6KE150A
FB
U2B
PC817A
BP
U2A
PC817A
R12
1 kΩ
S
C4
100 nF
50 V
VR6
BZX79-C11
11 V
PI-4487-081506
Figure 1. Schematic Diagram of 3 W Bias Supply using LinkSwitch-TN in StackFET Configuration.
DI-124
September 2006
DI-89 DI-124
75
Efficiency (%)
70
Key Design Points
• The input stage (to the left of C9) can be omitted in
applications that have a high-voltage DC bus. Capacitor
C9 is still required to provide local decoupling.
• Long cores (EEL) are ideal for this application to provide
greater bobbin width to accommodate the increased
margins required to meet safety spacings at the high
operating voltage.
• Zener diodes VR1-3 can be replaced with a single
P6KE540 device.
• The value of capacitors C5 to C8 can be reduced to 10 µF
if operation down to 57 VAC is not required (100 VAC
minimum).
• Use 0.5 W resistors for R13-16 and R6-8 to provide
adequate voltage rating.
• Efficiency falls at high line due to switching losses.
Reducing transformer capacitance by adding layers of
tape between the primary winding layers minimizes this.
70
45
40
50
dBµV
350
450
550
TRANSFORMER PARAMETERS
Core Material
Bobbin
EEL16, gap for ALG of 70 nH/T2
6+4 pin (Ying Chin YC-1604-1)
with 3 mm + 3 mm tape margins
AV
Winding Order
(pin numbers)
Shield (5-NC), tape, primary
(7-5), tape between layers,
shield (9-10), tape, 12 V / (4-1),
tape
QP
Inductance
Primary: 3.5 mH ±10%
Leakage: 160 µH (max)
Primary Resonant
500 kHz (min)
Frequency
AV
0
Table 1. Transformer Design Parameters.
-10
-20
0.15
250
Figure 3. Full Load Efficiency vs. Input Voltage.
20
10
150
AC Input Voltage (V)
40
30
55
Winding Details
QP
50
60
Shield: 23T, 2 × 36 AWG
Primary: 184T, 36 AWG
Shield: 12T, 2 × 29 AWG
Secondary: 30T, 29 AWG TIW
EN55022B Limits
60
65
50
PI-4492-090706
80
PI-4493-081806
80
with load, scaling switching losses and maximizing efficiency.
The use of LinkSwitch-TN further improves efficiency due to
its 66 kHz switching frequency.
TIW = Triple Insulated Wire, NC = No Connect, FL = Flying Lead
1.0
10.0
100.0
MHz
Figure 2. Conducted EMI (230 VAC, EN55022B Limits,
AV and QP Results).
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Rev. A 09/06