MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts General Description Features The MAX16056–MAX16059 are ultra-low-current 125nA (typ) microprocessor (µP) supervisory circuits that monitor a single system supply voltage. These devices assert an active-low reset signal whenever the V CC supply voltage drops below the factory-trimmed reset threshold, manual reset is pulled low, or the watchdog timer runs out (MAX16056/MAX16058). The reset output remains asserted for an adjustable reset timeout period after V CC rises above the reset threshold. Factorytrimmed reset threshold voltages are offered from 1.575V to 4.625V in approximately 100mV increments (see Table 1). o Ultra-Low 125nA (typ) Supply Current o 1.1V to 5.5V Operating Supply Range o Factory-Set Reset Threshold Options from 1.575V to 4.625V in Approximately 100mV Increments o Capacitor-Adjustable Reset Timeout o Capacitor-Adjustable Watchdog Timeout (MAX16056/MAX16058) o Watchdog Timer Capacitor Open Detect Function o Optional Watchdog Disable Function (MAX16056/MAX16058) o Manual Reset Input o Guaranteed RESET Valid for VCC ≥ 1.1V o Push-Pull or Open-Drain RESET Output Options o Power-Supply Transient Immunity o Small, 3mm x 3mm TDFN Package These devices feature adjustable reset and watchdog timeout using external capacitors. The MAX16056/ MAX16058 contain a watchdog timer with a watchdog select input (WDS) that multiplies the watchdog timeout period by 128. The MAX16057/MAX16059 do not have the watchdog feature. The MAX16056–MAX16059 are available in either pushpull or open-drain output-type configurations (see the Ordering Information). These devices are fully specified over the -40°C to +125°C automotive temperature range. The MAX16056/MAX16058 are available in the 8-pin TDFN package, and the MAX16057/MAX16059 are available in the 6-pin TDFN package. Applications Portable/Battery-Powered Equipment PDAs/Cell Phones MP3 Players/Pagers Glucose Monitors/Patient Monitors Metering/HVAC Typical Operating Circuit appears at end of data sheet. Ordering Information PINPACKAGE PART MAX16056ATA_ _+T 8 TDFN-EP* MAX16057ATT_ _+T 6 TDFN-EP* RESET OUTPUT WATCHDOG TIMER Push-Pull Yes Push-Pull No MAX16058ATA_ _+T 8 TDFN-EP* Open-Drain Yes MAX16059ATT_ _+T Open-Drain No 6 TDFN-EP* Note: All devices are specified over the -40°C to +125°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad. “_ _” represents the two number suffix needed when ordering the reset threshold voltage value (see Table 1). Standard versions and their package top marks are shown in Table 3 at the end of data sheet. Pin Configurations TOP VIEW VCC WDS WDI SRT VCC N.C. SRT 8 7 6 5 6 5 4 MAX16056 MAX16058 MAX16057 MAX16059 EP 1 2 RESET GND EP 3 4 1 2 3 SWT MR RESET GND MR TDFN *CONNECT EXPOSED PAD TO GND. TDFN For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-4686; Rev 2; 4/13 MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts ABSOLUTE MAXIMUM RATINGS Junction-to-Ambient Thermal Resistance (θJA) (Note 1) 6-Pin TDFN ...................................................................42°C/W 8-Pin TDFN ...................................................................41°C/W Junction-to-Case Thermal Resistance (θJC) (Note 1) 6-Pin TDFN .....................................................................9°C/W 8-Pin TDFN .....................................................................8°C/W Operating Temperature Range .........................-40°C to +125°C Storage Temperature Range .............................-65°C to +150°C Junction Temperature .....................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C VCC to GND ..............................................................-0.3V to +6V SRT, SWT, WDS, MR, WDI, to GND ...........-0.3V to (VCC + 0.3V) RESET (Push-Pull) to GND .........................-0.3V to (VCC + 0.3V) RESET (Open-Drain) to GND ...................................-0.3V to +6V Input Current (all pins) .................................................... ±20mA Output Current (RESET) ................................................. ±20mA Continuous Power Dissipation (TA = +70°C) 6-Pin TDFN (derate 23.8mW/°C above +70°C) .........1905mW 8-Pin TDFN (derate 24.4mW/°C above +70°C) .........1951mW Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 1.2V to 5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 2) PARAMETER Supply Voltage Supply Current SYMBOL VCC ICC CONDITIONS MIN Hysteresis VTH VHYST 5.5 TA = -40°C to 0°C 1.2 5.5 VCC > VTH + 150mV, no load, reset output deasserted (Note 3) VCC = 5.0V, TA = -40°C to +85°C 142 210 VCC = 3.3V, TA = -40°C to +85°C 132 185 VCC = 1.8V, TA = -40°C to +85°C 125 175 VCC = 5.0V, TA = -40°C to +125°C 142 430 VCC = 3.3V, TA = -40°C to +125°C 132 415 VCC = 1.8V, TA = -40°C to +125°C 125 400 VCC falling (see Table 1) UNITS V nA 7 15 TA = +25°C VTH 1.5% VTH + 1.5% TA = -40°C to +125°C VTH 2.5% VTH + 2.5% µA V VCC rising 0.5 % 80 µs VCC to Reset Delay tRD VCC falling from (VTH + 100mV) to (VTH - 100mV) at 10mV/µs Reset Timeout Period tRP CSRT = 2700pF (Note 4) 2 MAX 1.1 VCC < VTH, no load, reset output asserted VCC Reset Threshold TYP TA = 0°C to +125°C 10.5 14.18 17.0 ms Maxim Integrated MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts ELECTRICAL CHARACTERISTICS (continued) (VCC = 1.2V to 5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS SRT Ramp Current IRAMP1 TA = -40°C to VSRT = 0V to VRAMP1, +125°C VCC = 1.6V to 5V TA = +25°C SRT Ramp Threshold VRAMP1 VCC = 1.6V to 5V (VRAMP rising) Watchdog Timeout Clock Period SWT Ramp Current SWT Ramp Threshold tWDPER IRAMP2 VRAMP2 VOL TA = +25°C TA = -40°C to +125°C TA = -40°C to VSWT = 0V to VRAMP2, +125°C VCC = 1.6V to 5V TA = +25°C VCC = 1.6V to 5V (VRAMP2 rising) MIN TYP MAX 197 240 282 210 240 270 1.173 1.235 1.297 5 6.4 8 3.5 6.4 9.5 197 240 282 210 240 270 1.173 1.235 1.297 0.3 VCC ≥ 2.7V, ISINK = 1.2mA 0.3 VCC ≥ 4.5V, ISINK = 3.2mA VOH RESET Output-Leakage Current, Open Drain ILKG MAX16056/MAX16057 0.8 x VCC VCC ≥ 2.25V, ISOURCE = 500µA 0.8 x VCC VCC ≥ 4.5V, ISOURCE = 800µA 0.8 x VCC 1.0 0.7 x VCC tMPW µs 200 tMRD ns 250 WDI Minimum Pulse Width (Note 5) 150 Input Leakage Current MR, WDI, WDS is connected to GND or VCC -100 Note 2: Note 3: Note 4: Note 5: µA V 1 MR Glitch Rejection MR to RESET Delay V 0.3 x VCC VIL MR Minimum Pulse Width ms V VCC > VTH, reset not asserted, VRESET = 5.5V (MAX16058/MAX16059) Input-Logic Levels V 0.4 VCC ≥ 1.8V, ISOURCE = 200µA VIH nA nA VCC ≥ 1.0V, ISINK = 50µA RESET Output Voltage UNITS ns ns +100 nA Devices are production tested at TA = +25°C. Specifications over temperature limits are guaranteed by design. WDI input period is 1s with tRISE and tFALL < 50ns. Worst case of SRT ramp current and voltage is used to guarantee minimum and maximum limits. Guaranteed by design, not production tested. Maxim Integrated 3 MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Typical Operating Characteristics (VCC = 2.5V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE TA = -40NC TA = +25NC 1.4 200 150 1.2 1.0 0.8 0.6 100 0.1 MAX16056 toc03 1.6 VCC = 3.3V 50 VCC = 1.8V 0.4 0.2 0 0 0 50 100 150 200 250 300 -40 -25 -10 5 20 35 50 65 80 95 110 125 VCC (V) TEMPERATURE (NC) CSRT (nF) NORMALIZED RESET TIMEOUT PERIOD vs. TEMPERATURE NORMALIZED WATCHDOG TIMEOUT PERIOD vs. TEMPERATURE MAXIMUM VCC TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVE 1.03 1.02 1.00 0.98 1.02 1.01 1.00 0.99 0.96 0.98 0.94 0.97 0.92 0.96 0.90 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (NC) TEMPERATURE (NC) VCC FALLING FROM VTH + 100mV 10 100 1000 VCC TO RESET DELAY vs. TEMPERATURE MAX16056 toc07 120 VCC = VTH + 100mV TO VTH - 100mV 110 1.010 100 1.005 tRD (Fs) NORMALIZED VTH 10 RESET THRESHOLD OVERDRIVE (mV) NORMALIZED RESET THRESHOLD VOLTAGE vs. TEMPERATURE 1.015 RESET OCCURS ABOVE THIS LINE 100 1 0.95 -40 -25 -10 5 20 35 50 65 80 95 110 125 1.020 1000 MAX16056 toc08 NORMALIZED tWD 1.04 1.04 TRANSIENT DURATION (Fs) 1.06 MAX16056 toc05 1.05 MAX16056 toc04 1.08 MAX16056 toc06 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.10 NORMALIZED tRP 1.8 VCC = 5.5V 250 VCC = 2.5V 1.000 0.995 90 80 70 0.990 60 0.985 50 0.980 4 2.0 MAX16056 toc02 300 RESET IS NOT ASSERTED VTH = 1.575V tRP (s) 1.0 TA = +85NC 350 SUPPLY CURRENT (nA) ICC (FA) VTH = 2.23V MAX16056 toc01 10.0 TA = +125NC RESET TIMEOUT PERIOD vs. CSRT SUPPLY CURRENT vs. TEMPERATURE -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (NC) TEMPERATURE (NC) Maxim Integrated MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Typical Operating Characteristics (continued) (VCC = 2.5V, TA = +25°C, unless otherwise noted.) RESET OUTPUT-LOW VOLTAGE vs. SINK CURRENT VCC = 1.8V 0.15 0.10 VCC = 3.3V 0.05 0 1.0 0.40 0.9 0.8 0.35 0.30 VCC = 1.8V 0.25 0.20 VCC = 3.3V 0.15 VCC = 2.5V 0.10 0.7 0.6 0.5 0.4 0.3 0.2 0.05 0.1 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 ISINK (mA) MAX16056 toc11 0.45 SUPPLY CURRENT (FA) VOL (V) 0.20 SUPPLY CURRENT vs. WATCHDOG SWITCHING FREQUENCY MAX16056 toc10 VCC = 2.5V 0.50 OUTPUT-HIGH VOLTAGE (VCC-VOH) (V) 0.25 MAX16056 toc09 0.30 RESET OUTPUT-HIGH VOLTAGE vs. SOURCE CURRENT 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.01 ISOURCE (mA) 0.1 1 10 1000 10,000 100 WATCHDOG SWITCHING FREQUENCY (kHz) MANUAL RESET DELAY vs. TEMPERATURE MANUAL RESET DELAY MAX16056 toc13 MAX16056 toc12 270 268 266 MR 1V/div tMRD (ns) 264 262 260 RESET 1V/div 258 256 254 252 250 -40 -25 -10 5 20 35 50 65 80 95 110 125 200ns/div TEMPERATURE (NC) RESET SOURCE CAPABILITY vs. SUPPLY VOLTAGE RESET SINK CAPABILITY vs. SUPPLY VOLTAGE VRESET = 0.8 x VCC 3.5 SOURCE CURRENT (mA) SINK CURRENT (mA) 8 7 6 5 4 3 2 MAX16056 toc15 VRESET = 0.3V 9 4.0 MAX16056 toc14 10 3.0 2.5 2.0 1.5 1.0 0.5 1 0 0 0 0.5 1.0 1.5 2.0 VCC (V) 2.5 3.0 3.5 4.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VCC (V) Maxim Integrated _______________________________________________________________________________________________________ 55 MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Pin Description PIN MAX16056/ MAX16058 MAX16057/ MAX16059 NAME FUNCTION Push-Pull or Open-Drain Reset Output. RESET asserts whenever VCC drops below the selected reset threshold voltage (VTH) or manual reset is pulled low. RESET remains low for the reset timeout period after all reset conditions are deasserted, and then goes high. The watchdog timer triggers a reset pulse (tRP) whenever a watchdog fault occurs (MAX16056/MAX16058). 1 1 RESET 2 2 GND Ground 3 — SWT Watchdog Timeout Input. Connect a capacitor between SWT and GND to set the basic watchdog timeout period (tWD). Determine the period by the formula tWD = Floor[CSWT x 5.15 x 106/6.4ms] x 6.4ms + 3.2ms (Note 6) with tWD in seconds and CSWT in Farads, or use Table 2. Extend the basic watchdog timeout period by using the WDS input. Connect SWT to ground to disable the watchdog timer function. The value of the capacitor must be between 2275pF and 0.54µF to have a valid watchdog timeout period. 4 3 MR Manual-Reset Input. Drive MR low to manually reset the device. RESET remains asserted for the reset timeout period after MR is released. There is no internal pullup on MR. MR must not be left unconnected. Connect MR to VCC if not used. SRT Reset Timeout Input. Connect a capacitor from SRT to GND to select the reset timeout period. Determine the period as follows: tRP = 5.15 x 106 x CSRT with tRP in seconds and CSRT in Farads, or use Table 2. The value of the capacitor must be between 39pF and 4.7µF. WDI Watchdog Input. A falling transition must occur on WDI within the selected watchdog timeout period or a reset pulse occurs. The watchdog timer clears when a falling transition occurs on WDI or whenever RESET is asserted. Connect SWT to ground to disable the watchdog timer function. 5 6 4 — 7 — WDS Watchdog Select Input. WDS selects the watchdog timeout mode. Connect WDS to ground to select normal mode. The watchdog timeout period is tWD. Connect WDS to VCC to select extended mode, multiplying the basic timeout period (tWD) by a factor of 128. A change in the state of WDS clears the watchdog timer. 8 6 VCC Supply Voltage. VCC is the power-supply input and the input for fixed threshold VCC monitor. For noisy systems, bypass VCC with a 0.1µF capacitor to GND. — 5 N.C. — — EP No Connection. Not internally connected. Exposed Pad. Connect EP to GND or leave unconnected. Note 6: Floor: take the integral value. 6 Maxim Integrated MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Detailed Description The MAX16056–MAX16059 are ultra-low-current 125nA (typ) µP supervisory circuits that monitor a single system supply voltage. These devices assert an active-low reset signal whenever the VCC supply voltage drops below the factory-trimmed reset threshold, manual reset is pulled low, or the watchdog timer runs out (MAX16056/MAX16058). The reset output remains asserted for an adjustable reset timeout period after VCC rises above the reset threshold. The reset and watchdog delay periods are adjustable using external capacitors. RESET Output The MAX16056–MAX16059 µP supervisory circuits assert a reset to prevent code-execution errors during powerup, power-down, and brownout conditions. The reset output is guaranteed to be valid for VCC down to 1.1V. When VCC falls below the reset threshold, the RESET output asserts low. Once VCC exceeds the reset threshold plus the hysteresis, an internal timer keeps the reset output asserted for the capacitor-adjusted reset timeout period (tRP), then after this interval the reset output deasserts (see Figure 1). The reset function features immunity to power-supply voltage transients. Manual-Reset Input (MR) Many µP-based products require manual-reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. The MAX16056– MAX16059 feature an MR input. A logic-low on MR asserts a reset. RESET remains asserted while MR is low and for the timeout period, tRP, after MR returns high. Connect MR to VCC if unused. MR can be driven with CMOS logic levels or with open-drain/collector outputs (with a pullup resistor). Connect a normally open momentary switch from MR to GND and a resistor from MR to VCC to implement a manual-reset function; external debounce circuitry is not required. If MR is driven by long cables or the device is used in a noisy environment, connect a 0.1µF capacitor from MR to GND to provide additional noise immunity. Maxim Integrated Watchdog Timer The MAX16056/MAX16058’s watchdog timer circuitry monitors the µP’s activity. If the µP does not toggle (high-to-low) the watchdog input (WDI) within the capacitor-adjustable watchdog timeout period (tWD), RESET asserts for the reset timeout period (tRP). The internal watchdog timer is cleared by: 1) any event that asserts RESET, by 2) a falling transition at WDI (that can detect pulses as short as 150ns) or by 3) a transition (high-to-low or low-to-high) at WDS. While reset is asserted, the watchdog timer remains cleared and does not count. As soon as reset deasserts, the watchdog timer resumes counting. There are two modes of watchdog operation, normal mode and extended mode. In normal mode (Figure 2), the watchdog timeout period is determined by the value of the capacitor connected between SWT and ground. In extended mode (Figure 3), the watchdog timeout period is multiplied by 128. For example, in extended mode, a 0.33µF capacitor gives a watchdog timeout period of 217s (see Table 2). To disable the watchdog timer function, connect SWT to ground. When VCC ramps above VTH + VHYST, the value of the external SWT capacitor is sampled after RESET goes high. When sampling is finished, the capacitor value is stored in the device and is used to set watchdog timeout. If RESET goes low before sampling is finished, the device interrupts sampling, and sampling is restarted when RESET goes high again. If the external SWT capacitor is less than 470pF, the sampling result sets the watchdog timeout to zero. This causes the watchdog to assert RESET continuously after sampling is finished. If a PCB manufacturing defect caused the connection to CSWT to be broken, the capacitance is very low and RESET is continuously asserted. If the external SWT capacitor is greater than 0.47µF, the sampling result sets the watchdog timeout to be infinite, disabling the watchdog function. 7 MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts VTH + VHYST VTH VCC tRP tRP tMRD tRD RESET tMPW MR Figure 1. RESET Timing Relationship VCC tRP tWD WDI 0V VCC RESET 0V NORMAL MODE (WDS = GND) Figure 2. Watchdog Timing Diagram, Normal Mode, WDS = GND VCC tWD x 128 WDI 0V VCC tRP RESET 0V EXTENDED MODE (WDS = VCC) Figure 3. Watchdog Timing Diagram, Extended Mode, WDS = VCC 8 Maxim Integrated MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Applications Information Selecting the Reset Timeout Capacitor The reset timeout period is adjustable to accommodate a variety of µP applications. To adjust the reset timeout period (tRP), connect a capacitor (CSRT) between SRT and ground. The reset timeout capacitor is calculated as follows: CSRT = tRP/(5.15 x 106) with tRP in seconds and CSRT in Farads. CSRT must be a low-leakage (< 10nA) type capacitor. A ceramic capacitor with low temperature coefficient dielectric (i.e., X7R) is recommended. Selecting Watchdog Timeout Capacitor The watchdog timeout period is adjustable to accommodate a variety of µP applications. With this feature, the watchdog timeout can be optimized for software execution. The programmer can determine how often the watchdog timer should be serviced. Adjust the watchdog timeout period (tWD) by connecting a capacitor (CSWT) between SWT and GND. For normal mode operation, calculate the watchdog timeout as follows: tWD = Floor[CSWT x 5.15 x 106/6.4ms] x 6.4ms + 3.2ms with tWD in seconds and CSWT in Farads. (Floor: take the integral value) (Figures 2 and 3) The maximum tWD is 296s. If the capacitor sets tWD greater than the 296s, tWD = infinite and the watchdog timer is disabled. CSWT must be a low-leakage (< 10nA) type capacitor. A ceramic capacitor with low temperature coefficient dielectric (i.e., X7R) is recommended. Watchdog Timeout Accuracy The watchdog timeout period is affected by the SWT ramp current (IRAMP2) accuracy, the SWT ramp threshold (VRAMP2) and the watchdog timeout clock period (tWDPER). In the equation above, the constant 5.15 x 106 is equal to VRAMP2/IRAMP2, and 6.4ms equals the watchdog timeout clock period. Calculate the timeout Maxim Integrated accuracy by substituting the minimum, typical, and maximum values into the equation. For example, if CSWT = 100nF. tWDMIN = Floor[100 x 10-9 x 1.173/(282 x 10-9)/9.5ms] x 3.5ms + 0.5 x 3.2ms = 141.7ms tWDNOM = Floor[100 x 10-9 x 1.235/(240 x 10-9)/6.4ms] x 6.4ms + 0.5 x 6.4ms = 515.2ms tWDMAX = Floor[100 x 10-9 x 1.297/(197 x 10-9)/3.5ms] x 9.5ms + 0.5 x 9.5ms = 1790.75ms Transient Immunity For applications with higher slew rates on VCC during power-up, additional bypass capacitance may be required. The MAX16056–MAX16059 are relatively immune to short-duration supply voltage transients, or glitches on VCC. The Maximum VCC Transient Duration vs. Reset Threshold Overdrive graph in the Typical Operating Characteristics shows this transient immunity. The area below the curve of the graph is the region where these devices typically do not generate a reset pulse. This graph was generated using a falling pulse applied to VCC, starting 100mV above the actual reset threshold (VTH) and ending below this threshold (reset threshold overdrive). As the magnitude of the transient increases, the maximum allowable pulse width decreases. Typically, a 100mV VCC transient duration of 40µs or less does not cause a reset. Using the MAX16056–MAX16059 for Reducing System Power Consumption Using the RESET output to control an external p-channel MOSFET to control the on-time of a power supply can result in lower system power consumption in systems that can be regularly put to sleep. By tying the WDI input to ground, the RESET output becomes a low-frequency clock output. When RESET is low, the MOSFET is turned on and power is applied to the system. When RESET is high, the MOSFET is turned off and no power is consumed by the system. This effectively reduces the shutdown current of the system to zero (Figure 4). 9 MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts BAT 1MΩ 0.1μF 0.1μF VCC VCC1 RESET μP MAX16056 MR WDI MANUAL POWER-ON SRT SWT CSWT GND WDS CSRT VCC RESET VCC1 tRP tWD tRP Figure 4. Using MAX16056–MAX16059 to Reduce System Power Consumption 10 Maxim Integrated MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Interfacing to Other Voltages for Logic Compatibility The open-drain RESET output can be used to interface to a µP with other logic levels. The open-drain output is connected to a voltage from 0V to 5.5V as shown in Figure 5. Generally, the pullup resistor connected to RESET connects to the supply voltage that is being monitored at the device’s VCC input. However, some systems use the open-drain output to level-shift from the supervisor’s monitored supply to another supply voltage. As the supervisor’s VCC decreases, so does the device’s ability to sink current at RESET. Ensuring a Valid RESET Down to VCC = 0V (Push-Pull RESET) When VCC falls below 1.1V, the current-sinking capability of RESET decreases drastically. The high-impedance CMOS logic inputs connected to RESET can drift to undetermined voltages. This presents no problems in most applications, since most µPs and other circuitry do not operate with VCC below 1.1V. In those applications where RESET must be valid down to 0, add a pulldown resistor between the MAX16056/MAX16057 push-pull RESET output and GND. The resistor sinks any stray leakage currents, holding RESET low (Figure 6). Choose a pulldown resistor that accommodates leakages, such that RESET is not significantly loaded and is capable of pulling to GND. The external pulldown cannot be used with the open-drain RESET output of the MAX16058/MAX16059. 3.3V 5V VCC VCC VCC MAX16058 MAX16059 VCC 100kΩ μP RESET MAX16056 MAX16057 RESET RESET 2MΩ GND GND Figure 5. Interfacing with Other Voltage Levels Maxim Integrated GND Figure 6. Ensuring RESET Valid to VCC = GND 11 MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Table 1. Threshold Suffix Guide SUFFIX 12 VCC THRESHOLD FALLING (V) MIN TYP MAX 46 4.509 4.625 4.741 45 4.388 4.500 4.613 44 4.266 4.375 4.484 43 4.193 4.300 4.408 42 4.095 4.200 4.305 41 3.998 4.100 4.203 40 3.900 4.000 4.100 39 3.802 3.900 3.998 38 3.705 3.800 3.895 37 3.608 3.700 3.793 36 3.510 3.600 3.690 35 3.413 3.500 3.588 34 3.315 3.400 3.485 33 3.218 3.300 3.383 32 3.120 3.200 3.280 31 2.998 3.075 3.152 30 2.925 3.000 3.075 29 2.852 2.925 2.998 28 2.730 2.800 2.870 27 2.633 2.700 2.768 26 2.559 2.625 2.691 25 2.438 2.500 2.563 24 2.340 2.400 2.460 23 2.255 2.313 2.371 225 2.180 2.235 2.290 22 2.133 2.188 2.243 21 2.048 2.100 2.153 20 1.950 2.000 2.050 19 1.853 1.900 1.948 18 1.755 1.800 1.845 17 1.623 1.665 1.707 16 1.536 1.575 1.614 Maxim Integrated MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Table 2. Capacitor Selection Guide CAPACITANCE (pF) tRP (ms) tWD (ms) tWD x 128 (ms) 39 47 56 68 82 100 120 0 (no capacitor is connected) 150 180 220 270 330 Not recommended 390 470 560 680 820 1000 1200 Indeterminate (0, 9.6, or 16) Indeterminate (0, 1228.8, or 1636) 1641 1500 1800 2200 2700 14.18 16 3300 16.99 16 1641 3900 20.1 22.4 2460 4700 24.21 22.4 2460 5600 28.84 28.8 3280 6800 35.00 35.2 4099 8200 42.23 41.6 4918 10,000 51.5 54.4 6556 12,000 61.8 60.8 7376 15,000 77.25 80 9833 18,000 92.7 92.8 11,472 Maxim Integrated 13 MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Table 2. Capacitor Selection Guide (continued) CAPACITANCE (pF) 14 tRP (ms) tWD (ms) tWD x 128 (ms) 22,000 113.3 112 13,929 27,000 139.05 137.6 17,206 33,000 169.95 169.6 21,302 39,000 200.85 201.6 25,398 47,000 242.05 240 30,313 56,000 288.4 291.2 36,867 68,000 350.2 348.8 44,240 82,000 422.3 419.2 53,251 100,000 515 515.2 65,539 120,000 618 617.6 78,646 150,000 772.5 771.2 98,307 180,000 927 924.8 117,968 220,000 1133 1129.6 144,182 270,000 1390.5 1392 177,769 330,000 1699.5 1699.2 217,091 390,000 2008.5 2006.4 256,412 470,000 2420.5 2416 308,841 680,000 3502 820,000 4223 1,000,000 5150 1,500,000 7725 2,200,000 11,330 3,300,000 16,995 4,700,000 24,205 Indeterminate (may be infinite and watchdog is disabled) Infinite (watchdog is disabled) Maxim Integrated MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Table 3. Standard Versions Maxim Integrated PART TOP MARK MAX16056ATA17+ BKZ MAX16056ATA23+ BLA MAX16056ATA26+ BLB MAX16056ATA29+ BLC MAX16056ATA31+ BLD MAX16056ATA46+ BLE MAX16057ATT17+ ATQ MAX16057ATT23+ ATR MAX16057ATT26+ ATS MAX16057ATT29+ ATT MAX16057ATT31+ AUC MAX16057ATT46+ AUD MAX16058ATA16+ BLF MAX16058ATA22+ BLG MAX16058ATA26+ BLH MAX16058ATA29+ BLI MAX16058ATA31+ BLJ MAX16058ATA44+ BLK MAX16059ATT16+ ATW MAX16059ATT22+ ATX MAX16059ATT26+ ATY MAX16059ATT29+ ATZ MAX16059ATT31+ AUA MAX16059ATT44+ AUB 15 MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Typical Operating Circuit BAT 1MΩ 0.1μF VCC VCC RESET MAX16056 MR μP WDI MANUAL RESET SRT SWT CSWT GND CSRT Package Information Chip Information PROCESS: BiCMOS 16 WDS For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 8 TDFN-EP T833-2 21-0137 90-0059 6 TDFN-EP T633-2 21-0137 90-0058 Maxim Integrated MAX16056–MAX16059 125nA Supervisory Circuits with CapacitorAdjustable Reset and Watchdog Timeouts Revision History REVISION NUMBER REVISION DATE 0 6/09 DESCRIPTION Initial release PAGES CHANGED — 1 6/10 Updated Absolute Maximum Ratings, Electrical Characteristics, and Table 3. 2 4/13 Removed Automotive Infotainment from Applications sections 2, 3, 15 1 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 17 © 2013 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.