MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability General Description ♦ Programmable Switching Frequency from 500kHz to 4MHz ♦ Thermal Shutdown and Hiccup-Mode ShortCircuit Protection ♦ 20µA Shutdown Current ♦ 100% Maximum Duty Cycle ♦ Space-Saving (5mm x 5mm) 28-Pin TQFN Package RFID Reader Cards Power-over-Ethernet (PoE) IP Phones N.C. 18 17 16 15 N.C. 22 14 N.C. COMP2 23 13 N.C. 12 COMP1 11 FB1 10 EN1 9 DVDD1 8 PGND1 MAX15021 AVIN 27 2 3 4 5 6 7 LX1 PVIN1 PVIN1 LX1 PGND1 28 TQFN-EP* +Denotes a lead-free package. *EP = Exposed pad. /V denotes an automotive qualified part. 1 PGND1 PIN-PACKAGE *EP + RT 28 SEL Ordering Information -40°C to +125°C 19 SGND 26 Networking/Telecom MAX15021ATI/V+ 20 EN2 25 Multivoltage Supplies TEMP RANGE 21 FB2 24 Automotive Multimedia PART DVDD2 Applications PGND2 TOP VIEW LX2 Pin Configuration PVIN2 The MAX15021 is available in a space-saving, 5mm x 5mm, 28-pin TQFN-EP package and is specified for operation from -40°C to +125°C temperature range. ♦ Lossless, Cycle-by-Cycle Current Sensing ♦ External Compensation for Maximum Flexibility ♦ Digital Soft-Start and Soft-Stop for Tracking Applications ♦ Digital Soft-Start into a Prebiased Load for Sequencing Applications ♦ Sequencing or Coincident/Ratiometric Tracking N.C. The MAX15021 offers the ability to track (coincident or ratiometric) or sequence during power-up and powerdown operation. When sequencing, it powers up glitchfree into a prebiased output. Additional features include an internal undervoltage lockout with hysteresis and a digital soft-start/soft-stop for glitch-free power-up and power-down. Protection features include lossless cycle-by-cycle current limit, hiccup-mode output short-circuit protection, and thermal shutdown. ♦ 2.5V to 5.5V Input-Voltage Range ♦ Dual-Output Synchronous Buck Regulators ♦ Integrated Switches for 4A and 2A Output Currents ♦ 180° Out-Of-Phase Operation ♦ Output Voltage Adjustable from 0.6V to VAVIN N.C. The MAX15021 is a dual-output, pulse-width-modulated (PWM), step-down DC-DC regulator with tracking (coincident and ratiometric) and sequencing options. The device operates from 2.5V to 5.5V and each output can be adjusted from 0.6V to the input supply (VAVIN). The MAX15021 delivers up to 4A (regulator 1) and 2A (regulator 2) of output current. This device offers the ability to adjust the switching frequency from 500kHz to 4MHz and provides the capability of optimizing the design in terms of size and performance. The MAX15021 utilizes a voltage-mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. The dual switching regulators operate 180° out-of-phase, thereby reducing the RMS input ripple current and thus the size of the input bypass capacitor significantly. Features *EP = EXPOSED PAD. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-4106; Rev 1; 8/12 MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70°C) 28-Pin TQFN (derate 34.5mW/°C above +70°C) .....2758.6mW Junction-to-Case Thermal Resistance (θJC)(Note 2) .........2°C/W Junction-to-Ambient Thermal Resistance (θJA)(Note 2) ..29°C/W Operating Temperature Range .........................-40°C to +125°C Maximum Junction Temperature .....................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C AVIN, PVIN_, DVDD_, EN_, FB_, RT, SEL to SGND .........................................................-0.3V to +6V COMP_ to SGND .....................................-0.3V to (VAVIN + 0.3V) PGND_ to SGND ...................................................-0.3V to +0.3V LX_ Current (Note 1) Regulator 1...............................................................................6A Regulator 2...............................................................................3A Current into Any Pin other than PVIN_, LX_, and PGND_ ..............................................................50mA Note 1: LX_ has internal diodes to PGND_ and PVIN_. Applications that forward bias these diodes should take care not to exceed the IC’s package power dissipation. Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations see www.maximintegrated.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVIN = VPVIN_ = VDVDD_ = 3.3V, VPGND_ = VSGND_ = 0V, RT = 25kΩ, and TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 5.5 V 2.3 V SYSTEM SPECIFICATIONS Input-Voltage Range VAVIN = VPVIN1 = VPVIN2 = VDVDD1 = VDVDD2 2.5 Undervoltage Lockout Threshold AVIN rising 2.1 Undervoltage Lockout Hysteresis 2.2 0.12 V Operating Supply Current VEN_= 1.3V, VFB_ = 0.8V 3.5 6 mA Shutdown Supply Current VEN_ = 0V 20 65 µA PWM DIGITAL SOFT-START/SOFT-STOP Soft-Start/Soft-Stop Duration Reference Voltage Steps 4096 Clock Cycles 64 Steps PWM ERROR AMPLIFIERS FB1, FB2 Input Bias Current -1 FB1, FB2 Voltage Set-Point 0.593 COMP1, COMP2 Voltage Range ICOMP_ = -250µA to +250µA 0.599 0.3 +1 µA 0.605 V VAVIN - 0.5 V Error-Amplifier Open-Loop Gain 80 dB Error-Amplifier Unity-Gain Bandwidth 12 MHz POWER MOSFETs Regulator 1 p-Channel MOSFET RDSON VDVDD1 = 5V 50 90 mΩ Regulator 1 n-Channel MOSFET RDSON VDVDD1 = 5V 30 50 mΩ Regulator 1 Gate Charge VDVDD1 = 5V Maximum LX1 RMS Current 8 nC 4 A Regulator 2 p-Channel MOSFET RDSON VDVDD2 = 5V 100 180 mΩ Regulator 2 n-Channel MOSFET RDSON VDVDD2 = 5V 60 100 mΩ Regulator 2 Gate Charge VDVDD2 = 5V 4 nC 2 A Maximum LX2 RMS Current 2 Maxim Integrated MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability ELECTRICAL CHARACTERISTICS (continued) (VAVIN = VPVIN_ = VDVDD_ = 3.3V, VPGND_ = VSGND_ = 0V, RT = 25kΩ, and TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX VAVIN = 3.3V 4.5 4.9 5.3 VAVIN = 2.5V 3.4 3.65 3.95 VAVIN = 3.3V 4.0 4.9 5.65 VAVIN = 2.5V 3.0 3.7 4.25 VAVIN = 3.3V 2.25 2.45 2.65 VAVIN = 2.5V 1.70 1.85 1.98 VAVIN = 3.3V 2.0 2.5 2.83 VAVIN = 2.5V 1.5 1.85 2.13 UNITS PWM CURRENT LIMIT AND HICCUP MODE Regulator 1 Peak Current Limit Regulator 1 Valley Current Limit Regulator 2 Peak Current Limit Regulator 2 Valley Current Limit A A A A Number of Cumulative Current-Limit Events to Hiccup NCL 4 Clock Cycles Number of Consecutive Noncurrent Limit Cycles to Clear NCL NCLR 3 Clock Cycles Hiccup Timeout NHT 8192 Clock Cycles ENABLE/SEL EN_ Threshold VEN_ rising 1.207 EN_ Hysteresis 1.225 1.243 V +2.5 µA 0.12 EN_ Input Current -2.5 SEL High Threshold V 0.85 x VAVIN SEL Low Threshold V 0.2 x VAVIN SEL Input Bias Current V Present only during startup -100 +100 µA fSW = 3MHz x [VRT(V)/1.067(V)] (Note 4) 500 4000 kHz fSW ≤ 1500kHz -6 +6 fSW > 1500kHz -10 +10 OSCILLATOR Switching Frequency Range fSW Oscillator Accuracy Phase Shift Between Regulators 180 RT Current RT Voltage Range 0 < VRT < 1.067V VRT 31.30 32 0.13 Minimum Controllable On-Time Minimum Controllable Off-Time PWM Ramp Amplitude PWM Ramp Valley % Degrees 32.58 1.067 µA V 60 ns 60 ns VAVIN/4 V 0.3 V +160 °C 15 °C THERMAL SHUTDOWN Thermal Shutdown Temperature Thermal Shutdown Hysteresis Temperature rising Note 3: Specifications are 100% production tested at TA = +25°C and TA = +125°C. Maximum and minimum specifications over temperature are guaranteed by design. Note 4: When operating with VAVIN = 2.5V, the maximum switching frequency should be derated to 3MHz. Maxim Integrated 3 MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Typical Operating Characteristics (VAVIN = VDVDD1 = VDVDD2 = VPVIN1 = VPVIN2 = 5V, VOUT1 = 3.3V, VOUT2 = 1.5V, VPGND_ = 0V, RT = 16.5kΩ. TA = +25°C, unless otherwise noted.) VPVIN1 = 5V 50 40 30 60 VOUT1 = 1.8V 50 VOUT1 = 3.3V 40 5000 VOUT2 = 1.5V fSW = 2MHz EN1 = 0V 0 1000 100 100 5000 LOAD CURRENT (mA) CHANNEL 2 EFFICIENCY vs. LOAD CURRENT CHANNEL 1 LOAD REGULATION CHANNEL 2 LOAD REGULATION 3.318 3.316 VOUT2 = 2.5V VOUT1 (V) VOUT2 = 1.5V 60 VOUT2 = 1.0V 40 30 1.5055 3.312 1.5050 3.310 3.308 3.306 20 VPVIN2 = 3.3V fSW = 2MHz 1.5020 3000 1000 1.5040 1.5025 3.300 100 1.5045 1.5030 VPVIN1 = 5V fSW = 2MHz 3.302 0 VPVIN2 = 5V 1.5035 3.304 VPVIN2 = 5V fSW = 2MHz EN1 = 0V 10 1.5060 3.314 0 LOAD CURRENT (mA) 0.5 1.0 1.5 2.0 3.0 2.5 LOAD CURRENT (A) 0 0.25 0.50 0.75 1.00 1.25 1.50 LOAD CURRENT (A) SWITCHING FREQUENCY vs. TEMPERATURE SWITCHING FREQUENCY vs. RT RESISTANCE 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.5 CHANGE IN SWITCHING FREQUENCY (%) MAX15021 toc07 4.5 MAX15021 toc08 70 1.5065 VOUT2 (V) 80 1.5070 MAX15021 toc05 MAX15021 toc04 3.320 3000 1000 LOAD CURRENT (mA) 90 SWITCHING FREQUENCY (MHz) 40 LOAD CURRENT (mA) 100 50 PVIN2 = 5V 50 10 0 1000 100 60 20 VPVIN1 = 5V fSW = 2MHz EN2 = 0V 10 0 PVIN2 = 3.3V 70 30 20 VOUT1 = 1.8V fSW = 2MHz EN2 = 0V 10 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 fSW = 2MHz -0.5 0 0 5 10 15 20 25 RT RESISTANCE (kΩ) 4 80 VOUT1 = 1.0V 30 20 EFFICIENCY (%) 70 90 MAX15021 toc06 60 80 EFFICIENCY (%) VPVIN1 = 3.3V 90 EFFICIENCY (%) 80 100 MAX15021 toc02 90 EFFICIENCY (%) 100 MAX15021 toc01 100 70 CHANNEL 2 EFFICIENCY vs. LOAD CURRENT CHANNEL 1 EFFICIENCY vs. LOAD CURRENT MAX15021 toc03 CHANNEL 1 EFFICIENCY vs. LOAD CURRENT 30 35 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) Maxim Integrated MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Typical Operating Characteristics (continued) (VAVIN = VDVDD1 = VDVDD2 = VPVIN1 = VPVIN2 = 5V, VOUT1 = 3.3V, VOUT2 = 1.5V, VPGND_ = 0V, RT = 16.5kΩ. TA = +25°C, unless otherwise noted.) QUIESCENT CURRENT vs. TEMPERATURE 4.50 4.25 4.00 3.75 3.50 3.25 3.00 2.75 NO SWITCHING REGULATOR 1 ENABLED VOUT1 = 3.3V REGULATOR 2 ENABLED VOUT2 = 1.5V -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) NORMALIZED UNDERVOLTAGE LOCKOUT THRESHOLD vs. TEMPERATURE EN_ THRESHOLD vs. TEMPERATURE 1.030 1.025 1.020 1.260 MAX15021 toc11 1.015 1.255 1.250 EN_ THRESHOLD (V) NORMALIZED UVLO THRESHOLD (V) 2.50 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1.010 1.005 1.000 0.995 0.990 0.985 0.980 MAX15021 toc12 QUIESCENT CURRENT (mA) 4.75 SWITCHING CURRENT (mA) MAX15021 toc09 5.00 MAX15021 toc10 SWITCHING CURRENT vs. TEMPERATURE 1.245 1.240 1.235 1.230 1.225 1.220 0.975 0.970 1.215 VUVLO (NOM) = 2.2V 1.210 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (°C) TEMPERATURE (°C) COINCIDENT TRACKING SOFT-START COINCIDENT TRACKING SOFT-STOP MAX15021 toc13 MAX15021 toc14 VAVIN 5V/div 0V VAVIN 5V/div 0V VOUT1 1V/div VOUT1 VOUT2 1V/div VOUT2 EN1 1V/div 0V 0V 1ms/div Maxim Integrated 400μs/div 5 MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Typical Operating Characteristics (continued) (VAVIN = VDVDD1 = VDVDD2 = VPVIN1 = VPVIN2 = 5V, VOUT1 = 3.3V, VOUT2 = 1.5V, VPGND_ = 0V, RT = 16.5kΩ. TA = +25°C, unless otherwise noted.) CHANNEL 1 LOAD STEP RESPONSE CHANNEL 1 LOAD STEP RESPONSE MAX15021 toc15 MAX15021 toc16 EN2 = 0V EN2 = 0V VPVIN1 5V/div 0V VPVIN1 5V/div 0V VOUT1 3.3V, AC-COUPLED 100mV/div VOUT1 3.3V, AC-COUPLED 100mV/div IOUT1 2A/div 0A IOUT1 2A/div 0A 20μs/div 20μs/div CHANNEL 2 LOAD STEP RESPONSE CHANNEL 2 LOAD STEP RESPONSE MAX15021 toc17 MAX15021 toc18 EN1 = 0V EN1 = 0V VPVIN2 5V/div 0V VPVIN2 5V/div 0V VOUT2 1.5V, AC-COUPLED 100mV/div VOUT2 1.5V, AC-COUPLED 100mV/div IOUT2 1A/div 0A IOUT2 1A/div 0A 20μs/div 20μs/div 180° OUT-OF-PHASE OPERATION MAX15021 toc19 PVIN1 = PVIN2 5V/div 0V VLX1 5V/div 0V VLX2 5V/div 0V IOUT1 = 3A IOUT2 = 1.5A 200ns/div 6 Maxim Integrated MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Pin Description PIN NAME FUNCTION 1 SEL Track/Sequence Select Input. Connect SEL to ground to configure the device as a sequencer. Connect SEL to AVIN for tracking with output 1 as the master. Leave SEL unconnected for tracking with output 2 as the master. Use the output with the higher voltage as the master and the output with the lower voltage as the slave. 2, 7, 8 PGND1 3, 6 LX1 4, 5 PVIN1 Input Supply Voltage for Regulator 1. Connect to an external voltage source from 2.5V to 5.5V. Bypass PVIN1 to PGND1 with a 1µF (min) ceramic capacitor. 9 DVDD1 Switch Driver Supply for Regulator 1. Connect externally to PVIN1. 10 EN1 Enable Input for Regulator 1. When configured as a sequencer, EN1 must exceed 1.225V (typ) for the PWM controller to begin regulating output 1. When configured as a tracker, connect EN1 to the center tap of a resistive divider from the regulator 2 output. 11 FB1 Feedback Regulation Point for Regulator 1. Connect FB1 to the center tap of a resistive divider from the regulator 1 output to SGND to set the output voltage. The FB1 voltage regulates to 0.6V (typ). 12 COMP1 13, 14, 15, 20, 21, 22 N.C. 16 DVDD2 Switch Driver Supply for Regulator 2. Connect externally to PVIN2. 17 PGND2 Power Ground Connection for Regulator 2. Connect the negative terminals of the input and output filter capacitors to PGND2. Connect PGND2 externally to SGND at a single point, typically at the negative terminal of the input capacitor. 18 LX2 19 PVIN2 23 COMP2 Power Ground Connection for Regulator 1. Connect the negative terminals of the input and output filter capacitor to PGND1. Connect PGND1 externally to SGND at a single point, typically at the negative terminal of the input capacitor. Inductor Connection for Regulator 1. LX1 is the drain connection of the internal high-side p-channel MOSFET and the drain connection of the internal synchronous n-channel MOSFET for regulator 1. Error-Amplifier Output for Regulator 1. Connect COMP1 to the compensation feedback network. No Connection. Do not connect. Inductor Connection for Regulator 2. LX2 is the drain connection of the internal high-side p-channel MOSFET and the drain connection of the internal synchronous n-channel MOSFET for regulator 2. Input Supply Voltage for Regulator 2. Connect to an external voltage source from 2.5V to 5.5V. Bypass PVIN2 to PGND2 with a 1µF (min) ceramic capacitor. Error-Amplifier Output for Regulator 2. Connect COMP2 to the compensation feedback network. 24 FB2 Feedback Regulation Point for Regulator 2. Connect to the center tap of a resistive divider from the regulator 2 output to SGND to set the output voltage. The FB2 voltage regulates to 0.6V (typ). 25 EN2 Enable Input for Regulator 2. When configured as a sequencer, EN2 must exceed 1.225V (typ) for the PWM controller to begin regulating output 2. When configured as a tracker, connect EN2 to the center tap of a resistive divider from the regulator 1 output. 26 SGND Signal Ground. Connect SGND to PGND_ at a single point, typically near negative terminal of the input bypass capacitor. 27 AVIN Input Voltage. Bypass AVIN to SGND with a 100nF (min) ceramic capacitor. 28 RT Oscillator Timing Resistor Connection. Connect a 4.2kΩ to 33kΩ resistor from RT to SGND to program the switching frequency from 500kHz to 4MHz. — EP Exposed Pad. Connect EP to a large copper plane at SGND potential to improve thermal dissipation. Do not use as the main SGND connection. Maxim Integrated 7 MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Functional Diagrams AVIN SEL SGND ON1 ON2 SHDN MAX15021 SEQ1 1.225V 1.1V EN CONFIG PWM CONTROLLER 1 SEQ2 SEL DECODE SEQ1 0.6V REF VREF CLK1 VREF VR1 EN1 ON1 SEQ1 SEQ2 DOWN1 DIGITAL SOFT-START AND SOFT-STOP EN1 SHDN THERMAL SHDN OVL CONFIG SEQ1 1.225V 1.1V OVL1 DVDD1 OVL2 PVIN1 CLK1 CLK2 E/A HIGH-SIDE CURRENT SENSE OVL1 RES OVERLOAD MANAGEMENT FB1 ILIM1 AVIN D COMP1 RT EN OSC CLK2 CPWM CLK1 RAMP LEVEL SHIFT Q BREAKBEFOREMAKE LX1 D0 LOW-SIDE CURRENT SENSE CLK PGND1 8 Maxim Integrated MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Functional Diagrams (continued) SEQ2 SHDN EN2 MAX15021 ON1 ON2 ON2 1.225V 1.1V PWM CONTROLLER 2 SEQ1 EN CONFIG SEQ2 SEQ1 SEQ2 VREF CLK2 DOWN2 DIGITAL SOFT-START AND SOFT-STOP VREF VR2 EN2 OVL1 OVL CONFIG SEQ1 E/A DVDD2 OVL2 PVIN2 CLK1 CLK2 FB2 HIGH-SIDE CURRENT SENSE OVL2 RES OVERLOAD ILIM2 MANAGEMENT AVIN D COMP2 CPWM CLK2 RAMP LEVEL SHIFT CLK Q BREAKBEFOREMAKE LX2 D0 LOW-SIDE CURRENT SENSE PGND2 Maxim Integrated 9 MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Detailed Description The MAX15021 incorporates dual-output, PWM, stepdown, DC-DC regulators with tracking and sequencing options. The device operates over the input-voltage range of 2.5V to 5.5V. Each PWM regulator provides an adjustable output down to 0.6V and delivers up to 4A (regulator 1) and 2A (regulator 2) of load current. The high switching frequency (up to 4MHz) and integrated power switches optimize the MAX15021 for high-performance and small-size power management solutions. Each of the MAX15021 PWM regulator sections utilizes a voltage-mode control scheme for good noise immunity and offers external compensation allowing for maximum flexibility with a wide selection of inductor values and capacitor types. The device operates at a fixed switching frequency that is programmable from 500kHz to 4MHz with a single resistor. Operating the regulators with 180° out-of-phase clocking, and at frequencies up to 4MHz, significantly reduces the RMS input ripple current. The resulting peak input current reduction (and increase in the ripple frequency) significantly reduces the required amount of input bypass capacitance. The MAX15021 provides coincident tracking, ratiometric tracking, or sequencing to allow tailoring of powerup/power-down sequence depending on the system requirements. When sequencing, it powers up glitchfree into a prebiased output. The MAX15021 includes internal undervoltage lockout with hysteresis, digital soft-start/soft-stop for “glitch-free” power-up and power-down. Protection features include lossless, cycle-by-cycle current limit, hiccup-mode output short-circuit protection, and thermal shutdown. when soft-start is completed, regardless of the output capacitance and load. For tracking applications, soft-stop commences when the enable input falls below 1.1V (typ). The soft-stop circuitry ramps down the reference voltage controlling the outputvoltage rate of fall. The output voltage is decremented through 64 equal steps in 4096 clock cycles. Oscillator Use an external resistor at RT to program the MAX15021 switching frequency from 500kHz to 4MHz. Calculate the appropriate resistor at RT for the desired output switching frequency (fSW): f [kHz] × 1.067[V] RT [kΩ] = SW 32[μA] × 4[MHz] Tracking/Sequencing The MAX15021 features coincident/ratiometric tracking and sequencing (see Figure 1). Connect SEL to ground to configure the device as sequencer. Connect SEL to AVIN for tracking with output 1 as the master. Leave SEL unconnected for tracking with output 2 as the master. Assign the output with the higher voltage as the master. VOUT1 VOUT2 SOFT-STOP SOFT-START a) COINCIDENT TRACKING OUTPUTS Undervoltage Lockout (UVLO) The supply voltage (VAVIN) must exceed the default UVLO threshold before any operation starts. The UVLO circuitry keeps the MOSFET drivers, oscillator, and all the internal circuitry shut down to reduce current consumption. The UVLO rising threshold is 2.2V (typ) with a 120mV (typ) hysteresis. VOUT1 VOUT2 b) RATIOMETRIC TRACKING OUTPUTS Digital Soft-Start/Soft-Stop The MAX15021 soft-start feature allows the load voltage to ramp up in a controlled manner, eliminating output-voltage overshoot. Soft-start begins after VAVIN exceeds the undervoltage lockout threshold and the enable input is above 1.225V (typ). The soft-start circuitry ramps up the reference voltage, controlling the rate of rise of the output voltage, and reducing input surge currents during startup. The soft-start duration is 4096 clock cycles. The output voltage is incremented through 64 equal steps. The output reaches regulation 10 SOFT-STOP SOFT-START VOUT1 VOUT2 SOFT-START SOFT-STOP c) SEQUENCED OUTPUTS Figure 1. Graphical Representation of Coincident Tracking, Ratiometric Tracking, and Sequencing Maxim Integrated MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Coincident/Ratiometric Tracking The enable inputs in conjunction with digital soft-start and soft-stop provide coincident/ratiometric tracking. Track an output voltage by connecting a resistive divider from the output being tracked to its enable input. For example, for VOUT2 to coincidentally track V OUT1, connect the same resistive divider used for FB2, from VOUT1 to EN2 to SGND (see Figure 2). Track ratiometrically by connecting EN_ to SGND. This synchonizes the soft-start and soft-stop of all the regulator references, and hence their respective output voltages will track ratiometrically (see Figure 2). when the other output is shorted to ground. When the slave is shorted and enters hiccup mode, the master will soft-stop. When the master is shorted and the part enters in hiccup mode, the slave will ratiometrically softstop. Coming out of hiccup mode, both outputs will softstart coincidently or ratiometrically depending on their initial configuration. During the thermal shutdown or power-off when the input falls below its UVLO, the output voltages decrease at a rate depending on the respective output capacitance and load. See Figure 1 for a graphical representation of coincident/ratiometric tracking. When the MAX15021 regulators are configured as voltage trackers, output short-circuit fault conditions at either master or slave output are handled carefully—neither the master nor slave output will remain energized Sequencing When sequencing, the voltage at the enable inputs must exceed 1.225V (typ) for each PWM controller to start (see Figure 1c). RATIOMETRIC TRACKING COINCIDENT TRACKING COINCIDENT TRACKING VRIN1 VRIN1 VRIN2 EN1 EN1 EN2 EN2 VOUT1 VOUT2 RA SEL RC AVIN EN2 EN1 OUTPUT 1 IS THE MASTER AND OUTPUT 2 IS THE SLAVE. RB RD VRIN2 VOUT2 VOUT1 RA EN2 FB2 RC FB1 RB RD EN1 SEL UNCONNECTED OUTPUT 2 IS THE MASTER AND OUTPUT 1 IS THE SLAVE. SEL AVIN OUTPUT 1 IS THE MASTER AND OUTPUT 2 IS THE SLAVE. SEL UNCONNECTED OUTPUT 2 IS THE MASTER AND OUTPUT 1 IS THE SLAVE. Figure 2. Ratiometric Tracking and Coincident Tracking Configurations Maxim Integrated 11 MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Error Amplifier The output of the internal voltage-mode error amplifier (COMP_) is provided for frequency compensation (see the Compensation-Design Guidelines section). FB_ is the inverting input of the error amplifier. The error amplifier has an 80dB open-loop gain and a 12MHz gain bandwidth (GBW) product. CURRENT LIMIT IN COUNT OF 4 NCL INITIATE HICCUP TIMEOUT NHT CLR Output Short-Circuit Protection (Hiccup Mode) The MAX15021 features lossless, high-side peak current limit and low-side, valley current limit. At short duty cycles, both limits are active. At high duty cycles, only the high-side peak current limit is active. Either limit causes the hiccup mode count (NCL) to increment. For duty cycles less than 50%, the low-side valley current limit is active. Once the high-side MOSFET turns off, the voltage across the low-side MOSFET is monitored. If this voltage does not exceed the current-limit threshold at the end of the cycle, the high-side MOSFET turns on normally at the start of the next cycle. If the voltage exceeds the current-limit threshold just before the beginning of a new PWM cycle, the controller skips that cycle. During severe overload or short-circuit conditions, the switching frequency of the device appears to decrease because the on-time of the low-side MOSFET extends beyond a clock cycle. If the current-limit threshold is exceeded for more than four cumulative clock cycles (NCL), the device shuts down for 8192 clock cycles (hiccup timeout) and then restarts with a soft-start sequence. If three consecutive cycles pass without a current-limit event, the count of NCL is cleared (see Figure 3). Hiccup mode protects the device against a continuous output short circuit. The internal current limit is constant from 5.5V down to 3V and decreases linearly by 50% from 3V to 2V. See the Electrical Characteristics table. Thermal-Overload Protection The MAX15021 features an integrated thermal-overload protection with temperature hysteresis. Thermal-overload protection limits the total power dissipation in the device and protects it in the event of an extended thermal fault condition. When the die temperature exceeds +160°C, an internal thermal sensor shuts down the device, turning off the internal power MOSFETs and allowing the die to cool. After the die temperature falls by +15°C, the part restarts with a soft-start sequence. 12 IN COUNT OF 3 NCLR CLR Figure 3. Hiccup-Mode Block Diagram Startup into a Prebiased Output (Sequencing Mode) In sequencing mode, the regulators start into a prebiased output and soft-stop is disabled. During soft-start, the complementary switching sequence is inhibited until the PWM comparator commands its first PWM pulse. Until then, the converters do not sink current from the outputs. The first PWM pulse occurs when the ramping reference voltage increases above the FB_ voltage. PWM Controllers Design Procedure Setting the Switching Frequency Connect a 4.2kΩ to 33kΩ resistor from RT to SGND to program the switching frequency from 500kHz to 4MHz. Calculate the resistor connected to RT using the following equation: f [kHz] × 1.067[V] RT [kΩ] = SW 32[μA] × 4[MHz] Higher frequencies allow designs with lower inductor values and less output capacitance. At higher switching frequencies core losses, gate-charge currents, and switching losses increase. When operating from VAVIN ≤ 3V, the switching frequency (fSW) should be derated to 3MHz (maximum). Maxim Integrated MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Effective Input-Voltage Range Although the MAX15021’s regulators can operate from input supplies ranging from 2.5V to 5.5V, the input-voltage range can be effectively limited by the MAX15021’s duty-cycle limitations for a given output voltage (V OUT_ ). The maximum input voltage (VPVIN_MAX) can be effectively limited by the controllable minimum on-time (tON(MIN)): VPVIN_MAX [V] ≤ VOUT_ [V] t ON(MIN) [μs] × fSW [MHz] where tON(MIN) is 0.06µs (typ). The minimum input voltage (VPVIN_MIN) can be effectively limited by the maximum controllable duty cycle and is calculated using the following equation: VPVIN_MIN [V] ≥ VOUT_ [V] 1− (t OFF(MIN) [μs] × fSW [MHz]) where V OUT_ is the regulator output voltage and tOFF(MIN) is the 0.06µs (typ) controllable off-time. Inductor Selection Three key inductor parameters must be specified for operation with the MAX15021: inductance value (L), peak inductor current (IPEAK), and inductor saturation current (ISAT). The minimum required inductance is a function of operating frequency, input-to-output voltage differential, and the peak-to-peak inductor current (ΔIP-P). Higher ΔIP-P allows for a lower inductor value. A lower inductance minimizes size and cost and improves large-signal and transient response. However, efficiency is reduced due to higher peak currents and higher peak-to-peak output-voltage ripple for the same output capacitor. A higher inductance increases efficiency by reducing the ripple current; however, resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current levels especially when the inductance is increased without also allowing for larger inductor dimensions. Choose the inductor’s peak-to-peak current, ΔIP-P, in the range of 20% to 50% of the full load current; as a rule of thumb 30% is typical. Calculate the inductance, L, using the following equation: L[μH] = Maxim Integrated VOUT_ [V] × (VPVIN_ [V] − VOUT_ [V]) VPVIN_ [V] × fSW [MHz] × ΔIP−P [A] where VPVIN_ is the input supply voltage, VOUT_ is the regulator output voltage, and fSW is the switching frequency. Use typical values for VPVIN_ and VOUT_ so that efficiency is optimum for typical conditions. The switching frequency (fSW) is programmable between 500kHz and 4MHz (see the Oscillator section). The peak-to-peak inductor current (ΔI P-P ), which reflects the peak-to-peak output ripple, is largest at the maximum input voltage. See the Output-Capacitor Selection section to verify that the worst-case output current ripple is acceptable. Select an inductor with a saturation current, ISAT, higher than the maximum peak current to avoid runaway current during continuous output short-circuit conditions. Also, confirm that the inductor’s thermal performances and projected temperature rise above ambient does not exceed its thermal capacity. Many inductor manufacturers provide bias/load current versus temperature rise performance curves (or similar) to obtain this information. Input-Capacitor Selection The discontinuous input current of the buck converter causes large input ripple currents and therefore, the input capacitor must be carefully chosen to withstand the input ripple current and keep the input-voltage ripple within design requirements. The input-voltage ripple is comprised of ΔVQ (caused by the capacitor discharge) and ΔVESR (caused by the ESR of the input capacitor). The total voltage ripple is the sum of ΔVQ and ΔVESR which peaks at the end of the on-cycle. Calculate the required input capacitance and ESR for a specified ripple using the following equations: ESR[mΩ] = ΔVESR[mV] ΔIP −P ⎞ ⎛ ⎜ ILOAD(MAX) + ⎟ [A] ⎝ 2 ⎠ ⎛V [V] ⎞ ILOAD(MAX)[A] × ⎜ OUT_ ⎟ ⎝ VPVIN_ [V] ⎠ CPVIN_ [μF] = ΔVQ[V] × fSW [MHz] ΔIP −P [A] = (VPVIN_ − VOUT_ )[V] × VOUT_ [V] VPVIN_ [V] × fSW [MHz] × L[μH] ILOAD(MAX) is the maximum output current, ΔIP-P is the peak-to-peak inductor current, and VPVIN_ is the input supply voltage, VOUT_ is the regulator output voltage, and fSW is the switching frequency. 13 MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Use the following equation to calculate the input ripple when only one regulator is enabled: ICIN(RMS)[A] = ILOAD(MAX)[A] × ( ) VOUT_ [V] × VPVIN_ − VOUT_ [V] VPVIN_ [V] The MAX15021 includes UVLO hysteresis to avoid possible unintentional chattering during turn-on. Use additional bulk capacitance if the input source impedance is high. If using a lower input voltage, additional input capacitance helps to avoid possible undershoot below the undervoltage lockout threshold during transient loading. Output-Capacitor Selection The allowed output-voltage ripple and the maximum deviation of the output voltage during load steps determine the required output capacitance and its ESR. The output ripple is mainly composed of ΔVQ (caused by the capacitor discharge) and ΔVESR (caused by the voltage drop across the equivalent series resistance of the output capacitor). The equations for calculating the output capacitance and its ESR are: ΔIP−P [A] 8 × ΔVQ [V] × fSW [MHz] 2 × ΔVESR [mV] ESR[mΩ] = ΔIP−P [A] COUT [μF] = where ΔIP-P is the peak-to-peak inductor current, and fSW is the switching frequency. ΔVESR and ΔVQ are not directly additive since they are out of phase from each other. If using ceramic capacitors, which generally have low ESR, ΔVQ dominates. If using electrolytic capacitors, ΔVESR dominates. The allowable deviation of the output voltage during fast load transients also affects the output capacitance, its ESR, and its equivalent series inductance (ESL). The output capacitor supplies the load current during a load step until the controller responds with an increased duty cycle. The response time (tRESPONSE) depends on the gain bandwidth of the controller (see the Compensation-Design Guidelines section). The resistive drop across the output capacitor’s ESR (ΔVESR), the drop across the capacitor’s ESL (ΔVESL), and the capacitor discharge (ΔVQ) cause a voltage droop during the load-step (ISTEP). Use a combination of low-ESR tantalum/aluminum electrolyte and ceramic capacitors for better load transient and voltage ripple performance. Nonleaded capacitors and capacitors in parallel help reduce the ESL. Keep the maximum out- 14 put voltage deviation below the tolerable limits of the electronics being powered. Use the following equations to calculate the required output capacitance, ESR, and ESL for minimal output deviation during a load step: ΔVESR [mV] ISTEP [A] ISTEP [A] × t RESPONSE [μs] COUT [μF] = ΔVQ [V] ΔVESL [mV] × t STEP [μs] ESL[nH] = ISTEP [A] ESR[mΩ] = where ISTEP is the load step, tSTEP is the rise time of the load step, and tRESPONSE is the response time of the controller. Compensation-Design Guidelines The MAX15021 uses a fixed-frequency, voltage-mode control scheme that regulates the output voltage by comparing the output voltage against a fixed reference. The subsequent “error” voltage that appears at the error-amplifier output (COMP_) is compared against an internal ramp voltage to generate the required duty cycle of the pulse-width modulator. A second-order lowpass LC filter removes the switching harmonics and passes the DC component of the pulse-width-modulated signal to the output. The LC filter has an attenuation slope of -40dB/decade and introduces 180° of phase shift at frequencies above the LC resonant frequency. This phase shift in addition to the inherent 180° of phase shift of the regulator’s negative feedback system turns the feedback into unstable positive feedback. The error amplifier and its associated circuitry must be designed to achieve a stable closed-loop system. The basic controller loop consists of a power modulator (comprised of the regulator’s pulse-width modulator, associated circuitry, and LC filter), an output feedback divider, and an error amplifier. The power modulator has a DC gain set by VAVIN/VRAMP where the ramp voltage (VRAMP) is a function of the VAVIN and results in a fixed DC gain of 4V/V, providing effective feed-forward compensation of input-voltage supply DC variations. The feed-forward compensation eliminates the dependency of the power modulator’s gain on the input voltage such that the feedback compensation of the error amplifier requires no modifications for nominal input-voltage changes. The output filter is effectively modeled as a double-pole and a single zero set by the output inductance (L), the DC resistance of the inductor (DCR), the output capacitance (COUT) and its equivalent series resistance (ESR). Maxim Integrated MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability VAVIN V = AVIN = 4V/V VRAMP VAVIN 4 1 1 fLC = ≈ 2 L π × × COUT ⎛R + ESR ⎞ 2π × L × COUT × ⎜ OUT ⎟ ⎝ ROUT + DCR ⎠ GainMOD(DC) = fESR = 1 2π × ESR × COUT ROUT is the load resistance of the regulator, fLC is the resonant break frequency of the filter, and fESR is the ESR zero of the output capacitor. See the Closed-Loop Response and Compensation of Voltage-Mode Regulators section for more information on fLC and fESR. The switching frequency (f SW ) is programmable between 500kHz and 4MHz. Typically, the crossover frequency (fCO)—the frequency at which the system’s closed-loop gain is equal to unity (crosses 0dB)— should be set at or below one-tenth the switching frequency (fSW/10) for stable closed-loop response. The MAX15021 provides an internal voltage-mode error amplifier with its inverting input and its output available to the user for external frequency compensation. The flexibility of external compensation for each controller offers a wide selection of output filtering components, especially the output capacitor. For cost-sensitive applications, MAX15021 fig04a 40 use aluminum electrolytic capacitors while for spacesensitive applications, use low-ESR tantalum or multilayer ceramic chip (MLCC) capacitors at the output. The higher switching frequencies of the MAX15021 allow the use of MLCC as the primary filter capacitor(s). First, select the passive and active power components that meet the application output ripple, component size, and component cost requirements. Second, choose the small-signal compensation components to achieve the desired closed-loop frequency response and phase margin as outlined below. Closed-Loop Response and Compensation of Voltage-Mode Regulators The power modulator’s LC lowpass filter exhibits a variety of responses, dependent on the value of the L and C and their parasitics. Higher resistive parasitics reduce the Q of the circuit, reducing the peak gain and phase of the system; however, efficiency is also reduced under these circumstances. One such response is shown in Figure 4a. In this example, the ESR zero occurs relatively close to the filter’s resonant break frequency, fLC. As a result, the power modulator’s uncompensated crossover is approximately one-third the desired crossover frequency, fCO. Note also, the uncompensated rolloff through the 0dB plane follows a single-pole, -20dB/decade slope, and 90° of phase lag. In this instance, the inherent phase margin ensures a stable system; however, the gain-bandwidth product is not optimized. fLC -45 fESR < GMOD -40 -90 -60 -135 MAGNITUDE (dB) -20 PHASE (DEGREES) MAGNITUDE (dB) |GMOD| 0 10 100 1k 10k 100k 1M -180 10M FREQUENCY (Hz) Figure 4a. Power Modulator Gain and Phase Response with Lossy Bulk Output Capacitor(s) (Aluminum) Maxim Integrated fCO |GEA| 0 45 0 -20 -45 fESR < GMOD -40 -80 90 fLC 20 180 135 40 |GMOD| ASYMPTOTE 0 < GEA 60 45 20 MAX15021 fig04b 80 90 -90 -60 -135 |GMOD| -80 10 100 PHASE (DEGREES) Below are equations that define the power modulator: 1k 10k 100k 1M -180 10M FREQUENCY (Hz) Figure 4b. Power Modulator and Type II Compensator Gain and Phase Response with Lossy Bulk Output Capacitor(s) (Aluminum) 15 MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability MAX15021 fig04c 40 |GMOD| 20 gentler response of the previous example. This is due to the filter components’ lower parasitic (DCR and ESR) and corresponding higher frequency of the inherent ESR zero. In this example, the desired crossover frequency occurs below the ESR zero frequency. In this example, a compensator with an inherent midfrequency double-zero response is required to mitigate the effects of the filter’s double-pole phase lag. This is available with the Type III topology. As demonstrated in Figure 4d, the Type III’s midfrequency double-zero gain (exhibiting a +20dB/dec slope, noting the compensator’s pole at the origin) is designed to compensate for the power modulator’s double-pole -40dB/decade attenuation at the desired crossover frequency, fCO (again, GainE/A + GainMOD = 0dB at fCO) (see Figure 4d). In the above example the power modulator’s inherent (midfrequency) -40dB/decade rolloff is mitigated by the midfrequency double zero’s +20dB/decade gain to extend the active regulation gain-bandwidth of the voltage regulator. As shown in Figure 4d, the net result is an approximate doubling in the controller’s gain bandwidth while providing greater than 55 degrees of phase margin (the difference between GainE/A and GainMOD respective phases at crossover, fCO). Design procedures for both Type II and Type III compensators are shown below. 90 MAX15021 fig04d 80 60 45 -20 -45 < GMOD -40 -90 MAGNITUDE (dB) fESR PHASE (DEGREES) MAGNITUDE (dB) 0 fLC 203 < GEA 40 0 |GEA| 135 fLC 20 68 fCO 0 -135 -20 < GMOD 100 1k 10k 100k 1M -180 10M FREQUENCY (Hz) Figure 4c. Power Modulator Gain and Phase Response with Low-Parasitic Capacitor(s) (MLCCs) 16 -68 -135 -60 -203 fESR -80 10 0 |GMOD| -40 |GMOD| ASYMPTOTE -60 270 PHASE (DEGREES) As seen in Figure 4b, a Type II compensator provides for stable closed-loop operation, leveraging the +20dB/ decade slope of the capacitor’s ESR zero, while extending the closed-loop gain-bandwidth of the regulator. The zero crossover now occurs at approximately three times the uncompensated crossover frequency, fCO. The Type II compensator’s midfrequency gain (approximately 12dB shown here) is designed to compensate for the power modulator’s attenuation at the desired crossover frequency, fCO (GainE/A + GainMOD = 0dB at fCO). In this example, the power modulator’s inherent -20dB/decade rolloff above the ESR zero (fZERO,ESR) is leveraged to extend the active regulation gain-bandwidth of the voltage regulator. As shown in Figure 4b, the net result is a three times increase in the regulator’s gain bandwidth while providing greater than 75° of phase margin (the difference between Gain E/A and GainMOD respective phases at crossover, fCO). Other filter schemes pose their own problems. For instance, when choosing high-quality filter capacitor(s), e.g. MLCCs, the inherent ESR zero may occur at a much higher frequency, as shown in Figure 4c. As with the previous example, the actual gain and phase response is overlaid on the power modulator’s asymptotic gain response. One readily observes the more dramatic gain and phase transition at or near the power modulator’s resonant frequency, fLC, versus the -80 10 100 1k 10k 100k 1M -270 10M FREQUENCY (Hz) Figure 4d. Power Modulator and Type III Compensator Gain and Phase Response with Low Parasitic Capacitors (MLCCs) Maxim Integrated MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Type II: Compensation when fCO > fZERO,ESR When the fCO is greater than fESR, a Type II compensation network provides the necessary closed-loop compensated response. The Type II compensation network provides a midband compensating zero and a high-frequency pole (see Figures 5a and 5b). R F C F provides the midband zero f MID,ZERO , and RFCCF provides the high-frequency pole, fHIGH,POLE. Use the following procedure to calculate the compensation network components. Calculate the fESR and LC double pole, fLC: fESR = fLC ≈ 1 2π × ESR × COUT 1 CF FB_ COMP_ R2 VREF Figure 5a. Type II Compensation Network 2π × L × COUT fZ1 ≤ fLC Set the compensator’s high-frequency pole, fP1, at or below one-half the switching frequency, fSW: f fP1 ≤ SW 2 To maximize the compensator’s phase lead, set the desired crossover frequency, fCO, equal to the geometric mean of the compensator’s leading zero, fZ1, and high-frequency pole, fP1, as follows: fCO = fZ1 × fP1 Select the feedback resistor, RF, in the range of 3.3kΩ to 30kΩ. Calculate the gain of the modulator (GainMOD)—comprised of the regulator’s pulse-width modulator, LC filter, feedback divider, and associated circuitry—at the desired crossover frequency, fCO, using the following equation: ESR [mΩ] (2π × fCO [kHz] × L[μH]) × VFB [V] VOUT_ [V] where VFB is the 0.6V (typ) FB_ input-voltage set-point, L is the value of the regulator inductor, ESR is the Maxim Integrated RF R1 GAIN (dB) where COUT is the regulator output capacitor and ESR is the series resistance of C OUT . See the OutputCapacitor Selection section for more information on calculating COUT and ESR. Set the compensator’s leading zero, fZ1, at or below the filter’s resonant double-pole frequency from: GainMOD = 4(V/V) × CCF VOUT_ 1ST ASYMPTOTE (ωR1CF)-1 2ND ASYMPTOTE (RFR1)-1 3RD ASYMPTOTE (ωRFCCF)-1 1ST POLE (AT ORIGIN) ω (rad/sec) 2ND POLE (RFCCF)-1 1ST ZERO (RFCF)-1 Figure 5b. Type II Compensation Network Response series resistance of the output capacitor, and VOUT_ is the desired output voltage. The gain of the error amplifier (GainE/A) in the midband frequencies is: R [kΩ] GainE/A = F R1 [kΩ] The total loop gain is the product of the modulator gain and the error amplifier gain at fCO and should be set equal to 1 as follows: GainMOD x GainE/A = 1 So: ⎡ RF ⎤ ⎡ 4 ×ESR x VFB ⎤ 20 × log10 ⎢⎣ R1 ⎥⎦ + 20 × log10 ⎢⎢ 2 π × fCO ×L x VOUT_ ⎥⎥ = 0dB ⎣ ⎦ RF 4 × ESR x VFB × =1 R1 2π × fCO × L x VOUT_ 17 MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Solving for R1: R1 [kΩ] = VOUT_ RF [kΩ] × 4 × ESR[mΩ] × VFB [V] 2π × fCO [kHz] × L[μH] × VOUT_ [V] where VFB is the 0.6V (typ) FB_ input-voltage set-point, L is the value of the regulator inductor, ESR is the series resistance of the output capacitor, and VOUT_ is the desired output voltage. RI CCF CI FB_ COMP_ R2 VREF 1) CF is determined from the compensator’s leading zero, fZ1, and RF as follows: CF [μF] = 1 2π × RF [kΩ] × fZ1[kHz] CF RF R1 Figure 6a. Type III Compensation Network GAIN (dB) 2) CCF is determined from the compensator’s high-frequency pole, fP1, and RF as follows: 1 CCF [μF] = 2π × RF [kΩ] × fP1[kHz] 1ST ASYMPTOTE (ωR1CF)-1 VFB [V] VOUT_ [V] − VFB [V] where VFB = 0.6V (typ) and VOUT_ is the output voltage of the regulator. Type III: Compensation when fCO < fESR As indicated above, the position of the output capacitor’s inherent ESR zero is critical in designing an appropriate compensation network. When low-ESR ceramic output capacitors (MLCCs) are used, the ESR zero frequency (fESR) is usually much higher than the desired crossover frequency (fCO). In this case, a type III compensation network is recommended (see Figure 6a). As shown in Figure 6b, the Type III compensation network introduces two zeros and three poles into the control loop. The error amplifier has a low-frequency pole at the origin, two zeros, and two higher frequency poles at the following frequencies: 1 2π × R F × C F 1 fZ2 = 2π × CI × (R1 + RI ) fZ1 = Two midband zeros (fZ1 and fZ2) are designed to compensate for the pair of complex poles introduced by the LC filter. 18 ( ) 2ND ASYMPTOTE 3RD ASYMPTOTE RF 1 (ωRFCI)-1 R1 5TH ASYMPTOTE (ωRICCF)-1 ( ) 3) Calculate R2 using the following equation: R2 [kΩ] = R1[kΩ] × 4TH ASYMPTOTE RF RI 1ST POLE (AT ORIGIN) 1ST ZERO 2ND POLE (RFCF)-1 (RICI)-1 2ND ZERO (R1CI)-1 3RD POLE (RFCCF)-1 ω (rad/sec) Figure 6b. Type III Compensation Network Response fP1 introduces a pole at zero frequency (integrator) for nulling DC output voltage errors. fP1= at the origin (0Hz) Depending on the location of the ESR zero (fESR), fP2 can be used to cancel it, or to provide additional attenuation of the high-frequency output ripple. fP2 = 1 2π × RI × CI fP3 attenuates the high-frequency output ripple. fP3 = 1 ( 2π × RF × CF CCF ) = 1 C × CCF 2π × R F × F CF + CCF Since CCF << CF then: fP3 = 1 2π × RF × CCF Maxim Integrated MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability The locations of the zeros and poles should be such that the phase margin peaks around fCO. Solving for CI: Set the ratios of fCO-to-fZ and fP-to-fCO equal to one another, e.g., fCO = fP = 5 is a good number to get approximately fZ fCO 60° of phase margin at fCO. Whichever technique, it is important to place the two zeros at or below the double pole to avoid the conditional stability issue. The following procedure is recommended: 1) Select a crossover frequency, fCO, at or below onetenth the switching frequency (fSW): CI [pF] = f [kHz] fCO [kHz] ≤ SW 10 2) Calculate the LC double-pole frequency, fLC : fLC [MHz] ≈ 1 2π × L[μH] × COUT [μF] where COUT is the output capacitor of the regulator. 3) Select the feedback resistor, RF, in the range of 3.3kΩ to 30kΩ. 1 4) Place the compensator’s first fZ1 = π × 2 R F × CF zero at or below the output filter’s double-pole, fLC , as follows: CF [μF] = 1 2π × RF [kΩ] × 0.5 × fLC [kHz] 5) The gain of the modulator (GainMOD)—comprised of the regulator’s pulse-width modulator, LC filter, feedback divider, and associated circuitry—at the crossover frequency is: GainMOD = 4 × 1 The total loop gain is the product of the modulator gain and the error amplifier gain at fCO should be equal to 1, as follows: GainMOD x GainE/A = 1 So: 6) For those situations where fLC < fCO < fESR < fSW/2, as with low-ESR tantalum capacitors, the compensator’s second pole (fP2) should be used to cancel fESR. This provides additional phase margin. On the system Bode plot, the loop gain maintains its +20dB/decade slope up to 1/2 of the switching frequency verses flattening out soon after the 0dB crossover. Then set: fP2 = fESR If a ceramic capacitor is used, then the capacitor ESR zero, fESR, is likely to be located even above one-half of the switching frequency, that is fLC < fCO < fSW/2 < fESR. In this case, the frequency of the second pole (fP2) should be placed high enough not to significantly erode the phase margin at the crossover frequency. For example, fP2 can be set at 5 x fCO, so that its contribution to phase loss at the crossover frequency fCO is only about 11°: fP2 = 5 x fCO Once fP2 is known, calculate RI: RI [kΩ] = 1 2π × fP2 [kHz] × CI [μF] 7) Place the second zero (fZ2) at 0.2 x fCO or at fLC, whichever is lower, and calculate R1 using the following equation: R1[kΩ] = 1 2π × fZ2[kHz] × CI[μF] 8) Place the third pole (fP3) at 1/2 the switching frequency and calculate CCF from: CCF [nF] = 1 π 2 × 0.5 × f [MHz] × RF [kΩ]) ( SW 9) Calculate R2 as: R2 [kΩ] = R1[kΩ] × 1 2 (2π × fCO[kHz]) × COUT [μF] × L[μH] × 2π × fCO[kHz] × CI[pF] × RF [kΩ] = 1 Maxim Integrated 4 × RF [kΩ] (2π × fCO [MHz])2 × L[μH] × COUT [μF] The gain of the error amplifier (GainE/A) in midband frequencies is: GainE/A = 2π × fCO [kHz] × CI [μF] × RF [kΩ] 4× (2π × fCO [kHz] × L[μH] × COUT [μF]) VFB [V] VOUT_ [V] − VFB [V] where VFB = 0.6V (typ). 19 MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Applications Information PCB Layout Guidelines Careful PCB layout is critical to achieve clean and stable operation. Follow these guidelines for good PCB layout: 1) Place decoupling capacitors as close as possible to the IC pins. 2) Keep SGND and PGND isolated and connect them at one single point close to the negative terminal of the input filter capacitor. 3) Route high-speed switching nodes away from sensitive analog areas (FB_, COMP_, and EN_). 4) Distribute the power components evenly across the board for proper heat dissipation. 6) Place the bank of the output capacitors close to the load. 7) Connect the MAX15021 exposed pad to a large copper plane to maximize its power dissipation capability. Connect the exposed pad to SGND plane. Do not connect the exposed pad to the SGND pin directly underneath the IC. 8) Use 2oz. copper to keep trace inductance and resistance to a minimum. Thin copper PCBs can compromise efficiency since high currents are involved in the application. Also thicker copper conducts heat more effectively, thereby reducing thermal impedance. 9) A reference PCB layout included in the MAX15021 Evaluation Kit is also provided to further aid layout. 5) Ensure timing resistor and all feedback connections are short and direct. Place feedback resistors as close as possible to the IC. 20 Maxim Integrated MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Typical Operating Circuits VIN CI2 R1FB2 RI2 C1 R1 CF2 RF2 R2FB2 C2 CIN2 AVIN EN2 PVIN2 DVDD2 CDD2 CCF2 FB2 COMP2 LX2 L2 VOUT2 RS2 COUT2 CS2 PGND2 VIN CDD1 DVDD1 EN1 MAX15021 VIN VAVIN CIN1 PVIN1 VOUT1 L1 LX1 RS1 COUT1 CS1 PGND1 CI1 RI1 R1FB1 R1EN2 R2FB1 R2EN2 FB1 RT PGND SGND SGND SEL COMP1 VAVIN RT CT CF1 RF1 CCF1 Figure 7. MAX15021 Double Buck with Tracking Maxim Integrated 21 MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Typical Operating Circuits (continued) VOUT1 VIN CI2 R1OUT2 RI2 C1 R1 CF2 RF2 R2OUT2 C2 CIN2 AVIN EN2 PVIN2 CDD2 DVDD2 CCF2 FB2 COMP2 LX2 L2 VOUT2 RS2 COUT2 CS2 PGND2 VIN CDD1 DVDD1 EN1 VIN MAX15021 VAVIN CIN1 PVIN1 VOUT1 L1 LX1 RS1 COUT1 CS1 PGND1 CI1 RI1 R1OUT1 FB1 RT PGND SGND SEL COMP1 R2OUT1 SGND CF1 RT CT RF1 CCF1 Figure 8. MAX15021 Double Buck with Sequencing 22 Maxim Integrated MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Package Information Chip Information PROCESS: BiCMOS Maxim Integrated For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 28 TQFN-EP T2855+6 21-0140 90-0026 23 MAX15021 Dual, 4A/2A, 4MHz, Step-Down DC-DC Regulator with Tracking/Sequencing Capability Revision History REVISION NUMBER REVISION DATE 0 5/08 Initial release — 1 8/12 Added automotive qualified part to Ordering Information 1 DESCRIPTION PAGES CHANGED Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 24 Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 © 2012 Maxim Integrated Products, Inc. The Maxim logo and Maxim Integrated are trademarks of Maxim Integrated Products, Inc.