FAIRCHILD FIN224AC

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FIN224AC
µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Features
FIN224AC to FIN24AC Comparison
■ Industry smallest 22-bit Serializer/ Deserializer pair
■ Up to 20% power reduction
■ Low power for minimum impact on battery life
■ Double wide CKP pulse on FIN224AC, Mode 3
■
■
■
■
■
■
■
■
■
■
– Multiple power-down modes
100nA in standby mode, 5mA typical operating
conditions
Highly rolled LVCMOS edge rate option to meet
regulatory requirements
Cable reduction: 25:4 or greater
Differential signaling:
––90dBm EMI when using CTL in lab conditions
–Minimized shielding
–Minimized EMI filter
–Minimum susceptibility to external interference
Up to 22 bits in either direction
Up to 26MHz parallel interface operation
Voltage translation from 1.65V to 3.6V
High ESD protection: > 15kV HBM
Parallel I/O power supply (VDDP) range, 1.65V - 3.6V
Can support Microcontroller or RGB pixel interface
Applications
■ Image sensors
■ Small displays
– LCD, cell phone, digital camera, portable gaming,
printer, PDA, video camera, automotive
■ Rolled edge rate for deserializer outputs on
FIN224AC, for single display applications
■ Same voltage range
■ Same pinout and package
General Description
The FIN224AC µSerDes™ is a low-power Serializer/
Deserializer (SerDes) that can help minimize the cost
and power of transferring wide signal paths. Through the
use of serialization, the number of signals transferred
from one point to another can be significantly reduced.
Typical reduction is 4:1 to 6:1 for unidirectional paths.
For bidirectional operation, using half duplex for multiple
sources, it is possible to reach signal reduction close to
10:1. Through the use of differential signaling, shielding
and EMI filters can also be minimized, further reducing
the cost of serialization. The differential signaling is also
important for providing a noise-insensitive signal that can
withstand radio and electrical noise sources. Major
reduction in power consumption allows minimal impact
on battery life in ultra-portable applications. A unique
word boundary technique assures that the actual word
boundary is identified when the data is deserialized. This
guarantees that each word is correctly aligned at the
deserializer on a word-by-word basis through a unique
sequence of clock and data that is not repeated except
at the word boundary. It is possible to use a single PLL
for most applications including bi-directional operation.
Ordering Information
Order Number
Package
Number
Pb-Free
FIN224ACGFX
BGA042
Yes
42-Ball Ultra Small Scale Ball Grid Array (USS-BGA),
JEDEC MO-195, 3.5mm Wide (Slow LVCMOS Edge Rate)
FIN224ACMLX
MLP040
Yes
40-Terminal Molded Leadless Package (MLP), Quad,
JEDEC MO-220, 6mm Square (Slow LVCMOS Edge Rate)
Package Description
Pb-Free package per JEDEC J-STD-020B. BGA and MLP packages available in tape and reel only.
µSerDesTM is a trademark of Fairchild Semiconductor Corporation.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
November 2006
LVCMOS
22
LVCMOS
CTL
FIN224AC
Serializer
FIN224AC
Deserializer
4
22
Figure 1. Conceptual Diagram
Functional Block Diagram
PLL
CKREF
STROBE
0
+
CKS0+
-
CKS0-
I
cksint
Register
DP[21:22]
Word
Boundary
Generator
Serializer
Control
DSO+/DSI-
+
-
Serializer
DP[1:20]
DSO-/DSI+
DP[23:24]
+
Register
Register
oe
Deserializer
-
Deserializer
Control
cksint
CKSI+
CKSI100
Termination
WORD CK
Generator
CKP
+
-
100 Gated
Termination
Control Logic
S1
S2
DIRO
Freq
Control
Direction
Control
DIRI
oe
Power Down
Control
Figure 2. Block Diagram
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
2
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Basic Concept
Terminal
Name
I/O Type
Number of
Terminals
DP[1:20]
I/O
20
LVCMOS parallel I/O, Direction controlled by DIRI pin
DP[21:22]
I
2
LVCMOS parallel unidirectional inputs
DP[23:24]
O
2
LVCMOS unidirectional parallel outputs
CKREF
IN
1
LVCMOS clock input and PLL reference
STROBE
IN
1
LVCMOS strobe signal for latching data into the serializer
CKP
OUT
1
LVCMOS word clock output
DSO+ / DSIDSO- / DSI+
DIFF-I/O
2
CTL differential serial I/O data signals(1)
DSO: Refers to output signal pair
DSI: Refers to input signal pair
DSO(I)+: Positive signal of DSO(I) pair
DSO(I)-: Negative signal of DSO(I) pair
CKSI+
CKSI-
DIFF-IN
2
CTL differential deserializer input bit clock
CKSI: Refers to signal pair
CKSI+: Positive signal of CKSI pair
CKSI-: Negative signal of CKSI pair
CKSO+
CKSO-
DIFF-OUT
2
CTL differential serializer output bit clock
CKSO: Refers to signal pair
CKSO+: Positive signal of CKSO pair
CKSO-: Negative signal of CKSO pair
S1
IN
1
S2
IN
1
LVCMOS mode selection terminals used to select frequency range for
the reflect, CKREF
DIRI
IN
1
LVCMOS control input used to control direction of data flow:
DIRI = “1” Serializer
DIRI = “0” Deserializer
DIRO
OUT
1
LVCMOS control output inversion of DIRI
VDDP
Supply
1
Power supply for parallel I/O and translation circuitry
VDDS
Supply
1
Power supply for core and serial I/O
VDDA
Supply
1
Power supply for analog PLL circuitry
GND
Supply
2
For ground signals (2 for µBGA, 1 for MLP)
Description of Signals
Notes:
1. The DSO/DSI serial port pins have been arranged such that if one device is rotated 180 degrees with respect to the
other device, the serial connections properly align without the need for any traces or cable signals to cross. Other
layout orientation may require that traces or cables cross.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
3
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Terminal Description
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
31 CKREF
32 STROBE
33 DP[1]
34 DP[2]
35 DP[3]
36 DP[4]
37 DP[5]
38 DP[6]
22 S2
10
21 VDDS
DP[17]
DP[18]
DP[19]
DP[20]
DP[21]
DP[22]
DP[23]
DP[24]
S1
VDDA
20
23 DIRI
9
19
24 CKSI+
8
18
25 CKSI-
7
17
26 DSO-
6
16
27 DSO+
5
15
28 CKSO-
4
14
29 CKSO+
3
13
30 DIRO
2
12
1
11
DP[9]
DP[10]
DP[11]
DP[12]
VDDP
CKP
DP[13]
DP[14]
DP[15]
DP[16]
39 DP[7]
40 DP[8]
Connection Diagrams
Figure 3. Terminal Assignments for µBGA
(Top View)
Pin Assignments
1
2
3
4
5
6
A
DP[9]
DP[7]
DP[5]
DP[3]
DP[1]
CKREF
B
DP[11]
DP[10]
DP[6]
DP[2]
STROBE
DIRO
CKSO+
CKSO-
C
CKP
DP[12]
DP[8]
DP[4]
D
DP[13]
DP[14]
VDDP
GND
E
DP[15]
DP[16]
GND
VDDS
CKSI+
CKSI-
F
DP[17]
DP[18]
DP[21]
VDDA
S2
DIRI
J
DP[19]
DP[20]
DP[22]
DP[23]
DP[24]
S1
DSO-/DSI+ DSO+/DSI-
Figure 4. Terminal Assignments for µBGA
(Top View)
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
4
Turn-Around Functionality
The FIN224AC has the ability to be used as a 22-bit serializer or a 22-bit deserializer. Pins S1 and S2 must be
set to accommodate the clock reference input frequency
range of the serializer. Table 1 shows the pin programming of these options based on the S1 and S2 control
pins. The DIRI pin controls whether the device is a serializer or a deserializer. When DIRI is asserted LOW, the
device is configured as a deserializer. When the DIRI pin
is asserted HIGH, the device is configured as a serializer. Changing the state on the DIRI signal reverses the
direction of the I/O signals and generate the opposite
state signal on DIRO. For unidirectional operation the
DIRI pin should be hardwired to the HIGH or LOW state
and the DIRO pin should be left floating. For bi-directional operation, the DIRI of the master device is driven
by the system and the DIRO signal of the master is used
to drive the DIRI of the slave device.
The device passes and inverts the DIRI signal through
the device asynchronously to the DIRO signal. Care
must be taken by the system designer to ensure that no
contention occurs between the deserializer outputs and
the other devices on this port. Optimally the peripheral
device driving the serializer should be put into a HIGHimpedance state prior to the DIRI signal being asserted.
When a device with dedicated data outputs turns from a
deserializer to a serializer, the dedicated outputs remain
at the last logical value asserted. This value only
changes if the device is once again turned around into a
deserializer and the values are overwritten.
Power-Down Mode: (Mode 0)
Mode 0 is used for powering down and resetting the
device. When both of the mode signals are driven to a
LOW state, the PLL and references are disabled, differential input buffers are shut off, differential output buffers
are placed into a HIGH-impedance state, LVCMOS outputs are placed into a HIGH-impedance state, and LVCMOS inputs are driven to a valid level internally.
Additionally all internal circuitry is reset. The loss of
CKREF state is also enabled to ensure that the PLL only
powers-up if there is a valid CKREF signal.
Serializer/Deserializer with Dedicated I/O Variation
The serialization and deserialization circuitry is set up for
24 bits. Because of the dedicated inputs and outputs,
only 22 bits of data are ever serialized or deserialized.
Regardless of the mode of operation, the serializer is
always sending 24 bits of data plus 2 boundary bits and
the deserializer is always receiving 24 bits of data and 2
word boundary bits. Bits 23 and 24 of the serializer
always contain the value of zero and are discarded by
the deserializer. DP[21:22] input to the serializer is deserialized to DP[23:24] respectively.
In a typical application mode, signals of the device do not
change states other than between the desired frequency
range and the power-down mode. This allows for system-level power-down functionality to be implemented
via a single wire for a SerDes pair. The S1 and S2 selection signals that have their operating mode driven to a
“logic 0” should be hardwired to GND. The S1 and S2
signals that have their operating mode driven to a “logic
1” should be connected to a system-level power-down or
reset signal.
Table 1. Control Logic Circuitry
Mode
Number
S2
S1
DIRI
Description
0
0
0
x
Power-Down Mode
1
0
1
1
22-Bit Serializer 2MHz to 5MHz CKREF
0
1
0
22-Bit Deserializer
1
0
1
22-Bit Serializer 5MHz to 15MHz CKREF
2
3
1
0
0
22-Bit Deserializer
1
1
1
22-Bit Serializer 10MHz to 26MHz CKREF (Divide by 2 Serial Data)
(Note: FIN224C required for RGB applications)
1
1
0
22-Bit Deserializer
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
5
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Control Logic Circuitry
The serializer configurations are described in the following sections. The basic serialization circuitry works essentially
identically in these modes, but the actual data and clock streams differ depending on if CKREF is the same as the
STROBE signal or not. When it is stated that CKREF does not equal STROBE, each signal is distinct and CKREF
must be running at a frequency high enough to avoid any loss of data condition. CKREF must never be a lower frequency than STROBE.
The PLL must receive a stable CKREF signal to achieve lock prior to any valid
data being sent. The CKREF signal can be used as the data STROBE signal
provided that data can be ignored during the PLL lock phase.
Serializer Operation: (Figure 5)
MODE 1 or MODE 2,
DIRI = 1,
CKREF = STROBE
DPI[1:24]
Once the PLL is stable and locked, the device can begin to capture and serialize
data. Data is captured on the rising edge of the STROBE signal and then serialized. The serialized data stream is synchronized and sent source synchronously
with a bit clock with an embedded word boundary. When operating in this mode,
the internal deserializer circuitry is disabled, including the serial clock, serial data
input buffers, the bi-directional parallel outputs, and the CKP word clock. The
CKP word clock is driven HIGH.
WORD n-1
WORD n
WORD n+1
CKREF/STROBE
DSO
b24 b25 b26
b1
b2
b3
b4
b22 b23 b24 b25 b26
b1
b2
b3
b4
B5
CKS0
WORD n-2
WORD n-1
WORD n
Figure 5. Serializer Timing Diagram (CKREF = STROBE)
Serializer Operation: (Figure 6),
DIRI = 1,
CKREF does not = STROBE
If the same signal is not used for CKREF and STROBE, the CKREF signal must
be run at a higher frequency than the STROBE rate to serialize the data correctly. The actual serial transfer rate remains at 13 times the CKREF frequency.
A data bit value of zero is sent when no valid data is present in the serial bit
stream. The operation of the serializer otherwise remains the same.
The exact frequency that the reference clock needs to run at depends upon the
stability of the CKREF and STROBE signal. If the source of the CKREF signal
implements spread spectrum technology, the max frequency of the spread spectrum clock should be used in calculating the ratio of STROBE frequency to the
CKREF frequency. Similarly, if the STROBE signal has significant cycle-to-cycle
variation, the maximum cycle-to-cycle time needs to be factored into the selection of the CKREF frequency.
CKREF
DP[1:24]
WORD n-1
WORD n
WORD n+1
STROBE
DSO
b1 b2 b 3 b 4 b 5 b6
b7
b22 b23 b24 b25 b26
b1 b2 b3
CKS0
No Data
WORD n-1
No Data
WORD n
Figure 6. Serializer Timing Diagram (CKREF does not equal STROBE)
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
6
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Serializer Operation Mode
When operating in mode 3, the effective serial speed is divided by two. This
mode has been implemented to accommodate cases where the reference clock
frequency is high compared to the actual strobe frequency. The actual strobe
frequency must be less than or equal to 50% of the CKREF frequency for this
mode to work properly. This mode, in all other ways, operates the same as
described in the section where CKREF does not equal STROBE.
Serializer Operation: (Figure 7),
MODE 3 (S1 = S2 = 1), DIRI = 1,
CKREF Divide by 2 mode
CKREF
DP[1:24]
WORD n-1
WORD n
WORD n+1
STROBE
DSO
b1
b2
b3
b4
b5
b6
b7
b22 b23 b24 b25 b26
b1
b2
b3
CKS0
No Data
WORD n-1
No Data
WORD n
Figure 7. CKREF > 2x STROBE Frequency; Mode 3 Operation (S1 = S2 = 1)
Serializer Operation: (Figure 8),
DIRI = 1, No CKREF
A third method of serialization can be acheived by providing a free-running bit
clock on the CKSI signal. This mode is enabled by grounding the CKREF signal
and driving the DIRI signal HIGH. At power-up, the device is configured to accept
a serialization clock from CKSI. If a CKREF is received, this device enables the
CKREF serialization mode. The device remains in this mode even if CKREF is
stopped. To re-enable this mode, the device must be powered down and then
powered back up with a “logic 0” on CKREF.
CKSI
DP[1:24]
WORD n-1
WORD n
WORD n+1
STROBE
DSO
b 1 b 2 b3 b 4 b 5 b 6 b 7
b22 b23 b24 b25 b26
b 1 b2 b3
CKS0
No Data
WORD n-1
No Data
WORD n
Figure 8. Serializer Timing Diagram Using Provided Bit Clock (No CKREF)
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
7
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Serializer Operation Mode (Continued)
The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI
clock signal pair. The following two sections describe the operation of the deserializer under two distinct serializer
source conditions. References to the CKREF and STROBE signals refer to the signals associated with the serializer
device used in generating the serial data and clock signals that are inputs to the deserializer. When operating in this
mode, the internal serializer circuitry is disabled, including the parallel data input buffers. If there is a CKREF signal
provided, the CKSO serial clock continues to transmit bit clocks. Upon device power-up (S1 or S2 = 1), all deserializer
output data pins are driven LOW until valid data is passed through the deserializer.
When the DIRI signal is asserted LOW, the device is configured as a deserializer. Data is captured on the serial port and deserialized through use of the bit
clock sent with the data. The word boundary is defined in the actual clock and
data signal. Parallel data is generated at the time the word boundary is defined
in the actual clock and data signal. Parallel data is generated at the time the
word boundary is detected. The falling edge of CKP occurs approximately six bit
times after the falling edge of CKSI. The rising edge of CKP goes HIGH approximately 13 bit times after CKP goes LOW. The rising edge of CKP is generated
approximately 13 bit times later. When no embedded word boundary occurs, no
pulse on CKP is generated and CKP remains HIGH.
Deserializer Operation: DIRI = 0
(Serializer Source:
CKREF = STROBE)
WORD n-1
DSI b24 b25 b26
WORD n
0
bj
0
bj+1
WORD n+1
bj+13 bj+14
b24 b25 b26
0
0
CKSI
CKPO
13 bit times
6 bit times
DP[1:24] WORD n-2
WORD n-1
WORD n
Figure 9. Deserializer Timing Diagram (Serializer Source: CKREF equals STROBE)
Deserializer Operation: DIRI = 0
(Serializer Source:
CKREF does not = STROBE)
The logical operation of the deserializer remains the same if the CKREF is equal
in frequency to the STROBE or at a higher frequency than the STROBE. The
actual serial data stream presented to the deserializer is different because it has
non-valid data bits sent between words. The duty cycle of CKP varies based on
the ratio of the frequency of the CKREF signal to the STROBE signal. The frequency of the CKP signal is equal to the STROBE frequency. The falling edge of
CKP occurs six bit times after the data transition. The LOW time of the CKP signal is equal to 13 serial bit times. In modes 1 and 2, the CKP LOW time equals
half of the CKREF period of the serializer. In mode 3, the CKP LOW is equal to
the CKREF period. The CKP HIGH time is approximately equal to the STROBE
period, minus the CKP LOW time. Figure 10 is representative of a waveform that
could be seen when CKREF is not equal to STROBE. If CKREF was significantly
faster, additional non-valid data bits would occur between data words.
WORD n-1
DSI b24 b25 b26
WORD n
b1
b6
b7
b8
b9
WORD n+1
b19 b20
b24 b25 b26
b1
b2
CKSI
CKPO
DP[1:24] WORD n-2
WORD n-1
WORD n
Figure 10. Deserializer Timing Diagram (Serializer Source: CKREF does not equal STROBE)
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
8
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Deserializer Operation Mode
The LVCMOS input buffers have a nominal threshold
value equal to half VDD. The input buffers are only operational when the device is operating as a serializer.
When the device is operating as a deserializer, the inputs
are gated off to conserve power.
tive greater sensitivity of the current sense receiver of
CTL allows it to work at much lower current drive and a
much lower voltage.
During power down mode, the differential inputs are disabled and powered down and the differential outputs are
placed in a HIGH-Z state. CTL inputs have an inherent
failsafe capability that supports floating inputs. When the
CKSI input pair of the serializer is unused, it can reliably
be left floating. Alternately both of the inputs can be connected to ground. CTL inputs should never be connected
to VDD. When the CKSO output of the deserializer is
unused, it should be allowed to float.
The LVCMOS 3-STATE output buffers are rated for a
source / sink current of approximately 0.5mA at 1.8V.
The outputs are active when the DIRI signal and either
S1 or S2 is asserted HIGH. When the DIRI signal and
either S1 or S2 is asserted LOW, the bi-directional LVCMOS I/Os is in a HIGH-Z state. Under purely capacitive
load conditions, the output swings between GND and
VDDP. When S1 or S2 initially transitions HIGH, the initial
state of the deserializer LVCMOS outputs is zero.
From
Serializer
Unused LVCMOS input buffers must be either tied off to
a valid logic LOW or a valid logic HIGH level to prevent
static current draw due to a floating input. Unused LVCMOS output should be left floating. Unused bi-directional
pins should be connected to GND through a high-value
resistor. If a FIN224AC device is configured as an unidirectional serializer, unused data I/O can be treated as
unused inputs. If the FIN224AC is hardwired as a deserializer, unused data I/O can be treated as unused outputs.
From
Control
To
Deserializer
+
–
Gated
Termination
(DS Pins Only)
Figure 11. Bi-Directional Differential
I/O Circuitry
The FIN224AC family offers fast and slow LVCMOS
edge rates to meet emissions and loading requirements.
Phase-Locked Loop (PLL) Circuitry
Differential I/O Circuitry
The CKREF input signal is used to provide a reference to
the PLL. The PLL generates internal timing signals capable of transferring data at 13 times the incoming CKREF
signal. The output of the PLL is a bit clock that is used to
serialize the data. The bit clock is also sent source synchronously with the serial data stream. There are two
ways to disable the PLL. The PLL can be disabled by
entering the Mode 0 state (S1 = S2 = 0). The PLL disables immediately upon detecting a LOW on both the S1
and S2 signals. When any of the other modes are
entered by asserting either S1 or S2 HIGH and by providing a CKREF signal, the PLL powers-up and goes
through a lock sequence. One must wait the specified
number of clock cycles prior to capturing valid data into
the parallel port.
The FIN224AC employs FSC proprietary Current Transistor Logic (CTL) Input / Output (I/O) technology. CTL is
a low-power, low-EMI differential swing I/O technology.
The CTL output driver generates a constant output
source and sink current. The CTL input receiver senses
the current difference and direction from the corresponding output buffer to which it is connected. This differs
from LVDS, which uses a constant current source output,
but a voltage sense receiver. Like LVDS, an input source
termination resistor is required to properly terminate the
transmission line. The FIN224AC device incorporates an
internal termination resistor on the CKSI receiver and a
gated internal termination resistor on the DS input
receiver. The gated termination resistor ensures proper
termination regardless of direction of data flow. The rela-
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
DS+
DS-
+
–
www.fairchildsemi.com
9
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
LVCMOS Data I/O
µSerDes Serializer
U20
F6
F5
J6
GPIO_MODE
J5
J4
J3
F3
J2
J1
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
J6
F5
F6
DIRI
S2
S1
S2
S1
DIRI
TP5
CKP
B5
A6
STROBE
CKREF
B6
DIRO
B6
DIRO
C1
CKP
DSO+/DSIDSO-/DSI+
CKSOCKSO+
CKSICKSI+
D6
D5
D5
D6
C6
C5
E6
E5
E6
E5
C6
C5
DSO-/DSI+
DSO+/DSICKSICKSI+
CKSOCKSO+
2.8V
2.8V
F4
E4
D3
VDDA
VDDS
VDDP
C3
.01µF
1nF
F4
E4
D3
2.8V
1.8V
C6
D4
E3
LCD_ENABLE_M
LCD_VSYNC_M
LCD_HSYNC_M
LCD17_M
LCD16_M
LCD15_M
LCD14_M
LCD13_M
LCD12_M
LCD
LCD11_M
LCD10_M
Controller
LCD9_M
Out
LCD8_M
LCD7_M
LCD6_M
LCD5_M
LCD4_M
LCD3_M
LCD2_M
LCD1_M
LCD0_M
CKREF
STROBE
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
FIN224AC
U22
C12
C11
.01µF
VDDA
VDDS
VDDP
GND
GND
A6
B5
PIXCLK_M
µSerDes DeSerializer
FIN224AC
C10
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
C1
PIXCLK_S
J5
J4
J3
F3
J2
J1
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
LCD_ENABLE_S
LCD_VSYNC_S
LCD_HSYNC_S
LCD17_S
LCD16_S
LCD15_S
LCD14_S
LCD13_S
LCD12_S
LCD11_S
LCD10_S
LCD9_S
LCD8_S
LCD7_S
LCD6_S
LCD5_S
LCD4_S
LCD3_S
LCD2_S
LCD1_S
LCD0_S
LCD
Display
In
E3
D4
VDDP
GND
GND
TP6
2.2µF 1nF
Assumptions:
1) 18-bit Unidirectional RGB Application
2) Mode 2 Operation (5Mhz to 15Mhz CKREF)
3) VDDP= (1.65V to 3.6V)
Figure 12. FIN224AC RGB
µSerDes Serializer
CKREF
STROBE
F6
F5
J6
DIRI
S2
S1
J5
J4
J3
F3
J2
J1
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
U23
J6
F5
F6
STROBE
CKREF
B6
DIRO
D6
D5
D5
D6
DSO-/DSI+
DSO+/DSI-
CKSOCKSO+
C6
C5
E6
E5
CKSICKSI+
CKSICKSI+
E6
E5
C6
C5
CKSOCKSO+
F4
E4
D3
VDDA
VDDS
VDDP
B6
CKP
C1
DSO+/DSIDSO-/DSI+
2.8V
VDDA
VDDS
VDDP
F4
E4
D3
1.8V
C5
1nF
C9
.01uF
.01µF
TP3
2.8V
2.8V
C2
.01uF
.01µF
FIN224AC
S1
S2
DIRI
B5
A6
DIRO
D4
E3
LCD_/CS_M
LCD_ADDRESS_M
LCD17_M
LCD16_M
LCD15_M
LCD14_M
LCD13_M
LCD12_M
LCD
LCD11_M
LCD10_M
Controller
LCD9_M
Out
LCD8_M
LCD7_M
LCD6_M
LCD5_M
LCD4_M
LCD3_M
LCD2_M
LCD1_M
LCD0_M
TP1
A6
B5
µSerDes DeSerializer
FIN224AC
C8
C7
2.2uF 1nF
2.2µF
GND
GND
GPIO_MODE
U21
CKP
C1
LCD_/WRITE_ENABLE_S
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
J5
J4
J3
F3
J2
J1
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
LCD_/CS_S
LCD_ADDRESS_S
LCD17_S
LCD16_S
LCD15_S
LCD14_S
LCD13_S
LCD12_S
LCD11_S
LCD10_S
LCD
LCD9_S
LCD8_S
Display
LCD7_S
In
LCD6_S
LCD5_S
LCD4_S
LCD3_S
LCD2_S
LCD1_S
LCD0_S
E3
D4
REFCLK
LCD_/WRITE_ENABLE_M
VDDP
GND
GND
TP2
Assumptions:
1) 18-bit Unidirectional µController Application
2) Mode 3 Operation (10 Mhz to 20Mhz CKREF)
3) VDDP= (1.65V to 3.6V)
4) REFCLK is a continously running clock with a frequency
greater than /WRITE_ENABLE.
Figure 13. FIN224AC Microcontroller
Flex Circuit Design Guidelines
The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex
cable. The following best practices should be used when developing the flex cabling or Flex PCB:
■ Keep all four differential wires the same length.
■ Allow no noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential wires.
■ Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom.
■ Do not place test points on differential serial wires.
■ Use differential serial wires a minimum of 2cm away from the antenna.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
10
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Application Mode Diagrams
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed.
The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics
tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines
the conditions for actual device operation.
Symbol
VDD
Parameter
Min.
Max.
Unit
Supply Voltage
-0.5
+4.6
V
ALL input/Output Voltage
-0.5
+4.6
V
CTL Output Short Circuit Duration
Continuous
+150
°C
TJ
Maximum Junction Temperature
+150
°C
TL
Lead Temperature
+260
°C
All Pins
>2
kV
S1, S2, CKSO, CKSI, DSO, DSI, VDDA, VDDS, VDDP
(as specified in IEC61000-4-2)
>15
kV
Min.
Max.
Unit
VDDA, VDDS Supply Voltage
2.5
3.3
V
Supply Voltage
1.65
3.60
V
-30
+70
°C
100
mVp-p
TSTG
Storage Temperature Range
-65
Human Body Model, 1.5KΩ, 100pF
ESD
Recommended Operating Conditions
Symbol
VDDP
TA
VDDA-PP
Parameter
Operating
Temperature(2)
Supply Noise Voltage
Notes:
2. Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired.
The datasheet specification should be met, without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside
datasheet specifications.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
11
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Absolute Maximum Ratings
Over-supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min.
Typ.(3)
Max.
Unit
LVCMOS I/O
VIH
VIL
Input High Voltage
Input Low Voltage
Output High Voltage
IOH = 2.0mA
VOH
VDDP = 3.3±0.30
0.65 x VDDP
VDDP
GND
0.35 x VDDP
0.75 x VDDP
V
V
VDDP = 2.5±-0.20
VDDP = 1.8±0.18
Output Low Voltage
IOL = 2.0mA
VOL
VDDP = 3.3±0.30
0.25 x VDDP
V
5.0
µA
VDDP = 2.5±0.20
VDDP = 1.8±0.18
IIN
Input Current
VIN = 0V to 3.6V
-5.0
DIFFERENTIAL I/O
IODL
Output HIGH source current VOS = 1.0V
Output LOW sink current
VOS = 1.0V
IOS
Short-Circuit Output
Current
VOUT = 0V
IOZ
Disabled Output
Leakage Current
CKSO, DSO = 0V to VDDS
S2 = S1 = 0V
ITH
Differential Input Threshold See Figure 6 and Table 2
High Current
ITL
Differential Input Threshold See Figure 6 and Table 2
Low Current
IIZ
Disabled Input Leakage
Current
CKSI, DSI = 0V to VDDS
S2 = S1 = 0V
IIS
Short-Circuit Input Current
Vout =VDDS
VICM
Input Common Mode
Range
VDDS = 2.775 ±5%
RTRM
CKSI, DS Internal Receiver VID = 50mV, VIC = 925mV, DIRI = 0
Termination Resistor
| CKSI+ – CKSI– | = VID
IODH
-1.75
µA
0.950
µA
Driver Enabled
mA
Driver Disabled
±1
±5
µA
±5
µA
50
µA
±1
-50
µA
±5
uA
mA
0.5
VDDS-1
100
V
Ω
Notes:
3. Typical values are given for VDD = 2.775V and TA = 25°C. Positive current values refer to the current flowing into the
device and negative values refer to the current flowing out of the pins. Voltages are referenced to GROUND unless
otherwise specified (except ΔVOD and VOD).
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
12
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
DC Electrical Characteristics
Symbol
Parameter
Min. Typ.(4) Max. Unit
Test Conditions
IDDA1
VDDA Serializer Static Supply Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 1
450
µA
IDDA2
VDDA Deserializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 0
550
µA
IDDS1
VDDS Serializer Static Supply Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 1
4
mA
IDDS2
VDDS Deserializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 0
4.5
mA
IDD_PD
VDD Power-Down Supply Current
IDD_PD = IDDA
S1 = S2 = 0 All Inputs at GND or VDD
0.1
µA
9
mA
IDD_SER1 26:1 Dynamic Serializer
Power Supply Current
IDD_SER1 = IDDA+IDDS+IDDP
CKREF = STROBE S2 = 0 2MHz
DIRI = H
S1 = 1 5MHz
S2 = 1 5MHz
S1 = 0 15MHz
S2 = 1 10MHz
S1 = 1 26MHz
IDD_DES1 26:1 Dynamic Deserializer
Power Supply Current
IDD_DES1 = IDDA+IDDS+IDDP
IDD_SER2 26:1 Dynamic Serializer
Power Supply Current
IDD_SES2 = IDDA+IDDS+IDDP
CKREF = STROBE S2 = 0 2MHz
DIRI = L
S1 = 1 5MHz
14
9
17
9
16
5
6
S2 = 1 5MHz
S1 = 0 15MHz
4
S2 = 1 10MHz
S1 = 1 26MHz
7
NO CKREF
STROBE Active
CKSI = 15x STROBE
DIRI = H
mA
5
11
2MHz
8
5MHz
8
10MHz
10
15MHz
12
mA
Notes:
4. Typical values are given for VDD = 2.775V and TA = 25°C. Positive current values refer to the current flowing into the
device and negative values refer to the current flowing out of the pins. Voltages are referenced to GROUND unless
otherwise specified (except ΔVOD and VOD).
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
13
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Power Supply Currents
Characteristics at recommended over-supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min.
Typ.(5)
Max.
Unit
200
66
38.46
T
500
200
100.00
ns
Serializer Input Operating Conditions
tTCP
CKREF Clock Period
(2MHz – 26MHz)
CKREF = STROBE S2=0 S1=1
See Figure 14
S2=1 S1=0
S2=1 S1=1
fREF
CKREF Frequency Relative to
STROBE
CKREF does not =
STROBE
S2=0 S1=1
2.25 x
fSTROBE
MHz
tCPWH
CKREF Clock High Time
0.2
0.5
T
tCPWL
CKREF Clock Low Time
0.2
0.5
T
tCLKT
LVCMOS Input Transition Time
See Figure 16
tSPWH
STROBE Pulse Width HIGH/LOW
See Figure 16
CKREF x 26
fMAX
Maximum Serial Data Rate
tSTC
DP(n) Setup to STROBE
tHTC
DP(n) Hold to STROBE
S2=0 S1=1
S2=1 S1=0
S2=1 S1=1
DIRI = 1
90.0
ns
(Tx4)/26
(Tx22)/26
ns
52
130
260
130
390
676
Mb/s
2.5
ns
2.0
ns
Serializer AC Electrical Characteristics
tTCCD
Transmitter Clock Input to Clock
Output Delay
tSPOS
CKSO Position Relative to DS(6)
CKREF = STROBE
33a+1.5
35a+6.5
ns
-50.0
250.0
ps
200
µs
PLL AC Electrical Characteristics
tTPLLS0
Serializer Phase Lock Loop
Stabilization Time
See Figure 18
tTPLLD0
PLL Disable Time Loss of Clock
See Figure 21
30.0
µs
tTPLLD1
PLL Power-Down Time(7)
See Figure 22
20.0
ns
Deserializer Input Operating Conditions
tS_DS
Serial Port Setup Time,
DS-to-CKSI(8)
1.4
ns
tH_DS
Serial Port Hold Time,
DS-to-CKS(8)
-250
ps
Deserializer AC Electrical Characteristics
tRCOP
Deserializer Clock Output
(CKP OUT) Period(9)
See Figure 17
tRCOL
CKP OUT Low Time
tRCOH
CKP OUT High Time
See Figure 17
(Rising Edge STROBE)(9) Serializer source STROBE = CKREF
tPDV
Data Valid to CKP LOW
See Figure 17
(Rising Edge STROBE)
50.0
T
500.0
ns
13a-3
13a+3
ns
13a-3
13a+3
ns
8a-6
8a+1
ns
tROLH
Output Rise Time (20% to 80%)
(FIN224AC)
CL = 8pF
See Figure 14
18
ns
tROHL
Output Fall Time (20% to 80%)
(FIN224AC)
CL = 8pF
See Figure 14
18
ns
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
14
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
AC Electrical Characteristics
Control Logic Timing Controls
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
tPHL_DIR,
tPLH_DIR
Propagation Delay
DIRI-to-DIRO
DIRI LOW-to-HIGH or HIGH-to-LOW
17.0
ns
tPLZ, tPHZ
Propagation Delay
DIRI-to-DP
DIRI LOW-to-HIGH
25.0
ns
tPZL, tPZH
Propagation Delay
DIRI-to-DP
DIRI HIGH-to-LOW
25.0
ns
tPLZ, tPHZ
Deserializer Disable Time: DIRI = 0,
S0 or S1 to DP
S1(2) = 0 and S2(1) = LOW-to-HIGH Figure 23
25.0
ns
tPZL, tPZH
Deserializer Enable Time:
S0 or S1 to DP
DIRI = 0,(10)
S1(2) = 0 and S2(1) = LOW-to-HIGH Figure 23
2.0
µs
tPLZ, tPHZ
Serializer Disable Time:
S0 or S1 to CKSO, DS
DIRI = 1,
S1(2) = 0 and S2(1) = HIGH-to-LOW Figure 22
25.0
ns
tPZL, tPZH
Serializer Enable Time:
S0 or S1 to CKSO, DS
DIRI = 1,
S1(2) and S2(1) = LOW-to-HIGH Figure 22
65.0
ns
Notes:
10. Deserializer Enable Time includes the time required for internal voltage and current references to stabilize. This time
is significantly less than the PLL Lock Time and therefore does not limit overall system startup time.
Capacitance
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
CIN
Capacitance of Input Only Signals, DIRI = 1, S1 = S2 = 0,
CKREF, STROBE, S1, S2, DIRI
VDD = 2.5V
2.0
pF
CIO
Capacitance of Parallel Port Pins
DP1:12
DIRI = 1, S1 = S2 = 0,
VDD = 2.5V
2.0
pF
CIO-DIFF
Capacitance of Differential I/O Sig- DIRI = 0, S1 = S2 = 0,
nals
VDD = 2.775V
2.0
pF
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
15
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Notes:
5. Typical values are given for VDD = 2.775V and TA = 25°C. Positive current values refer to the current flowing into
device and negative values means current flowing out of the pins. Voltages are referenced to GROUND unless
otherwise specified (except DVOD and VOD).
6. Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO).
Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid.
7. The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the
state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies
dependent upon the operating mode of the device.
8. Signals are transmitted from the serializer source synchronously. Note that, in some cases, data is transmitted when
the clock remains at a HIGH state. Skew should only be measured when data and clock are transitioning at the same
time. Total measured input skew would be a combination of output skew from the serializer, load variations, and ISI
and jitter effects.
9. (a = (1/f)/13) Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling
edge of CKP occurs approximately eight bit times after a data transition or six bit times after the falling edge of
CKSO. Variation of the data with respect to the CKP signal is due to internal propagation delay differences of the
data and CKP path and propagation delay differences on the various data pins. Note that if the CKREF is not equal
to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle.The low time of CKP remains 13
bit times.
Setup Time
tROLH
STROBE
tROHL
80%
tSTC
DP[1:12]
80%
Data
20%
DPn 20%
tHTC
Hold Time
DPn
STROBE
DP[1:12]
8pF
Data
Setup: MODE0 = “0” or “1”, MODE1 = “1”, SER/DES = “1”
Figure 14. LVCMOS Output Load
and Transition Times
Figure 15. Serial Setup and Hold Time
Data Time
tCLKT
tPDV
tCLKT
90%
90%
CKP
Data
DP[1:12]
10%
10%
tRCOP
tTCP
CKREF
50%
CKREF
VIH
VIL
tCPWH
50%
50%
75%
50%
25%
tRCOH
tRCOL
tCPWL
Setup: EN_DES = “1”, CKSI and DSI are valid signals
Figure 16. LVCMOS Clock Parameters
Figure 17. Deserializer Data Valid Window
Time and Clock Output Parameters
tTPLS0
VDD/VDDA
tTCCD
S1 or S2
STROBE
CKREF
CKS0CKS0+
CKS0
VDIFF = 0
Note: STROBE = CKREF
Note: CKREF Signal is free running.
Figure 18. Serializer PLL Lock Time
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
VDD/2
Figure 19. Serializer Clock Propagation Delay
www.fairchildsemi.com
16
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
AC Loading and Waveforms
tTPPLD0
CKREF
tRCCD
CKSI-
CKS0
VDIFF = 0
CKSI+
CKP
VDD/2
Note: CKREF Signal can be stopped either High or LOW
Figure 20. Deserializer Clock Propagation Delay
Figure 21. PLL Loss of Clock Disable Time
tPZL(ZH)
tPLZ(HZ)
S1 or S2
tTPPLD1
DS+,CKS0+
S1 or S2
HIGHZ
DS+,CKS0-
CKS0
Note: CKREF must be active and PLL must be stable
Figure 22. PLL Power-Down Time
Figure 23. Serializer Enable and Disable Time
tPLZ(HZ)
tPZL(ZH)
S1 or S2
DP
Note: If S1(2) transitioning then S2(1) must = 0 for test to be valid
Figure 24. Deserializer Enable and Disable Times
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
17
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
AC Loading and Waveforms (Continued)
BGA Embossed Tape Dimension
Dimensions are in millimeters.
D
P0
T
P2
E
F
K0
W
Wc
B0
Tc
A0
P1
D1
User Direction of Feed
Package
A0
B0
D
D1
E
F
K0
P1
P0
P2
T
TC
W
WC
3.5 x 4.5
TBD
±0.1
TBD
±0.1
1.55
±0.05
1.5
Min.
1.75
±0.1
5.5
±0.1
1.1
±0.1
8.0
Typ.
4.0
Typ.
2.0
±0/05
0.3
Typ.
0.07
±0.005
12.0
±0.3
9.3
Typ.
Notes:
A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement
requirements (see sketches A, B, and C).
Shipping Reel Dimensions
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
18
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Tape and Reel Specification
1.0mm
maximum
10° maximum
Typical component
cavity center line
Typical component
center line
B0
10° maximum component rotation
Sketch A (Side or Front Sectional View)
Sketch C (Top View)
A0
Sketch B (Top View)
Component Rotation
1.0mm
maximum
Component lateral movement
Component Rotation
W1 Measured at Hub
W2 max Measured at Hub
B Min
Dia C
Dia A
max
Dia D
min
Dia N
DETAIL AA
See detail AA
W3
Tape
Width
Dia A
Dim B
Dia C
1.5 Min.
13.0
+0.5/–0.2
Dia D
Dim N
Dim W1
178 Min.
8.4
+2.0/–0
8
12
330 Max.
20.2 Min.
16
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
Dim W2
Dim W3
(LSL–USL)
14.4 Max.
7.9 ~ 10.4
18.4 Max.
11.9 ~ 15.4
22.4 Max.
15.9 ~ 19.4
www.fairchildsemi.com
19
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Dimensions are in millimeters.
MLP Embossed Tape Dimension
Dimensions are in millimeters.
D
P0
T
P2
E
F
K0
W
Wc
B0
Tc
A0
Package
A0
B0
5x5
5.35
±0.1
5.35
±0.1
6x6
6.30
±0.1
6.30
±0.1
P1
D
D1
E
F
1.55
±0.05
1.5
Min.
1.75
±0.1
5.5
±0.1
D1
K0
User Direction of Feed
P1
P0
P2
1.4
2.0
8 Typ. 4 Typ.
±0.1
±0.05
T
TC
W
WC
0.3
Typ.
0.07
±0.005
12
±0.3
9.3
Typ.
Notes:
Ao, Bo, and Ko dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement
requirements (see sketches A, B, and C).
Shipping Reel Dimension
Dimensions are in millimeters.
1.0mm
maximum
10° maximum
Typical component
cavity center line
Typical component
center line
B0
10° maximum component rotation
Sketch A (Side or Front Sectional View)
Sketch C (Top View)
A0
Sketch B (Top View)
Component Rotation
1.0mm
maximum
Component lateral movement
Component Rotation
W2 max Measured at Hub
W1 Measured at Hub
B Min
Dia C
Dia A
max
Dia D
min
Dia N
DETAIL AA
See detail AA
Tape
Width
Dia A
Dim B
Dia C
1.5 Min.
13.0
+0.5/–0.2
Dia D
W3
Dim N
Dim W1
178 Min.
8.4
+2.0/–0
8
12
330 Max.
20.2 Min.
16
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
Dim W2
Dim W3
(LSL–USL)
14.4 Max.
7.9 ~ 10.4
18.4 Max.
11.9 ~ 15.4
22.4 Max.
15.9 ~ 19.4
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20
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Tape and Reel Specification (Continued)
Dimensions are in millimeters unless otherwise noted.
2X
3.50
0.10 C
2X
(0.35)
(0.5)
0.10 C
(0.6)
2.5
(0.75)
TERMINAL
A1 CORNER
INDEX AREA
4.50
3.0
0.5
0.5
Ø0.3±0.05
BOTTOM VIEW
X42
0.15
0.05
C A B
C
0.89±0.082
(QA CONTROL VALUE)
0.45±0.05
1.00 MAX
0.21±0.04
0.10 C
C
0.2+0.1
-0.0
0.08 C
0.23±0.05
SEATING PLANE
LAND PATTERN
RECOMMENDATION
Figure 25. Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
21
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Physical Dimensions
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
(DATUM A)
Figure 26. Pb-Free 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
22
FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
23