FIN210AC 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz Features Data & Control Bits Frequency Capability Interface µController Usage Selectable Edge Rates Standby Current Core Voltage (VDDA/S) I/O Voltage (VDDP) ESD (I/O to GND) Package Ordering Information Description 10-bit 48MHz Camera or LCD Microcontroller, RGB, YUV m68 & i86 Yes <10µA 2.8 to 3.6V 1.65 to 3.6V 15kV 32-Terminal MLP (Preliminary) 42-Ball USS-BGA FIN210ACMLX (Preliminary) FIN210ACGFX The FIN210AC µSerDes™ is a low-power serializer / deserializer optimized for use in cell phone displays and camera paths. The device reduces a 10-bit data path to four wires. For camera applications, an additional master clock can be passed in the opposite direction of data flow. The device utilizes Fairchild’s proprietary ultra-low power, lowEMI technology. Applications Slider, Folder, & Clamshell Mobile Handsets Printers Security Cameras Related Resources For samples and questions, please contact: [email protected]. Typical Application Built-in voltage translation Internal Termination FIN210AC FIN210AC 12-Bit 10-Bit Des erializer Baseband 2 - + - 2 + - + - 12-Bit Serializer 10-Bit + Camera Module CTL™ Isolates interface for signal integrity Up to 48MHz Camera Module Figure 1. Mobile Phone Example © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 www.fairchildsemi.com µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz June 2009 Pin Name Description DIRI Control to determine serializer or deserializer configuration. CTL_ADJ Adjusts CTL drive to compensate for environmental conditions and length. S0 Configure frequency range for the PLL. 0 Deserializer 1 Serializer 0 Low drive (low power) 1 High drive (high power) See Table 1 Serializer (DIRI=1) Control Pin. S1 Configure frequency range for the PLL. See Table 1 Serializer (DIRI=1) Control Pin. PLL0 Divide or adjust the serial frequency. See Table 1 Serializer (DIRI=1) Control Pin. PLL1 CKREF STROBE DP[1:10] CKSO+ CKSODSO+ DSOCKSI+ CKSICKP Divide or adjust the serial frequency. See Table 1 Serializer (DIRI=1) Control Pin. LV-CMOS clock input and PLL reference. LV-CMOS strobe input for latching data (DP [1:12]) into the serializer on the rising edge. LV-CMOS parallel data input. (GND input if not used) CTL Differential serializer output bit clock. CKSO+: Positive signal; CKSO-: Negative signal. CTL Differential serial output data signals. DSO+: Positive signal; DSO-: Negative signal. CTL Differential deserializer input bit clock. No connect unless in “clock pass-through” mode. CKSI+: Positive signal; CKSI-: Negative signal. LV-CMOS word clock output or Pixel clock output. No connect unless in “clock pass-through” mode. LV-CMOS output, Inversion of DIRI in normal operation. Can be used to drive the DIRI No connect if not used. signal of the deserializer where the interface needs to be turned around. Power supply for parallel I/O. (All VDDP pins must be connected to VDDP) Power supply for serial I/O. Power supply for core. All GND pins must be connected to ground. BGA: all GND pads. MLP: Pin 29 & GND PAD must be grounded. No connect. (Do not connect to GND or VDD) /DIRO VDDP VDDS VDDA GND N/C Note: 1. 0=GND; 1=VDDP B DP[6] DP[5] DP[1] N/C STROBE /DIRO C CKP N/C DP[3] N/C CKSO+ CKSO - DP[4] 1 24 CKSO+ DP[5] 2 23 CKSO- DP[6] 3 D N/C DP[7] VDDP GND DSO- DSO+ VDDP 4 GND VDDS CKSI+ CKSI- F DP[10] GND N/C VDDA N/C DIRI G GND N/C PLL1 PLL0 S1 S0 DP[7] 6 20 CKSI19 CKSI+ DP[8] 7 18 DIRI DP[9] 8 17 VDDS GND 10 DP[9] 21 DSO- GND PAD DP[10] 9 DP[8] 22 DSO+ SERIALIZER CKP 5 E 25 /DIRO CKREF VDDA 16 N/C 26 CKREF CTL_ADJ S0 15 GND 27 STROBE DP[2] S1 14 DP[4] 28 CTL_ADJ A PLL0 13 6 29 GND 5 PLL1 12 4 30 DP[1] 3 GND 11 2 31 DP[2] 1 32 DP[3] FIN210AC (Serializer DIRI=1) Pin Configurations 32-pin MLP, 5 x 5mm, .5mm pitch (Top View) (Center pad must be grounded) 42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View) Figure 2. FIN210AC (Serializer DIRI=1) Pin Assignments (Top View) © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 www.fairchildsemi.com 2 µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz FIN210AC (Serializer DIRI=1) Pin Descriptions Pin Name Description DIRI Control to determine serializer or deserializer configuration. XTERM Control to determine if using internal or external termination S0 Signals used to define the edge rate of parallel I/O. 0 Deserializer 1 Serializer 0 Internal termination used 1 External termination required on CKSI & DSI See Table 2 Deserializer (DIRI=0) Control Pin. S1 Signals used to define the edge rate of parallel I/O. See Table 2 Deserializer (DIRI=0) Control Pin. PWS0 Configure CKP pulse width. See Table 2 Deserializer (DIRI=0) Control Pin. PWS1 Configure CKP pulse width. See Table 2 Deserializer (DIRI=0) Control Pin. /ENZ DP[1:10] CKP DSI+ DSICKSI+ CKSICKSO+ CKSOCKREF STROBE /DIRO VDDP VDDS VDDA GND N/C High-Z or known state outputs during power down See Table 5 Deserializer (DIRI=0) Control Pin. LV-CMOS parallel data output. (N/C if not used) LV-CMOS word clock output or Pixel clock output. CTL Differential serial input data signals. DSI+: Positive signal; DSI-: Negative signal. CTL Differential deserializer input bit clock. CKSI+: Positive signal; CKSI-: Negative signal. CTL Differential serializer output bit clock. No connect unless in “clock pass-through” mode. CKSO+: Positive signal; CKSO-: Negative signal. LV-CMOS clock input and PLL reference. No connect unless in “clock pass-through” mode. LV-CMOS strobe input for latching data into the serializer. No connect unless in “clock pass-through” mode. LV-CMOS Output. Inversion of DIRI in normal operation. No connect if not used. Power supply for parallel I/O. (All VDDP pins must be connected to VDDP) Power supply for serial I/O. Power supply for core. All GND pins must be connected to ground. BGA: all GND pads. MLP: Pin 28, 29, GND PAD must be grounded. No connect. BGA: G1, F2; MLP: 10, 11; (Do not connect to GND or VDD) Note: 2. 0=GND; 1=VDDP DP[6] DP[5] DP[1] N/C STROBE /DIRO C CKP DP[3] N/C CKSO+ CKSO- DP[4] 1 24 CKSO+ DP[5] 2 23 CKSO- DP[6] 3 N/C DP[7] VDDP GND DSI+ DSI- E DP[8] DP[9] GND VDDS CKSI+ CKSI- F DP[10] N/C N/C VDDA N/C DIRI G N/C N/C PWS1 PWS0 S1 S0 22 DSI- DESERIALIZER VDDP 4 CKP 5 21 DSI+ 20 CKSI- GND PAD DP[7] 6 19 CKSI+ DP[8] 7 18 DIRI DP[9] 8 17 VDDS DP[10] 9 D N/C 25 /DIRO B VDDA 16 CKREF 26 CKREF N/C S0 15 /ENZ 27 STROBE XTRM S1 14 DP[2] 28 /ENZ DP[4] PWS0 13 A 29 XTRM 6 PWS1 12 5 30 DP[1] 4 N/C 11 3 31 DP[2] 2 N/C 10 1 32 DP[3] FIN210AC (Deserializer DIRI=0) Pin Configurations 32-pin MLP, 5mm x 5mm, .5mm pitch (Top View) (Center pad must be grounded) 42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View) Figure 3. FIN210AC (Deserializer DIRI=0) Pin Assignments (Top View) © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 www.fairchildsemi.com 3 µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz FIN210AC (Deserializer DIRI=0) Pin Descriptions Table 1. Serializer (DIRI=1) Control Pin Function Conditions CKREF Control Pin PLL Multiplier STROBE PLL1 PLL0 S0 S1 Slow Frequencies Normal operation 5MHz to 15MHz ≤ CKREF (Up to 15MHz) 1 1 0 0 1 5MHz to 14.2MHz ≤ CKREF (Up to 14.2MHz) 0.947 0 0 0 1 With a fixed CKREF input; STROBE can be 1/2 the speed 5MHz to 15MHz ≤ CKREF / 2 (Up to 7.5MHz) 2 0 1 0 1 With a fixed CKREF input; STROBE can be 1/3 the speed 5MHz to 15MHz ≤ CKREF / 3 (Up to 5MHz) 3 1 1 0 1 Supports spread spectrum on CKREF Medium Frequencies Normal operation 10MHz to 30MHz ≤ CKREF (Up to 30MHz) 1 1 0 1 1 10MHz to 28.4MHz ≤ CKREF (Up to 28.4MHz) 0.947 0 0 1 1 With a fixed CKREF input; STROBE can be 1/2 the speed 10MHz to 30MHz ≤ CKREF / 2 (Up to 15MHz) 2 0 1 1 1 With a fixed CKREF input; STROBE can be 1/3 the speed 10MHz to 30MHz ≤ CKREF / 3 (Up to 10MHz) 3 1 1 1 1 Normal operation 18MHz to 48MHz ≤ CKREF (Up to 48MHz) 1 1 0 1 0 Supports spread spectrum on CKREF Fast Frequencies Supports spread spectrum on CKREF 18MHz to 45.4MHz ≤ CKREF (Up to 45.4MHz) 0.947 0 0 1 0 With a fixed CKREF input; STROBE can be 1/2 the speed 18MHz to 48MHz ≤ CKREF / 2 (Up to 24MHz) 2 0 1 1 0 With a fixed CKREF input; STROBE can be 1/3 the speed 18MHz to 48MHz ≤ CKREF / 3 (Up to 16MHz) 3 1 1 1 0 X X 0 0 Power-Down Table 2. Deserializer (DIRI=0) PWS Control Pins (Pulse Width Examples) CKP to STROBE CKP Pulse Width Low Time CKREF=19.2 MHz CKREF=26 MHz CKREF=48 MHz Reference PLL Pwidth Multiplier Multiplier (Serializer) Control Pin PWS0 PWS1 Serializer PLL Multiplier = 3 Non-Inverted 78.1ns 57.7ns 31.2ns 3 6 0 0 Inverted 78.1ns 57.7ns 31.2ns 3 6 1 0 Non-Inverted 156.3ns 115.4ns 62.5ns 3 12 0 1 Non-Inverted 208.3ns 153.8ns 83.3ns 3 16 1 1 Serializer PLL Multiplier = 2 Non-Inverted 52.1ns 38.5ns 20.8ns 2 6 0 0 Inverted 52.1ns 38.5ns 20.8ns 2 6 1 0 Non-Inverted 104.2ns 76.9ns 41.7ns 2 12 0 1 Non-Inverted 138.9ns 102.6ns 55.6ns 2 16 1 1 Serializer PLL Multiplier = 1 Non-Inverted 26ns 19.2ns 10.4ns 1 6 0 0 Inverted 26ns 19.2ns 10.4ns 1 6 1 0 Non-Inverted 52.1ns 38.5ns 20.8ns 1 12 0 1 69.4ns 51.3ns 27.8ns 1 16 1 1 X X 0 0 Non-Inverted Power-Down © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 www.fairchildsemi.com 4 µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz System Control Pin Deserializer S0 & S1 Control Pins (Note: All edge rates are typical values) LVCMOS Output Edge Rates S0 S1 Slow Edge Rates ~7 - 8ns (CL = 8pF) 0 1 Medium Edge Rates ~4 - 5ns (CL = 8pF) 1 1 1 0 0 0 Fast Edge Rates ~2 - 3ns (CL = 8pF) Power Down Pulse Width Calculations CKP Pulse Width Low Time=(PLL Multiplier • Pwidth Multiplier) / (CKREF•12) (1) Example: CKREF=26MHz; PLL Multiplier=1; Pwidth Multiplier=6 CKP Pulse width=(1 • 6) / (26MHz • 12)=19.2ns (2) CKREF = Strobe 50% Duty Cycle If CKREF = Strobe the below control states will provide a ~ 50% duty cycle pulse width output on CKP Table 4. CKREF = Strobe 50% Duty Cycle Serializer Deserializer PLL0 PLL1 PWS0 PWS1 1 0 0 0 Power-Down States When both S1 and S0 signals are 0, regardless of the state of the DIRI signal, the FIN210AC resets and powers down. The power-down mode shuts down all internal analog circuitry, disables the serial input and output of the device, and resets all internal digital logic. Table 5 indicates the state of the input states and output buffers in Power-Down mode. Table 5. Power-Down Signal Pins DIRI=1 (Serializer) DIRI=0 (Deserializer) /ENZ = 0 DIRI=0 (Deserializer) /ENZ = 1 DP[1:10] Inputs Disabled Outputs High-Z Outputs Low CKP HIGH High-Z High STROBE Input Disabled Input Disabled Input Disabled CKREF Input Disabled Input Disabled Input Disabled /DIRO 0 1 1 © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 www.fairchildsemi.com 5 µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz Table 3. Clock pass-through mode allows a harmonic rich clock source to be sent to the serializer in a CTL format to reduce the overall harmonic content of the phone, and can reduce the need for EMI filters. The Master Clock Pass through mode performs a translation to the clock in the CTL link, and does not serialize this signal. The following describes how to enable this functionality for an image sensor (See Figure 6). Deserializer Configuration (DIRI=0) 1. Connect CKREF(BGA pin A6) to GROUND 2. Connect master clock to STROBE (BGA pin B5) Serializer Configuration (DIRI=1) 1. CKSI passes master clock to CKP output (BGA pin C1) CKREF and STROBE Signals Please note that there is a setup and hold time between STROBE and data that must be met as seen on the electrical characteristics section. The relationship between CKREF and STROBE can be synchronous or asynchronous depending on what is available in the system. It is suggested that if the signals are synchronous and in normal operation that CKREF is tied to STROBE as close to the chip as possible. If you are running an asynchronous or spread spectrum setup, please be aware this may result on cycle jitter on the CKP signal. They cycle jitter does not effect the output data and clock relationship, the display or end application should continue to work as normal. PLL Note Please note that the PLL ranges can overlap, power consumption can be reduced by selecting the operation in the lower end of the higher speed PLL range. © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 www.fairchildsemi.com 6 µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz Clock Pass-Through Mode The following application diagrams illustrate the most typical applications for the FIN210 device. Specific configurations of the control pins may vary based on the needs of a given system. The following recommendations are valid for all of the applications shown. FIN210AC Serializer VDDP1 Baseband Processor D3 PIXEL CLK NC Data[7:0] HSYNC VSYNC A6 B5 C1 VDDP1 E4 F4 CKSO+ C5 C6 E5 E6 D6 D5 D6 CKSO- DSO+ D5 DSO- DP[8:1] DP[9] DP[10] F4 D3 VDDS/A VDDS/A CKREF STROBE CKP B3:E1 E2 F1 VDD E4 VDDP FIN210AC Deserializer VDDP2 LCD MODULE VDDP CKP C1 CKREF A6 B5 STROBE CKSI+ CKSI- PIXEL CLK B3:E1 Data[7:0] HSYNC VSYNC DP[8:1] E2 DP[9] F1 DP[10] A4 /ENZ DSI+ DSI- E6 F6 G3 G4 A4 G5 G6 A3 NC NCC6 CKSOCKSIXTRM F6 E5 NC NCC5 CKSO+ DIRI CKSI+ DIRI G3 PLL1 PWS1 G4 B6 B6 NC NC /DIRO PLL0 /DIRO PWS0 CTL_ADJ G5 S1 S1 G6 S0 S0 GND GND /RES /RES Figure 4. 8-Bit RGB Application (Example Shows BGA 42-Pin Package) Serializer Configuration: Deserializer Configuration: 10MHz to 30MHz Frequency Range (S1=S0=1) ~4 – 5ns output edge rates (S1=S0=1) Normal Mode (PLL1=0; PLL0=1) ~50% CKP PW,(PWS1=PWS0=0) FIN210AC Dese rializer VDDP1 Baseban d Processor D3 VDDP A6 MASTER CLK PIXEL CLK YUV[7:0] HSYNC VSYNC E4 B5 C1 B3:E1 E2 F1 A4 F6 G3 G4 A3 G5 G6 CKREF STROBE CKP E4 VDDS/A DSI+ DSICKSICKSI+ /ENZ DIRI PWS1 PWS0 XTRM S1 S0 VDD F4 CKSO+ CKSO- DP[8:1] DP[9] DP[10] FIN210AC Serializer /DIRO F4 VDDS/A C5 E5 C6 E6 D5 D6 D6 D5 E6 DP[8:1] DP[9] DP[10] DSO+ DSO- E5 CKSOC5 CKSO+ B6 B6 NC NC /DIRO GND D3 VDDP CKP CKREF STROBE CKSI+ CKSI- C6 VDDP2 DIRI PLL1 PLL0 CTL_ADJ S1 S0 GND Camera Module C1 MASTER CLK A6 B5 PIXEL CLK B3:E1 YUV[7:0] HSYNC VSYNC /RES E2 F1 F6 VDDP2 G3 G4 A4 G5 G6 /RES Figure 5. 8-Bit YUV 1.3MPixel CMOS Imager (Example Shows BGA 42-Pin Package) Deserializer Configuration: Serializer Configuration: ~2 – 3ns output edge rates (S1=0, S0=1) 18MHz to 48MHz Frequency Range (S1=0, S0=1) ~50% CKP PW,(PWS1=PWS0=0) Normal Mode (PLL1=0, PLL0=1) © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 www.fairchildsemi.com 7 µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz Application Diagrams FIN210AC Dese rializer VDDP1 Baseban d Processor D3 A6 MASTER CLK PIXEL CLK YUV[7:0] HSYNC VSYNC CKREF STROBE CKP B5 C1 B3:E1 F1 A4 /ENZ F6 DIRI PWS1 PWS0 XTRM S1 S0 G3 G4 A3 G5 G6 F4 E4 VDDS/A CKSO+ CKSODSI+ DSI- DP[8:1] DP[9] DP[10] E2 VDD E4 VDDP FIN210AC Serializer CKSICKSI+ /DIRO F4 VDDS/A C5 E5 C6 E6 D5 D6 D6 D5 E6 D3 VDDP CKSI+ CKSI- DP[8:1] DP[9] DP[10] DSO+ DSO- E5 CKSOC5 CKSO+ B6 B6 NC /DIRO GND Camera Module CKP CKREF STROBE C6 NC VDDP2 DIRI PLL1 PLL0 CTL_ADJ S1 S0 GND C1 MASTER CLK A6 B5 PIXEL CLK B3:E1 YUV[7:0] HSYNC VSYNC /RES E2 F1 VDDP2 F6 G3 G4 A4 G5 G6 /RES Figure 6. 8-Bit YUV 1.3MPixel CMOS Imager In Clock Pass-Through Mode Serializer Configuration: Deserializer Configuration: 18MHz to 48MHz Frequency Range (S1=0, S0=1) ~2 – 3ns output edge rates (S1=0, S0=1) Normal Mode (PLL1=0; PLL0=1) ~50% CKP PW,(PWS1=PWS0=0) Master clock bypass mode. FIN210AC Serializer VDDP1 Baseband Processor D3 VDDP SYS CLK /WE NC Data[7:0] A0 /CS0 E4 A6 B5 C1 B3:E1 E2 F1 CKREF STROBE CKP DP[8:1] DP[9] DP[10] VDDP1 F6 G3 G4 A4 G5 G6 DIRI PLL1 PLL0 CTL_ADJ S1 S0 GND FIN210AC Deserializer VDDP2 VDD E4 F4 VDDS/A F4 D3 VDDS/A CKSO+ C5 C6 CKSO- E5 E6 D6 DSO+ D5 D5 D6 DSO- CKSI+ CKSI- CKP C1 CKREF A6 B5 STROBE B3:E1 DP[8:1] E2 DP[9] F1 DP[10] DSI+ DSI- E6 NC NCC6 CKSOCKSIE5 NC NCC5 CKSO+ CKSI+ /DIRO B6 B6 NC NC MAIN LCD VDDP /ENZ /WE DATA[7:0] A0 /CS /RES A4 A3 XTRM F6 DIRI G3 PWS1 G4 PWS0 /DIRO G5 GND S1 G6 S0 /RES Figure 7. 8-Bit WRITE-Only Microcontroller Interface (Example Shows BGA 42-Pin Package) Serializer Configuration: Deserializer Configuration: 18MHz to 48MHz Frequency Range (S1=0, S0=1) ~7 – 8ns output edge rates (S1=1, S0=0) CKREF is twice as fast STROBE (PLL1=1; PLL0=0) ~50% CKP PW,(PWS1=PWS0=0) CKREF=26MHz & STROBE Frequency=10 MHz © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 www.fairchildsemi.com 8 µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz Application Diagrams (Continued) Flex Cabling: The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex cable. The following best practices should be used when developing the flex cabling or Flex PCB. Keep all four differential Serial Wires the same length. Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom. Do not allow noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential serial wires. Design goal of 100Ω differential characteristic impedance. Do not place test points on differential serial wires. Use differential serial wires a minimum of 2cm away from the antenna. For additional applications notes or flex guidelines see your sales representative or contact Fairchild directly. For samples and questions, please contact: [email protected]. © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 www.fairchildsemi.com 9 µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz Additional Application Information Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD Parameter Min. Supply Voltage All Input/Output Voltage CTL Output Short-Circuit Duration TSTG Max. Unit -0.5V +4.6 V -0.5 VDD+0.5 V +150 °C Continuous Storage Temperature Range -65 TJ Maximum Junction Temperature +150 °C TL Lead Temperature (Soldering, four seconds) +260 °C Human Body Model JESD22-A114 ESD Serial I/O Pins to GND 12 All Pins 8 Charged Device Model, JESD22-C101 2 IEC61000-4-2 15 kV Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VDDA, VDDS VDDP TA VDDA-PP Min. Max. Unit Supply Voltage Parameter 2.8 3.6 V Supply Voltage 1.65 3.60 V Operating Temperature -30 +70 ºC Supply Noise Voltage 100 © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 mVPP www.fairchildsemi.com 10 µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz Absolute Maximum Ratings Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. (3) Max. Unit LVCMOS I/O VIH Input High Voltage VIL Input Low Voltage 0.65xVDDP VDDP GND 0.35xVDDP V 0.75xVDDP VDDP V 0 0.25xVDDP V -5.0 5.0 µA IOH=-2.0mA, S1=0,S0=1 VOH Output High Voltage IOH=-0.4mA, S1=1,S0=0 IOH=-1.0mA, S1=1,S0=1 IOL=2.0mA, S1=0,S0=1 VOL Output Low Voltage IOL=0.4mA, S1=1,S0=0 IOL=1.0mA, S1=1,S0=1 IIN Input Current VIN= 0V to 3.6V DIFFERENTIAL I/O IODH Output HIGH Source Current VOS=1.0V IODL Output LOW Sink Current VOS=1.0V VGO Input Voltage Ground Offset(4) RTRM CKS Internal Receiver Termination Resistor CTL_ADJ=0 -4.1 CTL_ADJ=1 -5.3 CTL_ADJ=0 2.1 CTL_ADJ=1 3.1 mA mA 0 DS Internal Receiver Termination Resistor VID=50mV, VIC=925mV DIRI=0 VID=50mV, VIC=925mV DIRI=0 V 80 100 120 Ω 80 100 120 Ω Notes: 3. Typical values are given for VDD=2.775V and TA=25°C. Positive current values refer to the current flowing into the device and negative values refer to the current flowing out of pins. Voltages are referenced to GROUND unless otherwise specified (except ΔVOD and VOD). 4. VGO is the difference in device ground levels between the CTL driver and the CTL receiver. Power Supply Currents Symbol IDD_PD Parameter Test Conditions VDD Power-Down Supply Current S1=S0=0, All Inputs at GND or VDD Min. S1=L S0=H IDD_SER1 IDD_DES1 Dynamic Serializer Power Supply Current Dynamic Deserializer Power Supply Current Typ. Max. Unit 0.1 µA 20MHz 13 mA 48MHz 21 mA fCKREF=fSTRB, PLL1=0,PLL0=1; S1=H CTL_ADJ=0; CL=0pF S0=L 5MHz 10 mA 14MHz 16 mA S1=H S0=H 8MHz 11 mA 28MHz 18 mA S1=L S0=H 20MHz 10 mA 48MHz 19 mA S1=H S0=L 5MHz 8 mA 14MHz 9 mA S1=H S0=H 8MHz 9 mA 28MHz 12 mA fCKREF=fSTRB, PLL1=0,PLL0=1; CTL_ADJ=0; CL=0pF © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 www.fairchildsemi.com 11 µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz DC Electrical Characteristics Symbol CIN, CIO, CIO-DIFF Parameter Test Conditions Capacitance of Input Only Signals; Parallel Port Pins DP[1:10]; Differential I/O DIRI=1, S1=0, S0=0, VDD=2.5V Min. Typ. Max. 2 Unit pF AC Electrical Characteristics Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. Max. Unit Serializer Input Operating Conditions fCKREF fSTRB CKREF Clock Frequency (5MHz - ≤ 48MHz); fCKREF=fSTRB Strobe Frequency Relative to CKREF Frequency fCKREF ≠ fSTRB S1=0, S0=1 18 48 S1=1, S0=0 5 15 S1=1, S0=1 10 MHz 30 PLL1=0, PLL0=0 94.7 PLL1=0, PLL0=1 100 PLL1=1, PLL0=0 50 PLL1=1, PLL0=1 331/3 % of fCKREF tCPWH CKREF DC T=1/fCKREF 0.2 0.5 0.8 T tCPWL CKREF DC T=1/fCKREF 0.2 0.5 0.8 T 20 ns T x 8/12 ns tCLKT tSPWH/L (5) LVCMOS Input Transition Time 10-90% STROBE Pulse Width HIGH/LOW T=1/fCKREF T x 4/12 Setu p Tim e tSTC DP(n) Setup to STROBE t S TC S TR OBE (DIRI=1, f=5MHz) D P [1:1 0] H old T im e tHTC DP(n) Hold to STROBE ns 2.0 ns t HT C S TR OBE (DIRI=1, f=5MHz) 2.5 Data D P [1: 10] Data Serializer AC Electrical Characteristics tTCCD STROBE tTCCD Transmitter Clock Input to Clock Output Delay(6) tRCCD VDD/2 CKS- V =0 DIFF CKS+ CKP 19a+1.5 21a+6.5 ns 200 600 μs VDD/2 Note: STROBE=CKREF DIRI=1, fCKREF=fSTRB Phase Lock Loop (PLL) AC Electrical Characteristics tTPLLS0 Serializer PLL Stabilization Time CKREF Toggling and Stable tTPLLD0 PLL Disable Time Loss of Clock 30.0 μs tTPLLD1 PLL Power-Down Time 20.0 ns Continued on the following page… © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 www.fairchildsemi.com 12 µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz Pin Capacitance Tables Values are provided for over-supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. Max. Unit Deserializer AC Electrical Characteristics Data Valid CKP tRCOL DP [1:10] Data tRCOP CKP 50% tPDV PWS1 PWS0 fSTRB=fCKREF 0 0 fSTRB=fCKREF 0 1 6a-3 6a+3 fSTRB=.5x fCKREF 1 0 12a-3 12a+3 fSTRB=.5x fCKREF 1 1 16a-3 16a+3 8a-3 8a+3 tPDV 75% tRCOH 50% 25% tRCOL Data Valid to CKP HIGH (Rising Edge STROBE), CL=5pF 6a-3 6a+3 ns ns Setup: DIRI= 0, CKSI and DS are valid signals. tRFD tRFC Output Rise/Fall Time Data (20% to 80%) Output Rise/Fall Time CKP (20% to 80%) CL=8pF CL=8pF S1=0,S0=1 3 S1=1,S0=0 8 S1=1,S0=1 5 S1=0,S0=1 2 S1=1,S0=0 7 S1=1,S0=1 4 ns ns Notes: 5. 6. Parameter is characterized, but not production tested. The average bit time “a” is a function of the serializer CKREF frequency; a=(1/f)/12. Logic Timing Controls Symbol t PHL_DIR, tPLH_DIR tPLZ, tPHZ Parameter Test Conditions Propagation Delay DIRI to /DIRO Propagation Delay DIRI to DP Min. Typ. Max. Unit DIRI L->H or H->L 17 ns DIRI L->H or H->L 25 ns 25 ns 25 ns Deserializer Disable Time: S0 or S1 LOW to DPTri-State; DIRI=0, t tDISDES DISDES S1 or S0 DP Note: If S0(2) is transitioning, S1(1) must =0 for test to be valid. tDISSER Serializer Disable Time: S0 or S1 LOW to CKP HIGH © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 DIRI=1; S1(0) and S0(1)=H->L www.fairchildsemi.com 13 µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz AC Electrical Characteristics (Continued) MLP Embossed Tape Dimensions D P0 T P2 E F K0 W Wc B0 Tc A0 P1 D1 User Direction of Feed Package A0 ±0.1 B0 ±0.1 D ±0.5 D1 Min. E ±0.1 F ±0.1 K0 ±0.1 P1 Typ. P0 Typ. P2 ±0.5 T Typ. TC ±0/05 W ±0.3 WC Typ. 5x5 5.35 5.35 1.55 1.50 1.75 5.50 1.40 8.00 4.00 2.00 0.30 0.07 12.00 9.30 6x6 5.35 5.35 1.55 1.50 1.75 5.50 1.40 8.00 4.00 2.00 0.30 0.07 12.00 9.30 Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement requirements (see sketches A, B, and C). MLP Shipping Reel Dimensions 1.0mm maximum 10° maximum B0 10° maximum component rotation Sketch A (Side or Front Sectional View) Typical component cavity center line Typical component center line 1.0mm maximum Sketch C (Top View) A0 Sketch B (Top View) Component Rotation Component Lateral Movement Component Rotation W2 max Measured at Hub W1 Measured at Hub B Min Dia C Dia A max Dia D min Dia N DETAIL AA See detail AA W3 Tape Width Dia A Max. Dim B Min. Dia C +0.5/-0.2 Dia D Min. Dim N Min. Dim W1 +2.0/-0 Dim W2 Dim W3 (LSL-USL) 8 330.0 1.5 13.0 20.2 178.0. 8.4 14.4 7.9 ~ 10.4 12 330.0 1.5 13.0 20.2 178.0. 12.4 18.4 11.9 ~ 15.4 16 330.0 1.5 13.0 20.2 178.0. 16.4 22.4 15.9 ~ 19.4 Figure 8. MLP Tape and Reel © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 www.fairchildsemi.com 14 µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz Tape and Reel Specifications 0.15 C 5.00 B A 5.00 (0.76) (0.25 ) PIN #1 IDENT 5.38 MIN 0.15 C 3.37 MAX 3.86 MIN 0.80 MAX 0.10 C 0.20MIN X4 (0.20) 0.08 C 0.05 0.00 0.28 MAX C X40 SEATING PLANE 0.50TYP E 3.70 3.50 0.45 0.35 PIN #1 IDENT PIN #1 ID 0.50 3.70 3.50 (DATUM B) PIN #1 ID (DATUM A) 0.18-0.30 0.10 0.05 0.50 C A B C NOTES: A. CONFORMS TO JEDEC REGISTRATION MO-220, VARIATION WHHD-4. THIS PACKAGE IS ALSO FOOTPRINT COMPATIBLE WITH WHHD-5. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994. D. LAND PATTERN PER IPC SM-782. E. WIDTH REDUCED TO AVOID SOLDER BRIDGING. F. DIMENSIONS ARE NOT INCLUSIVE OF BURRS, MOLD FLASH, OR TIE BAR PROTRUSIONS. G. DRAWING FILENAME: MKT-MLP32Arev3. Figure 9. 32-Lead, Molded Leadless Package (MLP) Order Number Operating Temperature Range Package Description Eco Status Packing Method FIN210ACMLX -30 to 70°C 32-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 5mm Square Green Tape & Reel For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 www.fairchildsemi.com 15 µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz Physical Dimensions Figure 10. 42-Ball, Ball Grid Array (BGA) Package Note: Click here for tape and reel specifications, available at: http://www.fairchildsemi.com/products/analog/pdf/bga42_tr.pdf Order Number Operating Temperature Range Package Description Eco Status Packing Method FIN210ACGFX -30 to 70°C 42-Ball Ultra Small-Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5 x 4.5mm Wide, 0.5mm Ball Pitch RoHS Tape & Reel For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 www.fairchildsemi.com 16 µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz Physical Dimensions (Continued) µSerDes™ FIN210AC — 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz www.fairchildsemi.com © 2009 Fairchild Semiconductor Corporation FIN210AC • Rev. 1.0.1 17