A25L40P Series 4 Mbit, Low Voltage, Serial Flash Memory Preliminary With 85MHz SPI Bus Interface Document Title 4 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface Revision History History Issue Date 0.0 Initial issue August 29, 2006 0.1 Add the Fast Read Dual Operation Instruction April 4, 2006 Rev. No. Remark Preliminary Add QFN 8L (5 x 6mm) package type 0.2 Add QFN 8L (5 x 6mm) package outline dimensions April 20, 2006 0.3 Modify the Part No. for Top/Bottom boot sector type September 5, 2006 Add DIP 8(300mil) package type Modify the maximum clock rate to 75MHz 0.4 Add transient voltage (<20ns) on any pin to ground potential spec. May 25, 2007 Add the maximum clock rate of 3.0V~3.6V : 85MHz PRELIMINARY (May, 2007, Version 0.4) AMIC Technology Corp. A25L40P Series 4 Mbit, Low Voltage, Serial Flash Memory Preliminary With 85MHz SPI Bus Interface FEATURES GENERAL DESCRIPTION 4 Mbit of Flash Memory Flexible Sector Architecture (4/4/8/16/32)KB/64x7 KB Bulk Erase (4 Mbit) in 6s (typical) Sector Erase (512 Kbit) in 1s (typical) Page Program (up to 256 Bytes) in 3ms (typical) 2.7 to 3.6V Single Supply Voltage SPI Bus Compatible Serial Interface 85MHz Clock Rate (maximum) Deep Power-down Mode 1µA (typical) Top or Bottom boot block configuration available Electronic Signatures - JEDEC Standard two-Byte Signature (2013h) - RES Instruction, One-Byte, Signature (12h), for backward compatibility Package options - 8-pin SOP (150mil or 209mil), 16-pin SOP, 8-pin DIP (300mil) or 8-pin QFN - All Pb-free (Lead-free) products are RoHS compliant The A25L40P is a 4 Mbit (512K x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction. Pin Configurations SO8 Connections SO16 Connections A25L40P HOLD VCC DU DU DU DU S Q A25L40P S Q W VSS 1 2 3 4 8 VCC 7 HOLD 6 C 5 D 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C D DU DU DU DU VSS W Note: DU = Do not Use DIP8 Connections QFN8 Connections A25L40P S Q W VSS PRELIMINARY 1 2 3 4 A25L40P 8 VCC 7 HOLD 6 C 5 D (May, 2007, Version 0.4) S Q W VSS 1 1 2 3 4 8 7 6 5 VCC HOLD C D AMIC Technology Corp. A25L40P Series Block Diagram HOLD W High Voltage Generator Control Logic S C D I/O Shift Register Q Address register and Counter 256 Byte Data Buffer Status Register 7FFFFh Y Decoder Size of the read-only memory area 000FFh 00000h 256 Byte (Page Size) X Decoder Logic Symbol Pin Descriptions Pin No. Description C Serial Clock D Serial Data Input Q Serial Data Output S Chip Select W Write Protect HOLD Hold VCC Supply Voltage VSS Ground PRELIMINARY (May, 2007, Version 0.4) VCC D Q C S A25L40P W HOLD VSS 2 AMIC Technology Corp. A25L40P Series SIGNAL DESCRIPTION ( S ) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select ( S ) is required prior to the start of any instruction. Hold ( HOLD ). The Hold ( HOLD ) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select ( S ) driven Low. Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select ( S ). When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select Write Protect ( W ). The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register). SPI MODES falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 2, is the clock polarity when the bus master is in Stand-by mode and not transferring data: – C remains at 0 for (CPOL=0, CPHA=0) – C remains at 1 for (CPOL=1, CPHA=1) These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the PRELIMINARY (May, 2007, Version 0.4) 3 AMIC Technology Corp. A25L40P Series Figure 1. Bus Master and Memory Devices on the SPI Bus SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDO SDI SCK C Q D C Q D C Q D Bus Master (ST6, ST7, ST9, ST10, Other) CS3 CS2 SPI Memory Device SPI Memory Device SPI Memory Device S S S CS1 W HOLD W HOLD W HOLD Note: The Write Protect ( W ) and Hold ( HOLD ) signals should be driven, High or Low as appropriate. Figure 2. SPI Modes Supported CPOL CPHA 0 0 C 1 1 C D MSB Q PRELIMINARY (May, 2007, Version 0.4) MSB 4 AMIC Technology Corp. A25L40P Series OPERATING FEATURES Page Programming Status Register To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch, BP2, BP1, and BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. SRWD bit. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect ( W ) signal. The Status Register Write Disable (SRWD) bit and Write Protect ( W ) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits. Sector Erase and Bulk Erase The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved, a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction. Protection Modes Polling During a Write, Program or Erase Cycle The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the A25L40P boasts the following data protection mechanisms: Power-On Reset and an internal timer (tPUW) can provide protection against inadvertant changes while the power supply is outside the operating specification. Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Bulk Erase (BE) instruction completion The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect ( W ) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected Mode (HPM). In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertant Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Power-down instruction). A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete. Active Power, Stand-by Power and Deep Power-Down Modes When Chip Select ( S ) is Low, the device is enabled, and in the Active Power mode. When Chip Select ( S ) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Stand-by Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down Mode and Read Electronic Signature (RES) instruction) is executed. All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions. PRELIMINARY (May, 2007, Version 0.4) 5 AMIC Technology Corp. A25L40P Series Table 1. Protected Area Sizes A25L40PT Top Boot Block Status Register Content BP2 Bit BP1 Bit Memory Content BP0 Bit Protected Area Unprotected Area 1 0 0 0 none All sectors (eight sectors: 0 to 7) 1 1 1 All sectors (eight sectors: 0 to 7) none Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0. 2. The sector 7 include sector 7-0, sector 7-1, sector 7-2, sector 7-3 and sector 7-4. A25L40PU Bottom Boot Block Status Register Content Memory Content BP2 Bit BP1 Bit BP0 Bit 0 0 0 none Protected Area All sectors1 (eight sectors: 0 to 7) Unprotected Area 1 1 1 All sectors (eight sectors: 0 to 7) none Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0. 2. The sector 0 include sector 0-0, sector 0-1, sector 0-2, sector 0-3, and sector 0-4. PRELIMINARY (May, 2007, Version 0.4) 6 AMIC Technology Corp. A25L40P Series Hold Condition Serial Clock (C) next goes Low. This is shown in Figure 3. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. Normally, the device is kept selected, with Chip Select ( S ) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If Chip Select ( S ) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold ( HOLD ) High, and then to drive The Hold ( HOLD ) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select ( S ) Low. The Hold condition starts on the falling edge of the Hold ( HOLD ) signal, provided that this coincides with Serial Clock (C) being Low (as shown in Figure 3.). The Hold condition ends on the rising edge of the Hold ( HOLD ) signal, provided that this coincides with Serial Clock (C) being Low. If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C) being Low, the Hold condition ends after Chip Select ( S ) Low. This prevents the device from going back to the Hold condition. Figure 3. Hold Condition Activation C HOLD Hold Condition (standard use) PRELIMINARY (May, 2007, Version 0.4) 7 Hold Condition (non-standard use) AMIC Technology Corp. A25L40P Series MEMORY ORGANIZATION The memory is organized as: 524,288 bytes (8 bits each) 8 sectors (one (4/4/8/16/32) Kbytes & 64x7 Kbytes 2048 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable. Table 2. Memory Organization A25L40PT Top Boot Block Address Table Sector Sector Size (Kbytes) Address Range 7-4 4 7F000h 7FFFFh 7-3 4 7E000h 7EFFFh 7-2 8 7C000h 7DFFFh 7-1 16 78000h 7BFFFh 7-0 32 70000h 77FFFh 6 64 60000h 6FFFFh 5 64 50000h 5FFFFh 4 64 40000h 4FFFFh 3 64 30000h 3FFFFh 2 64 20000h 2FFFFh 1 64 10000h 1FFFFh 0 64 00000h 0FFFFh A25L40PU Bottom Boot Block Address Table Sector Sector Size (Kbytes) 7 64 70000h 7FFFFh 6 64 60000h 6FFFFh 5 64 50000h 5FFFFh 4 64 40000h 4FFFFh 3 64 30000h 3FFFFh 2 64 20000h 2FFFFh 1 64 10000h 1FFFFh 0-4 32 08000h 0FFFFh 0-3 16 04000h 07FFFh 0-2 8 02000h 03FFFh 0-1 4 01000h 01FFFh 0-0 4 00000h 00FFFh PRELIMINARY (May, 2007, Version 0.4) Address Range 8 AMIC Technology Corp. A25L40P Series INSTRUCTIONS sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select ( S ) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select ( S ) must driven High when the All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select ( S ) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 3. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Status Register (RDSR) or Release from Deep Power-down, Read Device Identification and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select ( S ) can be driven High after any bit of the data-out number of clock pulses after Chip Select ( S ) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. Table 3. Instruction Set Instruction One-byte Instruction Code Description Address Bytes Dummy Bytes Data Bytes WREN Write Enable 0000 0110 06h 0 0 0 WRDI Write Disable 0000 0100 04h 0 0 0 RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞ WRSR Write Status Register 0000 0001 01h 0 0 1 READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞ FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞ PP Page Program 0000 0010 02h 3 0 1 to 256 SE Sector Erase 1101 1000 D8h 3 0 0 BE Bulk Erase 1100 0111 C7h 0 0 0 DP Deep Power-down 1011 1001 B9h 0 0 0 RDID Read Device Identification 1001 1111 9Fh 0 0 1 to 4 RES Release from Deep Power-down, and Read Electronic Signature 1010 1011 ABh 0 3 1 to ∞ 0 0 0 Release from Deep Power-down PRELIMINARY (May, 2007, Version 0.4) 9 AMIC Technology Corp. A25L40P Series Write Enable (WREN) The Write Enable (WREN) instruction (Figure 4.) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select ( S ) Low, sending the instruction code, and then driving Chip Select ( S ) High. Figure 4. Write Enable (WREN) Instruction Sequence S 0 1 2 3 4 5 6 7 C Instruction D Q High Impedance Write Disable (WRDI) ﹣ Power-up The Write Disable (WRDI) instruction (Figure 5.) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip ﹣ ﹣ ﹣ ﹣ ﹣ Select ( S ) Low, sending the instruction code, and then driving Chip The Write Enable Latch (WEL) bit is reset under the following conditions: Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion Figure 5. Write Disable (WRDI) Instruction Sequence S 0 1 2 3 4 5 6 7 C Instruction D Q PRELIMINARY (May, 2007, Version 0.4) High Impedance 10 AMIC Technology Corp. A25L40P Series Read Status Register (RDSR) WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 6. BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 1.) becomes protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, both Block Protect (BP2, BP1, BP0) bits are 0. Table 4. Status Register Format b7 SRWD 0 0 BP2 BP1 BP0 WEL b0 WIP Status Register Write Protect Block Protect Bits SRWD bit. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect ( W ) signal. The Status Register Write Disable (SRWD) bit and Write Protect ( W ) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect ( W ) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Write Enable Latch Bit Write In Progress Bit The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. Figure 6. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Instruction D Status Register Out Status Register Out Q PRELIMINARY High Impedance (May, 2007, Version 0.4) 7 6 5 MSB 4 3 2 1 11 0 7 6 MSB 5 4 3 2 1 0 7 AMIC Technology Corp. A25L40P Series Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 1. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect ( W ) signal. The Status Register Write Disable (SRWD) bit and Write Protect ( W ) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered. driving Chip Select ( S ) Low, followed by the instruction code and the data byte on Serial Data Input (D). The instruction sequence is shown in Figure 7. The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the Status Register. b6 and b5 are always read as 0. Chip Select ( S ) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select ( S ) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Figure 7. Write Status Register (WRSR) Instruction Sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 C Status Register In Instruction 7 D Q PRELIMINARY High Impedance (May, 2007, Version 0.4) 6 5 4 3 2 1 0 MSB 12 AMIC Technology Corp. A25L40P Series Table 5. Protection Modes Signal SRWD Bit 1 0 W 0 0 1 1 0 1 Mode Memory Content Write Protection of the Status Register Protected Area1 Unprotected Area1 Software Protected (SPM) Status Register is Writable (if the WREN instruction has set the WEL bit) The values in the SRWD, BP2, BP1 and BP0 bits can be changed Protected against Page Program, Sector Erase and Bulk Erase Ready to accept Page Program and Sector Erase instructions Hardware Protected (HPM) Status Register is Hardware write protected The values in the SRWD, BP2, BP1 and BP0 bits cannot be changed Protected against Page Program, Sector Erase and Bulk Erase Ready to accept Page Program and Sector Erase instructions Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1. Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: The protection features of the device are summarized in Table 5. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect ( W ) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect ( W ): If Write Protect ( W ) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect ( W ) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status PRELIMINARY (May, 2007, Version 0.4) by setting the Status Register Write Disable (SRWD) bit after driving Write Protect ( W ) Low or by driving Write Protect ( W ) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect ( W ) High. If Write Protect ( W ) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used. 13 AMIC Technology Corp. A25L40P Series Read Data Bytes (READ) The device is first selected by driving Chip Select ( S ) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 8. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select ( S ) High. Chip Select ( S ) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 8. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction 24-Bit Address 23 22 21 D 3 2 1 0 MSB Q Data Out 2 Data Out 1 High Impedance 7 6 5 4 3 2 1 0 7 MSB Note: Address bits A23 to A19 are Don’t Care. PRELIMINARY (May, 2007, Version 0.4) 14 AMIC Technology Corp. A25L40P Series Read Data Bytes at Higher Speed (FAST_READ) Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select ( S ) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 9. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher instruction is terminated by driving Chip Select ( S ) High. Chip Select ( S ) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 9. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 C Instruction 24-Bit Address 23 22 21 D 2 3 1 0 MSB High Impedance Q S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy Byte D 7 6 5 4 3 2 1 0 Data Out 2 Data Out 1 Q 7 6 5 4 3 MSB 2 1 0 7 6 MSB 5 4 3 2 1 0 7 MSB Note: Address bits A23 to A19 are Don’t Care. PRELIMINARY (May, 2007, Version 0.4) 15 AMIC Technology Corp. A25L40P Series Page Program (PP) The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. Chip Select ( S ) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. The Page Program (PP) instruction is entered by driving Chip Select ( S ) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits As soon as Chip Select ( S ) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. (A7-A0) are all zero). Chip Select ( S ) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 12. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 2 and Table 1) is not executed. Figure 12. Page Program (PP) Instruction Sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 C Instruction Data Byte 1 24-Bit Address 23 22 21 3 2 1 MSB 0 5 7 6 4 3 0 1 2 2078 2079 2077 2076 2075 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2074 S 2073 MSB 2072 D 1 0 C Data Byte 2 D 7 6 5 4 3 2 MSB Data Byte 3 1 0 7 6 5 4 3 MSB 2 Data Byte 256 1 0 7 6 5 4 3 2 MSB Note: Address bits A23 to A19 are Don’t Care. PRELIMINARY (May, 2007, Version 0.4) 16 AMIC Technology Corp. A25L40P Series Sector Erase (SE) The Sector Erase (SE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip instruction is not executed. As soon as Chip Select ( S ) is driven High, the self-timed Sector Erase cycle (whose duration is tBE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Sector Erase (SE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Sector Erase (SE) instruction is ignored if one, or more, sectors are protected. Select ( S ) Low, followed by the instruction code on Serial Data Input (D). Chip Select ( S ) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 13. Chip Select ( S ) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Sector Erase Figure 13. Sector Erase (SE) Instruction Sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 C Instruction 24-Bit Address 23 22 21 D 3 2 1 0 MSB Notes: Address bits A23 to A19 are Don’t Care. PRELIMINARY (May, 2007, Version 0.4) 17 AMIC Technology Corp. A25L40P Series Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip is not executed. As soon as Chip Select ( S ) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected. Select ( S ) Low, followed by the instruction code on Serial Data Input (D). Chip Select ( S ) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 14. Chip Select ( S ) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction Figure 14. Bulk Erase (BE) Instruction Sequence S 0 1 2 3 4 5 6 7 C Instruction D Notes: Address bits A23 to A19 are Don’t Care. PRELIMINARY (May, 2007, Version 0.4) 18 AMIC Technology Corp. A25L40P Series Deep Power-down (DP) Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions. The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select ( S ) Low, followed by the instruction code on Serial Data Input (D). Chip Select ( S ) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 15. Driving Chip Select ( S ) High deselects the device, and puts the device in the Standby mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce the standby current (from ICC1 to ICC2, as specified in DC Characteristics Table.). Chip Select ( S ) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select ( S ) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-down mode is entered. Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature (RES) instruction. This releases the device from this mode. The Release from Deep Power-down and Read Electronic Signature (RES) instruction also allows the Electronic Signature of the device to be output on Serial Data Output (Q). Figure 15. Deep Power-down (DP) Instruction Sequence S 0 1 2 3 4 5 6 tDP 7 C Instruction D Stand-by Mode PRELIMINARY (May, 2007, Version 0.4) 19 Deep Power-down Mode AMIC Technology Corp. A25L40P Series Read Device Identification (RDID) The Read Identification (RDID) instruction allows the 8-bit manufacturer identification code to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 37h, plus the continuation identification for AMIC Technology. The device identification is assigned by the device manufacturer, and indicates the memory in the first bytes (20h), and the memory capacity of the device in the second byte (13h). The Device Identification of memory capacity is 13h. Any Read Identification (RDID) instruction while an Erase, or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 32-bit device identification, stored in the memory, being shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 16. The Read Identification (RDID) instruction is terminated by driving Chip Select ( S ) High at any time during data output. When Chip Select ( S ) is driven High, the device is put in the Stand-by Power mode. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The device is first selected by driving Chip Select ( S ) Low. Table 6. Read Identification (READ_ID) Data-Out Sequence Manufacture Identification Device Identification Continuation ID Manufacture ID Memory Type Memory Capacity 7Fh 37h 20h 13h Figure 16. Read Identification (RDID) Data-Out Sequence S 0 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 21 22 23 24 25 26 29 30 31 32 33 34 37 38 39 C Instruction D Q 31 High Impedance PRELIMINARY 30 29 26 25 24 23 Continuation ID (May, 2007, Version 0.4) 22 21 18 17 16 15 14 13 Manufacture ID 20 10 9 Memory Type 8 7 6 5 2 1 0 Memory Capacity AMIC Technology Corp. A25L40P Series Release from Deep Power-down Electronic Signature (RES) and edge of Serial Clock (C). Then, the 8-bit Electronic Signature, stored in the memory, is shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 17. The Release from Deep Power-down and Read Electronic Signature (RES) instruction is terminated by driving Chip Read Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature (RES) instruction. Executing this instruction takes the device out of the Deep Power-down mode. Select ( S ) High after the Electronic Signature has been read at least once. Sending additional clock cycles on Serial Clock The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic Signature, whose value for the A25L40P is 12h. (C), while Chip Select ( S ) is driven Low, cause the Electronic Signature to be output repeatedly. Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep Power-down and Read Electronic Signature (RES) instruction always provides access to the 8-bit Electronic Signature of the device, and can be applied even if the Deep Power-down mode has not been entered. When Chip Select ( S ) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Stand- Any Release from Deep Power-down and Read Electronic Signature (RES) instruction while an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. by Power mode is delayed by tRES2, and Chip Select ( S ) must remain High for at least tRES2 (max), as specified in AC Characteristics Table . Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The device is first selected by driving Chip Select ( S ) Low. The instruction code is followed by 3 dummy bytes, each bit being latched-in on Serial Data Input (D) during the rising Figure 17. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and Data-Out Sequence S 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 C Instruction 23 22 21 D tRES2 3 Dummy Bytes 3 2 1 0 MSB Q High Impedance 7 6 5 4 3 2 1 0 MSB Deep Power-down Mode Stand-by Mode Note: The value of the 8-bit Electronic Signature, for the A25L40P, is 12h. PRELIMINARY (May, 2007, Version 0.4) 21 AMIC Technology Corp. A25L40P Series Figure 18. Release from Deep Power-down (RES) Instruction Sequence S C D Q 0 1 2 3 4 5 6 tRES1 7 Instruction High Impedance Deep Power-down Mode Driving Chip Select ( S ) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic Signature has been transmitted for the first time (as shown in Figure 18.), still insures that the device is put into Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was PRELIMINARY (May, 2007, Version 0.4) Stand-by Mode previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES1, and Chip Select ( S ) must remain High for at least tRES1 (max), as specified in AC Characteristics Table. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. 22 AMIC Technology Corp. A25L40P Series POWER-UP AND POWER-DOWN tPUW after VCC passed the VWI threshold - tVSL afterVCC passed the VCC(min) level These values are specified in Table 7. If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for READ instructions even if the tPUW delay is not yet fully elapsed. At Power-up, the device is in the following state: At Power-up and Power-down, the device must not be selected (that is Chip Select ( S ) must follow the voltage applied on VCC) until VCC reaches the correct value: VCC (min) at Power-up, and then for a further delay of tVSL VSS at Power-down Usually a simple pull-up resistor on Chip Select ( S ) can be used to insure safe and proper Power-up and Power-down. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the POR threshold value, VWI – all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should be sent until the later of: The device is in the Standby mode (not the Deep Power-down mode). The Write Enable Latch (WEL) bit is reset. Normal precautions must be taken for supply rail decoupling, to stabilize the VCC feed. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 0.1µF). At Power-down, when VCC drops from the operating voltage, to below the POR threshold value, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.) Figure 19. Power-up Timing VCC VCC(max) VCC(min) tPU Full Device Access time PRELIMINARY (May, 2007, Version 0.4) 23 AMIC Technology Corp. A25L40P Series Table 7. Power-Up Timing Symbol VCC(min) tPU Parameter Min. Max. Unit VCC (minimum) 2.7 V VCC (min) to device operation 10 ms Note: These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). PRELIMINARY (May, 2007, Version 0.4) 24 AMIC Technology Corp. A25L40P Series Absolute Maximum Ratings* *Comments Storage Temperature (TSTG) . . . . . . . . . . -65°C to + 150°C Lead Temperature during Soldering (Note 1) D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to VCC+0.6V Transient Voltage (<20ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VCC+2.0V Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . -0.6V to +4.0V Electrostatic Discharge Voltage (Human Body model) (VESD) (Note 2) . . . . . . . . . . . . . . . . . . . -2000V to 2000V Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the AMIC SURE Program and other relevant quality documents. Notes: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly). 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω , R2=500Ω) DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 7. Operating Conditions Symbol Parameter Min. Max. Unit VCC Supply Voltage 2.7 3.6 V TA Ambient Operating Temperature –40 85 °C Table 8. Data Retention and Endurance Parameter Condition Min. Max. Unit Erase/Program Cycles At 85°C 100,000 Cycles per sector Data Retention At 85°C 20 Years Note: 1. This is preliminary data Table 9. Capacitance Symbol Parameter COUT Output Capacitance (Q) CIN Input Capacitance (other pins) Test Condition Min. Max. Unit VOUT = 0V 8 pF VIN = 0V 6 pF Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 33 MHz. PRELIMINARY (May, 2007, Version 0.4) 25 AMIC Technology Corp. A25L40P Series Table 10. DC Characteristics Symbol Parameter Test Condition Min. Max. Unit ILI Input Leakage Current ±2 µA ILO Output Leakage Current ±2 µA ICC1 Standby Current 50 µA ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC S = VCC, VIN = VSS or VCC 10 µA ICC3 Operating Current (READ) C= 0.1VCC / 0.9.VCC at 50MHz, Q = open 20 mA C= 0.1VCC / 0.9.VCC at 33MHz, Q = open 15 mA ICC4 Operating Current (PP) 15 mA ICC5 Operating Current (WRSR) S = VCC S = VCC 15 mA ICC6 Operating Current (SE) 15 mA ICC7 Operating Current (BE) S = VCC S = VCC 15 mA VIL Input Low Voltage –0.5 0.3VCC V VIH Input High Voltage 0.7VCC VCC+0.4 V VOL Output Low Voltage IOL = 1.6mA 0.4 V VOH Output High Voltage IOH = –100µA VCC–0.2 V Note: 1. This is preliminary data at 85°C Table 11. Instruction Times Symbol Alt. Parameter Min. Typ. Max. Unit tW Write Status Register Cycle Time 5 15 ms tPP Page Program Cycle Time 3 5 ms tSE Sector Erase Cycle Time 1 3 s tBE Bulk Erase Cycle Time 4.5 10 s Note: 1. At 85°C 2. This is preliminary data Table 12. AC Measurement Conditions Symbol CL Parameter Min. Load Capacitance Max. 30 Input Rise and Fall Times Unit pF 5 ns Input Pulse Voltages 0.2VCC to 0.8VCC V Input Timing Reference Voltages 0.3VCC to 0.7VCC V VCC / 2 V Output Timing Reference Voltages Note: Output Hi-Z is defined as the point where data out is no longer driven. PRELIMINARY (May, 2007, Version 0.4) 26 AMIC Technology Corp. A25L40P Series Figure 20. AC Measurement I/O Waveform Input Levels Input and Output Timing Reference Levels 0.8VCC 0.7VCC 0.5VCC 0.3VCC 0.2VCC PRELIMINARY (May, 2007, Version 0.4) 27 AMIC Technology Corp. A25L40P Series Table 13. AC Characteristics Symbol Alt. Parameter Min. fC fC Clock Frequency for the following instructions: FAST_READ, PP, SE, BE, DP, RES, RDID, WREN, WRDI, RDSR, WRSR Clock Frequency for READ instructions fR tCH 1 tCLH tCL 1 tCLL Clock High Time Typ. Max. Unit D.C. 75/85 5 MHz D.C. 50 MHz 6 5 ns tCLCH 2 Clock Rise Time3 (peak to peak) 0.1 V/ns tCHCL 2 Clock Fall Time3 (peak to peak) 0.1 V/ns S Active Setup Time (relative to C) 5 ns S Not Active Hold Time (relative to C) 5 ns tSLCH tCSS tCHSL Clock Low Time ns tDVCH tDSU Data In Setup Time 5 ns tCHDX tDH Data In Hold Time 5 ns tCHSH S Active Hold Time (relative to C) 5 ns tSHCH S Not Active Setup Time (relative to C) 5 ns 100 ns tSHSL tCSH S Deselect Time tSHQZ 2 tDIS Output Disable Time 8 ns tCLQV tV Clock Low to Output Valid 8 ns tCLQX tHO Output Hold Time 0 ns tHLCH HOLD Setup Time (relative to C) 5 ns tCHHH HOLD Hold Time (relative to C) 5 ns tHHCH HOLD Setup Time (relative to C) 5 ns HOLD Hold Time (relative to C) 5 tCHHL ns tHHQX 2 tLZ HOLD to Output Low-Z 8 ns tHLQZ 2 tHZ HOLD to Output High-Z 8 ns tWHSL 4 Write Protect Setup Time 20 ns tSHWL 4 Write Protect Hold Time 100 ns tDP 2 tRES1 2 tRES2 2 S High to Deep Power-down Mode 3 µs S High to Standby Mode without Electronic Signature Read 30 µs S High to Standby Mode with Electronic Signature Read 30 µs tW Write Status Register Cycle Time 100 300 ms tpp Page Program Cycle Time 3 5 ms tSE Sector Erase Cycle Time 1 3 s tBE Bulk Erase Cycle Time 6 12 s Note: 1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. 5. VCC range 3.0V~3.6V for 85MHz. PRELIMINARY (May, 2007, Version 0.4) 28 AMIC Technology Corp. A25L40P Series Figure 21. Serial Input Timing tSHSL S tCHSL tSLCH tCHSH C tCHCL tDVCH tCLCH tCHDX D Q tSHCH MSB IN LSB IN High Impedance Figure 22. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tSHWL tWHSL S C D Q PRELIMINARY High Impedance (May, 2007, Version 0.4) 29 AMIC Technology Corp. A25L40P Series Figure 23. Hold Timing S tHLCH tHHCH tCHHL C tCHHH D tHLQZ tHHQX Q HOLD Figure 24. Output Timing S tCH C D ADDR.LSB IN tCLQV tCLQX tSHQZ tCL tCLQV tCLQX Q LSB OUT tQLQH tQHQL PRELIMINARY (May, 2007, Version 0.4) 30 AMIC Technology Corp. A25L40P Series Part Numbering Scheme Package Material Blank: normal F: PB free Temperature* Package M = 209 mil SOP 8 N = SOP 16 O = 150 mil SOP 8 Q = QFN 8 Boot Sector T = Top type U = Bottom type Device Version* Device Function P = Page Program & Sector Erase Device Density 05 = 512 Kbit 40 = 4 Mbit 80 = 8 Mbit 16 = 16 Mbit Device Voltage L = 2.7-3.6V Device Type A25 = AMIC Serial Flash * Optional PRELIMINARY (May, 2007, Version 0.4) 31 AMIC Technology Corp. A25L40P Series Ordering Information Part No. Speed (MHz) (2.7V~3.6V)/ (3.0V~3.6V) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (μA) Package A25L40PT-F 8 Pin Pb-Free DIP (300 mil) A25L40PT-UF 8 Pin Pb-Free DIP (300 mil) A25L40PTO-F 8 Pin Pb-Free SOP (150 mil) A25L40PTO-UF 8 Pin Pb-Free SOP (150 mil) A25L40PTM-F 75/85 20 15 50 A25L40PTM-UF 8 Pb-Free Pin SOP (209mil) 8 Pb-Free Pin SOP (209mil) A25L40PTN-F 16 Pin Pb-Free SOP A25L40PTN-UF 16 Pin Pb-Free SOP A25L40PTQ-F 8 Pin Pb-Free QFP A25L40PTQ-UF 8 Pin Pb-Free QFP A25L40PU-F 8 Pin Pb-Free DIP (300 mil) A25L40PU-UF 8 Pin Pb-Free DIP (300 mil) A25L40PUO-F 8 Pin Pb-Free SOP (150 mil) A25L40PUO-UF 8 Pin Pb-Free SOP (150 mil) A25L40PUM-F 75/85 20 15 A25L40PUM-UF 50 8 Pb-Free Pin SOP (209mil) 8 Pb-Free Pin SOP (209mil) A25L40PUN-F 16 Pin Pb-Free SOP A25L40PUN-UF 16 Pin Pb-Free SOP A25L40PUQ-F 8 Pin Pb-Free QFP A25L40PUQ-UF 8 Pin Pb-Free QFP -U is for industrial operating temperature range: -40°C ~ +85°C PRELIMINARY (May, 2007, Version 0.4) 32 AMIC Technology Corp. A25L40P Series Package Information unit: inches/mm P-DIP 8L Outline Dimensions Dimensions in inches Dimensions in mm Symbol Min Nom Max Min Nom Max A - - 0.180 - - 4.57 A1 0.015 - - 0.38 - - A2 0.128 0.130 0.136 3.25 3.30 3.45 B 0.014 0.018 0.022 0.36 0.46 0.56 B1 0.050 0.060 0.070 1.27 1.52 1.78 B2 0.032 0.039 0.046 0.81 0.99 1.17 C 0.008 0.010 0.013 0.20 0.25 0.33 D 0.350 0.360 0.370 8.89 9.14 9.40 E 0.290 0.300 0.315 7.37 7.62 8.00 E1 0.254 0.260 0.266 6.45 6.60 6.76 e1 - 0.100 - - 2.54 - L 0.125 - - 3.18 - - EA 0.345 - 0.385 8.76 - 9.78 S 0.016 0.021 0.026 0.41 0.53 0.66 Notes: 1. Dimension D and E1 do not include mold flash or protrusions. 2. Dimension B1 does not include dambar protrusion. 3. Tolerance: ±0.010” (0.25mm) unless otherwise specified. PRELIMINARY (May, 2007, Version 0.4) 33 AMIC Technology Corp. A25L40P Series Package Information unit: mm E e HE SOP 8L (150mil) Outline Dimensions A1 A b 0° ~ 8° D L Symbol Dimensions in mm A 1.35~1.75 A1 0.10~0.25 b 0.33~0.51 D 4.7~5.0 E 3.80~4.00 e 1.27 BSC HE 5.80~6.20 L 0.40~1.27 Notes: 1. Maximum allowable mold flash is 0.15mm. 2. Complies with JEDEC publication 95 MS –012 AA. 3. All linear dimensions are in millimeters (max/min). 4. Coplanarity: Max. 0.1mm PRELIMINARY (May, 2007, Version 0.4) 34 AMIC Technology Corp. A25L40P Series Package Information unit: mm 5 1 4 E 8 E1 SOP 8L (209mil) Outline Dimensions C A2 A D A1 b θ 0.25 e GAGE PLANE SEATING PLANE L Dimensions in mm Symbol Min Nom Max A 1.75 1.95 2.16 A1 0.05 0.15 0.25 A2 1.70 1.80 1.91 0.48 b 0.35 0.42 C 0.19 0.20 0.25 D 5.13 5.23 5.33 E 7.70 7.90 8.10 E1 5.18 5.28 5.38 e 1.27 BSC L 0.50 0.65 0.80 θ 0° - 8° Notes: Maximum allowable mold flash is 0.15mm at the package ends and 0.25mm between leads PRELIMINARY (May, 2007, Version 0.4) 35 AMIC Technology Corp. A25L40P Series Package Information unit: inch SOP 16L (300mil) Outline Dimensions 0.008 typ. D H E 1 0.02 x 45 9 16 8 0.016 typ. A 0.050 typ. D SEATING PLANE θ A1 0.004max. L Dimensions in inch Symbol Min Max A 0.093 0.104 A1 0.004 0.012 D 0.398 0.413 E 0.291 0.299 H 0.394 0.419 L 0.016 0.050 θ 0° 8° Notes: 1. Dimensions “D” does not include mold flash, protrusions or gate burrs. 2. Dimensions “E” does not include interlead flash, or protrusions. PRELIMINARY (May, 2007, Version 0.4) 36 AMIC Technology Corp. A25L40P Series Package Information unit: mm/mil 0.25 C QFN 8L (6 X 5 X 0.8mm) Outline Dimensions e 1 1 0.25 C b 2 3 4 6 5 L 4 D2 D C0.30 Pin1 ID Area 5 8 8 E 7 E2 A3 A1 A // 0.10 C Seating Plane Symbol y C Dimensions in mm Dimensions in mil Min Nom Max Min Nom Max A 0.700 0.750 0.800 27.6 29.5 31.5 A1 0.000 0.020 0.050 0.0 0.8 2.0 A3 0.203 REF 8.0 REF b 0.350 0.400 0.480 13.8 15.8 18.9 D 5.900 6.000 6.100 232.3 236.2 240.2 D2 3.200 3.400 3.600 126.0 133.9 141.7 E 4.900 5.000 5.100 192.9 196.9 200.8 E2 3.800 4.000 4.200 149.6 157.5 165.4 L 0.500 0.600 0.750 19.7 23.6 29.5 1.270 BSC e y 0 - 50.0 BSC 0.080 0 - 3.2 Note: 1. Controlling dimension: millimeters 2. Leadframe thickness is 0.203mm (8mil) PRELIMINARY (May, 2007, Version 0.4) 37 AMIC Technology Corp.