OSRAM PDSP1881

4.70 mm (0.180’’) 8-Character 5x7 Dot Matrix
Alphanumeric Programmable Display™
Lead (Pb) Free Product - RoHS Compliant
Red
Yellow
High Efficiency Red
Green
High Efficiency Green
PDSP1880
PDSP1881
PDSP1882
PDSP1883
PDSP1884
DESCRIPTION
FEATURES
• Eight 4.70 mm (0.180") Dot Matrix Characters in Red,
Yellow, High Efficiency Red, Green, or
High Efficiency Green
• Built-in 128 Character ROM,
Mask Programmable for Custom Fonts
• Readable from 2.5 meters (8 Feet)
• Built-in Decoders, Multiplexers and Drivers
• Wide Viewing Angle, X Axis ± 55°, Y Axis 65°
• Programmable Features:
– Individual Flashing Character
– Full Display Blinking
– Multi-Level Dimming and Blanking
– Clear Function
– Self Test
• Internal or External Clock
• End Stackable Dual-In-Line Plastic Package
• Read/Write Capability
• 16 User Definable Characters
The PDSP1880 (Red), PDSP1881 (Yellow), PDSP1882
(High Efficiency Red), PDSP1883 (Green), and
PDSP1884 (High Efficiency Green) are eight digit,
5 x 7 dot matrix, alphanumeric Programmable Displays.
The 4.70 mm (0.180’’) high digits are packaged in a rugged, high quality, optically transparent, 7.62 mm (0.300’’)
lead spacing, 30 pin plastic DIP.
The on-board CMOS has a built-in 128 character ROM.
The PDSP188X also has a user definable character
(UDC) feature, which uses a RAM that permits storage of
16 arbitrary characters, symbols or icons that are software-definable by the user. The character ROM itself is
mask programmable and easily modified by the manufacturer to provide specified custom characters.
The PDSP188X is designed for standard microprocessor
interface techniques, and is fully TTL compatible. The
Clock I/O and Clock Select pins allow the user to cascade multiple display modules.
ESD Warning:
2006-03-30
Standard precautions for
CMOS handling should be
observed.
1
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
Ordering Information
Type
Color of Emission
Character Height
mm (inch)
PDSP1880
red
PDSP1881
yellow
PDSP1882
high efficiency red
PDSP1883
green
Q68000A9108
PDSP1884
high efficiency green
Q68000A9109
Q68000A9105
Q68000A9106
4.70 (0.180)
V
Y
Pin 15
5.08 (0.200)
0.46 (0.018) typ.
10.16 (0.400)
2.54 (0.100) typ.
±0.13 (0.005)
CL
5.33 (0.210)
PDSP188X Z
YYWW
OSRAM
Pin 16
Color Code
Pin 15
LI Code
CL
4.01 (0.158) typ.
Date Code
0.25 (0.010)
Dimensions in mm (inch)
Pin 1
Identifier
0.51 (0.020)
Q68000A9107
1.52 (0.060) ref.
Package Outlines
Pin 1
Indicator
Ordering Code
5.71 (0.225)
0.3 (0.012) typ.
7.62 (0.300)
(Tol. non cum.)
1
2
3
4.57 (0.180)
11.43 (0.450) max.
0
5.36 (0.211)
2.68 (0.105)
2.29 (0.090)
42.93 (1.690) max.
2.54 (0.100)
CL
4
5
6
CL
Pin 1
Identifier
2006-03-30
7
IDOD5014
2
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
Maximum Ratings (TA=25°C)
Parameter
Symbol
Value
Unit
Operating temperature range
Top
– 40 … + 85
°C
Storage temperature range
Tstg
– 55 … + 100
°C
DC Supply Voltage, VCC to GND
(max. voltage with no LEDs on)
VCC
-0.3 to + 7.0
V
Operating Voltage, VCC to GND
(max. voltage with 20 dots/digits on)
5.5
V
Input Voltage Levels,
all inputs
-0.3 to VCC + 0.3
V
260
°C
85
%
4.0
kV
Solder Temperature
1.59 mm (0.063“) below seating plane, t < 5.0 s
TS
Relative Humidity (non-condensing)
ESD (100 pF, 1.5 kΩ)
(each pin)
VZ
Optical Characteristics at 25°C
(VCC=5.0 V at 100% brightness level)
2006-03-30
Green
PDSP1883
High Efficiency Green
PDSP1884
Dominant Wavelength
Unit
High Efficiency Red
PDSP1882
Peak Wavelength
Values
Yellow
PDSP1881
Peak Luminous Intensity
Symbol
Red
PDSP1880
Description
(min.) IVpeak
(typ.)
70
125
125
205
125
350
125
275
125
500
µcd/dot
µcd/dot
(typ.) λpeak
660
583
630
565
568
nm
(typ.) λdom
639
585
626
570
574
nm
3
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
Enlarged Character Format
Dimensions in mm (inch)
Switching Specifications
(over operating temperature range and VCC=4.5 V)
Symbol
Description
Min.
Units
Tacc
Display Access Time—Write
210
ns
Tacc
Display Access Time—Read
230
ns
R1
Tacs
Address Setup Time to CE
10
ns
R2
Tce
Chip Enable Active Time—Write
140
ns
Tce
Chip Enable Active Time—Read
160
ns
Tach
Address Hold Time to CE
20
ns
Tcer
Chip Enable Recovery Time
60
ns
Tces
Chip Enable Active Prior to
Rising Edge—Write
140
ns
Tces
Chip Enable Active Prior to
Rising Edge—Read
160
ns
Tceh
Chip Enable Hold to Rising Edge
of Read/Write Signal
0
ns
Tw
Write Active Time
100
ns
Twd
Data Valid Prior to
Rising Edge of Write Signal
50
ns
Tdh
Data Write Time
20
ns
Tr
Chip Enable Active Prior to Valid
Data
160
ns
Trd
Read Active Prior to Valid Data
95
ns
Tdf
Read Data Float Delay
10
ns
Trc
Reset Active Time
300
ns
R3
R4
R5
4.52 (0.178)
C0 C1 C2 C3 C4
0.254 (0.010) typ.
0.71 (0.028) typ.
2.49 (0.098)
R6
R7
0.56 (0.022) typ.
IDOD5015
Write Cycle Timing Diagram
Tacc
A0-A3
FL
Tacs
Tach
Tacs
Tce
Tcer
CE
Tceh
Tces
Tw
WR
Twd
Tdh
D0-D7
2006-03-30
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PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
Read Cycle Timing Diagram
Tacc
A0-A3
FL
Tacs
Tach
Tacs
Tce
Tcer
CE
Tceh
Tces
Tr
RD
Trd
Tdf
D0-D7
Character Set
D0
D1
D2
D3
D7 D6 D5 D4 HEX
ASCII
CODE
L L L L
0
L L L H
1
L L H L
2
L L H H
3
L H L L
4
L H L H
5
L H H L
6
L H H H
7
H X X X
8
L
L
L
L
0
H
L
L
L
1
L
H
L
L
2
H
H
L
L
3
L
L
H
L
4
H
L
H
L
5
L
H
H
L
6
H
H
H
L
7
L
L
L
H
8
H
L
L
H
9
L
H
L
H
A
H
H
L
H
B
L
L
H
H
C
H
L
H
H
D
L
H
H
H
E
H
H
H
H
F
UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC UDC
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
IDCS5086
Notes:
1. Upon power up, the device will initialize in a random state.
2. X=don’t care.
2006-03-30
5
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
DC Electrical Characteristics at 25°C
Parameters
Limits
Conditions
Min.
Typ.
Max.
Units
VCC
4.5
5.0
5.5
V
—
ICC Blank
—
0.65
1.0
mA
VCC=5.0 V, VIN=5.0 V
ICC 12 dots/digit on1) 2)
—
200
255
mA
VCC=5.0 V, “V” in all 8 digits
ICC 20 dots/digit on1) 2)
—
300
370
mA
VCC=5.0 V, “#” in all 8 digits
IILP (with pull-up)
Input Leakage
–18
–11
–5.0
µA
VCC=5.0 V, VIN=0 V to VCC
IIL (no pull-up)
Input Leakage
–1.0
—
+1.0
µA
VCC=5.0 V, VIN=5.0 V
(CLK, A0–A3, D0–D7)
VIH Input Voltage High
2.0
—
VCC
+0.3
V
VCC=4.5 V to 5.5 V
VIL Input Voltage Low
GND
–0.3
—
—
V
VCC=4.5 V to 5.5 V
VOL (D0–D7), Output Voltage Low
—
—
0.4
V
VCC=4.5 V, IOL=1.6 mA
VOL (CLK), Output Voltage Low
—
—
0.4
V
VCC=4.5 V, IOL=40 µA
VOH Output Voltage High
2.4
—
—
V
VCC=4.5 V, IOH=40 µA
θJC Thermal Resistance,
Junction to Case
—
25
—
°C/W
—
Clock I/O Frequency
28
57.34
81.14
kHz
VCC=4.5 to 5.5 V
FM, Digit Multiplex Frequency
125
256
362.5
Hz
VCC=4.5 to 5.5 V
Blinking Rate
0.98
2.0
2.83
Hz
—
Clock I/O Buss Loading
—
—
2.40
pF
—
Clock Out Rise Time
—
—
500
nsec
VCC=4.5 V, VOH=2.4 V
Clock Out Fall Time
—
—
500
nsec
VCC=4.5 V, VOH=0.4 V
(WR, CE, FL, RST, RD, CLKSEL)
Notes:
1)
ICC is an average value.
2)
ICC is measured with the display at full brightness. Peak ICC= 28/15 ICC average (#displayed).
Recommended Operating Conditions (TA = – 40°C to + 85°C)
Parameter
Symbol
Min.
Max.
Units
Supply Voltage
VCC
4.5
5.5
V
Input Voltage Low
VIL
—
0.8
V
Input Voltage High
VIH
2.0
—
V
Output Voltage Low
VOL
—
0.4
V
Output Voltage High
VOH
2.4
—
V
2006-03-30
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PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
Top View
0
Pin Assignments
1
2
3
4
5
6
7
Pin #
Name
Symbol
Definition
16
Supply
ground
GNDsup
Analog ground for LED drivers
17
—
NC
No connection
18
Logic
ground
GNDlog
Logic ground for digital
circuitry
19
Read
RD
Reads data from display when
RD=0. Also CE=0.
20
Data bit
zero
D0
Least significant data bit.
21
Data bit
one
D1
Second data bit.
22–24
No pins
—
No connections
25
Data bit
two
D2
Third data bit.
26
Data bit
three
D3
Fourth data bit.
27
Data bit
four
D4
Fifth data bit.
28
Data bit
five
D5
Sixth data bit.
29
Data bit
six
D6
Seventh data bit.
30
Data bit
seven
D7
Most significant data bit.
IDPA5110
Pin Assignments
Pin #
Name
Symbol
Definition
1
Reset
RST
Initializes display; clears Character
RAM (20H), Flash RAM (00H),
control word (00H), and resets
internal counters. UDC Address
Register and UDC RAM
unaffected.
2
3
Flash
Address
input
4
5
FL
Accesses Flash RAM. Address
inputs A0–A2 select digit address
while data bit D0 sets (D0=1) or
resets (D0=0) Flash bit, A3 and A4
ignored.
A0
A0–A2 select specific digits.
See Table „Memory Selection“
(page 9).
A1
Same as A0
A2
Same as A0
6
Address
input
A3
A3 and A4 access parts of memory
together with Flash pin. See Table
1.
7–9
No pins
—
No connections
10
Address
input
A4
Same as A3
11
Clock
Select
CLS
Selects internal or external clock
source. CLS=1 selects internal
clock (master), CLS=0 selects
external clock (slave operation).
12
Clock
In/Out
CLK
Inputs or outputs clock as
determined by CLS.
13
Write
WR
Writes data into display when
WR=0. Note CE=0 to enable write
cycle.
14
Chip
Enable
CE
Enables display’s write and read
cycles when CE=0.
15
Positive
supply
VCC
Positive power supply input.
2006-03-30
Cascading Displays
The PDSP188X is designed to drive up to 16 other
PDSP188Xs with input loading of 15 pF each.
General requirements for cascading 16 displays
together:
• Determine the correct address for each display.
• Use CE from an address decoder to select the correct
display.
• Use CE from an address decoder to select the correct
display.
• Select one of the Displays to provide the Clock for the
other displays. Connect CLKSEL to VCC for this display.
• Tie CLKSEL to ground on other displays.
• Use RST to synchronize the blinking between the displays.
7
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
Cascading Diagram
RD
WR
FL
RST
VCC
RD
WR
FL RST CLK CLK
I/O SEL
Display
D0-D7 A0-A4
RD
WR
FL RST CLK CLK
I/O SEL
Display
Up to 14 more
displays in between
CE
D0-D7 A0-A4
CE
Data I/O
Address
A6
A7
A8
A9
0
Address Decode Chip 1 to 14
Address
Decoder
15
IDCD5031
Block Diagram
OSC
32
Counter
7
Counter
3
Counter
Row
Drivers
Character
RAM
Decode
Column
Drivers
8 Digit Display
128
Counter
Character
RAM
ROM
Word
Decode
64
ROM
5
25
Slave
D Latch
Holding
Register
Master
Column
Latch
25
Cursor
Controls
and
Display
MUX
5
Character
Decode
for Display
Data
Bus
4
UDC
Address
Register
4
Character
Decode
16
16
UDC
RAM
Self
Test
Control
Word
Register
Flash
RAM
(Read/Write)
IDBD5064
2006-03-30
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PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
Functional Description
The display's user interface is organized into five memory areas.
They are accessed using the Flash Input, FL , and address lines,
A3 and A4. All the listed RAMs and Registers may be read or written through the data bus. See Table „Memory Selection“ (page 9).
Each input pin is described in Pin Definitions.
Theory of Operation
The PDSP188X Display is designed to work with all major microprocessors. Data entry is via an eight bit parallel bus. Three bits of
address route the data to the proper digit location in the RAM.
Standard control signals like WR and CE allow the data to be written into the display.
D0–D7 data bits are used for both Character RAM and control
word data input. A3 acts as the mode selector. If A3=1, character
RAM is selected. Then input data bit D7 will determine whether
input data bits D0–D6 is ASCII coded data (D7=0) or UDC data
(D7=1). See section on „UDC Address Register and UDC RAM“
(page 10).
For normal operation FL pin should be held high. When FL is held
low, Flash RAM is accessed to set character blinking.
Five Basic Memory Areas
Character RAM
Stores either ASCII (Katakana)
character data or an UDC RAM
address
Flash RAM
1 x 8 RAM which stores Flash data
User-Defined
Character RAM
(UDC RAM)
Stores dot pattern for custom
characters
User-Defined Address
Register (UDC Address
Register)
Provides address to UDC RAM
when user is writing or reading
custom character
Control Word
Register
Enables adjustment of display
brightness, flash individual
characters, blink, self test or clearing
the display
The seven bit ASCII code is decoded by the Character ROM to
generate Column data. Twenty columns worth of data is sent out
each display cycle, and it takes fourteen display cycles to write into
eight digits.
The rows are multiplexed in two sets of seven rows each. The
internal timing and control logic synchronizes the turning on of
rows and presentation of column data to assure proper display
operation.
Power Up Sequence
Upon power up the display will come on at random. Thus the display should be reset on power-up. Reset will clear the Flash
RAM, Control Word Register and reset the internal counter. All
the digits will show blanks and display brightness level will be
100%.
The display must not be accessed until three clock pulses (110 µs
minimum using the internal clock) after the rising edge of the reset
line.
RST can be used to initialize display operation upon power up or
during normal operation. When activated, RST will clear the Flash
RAM and Control Word Register (00H) and reset the internal
counter. All eight display memory locations will be set to 20H to
show blanks in all digits.
FL pin enables access to the Flash RAM. The Flash RAM will set
(D0=1) or reset (D0=0) flashing of the character addressed by A0–
A2.
The 1 x 8 bit Control Word Register is loaded with attribute data if
A3=0.
Microprocessor Interface
The interface to a microprocessor is through the 8-bit data bus
(D0–D7), the 4-bit address bus (A0–A3) and control lines FL , CE
and WR.
To write data (ASCII/Control Word) into the display CE should be
held low, address and data signals stable and WR should be
brought low. The data is written on the low to high transition of
WR.
The Control Word is decoded by the Control Word Decode Logic.
Each code has a different function. The code for display brightness
changes the duty cycle for the column drivers. The peak LED current stays the same but the average LED current diminishes
depending on the intensity level.
The character Flash Enable causes 2.0 Hz coming out of the
counter to be ANDED with the column drive signal to make the column driver cycle at 2.0 Hz. Thus the character flashes at 2.0 Hz.
The Control Word Logic decodes attribute data for proper implementation.
Character ROM is designed for 128 ASCII characters. The ROM
is Mask Programmable for custom fonts.
The Clock Source could either be the internal oscillator
(CLKSEL=1) of the device or an external clock (CLKSEL=0) could
be an input from another HDSP211X display for synchronizing
blinking for multiple displays.
The Display Multiplexer controls the Row Drivers so no additional
logic is required for a display system.
The Display has eight digits. Each digit has 35 LEDs.
Memory Selection
FL
A4
A3
Section of Memory
A2–A0
Data Bits Used
0
X
X
Flash RAM
Character Address
D0
1
0
0
UDC Address Register
Don’t Care
D3–D0
1
0
1
UDC RAM
Row Address
D4–D0
1
1
1
Character RAM
Character Address
D7–D0
1
1
0
Control Word Register
Don’t Care
D7–D0
2006-03-30
9
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
The display Blink works the same way as the Flash Enable but
causes all twenty column drivers to cycle at 2.0 Hz thereby making
all eight digits blink at 2.0 Hz.
The Self Test function of the IC consists of two internal routines
which exercise major portions of the IC and illuminates all the
LEDs.
Clear bit clears the character RAM and writes a blank into the display memory. It however does not clear the control word.
ASCII Data or Control Word Data can be written into the display
at this point. For multiple display operation, CLK I/O must be
properly selected. CLK I/O will output the internal clock if CLKSEL=1, or will allow input from an external clock if CLKSEL=0.
UDC Address Register and UDC RAM
The UDC Address Register and UDC RAM allows the user to generate and store up to 16 custom characters. Each custom character is defined in 5 x 7 dot matrix pattern. It takes 8 write cycles to
define a custom character, one cycle to load the UDC Address
Register and 7 cycles to define the character. The contents of the
UDC Address Register will store the 4 bit address for one of the 16
UDC RAM locations. The UDC RAM is used to store the custom
character.
UDC Address Register
The UDC Address Register is selected by setting FL=1, A4=0,
A3=0. It is a 4 bit register and uses data bits, D3–D0 to store the
4 bit address code (D7–D4 are ignored). The address code
selects one of 16 UDC RAM locations for custom character generation.
Character RAM
The Character RAM is selected when FL , A4 and A3 are set to
1,1,1 during a read or write cycle. The Character RAM is a 8 by 8
bit RAM with each of the eight locations corresponding to a digit on
the display. Digit 0 is on the left side of the display and digit 7 is on
the right side of the display. Address lines, A2–A0 select the digit
address with A2 being the most significant bit and A0 being the
least significant bit. The two types of data stored in the Character
RAM are the ASCII coded data and the UDC Address Data. The
type of data stored in the Character RAM is determined by data bit,
D7. If D7 is low, then ASCII coded data is stored in data bits D6–
D0. If D7 is high, then UDC Address Data is stored in data bit D3–
D0.
The ASCII coded data is a 7 bit code used to select one of 128
ASCII characters permanently stored in the ASCII ROM.
UDC RAM
The UDC RAM is selected by setting FL=1, A4=0, A3=1. The RAM
is comprised of a 7 x 5 bit RAM. As shown in Table „UDC Character Map“ (page 11), address lines, A2-A0 select one of the 7 rows
of the custom character. Data bits, D4-D0 determine the 5 bits of
column data in each row. Each data bit corresponds to a LED. If
the data bit is high, then the LED is on. If the data bit is low, the
LED is off. To create a character, each of the 7 rows of column
data need to be defined. See Table „UDC Address Register and
UDC RAM“ (page 10) for logic.
The UDC Address data is a 4 bit code used to select one of the
UDC characters in the UDC RAM. There are up to 16 characters
available. See Table „Character RAM Access Logic“ (page 10).
Character RAM Access Logic
RST
CE
WR
RD
FL
A4
A3
A2
1
0
0
1
1
1
1
Character Address for
Digits 0–7
A1
A0
D7 D6 D5 D4 D3 D2 D1 D0
0
7 bit ASCII code for a Write Cycle
1
0
1
0
1
1
1
Character Address for
Digits 0–7
0
7 bit ASCII code read during a Read Cycle
1
0
0
1
1
0
0
Character Address for
Digits 0–7
1
D3–D0=UDC address for a Write Cycle
1
0
1
0
1
0
0
Character Address for
Digits 0–7
1
D3–D0=UDC address for Read Data
D7 D6 D5 D4 D3 D2 D1 D0
UDC Address Register and UDC Character RAM
RST
CE
WR
RD
FL
A4
A3
A2
1
0
0
1
1
0
0
Not used for UDC
Address Register
D3–D0=UDC RAM Address Code
for Write Cycle
1
0
1
0
1
0
0
Not used for UDC
Address Register
D3–D0=UDC RAM Address Code
for Read Cycle
1
0
0
1
1
0
1
A2–A0=Character
Row Address
D4–D0=Character Column Data
for Write Cycle
1
0
1
0
1
0
1
A2–A0=Character
Row Address
D4–D0=Character Column Data
read during a Read Cycle
2006-03-30
10
A1
A0
UDC
Address
Register
UDC
RAM
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
Flash RAM
The Flash RAM allows the display to flash one or more of the characters being displayed. The Flash Ram is accessed by setting FL
low. A4 and A3 are ignored. The Flash RAM is a 8 x 1 bit RAM with
each bit corresponding to a digit address. Digit 0 is on the left side
of the display and digit 7 is on the right side of the display. Address
lines, A2–A0 select the digit address with A2 being the most significant digit and A0 being the least significant digit. Data bit, D0, sets
and resets the flash bit for each digit. When D0 is high, the flash bit
is set; and when D0 is low, it is reset. See Table „Flash RAM
Access Logic“ (page 11).
Blink Function
Control Word bit, D4, enables or disables the Blink Function. When
D4 is 1, the Blink Function is enabled and all characters on the display will blink at approximately 2.0 Hz. The Blink Function will override the Flash Function if both functions are enabled. When D4 is
0, the Blink Function is disabled. When using an external clock, the
blink rate can be determined by dividing the clock rate by 28,672.
For synchronized blinking on multiple displays, see the Reset Section (page 12).
UDC Character Map
Control Word
The Control Word is used to set up the attributes required by the
user. It is addressed by setting FL=1, A4=1, A3=0. The Control
Word is an 8 bit register and is accessed using data bits, D7–D0.
See Table „Control Word Access Logic“ (page 11) and Figure
„Control Word Data Definition“ (page 12) for the logic and attributed control. The Control Word has 5 functions. They are brightness control, flashing character enable, blinking character
enable, self test, and clear (Flash and Character RAMS only).
Row Data
Brightness Control
Control Word bits, D2–D0, control the brightness of the display
with a binary code of 000 being 100% brightness and 111 being
display blank. See Figure „Control Word Data Definition“
(page 12) for brightness level versus binary code. The average ICC
can be calculated by multiplying the 100% brightness level ICC
value by the display’s brightness level. For example, a display set
to 80% brightness with a 100% average ICC value of 200 mA will
have an average ICC value of 200 mA x 80%=160 mA.
Column Data
A2
A1
A0
Row #
0
0
0
1
0
0
1
2
0
1
0
3
0
1
1
4
1
0
0
5
1
0
1
6
1
1
0
7
C1
C2
C3
C4
C5
D4
D3
D2
D1
D0
5x7
Dot Matrix
Pattern
Self Test
Control Word bits, D6 and D5, are used for the Self Test Function.
When D6 is 1, the Self Test is initiated. Results of the Self Test are
stored in bit D5. Control Word bit, D5, is a read only bit. When D5
is 1, Self Test has passed. When D5 is 0, Self Test failed is indicated. The Self Test function of the IC consists of two internal routines which exercise major portions of the IC and illuminates all of
the LEDs. The first routine cycles the ASCII decoder ROM through
all states and performs a check sum on the out-put. If the check
sum is correct, D5 is set to a 1 (Pass).
Flash Function
Control Word bit, D3, enables or disables the Flash Function.
When D3 is 1, the Flash Function is enabled and any digit with its
corresponding bit set in the Flash RAM will flash at approximately
2.0 Hz. When using an external clock, the flash rate can be determined by dividing the clock rate by 28,672. When D3 is 0, the
Flash Function is disabled and the contents of the Flash RAM is
ignored. For synchronized flashing on multiple displays, see the
Reset Section (page 12).
Flash RAM Access Logic
RST
CE
WR
RD
FL
A4
A3
A2
1
0
0
1
0
X
X
Flash RAM Address
for Digits 0–7
A1
A0
D7 D6 D5 D4 D3 D2 D1 D0
D0=Flash Data, 0=Flash Off and 1=Flash On
(Write Cycle)
1
0
1
0
0
X
X
Flash RAM Address
for Digits 0–7
D0=Flash Data, 0=Flash Off and 1=Flash On
(Read Cycle)
D7 D6 D5 D4 D3 D2 D1 D0
Control Word Access Logic
RST
CE
WR
RD
FL
A4
A3
A2
1
0
0
1
1
1
0
Not used for Control
Word
Control Word data for a Write Cycle,
see Figure „Control Word Data Definition“
(page 12)
1
0
1
0
1
1
0
Not used for Control
Word
Control Word data for a Read during a
Read Cycle
2006-03-30
11
A1
A0
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
The second routine provides a visual test of the LEDs. This is
accomplished by writing checkered and inversed checkered patterns to the display. Each pattern is displayed for approximately
2.0 sec. During the self test function the display must not be
accessed. The time needed to execute the self test function is calculated by multiplying the clock time by 262,144 (typical
time ≈ 4.6 s). At the end of the self test, the Character RAM is
loaded with blanks; the Control Word Register is set to zeroes
except D5; the Flash RAM is cleared and the UDC Address Register is set to all 1.0 sec.
Reset Function
The display should be reset on power up of the display
(RST=LOW). When the display is reset, the Character RAM, Flash
RAM, and Control Word Register are cleared.
The display's internal counters are reset. Reset cycle takes three
clock cycles (110 µs minimum using the internal clock). The display must not be accessed during this time.
To synchronize the flashing and blinking of multiple displays, it is
necessary for the display to use a common clock source and reset
all the displays at the same time to start the internal counters at
the same place.
While RST is low, the display must not be accessed by RD nor
WR.
Clear Function (see Figure „Control Word Data Definition“
(page 12) and Table „Clear Function“ (page 12))
Control Word bit, D7 clears the character RAM to 20 hex and the
flash RAM to all zeroes. The RAMs are cleared within three clock
cycles (110 µs minimum, using the internal clock) when D7 is set
to 1. During the clear time the display must not be accessed.
When the clear function is finished, bit 7 of the Control Word RAM
will be reset to a “0”.
Control Word Data Definition
D7
D6
Clear
Function
D5
Self Test
D4
D3
Blink
Function
Flash
Function
D2
D1
Key
D0
Brightness Control
D2
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
0
0
1
Brightness Control
100% Brightness
80% Brightness
53% Brightness
40% Brightness
27% Brightness
20% Brightness
13% Brightness
Blank Display
C
Clear Function
ST
Self test
BL
Blink function
FL
Flash function
Br
Brightness control
D3 Flash Function
0 Disabled
1 Enabled
D4 Blink Function
0 Disabled
1 Enabled (overrides Flash Function)
D6 D5 Self Test
0 X Normal Operation (X = bit ignored)
1 R Run Self Test, R = Test Result (1 = pass, 0 = fail)
D7 Clear Function
0 Normal Operation
1 Clear Flash RAM & Character RAM (Character RAM = 20 Hex)
IDCW5161
Clear Function
CE
WR
FL
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Operation
0
0
0
0
1
1
0
0
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Clear disabled
Clear user RAM, flash RAM
and display
X=don’t care
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12
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
Display Cycle Using Built-in ROM Example
Display message “Showtime.” Digit 0 is leftmost—closest to pin 1.
Logic levels: 0=Low, 1=High, X=Don’t care.
RST
CE
WR
RD
FL
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Operation
Display
0
X
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
Reset. No
Read/Write
Within 3 Clock
Cycles
All Blank
1
0
0
1
1
1
0
X
X
X
0
0
X
0
0
0
1
1
53% Brightness
Selected
All Blank
1
0
0
1
1
1
1
0
0
0
0
1
0
1
0
0
1
1
Write “S” to Digit 0
S
1
0
0
1
1
1
1
0
0
1
0
1
0
0
1
0
0
0
Write “H” to Digit 1
SH
1
0
0
1
1
1
1
0
1
0
0
1
0
0
1
1
1
1
Write “O” to Digit 2
SHO
1
0
0
1
1
1
1
0
1
1
0
1
0
1
0
1
1
1
Write “W” to Digit 3
SHOW
1
0
0
1
1
1
1
1
0
0
0
1
0
1
0
1
0
0
Write “T” to Digit 4
SHOWT
1
0
0
1
1
1
1
1
0
1
0
1
0
0
1
0
0
1
Write “I” to Digit 5
SHOWTI
1
0
0
1
1
1
1
1
1
0
0
1
0
0
1
1
0
1
Write “M” to Digit 6
SHOWTIM
1
0
0
1
1
1
1
1
1
1
0
1
0
0
0
1
0
1
Write “E” to Digit 7
SHOWTIME
Displaying User Defined Character Example
Load character “A” into UDC-5 and then display it in digit 2.
Logic levels: 0=Low, 1=High, X=Don‘t care
RST
CE
WR
RD
FL
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Operation
Display
0
X
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
Reset. No
Read/Write
Within 3 Clock
Cycles
All Blank
1
0
0
1
1
0
0
X
X
X
X
X
X
X
0
1
0
1
Select UDC-5
All Blank
1
0
0
1
1
0
1
0
0
0
X
X
X
0
1
1
1
0
Write into Row 1 of
UDC-5
All Blank
1
0
0
1
1
0
1
0
0
1
X
X
X
1
0
0
0
1
Write into Row 2 of
UDC-5
All Blank
1
0
0
1
1
0
1
0
1
0
X
X
X
1
0
0
0
1
Write into Row 3 of
UDC-5
All Blank
1
0
0
1
1
0
1
0
1
1
X
X
X
1
1
1
1
1
Write into Row 4 of
UDC-5
All Blank
1
0
0
1
1
0
1
1
0
0
X
X
X
1
0
0
0
1
Write into Row 5 of
UDC-5
All Blank
1
0
0
1
1
0
1
1
0
1
X
X
X
1
0
0
0
1
Write into Row 6 of
UDC-5
All Blank
1
0
0
1
1
0
1
1
1
0
X
X
X
1
0
0
0
1
Write into Row 7 of
UDC-5
All Blank
1
0
0
1
1
1
1
0
1
0
1
X
X
X
0
1
0
1
Write UDC-5 into
Digit 2
(Digit 2) A
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PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
Electrical and Mechanical Considerations
Voltage Transient Suppression
For best results power the display and the components that interface with the display to avoid logic inputs higher than VCC. Additionally, the LEDs may cause transients in the power supply line
while they change display states. The common practice is to place
a parallel combination of a 0.01 µF and a 22 µF capacitor between
VCC and GND for all display packages.
Optical Considerations
The 4.70 mm (0.180") high character of the PDSP188X gives
readability up to eight feet. Proper filter selection enhances readability over this distance.
Using filters emphasizes the contrast ratio between a lit LED and
the character background. This will increase the discrimination of
different characters. The only limitation is cost. Take into consideration the ambient lighting environment for the best cost/benefit
ratio for filters.
Incandescent (with almost no green) or fluorescent (with almost no
red) lights do not have the flat spectral response of sunlight. Plastic band-pass filters are an inexpensive and effective way to
strengthen contrast ratios. The PDSP1880 / PDSP1882 are
red / high efficiency red displays and should be matched with a
long wavelength pass filter in the 570 nm to 590 nm range. The
PDSP1883 should be matched with a yellow-green band-pass filter that peaks at 565 nm. For displays of multiple colors, neutral
density grey filters offer the best compromise.
Additional contrast enhancement is gained by shading the displays. Plastic band-pass filters with built-in louvers offer the next
step up in contrast improvement. Plastic filters can be improved
further with anti-reflective coatings to reduce glare. The trade-off is
fuzzy characters. Mounting the filters close to the display reduces
this effect. Take care not to overheat the plastic filter by allowing for
proper air flow.
Optimal filter enhancements are gained by using circular polarized,
anti-reflective, band-pass filters. The circular polarizing further
enhances contrast by reducing the light that travels through the filter
and reflects back off the display to less than 1%.
Several filter manufacturers supply quality filter materials. Some of
them are: Panelgraphic Corporation, W. Caldwell, NJ; SGL Homalite, Wilmington, DE; 3M Company, Visual Products Division, St.
Paul, MN; Polaroid Corporation, Polarizer Division, Cambridge,
MA; Marks Polarized Corporation, Deer Park, NY, Hoya Optics,
Inc., Fremont, CA.
One last note on mounting filters: recessing displays and bezel
assemblies is an inexpensive way to provide a shading effect in
overhead lighting situations. Several bezel manufacturers are:
R.M.F. Products, Batavia, IL; Nobex Components, Griffith Plastic
Corp., Burlingame, CA; Photo Chemical Products of California,
Santa Monica, CA; I.E.E.-Atlas, Van Nuys, CA.
ESD Protection
The input protection structure of the PDSP188X provides significant protection against ESD damage. It is capable of withstanding
discharges greater than 4.0 kV. Take all the standard precautions
normal for CMOS components. These include properly grounding
personnel, tools, tables, and transport carriers that come in contact with unshielded parts. If these conditions are not, or cannot be
met, keep the leads of the device shorted together or the parts in
anti-static packaging.
Soldering Considerations
The PDSP188X can be hand soldered with SN63 solder using a
grounded iron set to 260 °C.
Wave soldering is also possible. Use water soluble organic acid
flux or resin based RMA flux.
A wave temperature of 245 °C ± 5 °C with a dwell between 1.5 sec
to 3.0 sec can be used. Exposure to the wave should not exceed
temperatures above 260 °C for five seconds at 1.59 mm (0.063")
below the seating plane. The packages should not be immersed in
the wave.
Post Solder Cleaning Procedures
The least offensive cleaning solution is hot D.I. water (60 °C) for
less than 15 minutes. Addition of mild saponifiers is acceptable.
Do not use commercial dishwasher detergents.
For faster cleaning, solvents may be used. Exercise care in choosing solvents as some may chemically attack the polycarbonate
package. Maximum exposure should not exceed two minutes at
elevated temperatures. Acceptable solvents are TF (trichorotrifluorethane), and IPA.
Some major solvent manufacturers are: Allied Chemical Corporation, Specialty Chemical Division, Morristown, NJ;
Baron-Blakeslee, Chicago, IL; Dow Chemical, Midland, MI; E.I.
DuPont de Nemours & Co., Wilmington, DE.
For further information refer to Appnote 19 at www.osram-os.com
An alternative to soldering and cleaning the display modules is to
use sockets. Naturally, 28 pin DIP sockets 7.62 mm (0.300") wide
with 2.54 mm (0.100") centers work well for single displays. Multiple display assemblies are best handled by longer SIP sockets or
DIP sockets when available for uniform package alignment. Socket
manufacturers are Aries Electronics, Inc., Frenchtown, NJ; Garry
Manufacturing, New Brunswick, NJ; Robinson-Nugent, New
Albany, IN; and Samtec Electronic Hardward, New Albany, IN.
2006-03-30
14
PDSP1880, PDSP1881, PDSP1882, PDSP1883, PDSP1884
Revision History: 2006-03-30
Previous Version: 2004-12-09
Page
Subjects (major changes since last revision)
Date of change
all
Lead free device
2006-01-23
Published by
OSRAM Opto Semiconductors GmbH
Wernerwerkstrasse 2, D-93049 Regensburg
www.osram-os.com
© All Rights Reserved.
Attention please!
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved. Due to technical requirements components may contain
dangerous substances. For information on the types in question please contact our Sales Organization.
If printed or downloaded, please find the latest version in the Internet.
Packing
Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office.
By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing
material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs
incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose! Critical
components1) may only be used in life-support devices or systems2) with the express written approval of OSRAM OS.
1)
2)
A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
failure of that life-support device or system, or to affect its safety or the effectiveness of that device or system.
Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain
human life. If they fail, it is reasonable to assume that the health and the life of the user may be endangered.
2006-03-30
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