19-3209; Rev 1; 2/09 KIT ATION EVALU E L B A AVAIL Low-Power Audio/Video Switch for Dual SCART Connectors Features The MAX9598 dual SCART matrix routes audio and video signals between a set-top box decoder chip and two external SCART connectors under I2C control. Operating from a 3.3V supply and a 12V supply, the MAX9598 consumes 70mW during quiescent operation and 471mW during average operation when driving typical signals into typical loads. Video input detection, video load detection, and a 1.7mW low-power mode facilitate the design of lowpower set-top boxes. ♦ 70mW Quiescent Power Consumption The MAX9598 audio section contains a buffered crosspoint to route audio inputs to audio outputs. The DirectDrive® output amplifiers create a 2VRMS full-scale audio signal biased around ground, eliminating the need for bulky output capacitors and reducing clickand-pop noise. The zero-cross detection circuitry also further reduces clicks and pops by enabling audio sources to switch only during a zero-crossing. The MAX9598 video section contains a buffered crosspoint to route video inputs to video outputs. The standarddefinition video signals from the set-top box decoder chip are lowpass filtered to remove out-of-bandwidth artifacts. The MAX9598 also supports slow-switching and fast-switching signals. An interrupt signal from the MAX9598 informs the microcontroller (µC) when the system status has changed. The MAX9598 is available in a compact 40-pin thin QFN package and is specified over the 0°C to +70°C commercial temperature range. ♦ Video Reconstruction Filter with 10MHz Passband and 52dB Attenuation at 27MHz ♦ 1.7mW Low-Power Mode Consumption ♦ 0.1mW Shutdown Consumption ♦ Clickless/Popless, DirectDrive Audio ♦ Video Input Detection ♦ Video Load Detection ♦ 3.3V and 12V Supply Voltages Applications Set-Top Boxes TVs DVD Players Ordering Information PART TEMP RANGE PIN-PACKAGE MAX9598CTL+ 0°C to +70°C 40 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. DirectDrive is a registered trademark of Maxim Integrated Products, Inc. System Block Diagram VVID V12 3.3V 12V STB CHIP MAX9598 I2C μC INTERRUPT OUTPUT VAUD 3.3V RGB, Y/C, CVBS I2C INTERFACE AND REGISTERS CVBS L/R AUDIO VIDEO ENCODER STEREO AUDIO DAC RGB, Y/C, CVBS SINGLE-ENDED STEREO AUDIO VIDEO FILTERS AND CROSSPOINT AUDIO CROSSPOINT WITH DirectDrive OUTPUTS SLOW SWITCHING FAST SWITCHING TV SCART SLOW SWITCHING FAST SWITCHING Y/C, CVBS RGB, Y/C, CVBS L/R AUDIO VCR SCART SLOW SWITCHING FAST SWITCHING CHARGE PUMP EP GNDVID ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9598 General Description MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors ABSOLUTE MAXIMUM RATINGS VVID to GNDVID .......................................…………-0.3V to +4V V12 to EP .................................................…………-0.3V to +14V VAUD to EP ................................................…………-0.3V to +4V EP to GNDVID .........................................…………-0.1V to +0.1V All Video Inputs, VCRIN_FS to GNDVID ....…………-0.3V to +4V All Audio Inputs to EP...........................…………-1V to (EP + 1V) SDA, SCL, DEV_ADDR, INT to GNDVID ………… ...-0.3V to +4V TV_SS, VCR_SS to EP ..................…………-0.3V to (V12 + 0.3V) Current All Video/Audio Inputs....................................…………±20mA C1P, C1N, CPVSS ..........................................…………±50mA Output Short-Circuit Current Duration All Video Outputs, TVOUT_FS to VVID, GNDVID ...Continuous Audio Outputs to VAUD, EP ...................................Continuous TV_SS, VCR_SS to V12, EP ....................................Continuous Continuous Power Dissipation (TA = +70°C) 40-Pin Thin QFN (derate 26.3mW/°C above +70°C) ..........................2105.3mW Operating Temperature Range ..............................0°C to +70°C Junction Temperature .....................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0°C to +70°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Video Supply Voltage Range VVID Inferred from video PSRR test at 3V and 3.6V 3 3.3 3.6 V Audio Supply Voltage Range VAUD Inferred from audio PSRR test at 3V and 3.6V 3 3.3 3.6 V 11.4 12 12.6 V Normal operation (Note 2), with all video outputs enabled and muted 18.2 30 mA Low-power mode 500 1000 Shutdown 18.4 32 Normal operation (Note 2) 2.7 6 mA Shutdown 12 25 µA 3 100 V12 Supply Voltage Range VVID Quiescent Supply Current VAUD Quiescent Supply Current V12 IVID_Q IAUD_Q Inferred from slow-switching levels POR state V12 Quiescent Supply Current I12_Q Normal operation (Note 2) Slow-switching output sets to medium level 475 Shutdown 0.25 µA µA 10 VIDEO CHARACTERISTICS DC-COUPLED INPUT Input Voltage Range VIN Input Current IIN Input Resistance RIN RL = 75Ω to GNDVID or 150Ω to VVID/2, inferred from gain test VVID = 3V 1.15 VVID = 3.135V 1.2 VVID = 3.3V VP-P 1.3 VIN = 0.3V 1 5 300 µA kΩ AC-COUPLED INPUT Sync-Tip Clamp Level Sync Crush 2 VCLP Sync-tip clamp -13 -3.5 Sync-tip clamp, percentage reduction in sync pulse (0.3VP-P), guaranteed by input clamping current measurement _______________________________________________________________________________________ +6 mV 2 % Low-Power Audio/Video Switch for Dual SCART Connectors (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0°C to +70°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Input Clamping Current CONDITIONS MIN Sync-tip clamp, VIN = 0.3V Maximum Input Source Resistance Bias Voltage VBIAS Bias circuit 0.57 Bias circuit Av UNITS 1 2 µA Ω Output Level Guaranteed by output-voltage swing 1.95 2 -2 0.63 2.05 V/V +2 % 0.19 0.30 0.40 Bias circuit 1.35 1.50 1.62 Measured at output, VVID = 3.135V, VIN = VCLP to (VCLP +1.2V), RL = 150Ω to VVID/2, RL = 75Ω to GNDVID 2.34 Output disabled (load detection not active) 3V ≤ VVID ≤ 3.6V 2.46 2.3 2.34 ROUT Power-Supply Rejection Ratio 2.40 VP-P Output Short-Circuit Current Output Leakage Current V 2.3 Bias circuit, measured at output, VVID = 3V, VIN = (VBIAS - 0.575V) to (VBIAS + 0.575V), RL = 150Ω to VVID/2, RL = 75Ω to GNDVID Measured at output, VVID = 3.135V, VIN = (VBIAS - 0.6V) to (VBIAS + 0.6V), RL = 150Ω to VVID/2, RL = 75Ω to GNDVID V kΩ Sync-tip clamp (VIN = VCLP) Sync-tip clamp, measured at output, VVID = 3V, VIN = VCLP to (VCLP +1.15V), RL = 150Ω to VVID/2, RL = 75Ω to GNDVID Output-Voltage Swing 0.60 10 Guaranteed by output-voltage swing of TV_R/C_OUT, TV_G_OUT, and TV_B_OUT; first input signal set is VCR_R/C_IN, VCR_G_IN, and VCR_B_IN; second signal set is ENC_R/C_IN, ENC_G_IN, and ENC_B_IN DC Gain Mismatch Between R, G, and B Outputs Output Resistance MAX 300 Input Resistance DC CHARACTERISTICS DC Voltage Gain TYP 2.40 2.46 100 mA 0.5 Ω 10 50 µA dB AC CHARACTERISTICS Filter Passband Flatness VOUT = 2VP-P, f = 100kHz to 10MHz -1 f = 11MHz 3 f = 27MHz 52 dB Filter Attenuation VOUT = 2VP-P, attenuation is referred to 100kHz f = 54MHz 55 Slew Rate VOUT = 2VP-P, no filter in video path 60 V/µs ns Settling Time dB VOUT = 2VP-P, settle to 0.1% (Note 3) 400 Differential Gain DG 5-step modulated staircase, f = 4.43MHz 0.15 % Differential Phase DP 5-step modulated staircase, f = 4.43MHz 0.6 Degrees 2T = 200ns, bar time is 18µs; the beginning 2.5% and the ending 2.5% of the bar time are ignored 0.3 K% 2T Pulse-to-Bar K Rating _______________________________________________________________________________________ 3 MAX9598 ELECTRICAL CHARACTERISTICS (continued) MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors ELECTRICAL CHARACTERISTICS (continued) (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0°C to +70°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2T Pulse Response 2T = 200ns 0.2 K% 2T Bar Response 2T = 200ns, bar time is 18µs; the beginning 2.5% and the ending 2.5% of the bar time are ignored 0.2 K% Nonlinearity 5-step staircase 0.1 % Group Delay Distortion 100kHz ≤ f ≤ 5MHz, outputs are 2VP-P 11 ns Glitch Impulse Caused by Charge-Pump Switching Measured at outputs 100 pVs Peak Signal-to-RMS Noise 100kHz ≤ f ≤ 5MHz 70 dB Power-Supply Rejection Ratio f = 100kHz, 100mVP-P 42 dB Output Impedance f = 5MHz 2 Ω Video Crosstalk f = 4.43MHz -46 dB Reverse Isolation VCR SCART inputs to encoder inputs, fullpower mode with VCR being looped through to TV, f = 4.43MHz 92 dB Pulldown Resistance Enable VCR_R/C_OUT pulldown through I2C interface 4.6 7.5 Ω 4 4.05 V/V AUDIO CHARACTERISTICS Voltage Gain VIN = -0.707V to +0.707V 3.95 Gain Mismatch VIN = -0.707V to +0.707V -1.5 Flatness f = 20Hz to 20kHz, 0.25VRMS input Frequency Bandwidth Capacitive Drive +1.5 % 0.006 dB 0.25VRMS input, frequency where output is -3dB referenced to 1kHz 230 kHz No sustained oscillations, 75Ω series resistor on output 300 pF Input Resistance VIN = -0.707V to +0.707V 10 Input Bias Current VIN = 0V Input Signal Amplitude f = 1kHz, THD < 1% 0.5 Output DC Level No input signal, VIN grounded Signal-to-Noise Ratio f = 1kHz, 0.25VRMS input, 20Hz to 20kHz Total Harmonic Distortion Plus Noise RL = 3.33kΩ, f = 1kHz, 0.25VRMS input 0.0014 RL = 3.33kΩ, f = 1kHz, 0.5VRMS input 0.001 Output Impedance f = 1kHz Power-Supply Rejection Ratio DC MΩ 500 -3 +3 97 0.4 75 100 nA VRMS mV dB % Ω dB f = 1kHz 90 Mute Suppression f = 1kHz, 0.25VRMS input 110 dB Audio Crosstalk f = 1kHz, 0.25VRMS input 92 dB 4 _______________________________________________________________________________________ Low-Power Audio/Video Switch for Dual SCART Connectors (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0°C to +70°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VIDEO-TO-AUDIO INTERACTION Video input: f = 15kHz, 1VP-P signal, Audio input: f = 15kHz, 0.5VRMS signal Crosstalk 92 dB 580 kHz CHARGE PUMP Switching Frequency FAST SWITCHING Input Low Input High Level 0.4 V 10 µA 0.1 V 1 V Input Current Output Low Voltage IOL = 0.5mA Output High Voltage IOH = 0.5mA VVID - 0.1 Output Resistance V 7 Ω Rise Time 143Ω to GNDVID 12 ns Fall Time 143Ω to GNDVID 10 ns SLOW SWITCHING Input Low Voltage Input Medium Voltage 4.5 Input High Voltage 9.5 70 10kΩ to EP, 11.4V ≤ V12 ≤ 12.6V Output Medium Voltage 10kΩ to EP, 11.4V ≤ V12 ≤ 12.6V 5 Output High Voltage 10kΩ to EP, 11.4V ≤ V12 ≤ 12.6V 10 V 7 V V Input Current Output Low Voltage 2 100 µA 1.5 V 6.5 V V DIGITAL INTERFACE Input High Voltage VIH Input Low Voltage 0.7 x VVID V VIL Input Hysteresis VHYS Input Leakage Current IIH, IIL 0.3 x VVID 0.06 x VVID -1 Input Capacitance +1 6 0.1VVID < SDA < 3.3V, 0.1VVID < SCL < 3.3V, I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V+ is switched off Input Current -10 µA pF +10 µA 0.4 V 400 kHz Output Low Voltage SDA VOL Serial Clock Frequency fSCL 0 Bus Free Time Between a STOP and a START Condition tBUF 1.3 µs tHD, STA 0.6 µs Hold Time, (Repeated) START Condition ISINK = 6mA V V _______________________________________________________________________________________ 5 MAX9598 ELECTRICAL CHARACTERISTICS (continued) MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors ELECTRICAL CHARACTERISTICS (continued) (V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0°C to +70°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Low Period of the SCL Clock tLOW 1.3 µs High Period of the SCL Clock tHIGH 0.6 µs Setup Time for a Repeated START Condition tSU, STA 0.6 µs Data Hold Time tHD, DAT Data Setup Time tHD, DAT Fall Time of SDA Transmitting Setup Time for STOP Condition Pulse Width of Spike Suppressed tF (Note 4) 0.9 100 ISINK ≤ 6mA, CB = total capacitance of one bus line in pF, tR and tF measured between 0.3VVID and 0.7VVID, CB ≤ 400pF tSU, STO tSP 0 ns 100 ns 0.6 Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns µs µs 0 50 ns OTHER DIGITAL I/O DEV_ADDR Low Level 0.3 x VVID DEV_ADDR High Level 0.7 x VVID DEV_ADDR Input Current -1 V V +1 µA Interrupt Output Low Voltage IOL = 0.5mA 0.1 V Interrupt Output Leakage Current INT high impedance 10 µA Note 1: Note 2: Note 3: Note 4: 6 All devices are 100% production tested at TA = +25°C. Specifications over temperature limits are guaranteed by design. Normal operation mode is the POR state. The settling time is measured from the 50% of the input swing to the 0.1% of the final value of the output. A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. _______________________________________________________________________________________ Low-Power Audio/Video Switch for Dual SCART Connectors 0 -20 FILTER -30 -40 -50 1M 10M -40 -2.5 -50 -60 VOUT = 100mVP-P 100M 100k VOUT = 2VP-P -70 1M 10M 1M 100k 100M 10M FREQUENCY (Hz) VIDEO LARGE-SIGNAL GAIN FLATNESS vs. FREQUENCY VIDEO CROSSTALK vs. FREQUENCY GROUP DELAY vs. FREQUENCY -1.5 -2.0 -2.5 -3.0 MAX9598 toc06 100 -20 GROUP DELAY (ns) NO FILTER -1.0 100M 120 MAX9598 toc05 -10 VIDEO CROSSTALK (dB) -0.5 0 MAX9598 toc04 FILTER 0 -30 -40 -50 NO FILTER 80 60 40 -60 20 FILTER -70 VOUT = 2VP-P -4.0 -80 100k 1M 10M 100M 0 100k 1M 10M 100M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (Hz) VVID POWER-SUPPLY REJECTION RATIO vs. FREQUENCY VIDEO VOLTAGE GAIN vs. TEMPERATURE VIDEO OUTPUT VOLTAGE vs. INPUT VOLTAGE -15 -20 -25 -30 -35 2.02 2.01 2.00 1.99 1.98 -40 1.97 -45 1.96 -50 1 10 FREQUENCY (MHz) 100 3.0 2.5 2.0 1.5 1.0 0.5 0 1.95 0.1 3.5 OUTPUT VOLTAGE (V) 2.03 VOLTAGE GAIN (V/V) -10 VIN = 1VP-P, 100kHz 2.04 MAX9598 toc09 2.05 MAX9598 toc07 VVID = 3.3V + 100mVP-P MAX9598 toc08 GAIN FLATNESS (dB) -2.0 FILTER -30 FREQUENCY (Hz) 0.5 VVID PSRR (dB) -1.5 -20 FREQUENCY (Hz) 1.0 0 -1.0 -4.0 100k -5 NO FILTER -3.5 VOUT = 100mVP-P -70 -3.5 -10 -0.5 -3.0 -60 NO FILTER 0 GAIN (dB) GAIN FLATNESS (dB) GAIN (dB) -10 FILTER 0.5 10 MAX9598 toc02 NO FILTER 1.0 MAX9598 toc01 10 0 VIDEO LARGE-SIGNAL GAIN vs. FREQUENCY VIDEO SMALL-SIGNAL GAIN FLATNESS vs. FREQUENCY MAX9598 toc03 VIDEO SMALL-SIGNAL GAIN vs. FREQUENCY 0 20 40 TEMPERATURE (°C) 60 80 0 0.5 1.0 1.5 2.0 INPUT VOLTAGE (V) _______________________________________________________________________________________ 7 MAX9598 Typical Operating Characteristics (VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150Ω to GNDVID, audio load is 10kΩ to EP, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150Ω to GNDVID, audio load is 10kΩ to EP, TA = +25°C, unless otherwise noted.) DIFFERENTIAL GAIN AND PHASE 0 -0.1 f = 4.43MHz, NO FILTER -0.2 1 2 3 0.8 0.6 0.4 0.2 0 -0.2 -0.4 4 5 6 1 2 3 4 5 6 0.1 7 MAX9598 toc12 0 INPUT 200mV/div -0.1 f = 4.43MHz, FILTER -0.2 1 7 f = 4.43MHz, NO FILTER 2T RESPONSE 0.2 MAX9598 toc11 0.1 DIFFERENTIAL GAIN (%) MAX9598 toc10 0.2 DIFFERENTIAL PHASE (deg) DIFFERENTIAL PHASE (deg) DIFFERENTIAL GAIN (%) DIFFERENTIAL GAIN AND PHASE 2 3 4 0.8 0.6 0.4 0.2 0 -0.2 -0.4 5 6 7 OUTPUT 400mV/div f = 4.43MHz, FILTER 1 2 3 4 5 6 7 100ns/div FIELD SQUARE-WAVE RESPONSE NTC-7 VIDEO TEST SIGNAL 12.5T RESPONSE MAX9598 toc15 MAX9598 toc14 MAX9598 toc13 INPUT 0.5V/div INPUT 200mV/div INPUT 500mV/div OUTPUT 1V/div OUTPUT 400mV/div 10μs/div 2ms/div SYNC TIP CLAMP VOLTAGE vs. TEMPERATURE BIAS VOLTAGE vs. TEMPERATURE INPUT SYNC-TIP CLAMP CURRENT vs. TEMPERATURE 0.6 0.5 0.4 0.3 630 620 610 600 590 580 0.2 570 0.1 560 0 20 40 TEMPERATURE (°C) 60 80 VIN = 0.3V 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 550 0 1.4 MAX9598 toc18 640 BIAS VOLTAGE (mV) 0.7 MAX9598 toc17 0.8 650 INPUT SYNC-TIP CLAMP CURRENT (μA) 660 MAX9598 toc16 0.9 8 OUTPUT 1V/div 400ns/div 1.0 SYNC TIP CLAMP VOLTAGE (mV) MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors 0 20 40 TEMPERATURE (°C) 60 80 0 25 50 TEMPERATURE (°C) _______________________________________________________________________________________ 75 Low-Power Audio/Video Switch for Dual SCART Connectors INPUT CLAMP CURRENT vs. INPUT VOLTAGE 5 4 3 2 1 330 4 320 310 300 290 3 2 280 1 270 260 0 VIN = 0.25VRMS 0 250 0.5 1.0 1.5 2.0 2.5 3.5 0 20 40 60 10 80 100 1k 10k 100k 1M TEMPERATURE (°C) FREQUENCY (Hz) AUDIO CROSSTALK vs. FREQUENCY AUDIO TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY VAUD POWER-SUPPLY REJECTION RATIO vs. FREQUENCY 1 MAX9598 toc22 0 VIN = 0.25VRMS RL = 10kΩ TO GNDAUD -20 3.0 INPUT VOLTAGE (V) 0 MAX9598 toc24 0 VAUD = 3.3V + 100mVP-P -20 0.1 -60 VAUD PSRR (dB) THD+N (%) -40 VIN = 250mVRMS RL = 10kΩ 0.01 -80 -40 -60 -80 0.001 -100 -100 VIN = 500mVRMS RL = 10kΩ 0.0001 -120 100 1k 10k 10 100k 100 -120 1k 10k 100 1k 10k FREQUENCY (Hz) FREQUENCY (Hz) VVID SUPPLY CURRENT vs. TEMPERATURE VAUD SUPPLY CURRENT vs. TEMPERATURE V12 SUPPLY CURRENT vs. TEMPERATURE 30 25 20 15 10 5 4 3 2 0 0 20 40 TEMPERATURE (°C) 60 80 800 600 400 200 1 5 1000 100k MAX9598 toc27 6 V12 SUPPLY CURRENT (nA) 35 MAX9598 toc26 MAX9598 toc25 40 0 10 100k FREQUENCY (Hz) VAUD SUPPLY CURRENT (mA) 10 VVID SUPPLY CURRENT (mA) MAX9598 toc21 5 MAX9598 toc20 340 GAIN (V/V) 6 350 MAX9598 toc23 INPUT CLAMP CURRENT (μA) 7 OUTPUT LEVEL VOLTAGE (mV) MAX9598 toc19 8 AUDIO CROSSTALK (dB) AUDIO LARGE-SIGNAL FREQUENCY RESPONSE vs. GAIN OUTPUT LEVEL VOLTAGE vs. TEMPERATURE 0 0 20 40 TEMPERATURE (°C) 60 80 0 20 40 60 80 TEMPERATURE (°C) _______________________________________________________________________________________ 9 MAX9598 Typical Operating Characteristics (continued) (VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150Ω to GNDVID, audio load is 10kΩ to EP, TA = +25°C, unless otherwise noted.) MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors Pin Description PIN 10 NAME FUNCTION 1 SDA Bidirectional, I2C Data I/O. Output is open drain and tolerates up to 3.6V. 2 SCL I2C Clock Input 3 DEV_ADDR 4 INT 5 VAUD 6 C1P Charge-Pump Flying Capacitor Positive Terminal. Connect a 1µF capacitor from C1P to C1N. 7 C1N Charge-Pump Flying Capacitor Negative Terminal. Connect a 1µF capacitor from C1P to C1N. 8 CPVSS 9 ENC_INL Encoder Left-Channel Audio Input 10 ENC_INR Encoder Right-Channel Audio Input 11 VCR_INL VCR SCART Left-Channel Audio Input Device Address Set Input. Connect DEV_ADDR to GNDVID, VVID, SDA or SCL. See Table 3. Interrupt Output. This is an open-drain output that pulls down to GNDVID to indicate a change in the VCR slow-switching input, the activity status of the composite video inputs, or the load status of the composite video outputs. Audio Supply. Connect to a 3.3V supply. Bypass with a 10µF aluminum electrolytic capacitor in parallel with a 0.1µF ceramic capacitor to EP. Charge-Pump Negative Power Supply. Bypass CPVSS with a 1µF ceramic capacitor to EP. 12 VCR_INR VCR SCART Right-Channel Audio Input 13 TV_OUTL TV SCART Left-Channel Audio Output 14 VCR_OUTL VCR SCART Left-Channel Audio Output 15 VCR_OUTR VCR SCART Right-Channel Audio Output 16 TV_OUTR 17 TV_SS 18 V12 19 VCR_SS 20 TVOUT_FS TV SCART Fast-Switching Logic Output 21 VCRIN_FS VCR SCART Fast-Switching Input 22 ENC_B_IN Encoder Blue Video Input 23 ENC_G_IN Encoder Green Video Input 24 VCR_B_IN VCR SCART Blue Video Input 25 VCR_G_IN VCR SCART Green Video Input 26 TV_B_OUT TV SCART Blue Video Output 27 TV_G_OUT TV SCART Green Video Output 28 GNDVID 29 VCR_R/C_IN 30 VVID TV SCART Right-Channel Audio Output TV SCART Bidirectional Slow-Switch Signal +12V Supply. Bypass V12 with a 0.1µF capacitor to EP. VCR SCART Bidirectional Slow-Switch Signal Video Ground VCR SCART Red/Chroma Video Input Video and Digital Supply. Connect to a +3.3V supply. Bypass with a parallel 1µF and 0.1µF ceramic capacitor to GNDVID. VVID also serves as a digital supply for the I2C interface. ______________________________________________________________________________________ Low-Power Audio/Video Switch for Dual SCART Connectors PIN NAME 31 ENC_C_IN 32 ENC_R/C_IN Encoder Red/Chroma Video Input 33 TV_R/C_OUT TV SCART Red/Chroma Video Output 34 VCR_R/C_OUT 35 FUNCTION Encoder Chroma Video Input VCR SCART Red/Chroma Video Output VCR_Y/CVBS_OUT VCR SCART Luma/Composite Video Output 36 TV_Y/CVBS_OUT TV SCART Luma/Composite Video Output 37 VCR_Y/CVBS_IN VCR SCART Luma/Composite Video Input 38 TV_Y/CVBS_IN 39 ENC_Y_IN 40 ENC_Y/CVBS_IN EP EP TV SCART Luma/Composite Video Input Encoder Luma Video Input Encoder Luma/Composite Video Input Exposed Pad. The exposed pad is the internal ground for the audio amplifiers and charge pump. A low-impedance connection between ground and EP is required for proper isolation. Detailed Description The MAX9598 represents Maxim’s third generation of SCART1 audio/video (A/V) switches. Under I2C control, these devices route audio, video, and control information between the set-top box decoder chip and two SCART connectors. The audio signals are left audio and right audio. The video signals are composite video with blanking and sync (CVBS) and component video (red, green, blue). S-video (Y/C) can be transported across the SCART interface if CVBS is reassigned to luma (Y) and red is reassigned to chroma (C). Support for S-video is optional. The slow-switch signal and the fast-switch signal carry control information. The slowswitch signal is a 12V, trilevel signal that indicates whether the picture aspect ratio is 4:3 or 16:9 or causes the television to use an internal A/V source such as an antenna. The fast-switch signal indicates whether the television should display CVBS or RGB signals. CVBS, left audio, and right audio are full duplex. All the other signals are half duplex. Therefore, one device on the link must be designated as the transmitter and the other device must be designated as the receiver. The low-power consumption and the advanced monitoring functions of the MAX9598 enable the creation of lower power set-top boxes, televisions, and DVD players. Unlike competing SCART ICs, the audio and video circuits of the MAX9598 operate entirely from 3.3V rather than from 5V and 12V. Only the slow-switch circuit of the MAX9598 requires a 12V supply. The MAX9598 also has circuits that detect activity on the CVBS inputs, loads on the CVBS outputs, and the level of the slow-switch signals. The INT signal informs the µC if there are any changes so that the µC can intelligently decide whether to power up or power down the equipment. In addition, the MAX9598 has DirectDrive audio circuitry to eliminate click-and-pop noise. With DirectDrive, the DC bias of the audio line outputs is always at ground, no matter whether the MAX9598 is being powered up or powered down. Conventional audio line output drivers that operate from a single supply require series AC-coupling capacitors. During power-up, the DC bias on the AC-coupling capacitor moves from ground to a positive voltage, and during power-down, the opposite occurs. The changing DC bias usually causes an audible transient. 1SCART (from Syndicat des Constructeurs d’Appareils Radiorécepteurs et Téléviseurs) is a French-originated standard and associated 21-pin connector for connecting audio-visual equipment together. The official standard for SCART is CENELEC document number EN 50049-1. From Wikipedia. ______________________________________________________________________________________ 11 MAX9598 Pin Description (continued) MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors Audio Section The integrated charge pump inverts the +3.3V supply to create a -3.3V supply. The audio circuit operates from bipolar supplies so the audio signal is always biased to ground. The audio circuit is essentially a stereo, 2x2, nonblocking, audio crosspoint with output drivers. The encoder (stereo audio DAC) and the VCR are the two input sources, and the two outputs go to the TV SCART connector and the VCR SCART connector. See Figure 1. MAX9598 ZERO-CROSS DETECTOR VAUD EP AV = 4V/V ENC_INL TV_OUTL VCR_INL VAUD EP AV = 4V/V ZERO-CROSS DETECTOR VCR_OUTL VAUD EP AV = 4V/V ENC_INR TV_OUTR VCR_INR VAUD EP AV = 4V/V VAUD C1P C1N CPVSS VCR_OUTR CHARGE PUMP Figure 1. MAX9598 Audio Section Functional Diagram 12 ______________________________________________________________________________________ Low-Power Audio/Video Switch for Dual SCART Connectors Audio Outputs The MAX9598 audio output amplifiers feature Maxim’s patented DirectDrive architecture, thereby eliminating the need for output-coupling capacitors required by conventional single-supply audio line drivers. An internal charge pump inverts the positive supply (VAUD), creating a negative supply (CPVSS). The audio output amplifiers operate from these bipolar supplies with their outputs biased about audio ground (Figure 2). The benefit of this audio ground bias is that the amplifier outputs do not have a DC component. The DC-blocking capacitors required with conventional audio line drivers are unnecessary, conserving board space, reducing system cost, and improving frequency response. Conventional single-supply audio line drivers have their outputs biased about a nominal DC voltage (typically half the supply) for maximum dynamic range. Large coupling capacitors are needed to block this DC bias. Clicks and pops are created when the coupling capacitors are charged during power-up and discharged during power-down. The MAX9598 features a low-noise charge pump that requires only two small ceramic capacitors. The 580kHz switching frequency is well beyond the audio range and does not interfere with audio signals. The switch drivers feature a controlled switching speed that minimizes noise on the video outputs generated by turn-on and turn-off transients. MAX9598 Clickless Switching The TV audio channel incorporates a zero-crossing detect (ZCD) circuit that minimizes click noise due to abrupt signal level changes that occur when switching between audio signals at an arbitrary moment. To implement the zero-crossing function when switching audio signals, set the ZCD bit high (Audio Control Register 00h, bit 6). Then set the mute bit high (Audio Control Register, 00h, bit 0). Next, wait for a sufficient period of time for the audio signal to cross zero. This period is a function of the audio signal path’s low-frequency 3dB corner (fL3dB). Thus, if fL3dB = 20Hz, the time period to wait for a zero-crossing detect is 1/20Hz or 50ms. After the wait period, select a new audio source for the TV audio channel by writing to bits 1 and 0 of the TV Audio Control Register (01h). Finally, clear mute (Audio Control Register, 00h, bit 0) but leave ZCD (Audio Control Register, 00h, bit 6) high. The MAX9598 switches the signal out of mute at the next zero crossing. See Tables 10 and 11. VDD VOUT VDD/2 GND CONVENTIONAL DRIVER-BIASING SCHEME +VDD VOUT GND -VDD DirectDrive BIASING SCHEME Figure 2. Conventional Driver Output Waveform vs. MAX9598 Output Waveform The SCART standard specifies 2VRMS as the full-scale for audio signals. As the audio circuits process 0.5V RMS full-scale audio signals internal to the MAX9598, the gain-of-4 output amplifiers restore the audio signals to a full scale of 2VRMS. To select which audio input source is routed to the TV SCART connector, write to bits 1 and 0 of the TV Audio Control Register (01h). To select which audio input source is routed to the VCR SCART connector, write to bits 3 and 2 of the TV Audio Control Register (01h). The power-on default is for the TV and VCR audio outputs to be muted (the inputs of the output amplifiers are connected to audio ground). See Tables 8 and 11. Video Section The video circuit routes different video formats between the set-top box decoder, the TV SCART connector, and the VCR SCART connector. It also routes slow-switch and fast-switch control information. See Figure 3. ______________________________________________________________________________________ 13 MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors ACTIVITY DETECT ACTIVITY DETECT MAX9598 ACTIVITY DETECT ACTIVITY DETECT TV_Y/CVBS_IN CLAMP VCR_Y/CVBS_IN CLAMP ENC_Y/CVBS_IN CLAMP ENC_Y_IN CLAMP LOAD SENSE TV_Y/CVBS_OUT AV = 2V/V LPF LPF MUTE LOAD SENSE VCR_R/C_IN CLAMP/BIAS ENC_R/C_IN CLAMP/BIAS LPF ENC_C_IN CLAMP/BIAS LPF AV = 2V/V VCR_Y/CVBS_OUT AV = 2V/V TV_R/C_OUT AV = 2V/V VCR_R/C_OUT AV = 2V/V TV_G_OUT AV = 2V/V TV_B_OUT AV = 1V/V TVOUT_FS AV = 1V/V TV_SS AV = 1V/V VCR_SS MUTE VCR_G_IN CLAMP ENC_G_IN CLAMP LPF MUTE VCR_B_IN CLAMP ENC_B_IN CLAMP LPF MUTE VVID GNDVID VCRIN_FS 0.7V V12 +6V EP TO I2C x1 V12 +6V EP TO I2C x1 Figure 3. MAX9598 Video Section Functional Diagram 14 ______________________________________________________________________________________ Low-Power Audio/Video Switch for Dual SCART Connectors The MAX9598 restores the DC level of incoming, ACcoupled video signals with either transparent sync-tip clamps or bias circuits. When using an AC-coupled input, the transparent sync-tip clamp automatically clamps the input signal minimum to ground, preventing it from going lower. A small current of 1µA pulls down on the input to prevent an AC-coupled signal from drifting outside the input range of the part. Use sync-tip clamps with CVBS, RGB, and luma signals. The transparent sync-tip clamp is “transparent” when the incoming video signal is DC-coupled and at or above ground. Under such conditions, the clamp never activates. Therefore, the outputs of video DACs that typically generate signals between 0 and 1V can be directly connected to the MAX9598 inputs. The bias circuit accepts AC-coupled chroma, which is a subcarrier with the color information modulated onto it. The bias voltage of the bias circuits is 600mV. ENC_R/C_IN and VCR_R/C_IN can receive either a red video signal or a chroma video signal. Set the input configuration by writing to bits 7 and 3 of the VCR Video Input Control Register (08h). See Tables 8 and 14. The MAX9598 also has video input detection. When activated, activity detect circuits check if sync is present on incoming CVBS signals. If so, then there is a valid video signal. Read bits 0, 2, 4, and 5 of the Video Activity Status Register (0Fh) to determine the status of the CVBS inputs. See Table 19. Video Reconstruction Filter The video DAC outputs of the set-top box decoder chip need to be lowpass-filtered to reject the out-of-band noise. The MAX9598 integrates 6th-order, Butterworth filters. The filter passband (±1dB) is typically 10MHz, and the attenuation at 27MHz is 52dB. The filters are suited for standard-definition video. Video Outputs The video output amplifiers can both source and sink load current, allowing output loads to be DC- or AC-coupled. The amplifier output stage needs around 300mV of headroom from either supply rail. For video signals with a sync pulse, the sync tip will typically be at 300mV, as shown in Figure 4. For a chroma signal, the blank level will typically be at 1.5V, as shown in Figure 5. Table 1. Recommended Coupling for Incoming Video Signals and Input Circuit Configuration. (Use a 0.1µF Capacitor to AC-Couple a Video Signal into the MAX9598) VIDEO ORIGIN FORMAT VOLTAGE RANGE (V) COUPLING INPUT CIRCUIT CONFIGURATION External CVBS Unknown AC Transparent Sync Tip Clamp External RGB Unknown AC Transparent Sync Tip Clamp External Y Unknown AC Transparent Sync Tip Clamp External C Unknown AC Bias Circuit Internal CVBS 0 to 1 DC Transparent Sync Tip Clamp Internal R, G, B 0 to 1 DC Transparent Sync Tip Clamp Internal Y, C 0 to 1 DC Transparent Sync Tip Clamp Internal Y, Pb, Pr 0 to 1 DC Transparent Sync Tip Clamp Internal CVBS 2.3 to 3.3 AC Transparent Sync Tip Clamp Internal R, G, B 2.3 to 3.3 AC Transparent Sync Tip Clamp Internal Y 2.3 to 3.3 AC Transparent Sync Tip Clamp Internal C 2.3 to 3.3 AC Bias Circuit ______________________________________________________________________________________ 15 MAX9598 Video Inputs Whether the incoming video signal is AC-coupled or DC-coupled into the MAX9598 depends upon the origin, format, and voltage range of the video signal. Table 1 below shows the recommended connections. Always AC-couple an external video signal through a 0.1µF capacitor because its voltage is not well defined (see the Typical Application Circuit). For example, the video transmitter circuit might have a different ground than the video receiver, thereby level shifting the DC bias. The 60Hz power line “hum” might cause the video signal to slowly change DC bias. Internal video signals that are between 0 and 1V can be DC-coupled. Most video DACs generate video signals between 0 and 1V because the video DAC sources current into a ground-referenced resistor. For the minority of video DACs that generate video signals between 2.3V and 3.3V because the video DAC sinks current from a VVID-referenced resistor, AC-couple the video signal to the MAX9598. MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598 fig04 MAX9598 fig05 500mV/div 500mV/div 0V 0V 10μs/div 20μs/div Figure 4. MAX9598 Video Output with CVBS Signal (Multiburst Video Test Signal Shown) Figure 5. MAX9598 Video Output with Chroma (C) Signal (75% Color Bar Video Test Signal Shown) If the supply voltage is greater than 3.135V (5% below a 3.3V supply), each amplifier can drive two DC-coupled video loads to ground. If the supply is less than 3.135V, each amplifier can drive only one DC-coupled or AC-coupled video load. Slow Switching The MAX9598 supports the IEC 933-1, Amendment 1, trilevel slow switching that selects the aspect ratio for the display (TV). Under I2C control, the MAX9598 sets the slow-switching output voltage level. Table 2 shows the valid input levels of the slow-switching signal and the corresponding operating modes of the display device. The SCART standard allows for video signals to have a superimposed DC component within 0 to 2V. Therefore, most video signals are DC-coupled at the output. In the unlikely event that the video signal needs to be ACcoupled, the coupling capacitors should be 220µF or greater in order to keep the highpass filter formed by the 37.5Ω equivalent resistance of the video transmission line to a corner frequency of 4.8Hz or below in order to keep it well below the 25Hz frame rate of the PAL standard. The CVBS outputs have load sense circuits. If enabled, each load sense circuit checks for a load eight times per second by connecting an internal 15kΩ pullup resistor to the output for 1ms. If the output is pulled up, then no load is present. If the output stays low, then a load is connected. Read bits 1 and 3 to determine load status. See Table 19. The selection of video sources that are sent to the TV SCART connector are controlled by bits 0 to 4 of the TV Video Input Control Register (06h) while the selection of video sources that are sent to the VCR SCART connector are controlled by bits 0 to 2 of the VCR Video Input Control Register (08h). See Tables 8, 12, and 14. The video outputs can be enabled or disabled by bits 2 to 7 of the Output Enable Register (0Dh). See Table 16. 16 Two bidirectional ports are available for slow-switching signals for the TV and VCR. The slow-switching input status is continuously read and stored in the Status Register (0Eh). The slow-switching outputs can be set to a logic level or high impedance by writing to the TV Video Output Control Register (07h) and the VCR Video Output Control Register (09h). When enabled, INT becomes active low if the voltage level changes on TV_SS or VCR_SS. See Tables 8, 13, 15 and 18. Table 2. Slow-Switching Modes SLOW-SWITCHING SIGNAL VOLTAGE (V) 0 to 2 MODE Display device uses an internal source such as a built-in tuner to provide a video signal 4.5 to 7.0 Display device uses a video signal from the SCART connector and sets the display to 16:9 aspect ratio 9.5 to 12.6 Display device uses a signal from the SCART connector and sets the display to 4:3 aspect ratio ______________________________________________________________________________________ Low-Power Audio/Video Switch for Dual SCART Connectors I2C Serial Interface The MAX9598 features an I2C/SMBus™-compatible, 2wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the MAX9598 and the master at clock rates up to 400kHz. Figure 6 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. A master device writes data to the MAX9598 by transmitting a START (S) condition, the proper slave address with the R/W bit set to 0, followed by the register address and then the data word. Each transmit sequence is framed by a START (S) and a STOP (P) condition. Each word transmitted to the MAX9598 is 8 bits long and is followed by an acknowl- edge clock pulse. A master reads from the MAX9598 by transmitting the slave address with the R/W bit set to 0, the register address of the register to be read, a REPEATED START (Sr) condition, the slave address with the R/W bit set to 1, followed by a series of SCL pulses. The MAX9598 transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START (S) or REPEATED START (Sr) condition, an acknowledge or a not acknowledge, and a STOP (P) condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500Ω, is required on the SDA bus. SCL operates as only an input. A pullup resistor, typically greater than 500Ω, is required on SCL if there are multiple masters on the bus, or if the master in a singlemaster system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9598 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy. SDA tSU, STA tSU, DAT tHD, DAT tLOW tBUF tSU, STA tSP tSU, STO SCL tHIGH tHD, STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 6. I2C Serial-Interface Timing Diagram SMBus is a trademark of Intel Corporation. ______________________________________________________________________________________ 17 MAX9598 Fast Switching The fast-switching signal was originally used to switch between CVBS and RGB signals on a pixel-by-pixel basis so that on-screen display (OSD) information could be inserted. Since modern set-top box decoder chips have integrated OSD circuitry, there is no need to create OSD information using the older technique. Now, the fast-switching signal is just used to switch between CVBS and RGB signal sources. Set the source of the fast-switching signal by writing to bits 4 and 3 of the TV Video Output Control Register (07h). The fast switching signal to the TV SCART connector can be enabled or disabled by bit 1 of the Output Enable Register (0Dh). See Tables 8, 13, and 16. MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 7). A START condition from the master signals the beginning of a transmission to the MAX9598. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. write mode. The slave address is always the first byte of information sent to the MAX9598 after a START or a REPEATED START condition. The MAX9598 slave address is configurable with DEV_ADDR. Table 3 shows the possible slave addresses for the MAX9598. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9598 uses to handshake receipt of each byte of data when in write mode (see Figure 8). The MAX9598 pulls down SDA during the entire master-generated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication. The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the MAX9598 is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the MAX9598, followed by a STOP condition. Early STOP Conditions The MAX9598 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Slave Address The slave address is defined as the 7 MSBs (most significant bits) followed by the R/W (read/write) bit. Set the R/W bit to 1 to configure the MAX9598 to read mode. Set the R/W bit to 0 to configure the MAX9598 to S Sr CLOCK PULSE FOR ACKNOWLEDGMENT P START CONDITION SCL SCL 1 2 8 9 NOT ACKNOWLEDGE SDA SDA ACKNOWLEDGE Figure 7. START, STOP, and REPEATED START Conditions Figure 8. Acknowledge Table 3. Slave Address 18 DEV_ADDR B7 B6 B5 B4 B3 B2 B1 B0 WRITE ADDRESS (hex) READ ADDRESS (hex) GNDVID 1 0 0 1 0 1 0 R/W 94h 95h 97h VVID 1 0 0 1 0 1 1 R/W 96h SCL 1 0 0 1 1 0 0 R/W 98h 99h SDA 1 0 0 1 1 0 1 R/W 9Ah 9Bh ______________________________________________________________________________________ Low-Power Audio/Video Switch for Dual SCART Connectors Read Data Format The master presets the address pointer by first sending the MAX9598’s slave address with the R/W bit set to 0 followed by the register address after a START condition. The MAX9598 acknowledges receipt of its slave address and the register address by pulling SDA low during the ninth SCL clock pulse. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9598 transmits the contents of the specified register. Transmitted data is valid on the rising edge of the master-generated serial clock (SCL). The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read will be from the register address location set by the previous transaction and not 00h and subsequent reads will autoincrement the address pointer until the next STOP condition. Attempting to read from register addresses higher than 01h results in repeated reads from a dummy register containing FFh data. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figures 11 and 12 illustrate the frame format for reading data from the MAX9598. ACKNOWLEDGE FROM MAX9598 B7 ACKNOWLEDGE FROM MAX9598 SLAVE ADDRESS S 0 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9598 A REGISTER ADDRESS A DATA BYTE A R/W P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 9. Writing a Byte of Data to the MAX9598 ACKNOWLEDGE FROM MAX9598 ACKNOWLEDGE FROM MAX9598 S SLAVE ADDRESS ACKNOWLEDGE FROM MAX9598 0 A REGISTER ADDRESS R/W ACKNOWLEDGE FROM MAX9598 B7 B6 B5 B4 B3 B2 B1 B0 A DATA BYTE 1 B7 B6 B5 B4 B3 B2 B1 B0 A 1 BYTE DATA BYTE n A P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 10. Writing n Bytes of Data to the MAX9598 ______________________________________________________________________________________ 19 MAX9598 Write Data Format A write to the MAX9598 consists of transmitting a START condition, the slave address with the R/W bit set to 0, one data byte to configure the internal register address pointer, 1 or more data bytes, and a STOP condition. Figure 9 illustrates the proper frame format for writing 1 byte of data to the MAX9598. Figure 10 illustrates the frame format for writing n bytes of data to the MAX9598. The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9598. The MAX9598 acknowledges receipt of the address byte during the master-generated ninth SCL pulse. The second byte transmitted from the master configures the MAX9598’s internal register address pointer. The pointer tells the MAX9598 where to write the next byte of data. An acknowledge pulse is sent by the MAX9598 upon receipt of the address pointer data. The third byte sent to the MAX9598 contains the data that will be written to the chosen register. An acknowledge pulse from the MAX9598 signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential register address locations within one continuous frame. The master signals the end of transmission by issuing a STOP condition. MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors NOT ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MAX9598 S SLAVE ADDRESS ACKNOWLEDGE FROM MAX9598 ACKNOWLEDGE FROM MAX9598 0 A REGISTER ADDRESS R/W A Sr SLAVE ADDRESS REPEATED START 1 A DATA BYTE A R/W P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 11. Reading 1 Indexed Byte of Data from the MAX9598 ACKNOWLEDGE FROM MAX9598 S SLAVE ADDRESS 0 R/W ACKNOWLEDGE FROM MAX9598 ACKNOWLEDGE FROM MAX9598 A REGISTER ADDRESS A Sr SLAVE ADDRESS REPEATED START 1 A DATA BYTE A R/W P 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER Figure 12. Reading n Bytes of Indexed Data from the MAX9598 Interrupt Output When interrupt is enabled in modes 1 and 2 (see the Operating Modes section), INT, which is an open-drain output, pulls low under the following conditions: slowswitch signals change value, CVBS input signals are detected or disappear, and CVBS output loads are added or removed. When interrupt is enabled in mode 3, INT pulls low only when the slow-switch signal changes value. Enable INT by writing a 1 into bit 4 of register 01h. See Table 11. The interrupt can be cleared by reading register 0Eh and 0Fh. Applications Information Audio Inputs The maximum full-scale audio signal that can be applied to the audio inputs is 0.5V RMS biased at ground. The recommended application circuit to attenuate and bias an incoming audio signal is shown in Figure 13. The audio path has a gain of 4V/V so that the full scale of the audio output signal is 2VRMS. If less than 2VRMS full scale is desired at the audio outputs, then the full scale of the audio input signal should be proportionately decreased below 0.5VRMS. 20 STEREO AUDIO DACS 1μF MAX9598 6.65kΩ ENC_INL R1* 1μF 6.65kΩ ENC_INR R1* *R1 VALUES DAC = CS4334/5/8/9: R1 = 4.53kΩ ±1% DAC = PCM1742: R1 = 5.57kΩ ±1% Figure 13. Application Circuit to Connect Audio Source to Audio Inputs (1µF Capacitor Connected to the Ground-Referenced Resistors Biases the Audio Signal at Ground, Resistors Attenuate the Audio Signal) Operating Modes The MAX9598 has four operating modes, which can be set by writing to bits 6 and 7 of register 10h. See Table 17. ______________________________________________________________________________________ Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598 Table 4. Register Settings for Looping VCR Signals to the TV DESCRIPTION REGISTER BIT 7 6 5 4 01h 0 0 0 1 Loop VCR signals to the TV 06h 0 0 0 07h 0 0 0 08h x 0 COMMENTS 2 1 0 1 1 0 1 0 1 0 1 0 1 0 0 x x (Note 5) 0 0 x 1 1 1 (Note 6) 0 00h 3 Default 09h 0 0 0 0 0 1 1 0Dh 0 0 1 1 1 1 1 1 10h 1 0 0 0 0 0 0 0 Note 5: TV slow-switch output (bits 1 and 0) should be the same as VCR slow-switch input. Note 6: User has to set bits 7 and 3 appropriately depending upon whether signal is red or chroma. Shutdown All circuitry is shut down in the MAX9598 except for the I2C interface, which is designed with static CMOS logic. Except for register 10h, which sets the operating mode, the values in all the other I2C registers are preserved while entering, during, and leaving shutdown mode. Low-Power Mode Put the MAX9598 into low-power mode during standby. Everything is shut down except for the slow-switching circuits, CVBS input detection, CVBS load detection, and I2C interface. If interrupt is enabled, then INT will go active low whenever the slow-switch signal changes; a CVBS signal appears or disappears; or a CVBS load appears or disappears. The µC in the set-top box can then decide whether to change the MAX9598 to fullpower mode and loop VCR signals to the TV. Before entering low-power mode, the slow-switch signals should be set to high impedance. Except for registers 0Eh, 0Fh, and 10h, the value in all of the other I2C registers are preserved while entering, during, and leaving low-power mode. The values in registers 0Eh and 0Fh might change in low-power mode because they provide status on the slow switch signals, CVBS input, and CVBS outputs. The value in register 10h changes while entering or leaving low-power mode because bits 6 and 7 set the operating mode. Full-Power Mode with Video Input Detection and Video Load Detection In this mode, the MAX9598 is fully on. If interrupt is enabled, then INT will go active low whenever the slowswitch signal changes; a CVBS signal appears or disappears; or a CVBS load appears or disappears. The µC can decide whether to change the routing configuration or operating mode of the MAX9598. Full-Power Mode Without Video Input Detection and Video Load Detection This mode is similar to the above mode except that video input detection and video load detection are not active. If interrupt is enabled, then INT will go active low only when the slow-switch signal changes. Table 5. Quiescent Power Consumption OPERATING MODE POWER CONSUMPTION (mW) Shutdown. 0.1 Low-power mode with slow switching, CVBS input video detection, and video load detection active only. Audio circuitry is off. 1.7 Full-power mode WITH input video detection and video load detection active. 71 Full-power mode WITHOUT input video detection and video load detection active (power-on default). 70 ______________________________________________________________________________________ 21 MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors Table 6. Average Power Consumption OPERATING MODE POWER CONSUMPTION (mW) Full-power mode WITH input video detection and video load detection active. 471 Full-power mode WITHOUT input video detection and video load detection active (power-on default). 470 Table 7. Conditions for Average Power Consumption Measurement 22 PIN NAME TYPE SIGNAL LOAD 5 VAUD Supply 3.3V N/A 9 ENC_INL Input 0.25VRMS, 1kHz N/A 10 ENC_INR Input 0.25VRMS, 1kHz N/A 11 VCR_INL Input None N/A 12 VCR_INR Input None N/A 13 TV_OUTL Output 1VRMS, 1kHz 10kΩ to ground 14 VCR_OUTL Output 1VRMS, 1kHz 10kΩ to ground 15 VCR_OUTR Output 1VRMS, 1kHz 10kΩ to ground 16 TV_OUTR Output 1VRMS, 1kHz 10kΩ to ground 17 TV_SS Output 12V 10kΩ to ground 18 V12 Supply 12V N/A 19 VCR_SS Input 0 N/A 20 TVOUT_FS Output 3.3V 150Ω to ground 21 VCRIN_FS Input 0 N/A 22 ENC_B_IN Input 50% flat field N/A 23 ENC_G_IN Input 50% flat field N/A 24 VCR_B_IN Input None N/A 25 VCR_G_IN Input None N/A 26 TV_B_OUT Output 50% flat field 150Ω to ground 27 TV_G_OUT Output 50% flat field 150Ω to ground 28 GNDVID Supply 0 N/A 29 VCR_R/C_IN Input None N/A 30 VVID Supply 3.3V N/A 31 ENC_C_IN Input None N/A 32 ENC_R/C_IN Input 50% flat field N/A 33 TV_R/C_OUT Output 50% flat field 150Ω to ground 34 VCR_R/C_OUT Output 50% flat field 150Ω to ground 35 VCR_Y/CVBS_OUT Output 50% flat field 150Ω to ground 36 TV_Y/CVBS_OUT Output 50% flat field 150Ω to ground 37 VCR_Y/CVBS_IN Input None N/A 38 TV_Y/CVBS_IN Input None N/A 39 ENC_Y_IN Input None N/A 40 ENC_Y/CVBS_IN Input 50% flat field N/A ______________________________________________________________________________________ Low-Power Audio/Video Switch for Dual SCART Connectors Average power consumption is defined when the MAX9598 drives typical signals into typical loads. Table 6 shows the average power consumption in full-power mode and Table 7 shows the input and output conditions. S-Video The MAX9598 supports S-video from the set-top box to the TV, set-top box to the VCR, and VCR to the set-top box. S-video was not included in the original SCART specifications but was added afterwards. As a consequence, the luma (Y) signal of S-video shares the same SCART pin as the CVBS signal. Likewise, the chroma (C) signal shares the same SCART pin as the red sig- 0.1μF VCR_R/C_IN ENC_R/C_IN ENC_C_IN nal. The pins that can carry both CVBS and luma have Y/CVBS in their names, and the pins that can carry red and chroma have R/C in their names. Now, the Y/CVBS signals are full duplex while the R/C signals are half duplex. Therefore, S-video is limited to being half duplex. The MAX9598 has to transmit a chroma signal and receive a chroma signal on the same SCART pin, but not at the same time. The 75Ω resistor connected to VCR_R/C_OUT must act as a back termination resistor when the MAX9598 is transmitting chroma signal and as an input termination resistor when it is receiving a chroma signal. Figure 14 shows how the MAX9598 transmits a chroma signal to the VCR SCART connector while Figure 15 shows how the MAX9598 receives a chroma from the VCR SCART connector. Write a 0 into bit 2 of register 09h to open the pulldown switch at VCR_R/C_OUT. To close the pulldown switch, write a 0 into bit 6 of register 0Dh to turn off the output amplifier, and then write a 1 into bit 2, register 09h. See Tables 15 and 16. BIAS AV = 2V/V BIAS LPF BIAS LPF AV = 2V/V MAX9598 TV_R/C_OUT 75Ω VCR_R/C_OUT 75Ω TV SCART VCR SCART ON Figure 14. Gain-of-2 Amplifier on VCR_R/C_OUT Outputs Chroma Signal to VCR SCART Connector (Note the Pulldown Switch on VCR_R/C_OUT Is Open) ______________________________________________________________________________________ 23 MAX9598 Power Consumption The quiescent power consumption and average power consumption of the MAX9598 are very low because of 3.3V operation and low-power circuit design. Quiescent power consumption is defined when the MAX9598 is operating without loads and without any audio or video signals. Table 5 shows the quiescent power consumption in all four operating modes. MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors 0.1μF VCR_R/C_IN ENC_R/C_IN ENC_C_IN BIAS AV = 2V/V BIAS LPF BIAS LPF AV = 2V/V TV_R/C_OUT 75Ω VCR_R/C_OUT 75Ω MAX9598 TV SCART VCR SCART OFF Figure 15. VCR_R/C_IN Receives a Chroma Signal from the VCR SCART Connector. Notice that the Pulldown Switch on VCR_R/C_OUT Is Closed and that the Gain-of-2 Amplifier is Off. The Chroma Signal from VCR SCART IS Looped Through to the TV SCART in the Above Configuration. TV_OUTR 10kΩ MAX9598 MONO AUDIO 10kΩ TV_OUTL 75Ω TV SCART TV_Y/CVBS_OUT 75Ω OR GREATER 75Ω OR GREATER RF MODULATOR Figure 16. Application Circuit to Connect CVBS and Mono Audio from TV SCART to RF Modulator Interfacing to an RF Modulator If the set-top box modulates CVBS and mono audio onto an RF carrier (for example, channel 3), then a simple application circuit can provide the needed signals (see Figure 16). A 10kΩ resistor summer circuit between TV_OUTR and TV_OUTL creates the mono audio signal. The resistor-divider to ground on TV_Y/CVBS_OUT creates a video signal with normal amplitude. The unique feature of the MAX9598 that facilitates this application circuit is that the audio and video output amplifiers of 24 the MAX9598 can drive multiple loads if VAUD and VVID are both greater than 3.135V. Floating-Chassis Discharge Protection and ESD Some set-top boxes have a floating chassis problem in which the chassis is not connected to earth ground. As a result, the chassis can charge up to 500V. When a SCART cable is connected to the SCART connector, the charged chassis can discharge through a signal pin. The equivalent circuit is a 2200pF capacitor charged to ______________________________________________________________________________________ Low-Power Audio/Video Switch for Dual SCART Connectors 3.3V 3.3V 0.1μF +3.3V MAX9598 12V 0.1μF 0.1μF VAUD V12 STB CHIP VVID VAUD 75Ω TV_OUTR VAUD SDA μC 75Ω SCL CPVSS TV_OUTL MAX9598 V12 INT 75Ω CPVSS TV_SS VVID 75Ω DEV_ADDR EP TV_B_OUT VVID 75Ω GNDVID TV_G_OUT VVID 75Ω GNDVID TV_R/C_OUT VVID 75Ω GNDVID TVOUT_FS VVID 75Ω GNDVID TV_Y/CVBS_OUT VIDEO ENCODER TV SCART VVID 75Ω 0.1μF 75Ω ENC_Y/CVBS_IN GNDVID TV_Y/CVBS_IN 75Ω GNDVID 75Ω GNDVID 75Ω VAUD 75Ω ENC_R/C_IN VCR_OUTR VAUD 75Ω 1μF 7.68kΩ 75Ω CPVSS VCR_INR ENC_G_IN 2.55kΩ 75Ω VAUD CPVSS 75Ω 75Ω VCR_OUTL ENC_B_IN VAUD 75Ω 1μF 7.68kΩ CPVSS VCR_INL 75Ω ENC_Y_IN 2.55kΩ 75Ω V12 CPVSS 75Ω VCR_SS 75Ω VVID ENC_C_IN 0.1μF 75Ω 75Ω EP VCR_B_IN 75Ω VVID GNDVID VCR SCART 0.1μF 75Ω VCR_G_IN 75Ω GNDVID VVID 0.1μF 75Ω VCR_R/C_IN VVID GNDVID 75Ω VCR_R/C_OUT STEREO AUDIO DAC VVID GNDVID 1μF VCRIN_FS 6.65kΩ ENC_INL 75Ω R1* 1μF VVID GNDVID 75Ω VCR_Y/CVBS_OUT 6.65kΩ VVID ENC_INR 0.1μF 75Ω C1P *R1 VALUES DAC = CS4334/5/8/9: R1 = 4.53kΩ ±1% DAC = PCM1742: R1 = 5.57kΩ ±1% GNDVID VCR_Y/CVBS_IN R1* EP C1N CPVSS 1μF GNDVID 75Ω 1μF Figure 17. Application Circuit to Connect Series Resistors and External ESD Protection Diodes at MAX9598 Outputs ______________________________________________________________________________________ 25 MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors 311V connected through less than 0.1Ω to a signal pin. The MAX9598 is soldered on the PCB when it experiences such a discharge. Therefore, the current spike flows through both external and internal ESD protection devices and is absorbed by the supply bypass capacitors, which have high capacitance and low ESR. To better protect the MAX9598 against excess voltages during the cable discharge condition or ESD events, add series resistors to all inputs and outputs to the SCART connector if series resistors are not already present in the application circuit. Also add external ESD protection diodes (for example, BAV99) on all inputs and outputs to the SCART connector. Power-Supply Bypassing The MAX9598 features single 3.3V and 12V supply operation and requires no negative supply. The 12V supply, V12 is for the SCART switching function. For V12, place a 0.1µF bypass capacitor as close as possible. Connect all VAUD pins together to 3.3V and bypass with a 10µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor to audio ground. Bypass each VVID to video ground with a 0.1µF ceramic capacitor. Using a Digital Supply The MAX9598 was designed to operate from noisy digital supplies. The high PSRR (49dB at 100kHz) allows the MAX9598 to reject the noise from the digital power supplies (see the Typical Operating Characteristics). If the digital power supply is very noisy and stripes appear on the television screen, increase the supply bypass capacitance. An additional, smaller capacitor in parallel with the main bypass capacitor can reduce digital supply noise because the smaller capacitor has lower equivalent series resistance (ESR) and equivalent series inductance (ESL). Layout and Grounding For optimal performance, use controlled-impedance traces for video signal paths and place input termination resistors and output back-termination resistors Table 8. Data Format for Write Mode REGISTER ADDRESS (HEXADECIMAL) BIT 7 BIT 6 00h Not used ZCD 01h Not used Not used BIT 5 BIT 3 Not used Interrupt enable BIT 1 Not used 03h Not used 04h Not used TV audio selection Not used Not used Not used Not used Not used TV G and B video switch TV video switch 07h Not used 08h VCR_R/C_IN Clamp Not used Not used Not used ENC_R/C_IN clamp 09h Not used Not used Not used Not used Not used VCR_R/C_ OUT ground Set TV fast switching TV_B_OUT enable TV_Y/CVBS_ OUT enable 0Ah Not used 0Bh Not used 0Ch Not used 0Dh 10h BIT 0 TV audio output mute VCR audio selection 02h 06h BIT 2 Not used 05h 26 BIT 4 VCR_Y/CV BS_OUT enable VCR_R/C_ OUT enable Operating mode TV_R/C_ OUT enable TV_G_OUT enable Not used Set TV slow switching VCR video switch Set VCR slow switching TVOUT_FS enable Not used ______________________________________________________________________________________ Not used Low-Power Audio/Video Switch for Dual SCART Connectors REGISTER ADDRESS (HEXADECIMAL) BIT 7 BIT 6 0Eh Not used Power-on reset 0Fh BIT 5 BIT 4 BIT 3 VCR slow-switch input status Not used ENC_Y_IN input video detection Not used BIT 2 ENC_Y/CVBS_IN input video detection BIT 1 BIT 0 TV slow-switch input status VCR CVBS VCR CVBS TV CVBS input video output load output load detection TV CVBS input video detection Table 10. Register 00h: Audio Control DESCRIPTION BIT 7 6 5 4 3 2 1 TV Audio Mute Zero-Crossing Detector COMMENTS 0 0 Off 1 On (power-on default) 0 Off 1 On (power-on default) Table 11. Register 01h: TV Audio Control DESCRIPTION BIT 7 6 5 4 3 2 Input Source for TV Audio Input Source for VCR Audio Interrupt Enable COMMENTS 1 0 0 0 Encoder audio 0 1 VCR audio 1 0 Not used 1 1 Mute (power-on default) 0 0 Encoder audio 0 1 VCR audio 1 0 Not used 1 1 Mute (power-on default) 0 Disabled (power-on default) 1 Enabled close to the MAX9598. Avoid routing video traces parallel to high-speed data lines. The MAX9598 provides separate ground connections for video and audio supplies. For best performance, use separate ground planes for each of the ground returns and connect all ground planes together at a single point. Refer to the MAX9598 Evaluation Kit for a proven PCB layout example. If the MAX9598 is mounted using flow soldering or wave soldering, the ground via(s) for the exposed pad should have a finished hole size of at least 14 mils to ensure adequate wicking of soldering onto the exposed pad. If the MAX9598 is mounted using solder mask technique, the via requirement does not apply. In either case, a good connection between the exposed pad and ground is required in order to minimize noise from coupling onto the outputs. ______________________________________________________________________________________ 27 MAX9598 Table 9. Data Format for Read Mode MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors Table 12. Register 06h: TV Video Input Control BIT DESCRIPTION 7 6 5 4 3 2 1 COMMENTS 0 TV_Y/CVBS_OUT Input Sources for TV Video Input Sources for TV_G_OUT and TV_B_OUT TV_R/C_OUT 0 0 0 ENC_Y/CVBS_IN ENC_R/C_IN 0 0 1 ENC_Y_IN ENC_C_IN 0 1 0 VCR_Y/CVBS_IN VCR_R/C_IN 0 1 1 TV_Y/CVBS_IN MUTE 1 0 0 Not used Not used 1 0 1 Mute Mute 1 1 0 Mute Mute 1 1 1 Mute (power-on default) Mute (power-on default) TV_G_OUT TV_B_OUT 0 0 ENC_G_IN ENC_B_IN 0 1 VCR_G_IN VCR_B_IN 1 0 Mute Mute 1 1 Mute (power-on default) Mute (power-on default) Table 13. Register 07h: TV Video Output Control DESCRIPTION BIT 7 6 5 4 3 Set TV Slow Switching 0 Set TV Fast Switching 28 0 2 1 COMMENTS 0 0 0 Low (< 2V). Internal source (power-on default). 0 1 Medium (4.5V to 7V). External SCART source with 16:9 aspect ratio. 1 0 High impedance 1 1 High (> 9.5V). External SCART source with 4:3 aspect ratio. GNDVID (power-on default) 0 1 Not used 1 0 Same level as VCR_FB_IN 1 1 VVID ______________________________________________________________________________________ Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598 Table 14. Register 08h: VCR Video Input Control BIT DESCRIPTION 7 6 5 4 3 COMMENTS 2 1 0 0 0 0 ENC_Y/CVBS_IN ENC_R/C_IN 0 0 1 ENC_Y_IN ENC_C_IN 0 1 0 VCR_Y/CVBS_IN VCR_R/C_IN 0 1 1 TV_Y/CVBS_IN MUTE 1 0 0 Not used Not used 1 0 1 Mute Mute 1 1 0 Mute Mute 1 1 1 Mute (power-on default) Mute (power-on default) VCR_Y/CVBS_OUT Input Sources for VCR Video ENC_R/C_IN Clamp/Bias VCR_R/C_IN Clamp/Bias VCR_R/C_OUT 0 DC restore clamp active at input (power-on default) 1 Chrominance bias applied at input 0 DC restore clamp active at input (power-on default) 1 Chrominance bias applied at input Table 15. 09h: VCR Video Output Control DESCRIPTION BIT 7 6 5 4 3 2 Set VCR Function Switching COMMENTS 1 0 0 0 Low (< 2V). Internal source (power-on default) 0 1 Medium (4.5V to 7V). External SCART source with 16:9 aspect ratio. 1 0 High impedance 1 1 High (> 9.5V). External SCART source with 4:3 aspect ratio. 0 Normal operation. Pulldown on TV_R/C_OUT is off (power-on default). 1 Ground. Pulldown on TV_R/C_OUT is on, the output amplifier driving VCR_R/C_OUT turns off. VCR_R/C_OUT Ground ______________________________________________________________________________________ 29 MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors Table 16. Register 0Dh: Output Enable BIT DESCRIPTION 7 6 5 4 3 2 1 0 TVOUT_FS Enable 1 TV_Y/CVBS_OUT Enable TV_B_OUT Enable VCR_R/C_OUT Enable VCR_Y/CVBS_OUT Enable On Off (power-on default) 1 On 0 Off (power-on default) 1 On Off (power-on default) 1 TV_R/C_OUT Enable Off (power-on default) 0 0 TV_G_OUT Enable COMMENTS 0 On 0 Off (power-on default) 1 On 0 Off (power-on default) 1 On 0 Off (power-on default) 1 On Table 17. Register 10h: Operating Modes DESCRIPTION BIT 5 4 3 2 1 COMMENTS 7 6 0 0 0 Shutdown. 0 1 Low-power mode with slow switching, CVBS input video detection, and video load detection active only, audio circuitry is off. 1 0 Full-power mode WITH input video detection and video load detection active. 1 1 Full-power mode WITHOUT input video detection and video load detection active (power-on default). Operating Mode 30 ______________________________________________________________________________________ Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598 Table 18. Register 0Eh: Status DESCRIPTION BIT 7 6 5 4 3 2 TV Slow-Switching Input Status VCR Slow-Switching Input Status Power-On Reset COMMENTS 1 0 0 0 0 1 4.5V to 7V, external source with 16:9 aspect ratio 1 0 Not used 1 1 9.5V to 12.6V, external source with 4:3 aspect ratio 0 to 2V, internal source 0 0 0 to 2V, internal source 0 1 4.5V to 7V, external source with 16:9 aspect ratio 1 0 Not used 1 1 9.5V to 12.6V, external source with 4:3 aspect ratio 0 V_DIG is too low for digital logic to operate 1 V_DIG is high enough for digital logic to operate Table 19. Register 0Fh: Video Activity Status DESCRIPTION BIT 7 6 5 4 3 2 1 TV CVBS Input Video Detection TV CVBS Output Load 0 VCR CVBS Input Video Detection 1 VCR CVBS Output Load 0 1 ENC_Y/CVBS_IN Input Video Detection ENC_Y_IN Input Video Detection 0 COMMENTS 0 No video detected 1 Video detected 0 No load connected 1 Load connected No video detected Video detected 0 No load connected 1 Load connected No video detected Video detected 0 No video detected 1 Video detected ______________________________________________________________________________________ 31 MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors Typical Application Circuit 12V 3.3V 3.3V 0.1μF 3.3V V12 STB CHIP 0.1μF VVID 0.1μF VAUD 75Ω TV_OUTR SDA 75Ω TV_OUTL μC SCL 75Ω MAX9598 TV_SS INT 75Ω TV_B_OUT 75Ω DEV_ADDR TV SCART TV_G_OUT 75Ω TV_R/C_OUT 75Ω TVOUT_FS VIDEO ENCODER 75Ω TV_Y/CVBS_OUT ENC_Y/CVBS_IN 0.1μF TV_Y/CVBS_IN 75Ω 75Ω GNDVID ENC_R/C_IN 75Ω 75Ω VCR_OUTR ENC_G_IN 1μF 7.68kΩ VCR_INR 75Ω 2.55kΩ ENC_B_IN 75Ω VCR_OUTL 75Ω 1μF 7.68kΩ VCR_INL ENC_Y_IN 2.55kΩ 75Ω 75Ω VCR_SS 0.1μF ENC_C_IN VCR_B_IN 75Ω 75Ω VCR SCART 0.1μF VCR_G_IN 0.1μF 75Ω VCR_R/C_IN STEREO AUDIO DAC 75Ω VCR_R/C_OUT 1μF 6.65kΩ VCRIN_FS ENC_INL 75Ω R1* 1μF 75Ω 6.65kΩ VCR_Y/CVBS_OUT ENC_INR 0.1μF VCR_Y/CVBS_IN R1* C1P *R1 VALUES DAC = CS4334/5/8/9: R1 = 4.53kΩ ±1% DAC = PCM1742: R1 = 5.57kΩ ±1% 32 EP C1N CPVSS 75Ω 1μF 1μF ______________________________________________________________________________________ Low-Power Audio/Video Switch for Dual SCART Connectors VCRIN_FS ENC_B_IN ENC_G_IN VCR_B_IN TV_B_OUT VCR_G_IN TV_G_OUT GNDVID VCR_R/C_IN VVID TOP VIEW 30 29 28 27 26 25 24 23 22 21 20 TVOUT_FS ENC_C_IN 31 ENC_R/C_IN 32 19 VCR_SS TV_R/C_OUT 33 18 V12 17 TV_SS VCR_R/C_OUT 34 16 TV_OUTR VCR_Y/CVBS_OUT 35 MAX9598 TV_Y/CVBS_OUT 36 15 VCR_OUTR 14 VCR_OUTL VCR_Y/CVBS_IN 37 TV_Y/CVBS_IN 38 ENC_Y_IN 39 13 TV_OUTL EP* + 12 VCR_INR 11 VCR_INL 7 8 9 10 CPVSS ENC_INR 6 ENC_INL DEV_ADDR 5 C1N SCL 4 C1P 3 INT 2 VAUD 1 SDA ENC_Y/CVBS_IN 40 THIN QFN (6mm x 6mm) *EP = EXPOSED PAD Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ 33 MAX9598 Pin Configuration Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 40 TQFN-EP T4066+3 21-0141 QFN THIN.EPS MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors 34 ______________________________________________________________________________________ Low-Power Audio/Video Switch for Dual SCART Connectors ______________________________________________________________________________________ 35 MAX9598 Package Information (continued) For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. MAX9598 Low-Power Audio/Video Switch for Dual SCART Connectors Revision History REVISION NUMBER REVISION DATE 0 1/08 1 1/09 DESCRIPTION Initial release Corrected various errors PAGES CHANGED — 4, 10, 16, 18, 21, 27, 31, 33 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.