ASAHI KASEI [AKD4705-A] AKD4705-A AK4705 Evaluation Board Rev.0 GENERAL DESCRIPTION AKD4705-A is an evaluation board for quickly evaluating the AK4705, 2ch DAC with AV SCART switch. Evaluation requires audio/video analog analyzers/generators, a digital audio signal source, and a power supply. AKM’s ADC evaluation board can be also used for the audio source. Also included is a AK4112B digital audio interface receiver which receives S/PDIF compatible audio data. The digital audio data is available via optical connector or BNC. AKD4705-A --- AK4705 Evaluation Board (Cable for connecting with printer port of IBM-AT compatible PC and a control software are enclosed with board. This control software dose not support Windows NT.) FUNCTION BNC connectors for analog audio input/output BNC connectors for analog video input/output On-board clock generator BNC connector for an external clock input Compatible with 2 types of digital interface 1. Serial interface: Direct interface with evaluation boards for AKM’s A/D converter evaluation boards. 2. S/PDIF: On-board AK4112BVF as DIR that accepts optical input or BNC input 10pin header for serial control interface MO NO VVD2 D5V VVD1 +12V +5V Gnd OU JP10 TV Reg. JP11 PORT3 µ P- IF (Digital) OU JP8 Control Data TV JP9 10pin Heder OU Port1 AD DATA ROM DATA VC 10pin Header RO JP2 ~ 5 UT VC RX JP6 DIR RO PORT2 Opt In UT µ J1 EXT VC JP1 Clock Generator AK4705 RF TVI RV OU NL TV JP12 VC RC TV RC TVI FB TV NR VO VC TV RI TV VC ENCB ENCG ENCRC ENCV ENCC TVVIN ENCY VCRFB VCRVIN VCRG RI VCRRC VCRSB VCRB TVSB Figure 1. AKD4705-A Block Diagram Circuit diagram and PCB layout are attached at the end of this manual. <KM078601> 2006/08 -1- ASAHI KASEI [AKD4705-A] Operation sequence 1) Set up the power supply lines. (Note 1) [+12V] [+5V] [D5V] [VVD1] [VVD2] [AGND] [DGND] [VVSS2] (Orange) (Red) (Red) (Red) (Blue) (Black) (Black) (Black) = +11.4 ∼ +12.6V = +4.75 ∼ +5.25V (Note 2) = +4.75∼ +5.25V (Note 3) = +4.75∼ VVD2 (Note 4) = VDD1∼ +5.25V (Note 4) = 0V = 0V = 0V Note: 1. Each supply line should be distributed from the power supply unit. 2. JP9 (REG) should be open when the “+5V” jack is used. 3. JP8 (D-A) should be open when the “D5V” jack is used. 4. JP10 (VDD1) / JP11 (VDD2) should be open when the “VDD1” jack / “VDD2” jack are used independently. 2) Set-up the evaluation modes, jumper pins and DIP-switches. (Refer next sections.) 3) Connect the PORT3 (µP-I/F) with PC by the enclosed 10-wire flat cable. 4) Set up the PC and execute the enclosed control software. (Refer “CONTROL SOFTWARE MANUAL”.) 5) Turn the power on. 6) Reset the AK4705 once by bringing the SW1 (PDN) “L”, and return it to “H”. <KM078601> 2006/08 -2- ASAHI KASEI [AKD4705-A] Evaluation mode 1) S/PDIF mode (Optical Link or BNC: default) When the CM0 (DIP-switch S1_1 on board) is “L”, the AK4112B (DIR) generates MCLK, BICK, LRCK and SDATA from the received bit stream through PORT2 (TORX176: optical link) or J2 (BNC). This mode is used for the evaluation using CD test disk. The PORT1 (EXT) should be open. 1)-1. DIP-switch set-up No. 1 2 3 4 CM0 “L” “L” “L” “L” DIF2 “L” “L” “H” “H” DIF0 “L” “H” “L” “H” Audio Data Format of AK4112B 16bit LSB justified 18bit LSB justified 24bit MSB justified 24bit I2S Notes 1 2 3 4 (Default) Table 1. DIP-switch set-up (Note) AK4112B: DIF1=“L” Much the data format of the AK4705 via I2C-bus control as following notes. Note 1. 16bit LSB justified Set up the DIP-switch as follows. S1 AK4112B ON 1 2 3 4 5 (Reserved) (Reserved) CM0 DIF2 DIF0 OFF Set up the control registers DIF1/0 of the AK4705 by enclosed software as follows. Note 2. 18bit LSB justified Set up the DIP-switch as follows. S1 AK4112B ON 1 2 3 4 5 (Reserved) (Reserved) CM0 DIF2 DIF0 OFF Set up the control registers DIF1/0 of the AK4705 by enclosed software as follows. <KM078601> 2006/08 -3- ASAHI KASEI [AKD4705-A] Note 3. 24bit MSB justified Set up the DIP-switch as follows. S1 AK4112B ON 1 2 3 4 5 (Reserved) (Reserved) CM0 DIF2 DIF0 OFF Set up the control registers DIF1/0 of the AK4705 by enclosed software as follows. Note 4. 24bit I2S (Default) Set up the DIP-switch as follows. S1 AK4112B ON 1 2 3 4 5 (Reserved) (Reserved) CM0 DIF2 DIF0 OFF Set up the control registers DIF1/0 of the AK4705 by enclosed software as follows. <KM078601> 2006/08 -4- ASAHI KASEI [AKD4705-A] 1)-2. Jumper pins set up JP1 JP2 JP3 EXT MCLK (Open) (Default) JP5 BICK JP4 SDTI LRCK (Short) (Short) (Short) (Short) (Default) (Default) (Default) (Default) The JP6 selects the input port of S/PDIF bit stream form Port2 (TOTX176) or J2 (BNC RX). JP6 JP6 RX RX TORX TORX BNC BNC (BNC) (TORX) (Default) <KM078601> 2006/08 -5- ASAHI KASEI [AKD4705-A] 2) On-board X’tal mode/ Feeding external MCLK via BNC When the CM0 (DIP-switch S1_1 on board) is “H”, the AK4112B generates MCLK, BICK and LRCK from on-board X’tal or external clock form J1. SDATA should be fed via PORT1. 2)-1. DIP-switch set-up No. 1 CM0 “H” DIF1 Don’t care DIF0 Don’t care Table 2. DIP-switch set-up 2)-2. Jumper pins set up 2)-2-a. Using on-board X’tal JP1 JP2 JP3 EXT MCLK (Open) (Short) JP6: Don’t care. JP5 BICK JP4 SDTI LRCK (Short) (Open) (Short) JP4 SDTI JP5 LRCK (Open) (Short) 2)-2-b. Using external clock via BNC connector J1 JP1 JP2 JP3 EXT MCLK BICK (Short) (Short) (Short) JP6: Don’t care. Remove the on-board X’tal. <KM078601> 2006/08 -6- ASAHI KASEI [AKD4705-A] 3) Feeding all clocks from external Under the following set-up, all external signals can be fed to the AK4705 through POTR1 (EXT). The AKM’s evaluation board for ADC can be used. 3)-1. DIP-switch set-up No. 1 CM0 Don’t care DIF1 Don’t care DIF0 Don’t care Table 3. DIP-switch set-up 3)-2. Jumper pins set up JP5 JP1 JP2 JP3 EXT MCLK BICK JP4 SDTI LRCK (Open) (Open) (Open) (Open) (Open) JP6: Don’t care. Other jumper pins set up [JP12](VCRRC): Input Jack selection for the VCRRC pin of AK4705 When the VCRC pin of the AK4705 outputs 0V by setting CIO bit to “1”, the signal can be fed through the J27 (VCRCOUT) to VCRRC pin. “I”: The signal is fed through the J18 (VCRRC) to VCRRC pin. (Default) “I/O”: The signal is fed through the J27 (VCRCOUT) to VCRRC pin. The CIO bit of AK4705 should be set to “1”. JP12 JP12 I/O I I (I) I/O (I/O) (Default) [JP7](GND): Analog ground and digital ground Open: separated. (Default) Short: connected. (The jack “DGND” can be open.) JP7 DGND AGND (Open) (Default) <KM078601> 2006/08 -7- ASAHI KASEI [AKD4705-A] DIP-switch (S1) List No. 1 2 3 4 5 Switch Name CM0 DIF0 DIF2 - Default Function OFF ON ON OFF OFF S/P DIF mode (Refer the evaluation mode) 24 bit I2S mode (Refer the evaluation mode) (Reserved) (Reserved) Table 4. DIP-switch list Jumper List No. Jumper Name Function MCLK source set-up when CM0=”H”. 1 2,3, 4,5 EXT MCLK, BICK, LRCK, SDTI Open: X’tal (Default). Short: External clock via BNC (J1). Remove the on-board X’tal. Clock source set-up Short: Connect the DIR (AK4112B). (Default) Open: Separate the DIR. Supply clocks via Port1. S/PDIF’s port set-up when CM0=”L”. 6 RX 7 GND 8 D-A 9 REG TORX: Optical connector PORT2. (Default) BNC: BNC connector J2. Analog ground and digital ground Open: separated (Default). Short: connected (The connector “DGND” can be open.). Power supply source set-up for digital section of AKD4705-A. Open: from the “D5V” Jack. Short: from the regulator or the “+5V” Jack. Don’t connect anything to the “D5V” Jack. (Default) Power supply source set-up for VD of AK4705. Open: from the “+5V” Jack. Short: from the regulator. Don’t connect anything the “+5V” Jack. (Default) Power supply source set-up for VVD1 of AK4705. 10 VVD1 11 VVD2 Open: from the “VVD1” Jack. Short: from the regulator or the “+5V” Jack. Don’t connect anything to the “VVD1” Jack. (Default) Power supply source set-up for VVD1 of AK4705. Open: from the “VVD2” Jack. Short: from the regulator or the “+5V” Jack. Don’t connect anything to the “VVD2” Jack. (Default) Input Selection for VCRRC 12 VCRRC “I” side: Input to VCRRC from VCRRC jack. (Default) “I/O” side: Input to VCRC from VCRC jack. (Note: Refer CIO bit of AK4705) Table 5. Jumper list <KM078601> 2006/08 -8- ASAHI KASEI [AKD4705-A] Serial Control The AK4705-A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3 (µP-IF) with PC by 10 wire flat cable packed with the AKD4705-A. Be careful connector direction. Flat cable should be connected 10-pin header, red line put on 10pin header 5 and 6 pin. 1 10 SCL Connect SDA PC AKD4705-A SDA(ACK) RED 10 wire flat cable 5 10 pin Connector PORT3 6 µP-IF 10 pin Header Figure 2. Connection of 10 pin flat cable for PORT3 Input/Output port List Input Audio Signal Name Notes J5 (VCRINL), J3 (VCRINR), J9 (TVINL), J8 (TVINR) Max: 2Vrms Slow Blanking Input Output J12 (VCROUTL), J10 (VCROUTR), J6 (TVOUTL), J7 (TVOUTR), J4 (MONOOUT) Port2 (TORX176) or J2 BNC (RX) J13 (ENCB), J15 (ENCG), J17 (ENCRC), J19 (ENCC), J21 (ENCV), J23(ENCY), J25(TVVIN), J14(VCRVIN), J18(VCRRC; Note), J20(VCRG), J22(VCRB) J27 (VCRCOUT; Note), J29 (TVVOUT), J30 (TVRC), J31 (TVG), J32 (TVB), J33 (RFV), J34 (VCRVOUT) J24 (VCRSB) J24 (VCRSB) , J28 (TVSB) Fast Blanking Input Output J16 (VCRFB) J26 (TVFB) Output Digital Input Input Video Output Max: 3Vrm Max: D5V+0.3V Max: 1.5Vp-p Max: 3Vp-p Max: VP+0.3V Max: VP Max: VVD1+0.3V Max: VVD2 Note: Refer JP12 and CIO bit of the AK4705. Table 6. Input/Output port List The indication content for LED LED turns on during each output is “H”. [LE1] Indicates unlock or parity error of S/PDIF. Connected to the ERF pin of DIR (AK4112B). (Normally off.) [LE2] Indicates the validity status of S/PDIF. Connected to the V pin of DIR (AK4112B). (Normally off.) Toggle switch (SW1 on board) operation “H”: AK4705 is active. “L”: AK4705 is powered down. (Note: When the power of AKD4705-A is ON at first, SW1 should be switched from “L” to “H”.) <KM078601> 2006/08 -9- ASAHI KASEI [AKD4705-A] 4) Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD4705-A according to previous term. 2. Connect IBM-AT compatible PC with AKD4705-A by 10-line type flat cable (packed with AKD4705-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled “AK4705 Evaluation Kit” into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of “akd4705.exe” to set up the control program. 5. Then please evaluate according to the follows. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click “Port Reset” button. 3. Click “Write default” button Explanation of each buttons 1. [Port Reset]: 2. [Write default]: 3. [All Write]: 4. [Function1]: 5. [Function2]: 6. [Function3]: 7. [Function4]: 8. [Function5]: 9. [SAVE]: 10. [OPEN]: 11. [Write]: Set up the USB interface board (AKDUSBIF-A) when using the board. Initialize the register of AK4705. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Indication of data Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the part that is not defined in the datasheet. <KM078601> 2006/08 - 10 - ASAHI KASEI [AKD4705-A] Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes “H” or “1”. If not, “L” or “0”. If you want to write the input data to the AK4705, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to the AK4705, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate DATT There are dialogs corresponding to register of 02h. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4705 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to the AK4705, click [OK] button. If not, click [Cancel] button. <KM078601> 2006/08 - 11 - ASAHI KASEI [AKD4705-A] 4. [SAVE] and [OPEN] 4-1. [SAVE] All of current register setting values displayed on the main window are saved to the file. The extension of file name is “akr”. <Operation flow> (1) Click [SAVE] Button. (2) Set the file name and click [SAVE] Button. The extension of file name is “akr”. 4-2. [OPEN] The register setting values saved by [SAVE] are written to the AK4705. The file type is the same as [SAVE]. <Operation flow> (1) Click [OPEN] Button. (2) Select the file (*.akr) and Click [OPEN] Button. <KM078601> 2006/08 - 12 - ASAHI KASEI [AKD4705-A] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. The following is displayed. (2) Set the control sequence. Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file name is “aks”. Figure 1. Window of [F3] <KM078601> 2006/08 - 13 - ASAHI KASEI [AKD4705-A] 6. [Function4 Dialog] The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 2 opens. Figure 2. [F4] window <KM078601> 2006/08 - 14 - ASAHI KASEI [AKD4705-A] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. The sequence file name is displayed as shown in Figure 3. ( In case that the selected sequence file name is “DAC_Stereo_ON.aks”) Figure 3. [F4] window(2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name is “*.ak4”. [OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the change. <KM078601> 2006/08 - 15 - ASAHI KASEI [AKD4705-A] 7. [Function5 Dialog] The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to buttons and then executed. When [F5] button is clicked, the window as shown in Figure 4 opens. Figure 4. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 5. (In case that the selected file name is “DAC_Output.akr”) (2) Click [WRITE] button, then the register setting is executed. <KM078601> 2006/08 - 16 - ASAHI KASEI [AKD4705-A] Figure 5. [F5] windows(2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file name is “*.ak5”. [OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded. 7-3. Note (1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change. <KM078601> 2006/08 - 17 - ASAHI KASEI [AKD4705-A] MEASUREMENT RESULTS Audio [Measurement condition] • Measurement unit : Audio Precision System two Cascade • MCLK : 256fs • BICK : 64fs : 48kHz • fs : 10Hz∼20kHz • BW : 18bit • Bit • Power Supply : VD=5V, VDD1=5V, VDD2=5V, VP=12V • Interface : DIR • Temperature : Room • Volume#0=Volume#1=0dB • Measurement signal line path: DAC → Volume#0 → Volume#1 → TVOUTL/R Parameter S/(N+D) at 2Vrms Output DR S/N Input signal 1kHz, 0dBFS 1kHz, -60dBFS “0” data Measurement filter 20kLPF 22kLPF, A-weighted 22kLPF, A-weighted Results [dB] 93.3 96.8 97.0 Plots Figure 1-1. FFT (1kHz, 0dBFS input) at 2Vrms output Figure 1-2. FFT (1kHz, -60dBFS input) Figure 1-3. FFT (Noise floor) Figure 1-4. FFT (Out-of band noise) Figure 1-5. THD+N vs. Input Level (fin=1kHz) Figure 1-6. THD+N vs. fin (Input Level=0dBFS) Figure 1-7. Linearity (fin=1kHz) Figure 1-8. Frequency Response (Input Level=0dBFS) Figure 1-9. Crosstalk (Input Level=0dBFS) <KM078601> 2006/08 - 18 - ASAHI KASEI [AKD4705-A] Video [Measurement condition] • Signal Generator : Sony Tectonics TG2000 • Measurement unit : Sony Tectonics VM700T • Power Supply : VD=5V, VDD1=5V, VDD2=5V, VP=12V : BNC • Interface : Room • Temperature • Measurement signal line path: ENCV → TVVOUT, ENCRC → TVRC Parameter S/N Crosstalk DG DP Measurement conditions Input = 0% flat field Filter = Uni-weighted, BW= 15kHz to 5MHz Input = 100%red(ENCRC), Measured at TVVOUT Input = Modulated Lamp Input = Modulated Lamp Results 73.1 Unit dB -58.9 dB 0.67 0.83 % deg. Plots Figure 2-1. Noise spectrum (Input=0%flat field, BW=15kHz to 5MHz, uni weighted) Figure 2-3 Crosstalk (Input= 100% red (ENCRC), measured at TVVOUT) Figure 2-4 DG, DP (Input= Modulated Lamp) <KM078601> 2006/08 - 19 - ASAHI KASEI [AKD4705-A] Plots (Audio) AKM AK4705 DAC TVOUT S/(N+D) fs=48kHz +0 -20 -40 -60 d B r -80 A -100 -120 -140 -160 20 50 100 200 500 1k 2k 5k 10k 20k 2k 5k 10k 20k Hz Figure1-1. FFT (fin=1kHz Input Level=0dBFS) AKM AK4705 DAC TVOUT DR fs=48kHz +0 -20 -40 -60 d B r -80 A -100 -120 -140 -160 20 50 100 200 500 1k Hz Figure-1-2. FFT (fin=1kHz Input Level=-60dBFS) <KM078601> 2006/08 - 20 - ASAHI KASEI [AKD4705-A] AKM AK4705 DAC TVOUT S/N fs=48kHz +0 -20 -40 -60 d B r -80 A -100 -120 -140 -160 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure1-3. FFT (Noise Floor) Figure1-4. FFT (Outband Noise) AKM AK4705 DAC THD+N vs fin fs=48kHz -70 -73 -76 -79 -82 d B r -85 A -88 -91 -94 -97 -100 20 50 100 200 500 1k 2k Hz Figure1-5. THD+N vs. Input level (fin=1kHz) <KM078601> 2006/08 - 21 - ASAHI KASEI [AKD4705-A] AKM AK4705 DAC THD+N vs Input Level fs=48kHz -70 -73 -76 -79 -82 d B r -85 A -88 -91 -94 -97 -100 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure1-6. THD+N vs. Input Frequency (Input level=0dBFS) AKM AK4705 DAC Linerarty fs=48kHz +0 -12 -24 -36 -48 d B r -60 A -72 -84 -96 -108 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 +0 dBFS Figure1-7.Linearity (fin=1kHz) <KM078601> 2006/08 - 22 - ASAHI KASEI [AKD4705-A] AKM AK4705 DAC Frequency Responce fs=48kHz +1 +0.8 +0.6 +0.4 +0.2 d B r +0 A -0.2 -0.4 -0.6 -0.8 -1 20 50 100 200 500 1k 2k 5k 10k 20k 5k 10k 20k Hz Figure1-8. Frequency Response (Input level=0dBFS) AKM AK4705 DAC Crosstalk fs=48kHz -60 -65 -70 -75 -80 -85 d B -90 -95 -100 -105 -110 -115 -120 20 50 100 200 500 1k 2k Hz Figure1-9. Crosstalk (Input level=0dBFS) <KM078601> 2006/08 - 23 - ASAHI KASEI [AKD4705-A] Plots(Video) Figure 2-1. Noise spectrum (Input=0%flat field, BW=15kHz to 5MHz, uni weighted) <KM078601> 2006/08 - 24 - ASAHI KASEI [AKD4705-A] Figure 2-3 Crosstalk (Input= 100% red (ENCRC), measured at TVVOUT) Figure 2-4 DG, DP (Input= Modulated Lamp) <KM078601> 2006/08 - 25 - ASAHI KASEI [AKD4705-A] Revision History Date (YY/MM/DD) 05/09/27 06/08/30 Manual Board Reason Revision Revision KM078600 0 First Edition KM078601 0 Modification Contents Comment addition P1. Title: Evaluation board Rev.0 for AK4705 AK4705 Evaluation Board Rev.0 P3. 1)-1 DIP switch set-up: Table1 Add (Note) AK4112B: DIF1=“L” Add “Default ” P4. Notes 4. Modification 24bit I2S 24bit I2S (Default) P4. Note3, Note4: Delete the check mark of MUTE, STBY Comment addition Error Correct P5-P7. JP1 (EXT), JP2 (MCLK), JP3 (BICK), JP4 (SDTI), JP5 (LRCK), JP7 (GND): Add “Short”, “Open”, “Default ” JP6 (RX): Add “TORX”, “BNC”, “Default ” JP12 (VCRRC): Add “I”, “I/O”, “Default ” P8. DIP-switch (S1) List: Switch Name: DIF0, Default: OFF ON Switch Name: DIF2: Default: OFF ON P8. Jumper List: No.1: EXT Short: X’tal (default) Open: X’tal (Default) Open: External clock via BNC (J1) Short: External clock via BNC (J1) No.8: D-A Open: from the “D-5V” Jack.(default) Open: from the “D-5V” Jack. No.12: VCRRC “I” side: Input to VCRRC from VCRRC jack “I” side: Input to VCRRC from VCRRC jack (Default) P25. Figure 2-3. Y/C Crosstalk: Plot Correct <KM078601> 2006/08 - 26 - ASAHI KASEI [AKD4705-A] IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. • Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. • AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. • It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. <KM078601> 2006/08 - 27 - 5 4 3 2 1 37 38 39 40 41 42 43 44 45 46 47 48 CN1 1 CN3 D CN4 C17 2 C16 + 36 1 VCRC 2 VVSS 3 TVVOUT 4 VVD2 C23 + VSS 38 VD 39 MCLK BICK SDTI 40 41 42 LRCK SCL 43 44 SDA PDN 45 46 RFV 37 C12 VP 34 MONOOUT 33 TVOUTL 32 TVOUTR 31 VCROUTL 30 VCROUTR 29 TVINL 28 26 VCRINR 25 C18 33 0.1u C20 +C21 0.1u 10u C 32 31 30 29 28 24 13 10 23 B 22 ENCC ENCRC 34 10u 0.1u TVSB VCRINL VCRSB ENCG INT TVINR 11 VCRB ENCB 27 12 C19 36 10 VCRG 9 REFI 21 8 VVD1 9 20 0.1u 8 VCRRC 10k TVB VCRFB R555 7 19 C14 10u 35 AK 4705 18 + 7 TVG VCRVIN 10u 35 (VSS) DVCOM U3 TVVIN C15 TVRC 6 17 6 5 16 0.1u ENCY C22 C ENCV 10u C13 PVCOM 15 + 5 14 4 VCRVOUT TVFB (VVSS) 3 47 48 0.1u 10u + D B 27 11 26 24 23 22 21 20 19 18 17 16 15 14 13 12 25 CN2 A A Title Size AKD4705-A-48LQFP AK4705 Document Number A Date: 5 4 3 Sheet 2 1 of 1 Rev 1 0 5 4 3 2 1 R1 4112B_3.3V C1 5.1 0.1u 10u C3 + U2A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 JP1 2 EXT 22p 2 74HCU04 C5 J1 BNC (OPEN) R3 75 C 22p 12.288MHz 1 C6 X1 (OPEN) DVDD DVSS TVDD V/TX XTI XTO PDN R AVDD AVSS RX1 DIF0/RX2 DIF1/RX3 DIF2/RX4 CM0/CDTO CM1/CDTI OCKS1/CCLK OCKS0/CSN MCK01 MCK02 DAUX BICK SDTO LRCK ERF FS96 P/S AUTO 28 27 26 25 24 23 22 21 20 19 18 17 16 15 INTRUPT JP2 JP3 JP4 JP5 MCLK R6 4112B_3.3V C7 C8 + 0.1u 10u B 47u R11 100 6 5 5 GND VCC GND OUT C9 TORX176 0.1u R7 A 5 AK4112B ERF 1k LE2 R5 6 74HCU04 10 9 8 7 6 C 4 1k V U2D Logic 9 CM0 DIF0 DIF2 8 10 74HCU04 U2F 13 74HCU04 JP6 RX TORX BNC(RX) C11 BNC A Title 0.1u Size Document Number A Date: 5 12 10u 470 75 B U2E 11 C10 + J2 R8 LRCK LE1 R-PACK5R 4 3 2 1 BICK 100 PORT2 6 MCLK 74HCU04 5 4 3 2 1 L1 100 SW DIP-5 RP1 Logic 100 R12 R4 U2C 18k R9 Logic 3 1 2 3 4 5 D SDTI S1 CM0 DIF0 DIF2 Logic 10k R10 74HCU04 DIF2 R2 EXT 300 BICK SDTI LRCK AK4112BVF DIF0 PORT1 10 9 8 7 6 R82 10k R83 U2B PDN 1 2 3 4 5 Logic U1 0.1u Logic 1 CM0 C4 10u D MCLK BICK LRCK SDATA C2 + 4 3 AKD4705-A AK4112B Sheet 2 Rev 1 of 1 6 0 CN1 VCRC MCLK BICK SDTI LRCK SCL 2 1 +5V CN3 37 38 39 40 41 42 43 44 45 46 47 TVFB 48 D SDA VCRVOUT 3 PDN 4 RFV 5 1 D CN4 36 2 (VVSS2) 35 TVVOUT 3 VVD2 4 TVRC 5 34 +12V 33 MONOOUT 32 TVOUTL 31 TVOUTR 30 VCROUTL 29 VCROUTR C C TVG 6 TVB 7 VVD1 8 ENCB 9 ENCG 10 ENCRC 11 ENCC 12 28 CN2 Analog Ground VCRSB INTRUPT VCRB VCRG VCRRC VCRFB VCRVIN TVVIN GND ENCY JP7 TVSB ENCV A Title Document Number A Date: 5 4 3 27 TVINL 26 TVINR 25 VCRINL VCRINR A Size Digital Ground B 24 23 22 21 20 19 18 17 16 15 14 13 B AKD4705-A AK4705 Sheet 2 Rev 2 of 1 6 0 5 C24 2 R15 VCRINR R17 0.47u (open) R16 10u 300 J4 MONOOUT R18 300 10k (VVSS) (VVSS) C26 R20 C27 R19 10u VCRINL R21 0.47u D MONOOUT + J5 VCRINL C25 300 + (VVSS) 1 + J3 VCRINR 3 + D 4 (VVSS) J6 TVOUTL TVOUTL R22 300 10k (open) C29 10u 300 (open) (VVSS) C30 TVOUTR C R25 10k (VVSS) (VVSS) R28 C31 R27 10u TVINL R29 0.47u (VVSS) J7 TVOUTR + J9 TVINL 300 300 + (VVSS) FOR Analog input TVINR R26 0.47u R23 C28 R24 + J8 TVINR + C (VVSS) (VVSS) From Analog output (VVSS) J10 VCROUTL VCROUTL R30 300 10k (open) B (VVSS) R32 C33 10u 300 + B (VVSS) (VVSS) (VVSS) J12 VCROUTR VCROUTR R34 10k (VVSS) (VVSS) A A Title Size A Date: 5 4 3 AKD4705-A Document Number Rev Analog Input/Output Circuit Thursday, August 17, 2006 3 6 of Sheet 2 1 0 5 4 R35 3 U4 R36 2 3 4 5 6 7 8 9 A1 A2 A3 A4 A5 A6 A7 A8 1 19 G1 G2 Logic D PORT3 1 2 3 4 5 10 9 8 7 6 10k 470 R39 R40 10k 470 SCL SDA SDA(ACK) R41 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 2 100 R37 18 17 16 15 14 13 12 11 SCL Logic D1 R38 10k U5A 1 H L U5B 2 3 74HCT14 D 4 PDN 74HCT14 C34 SW1 74HCT541 51 1 0.1u PDN uP-I/F 1 U6A 2 74LS07 3 U6B 4 74LS07 U5C 5 6 74HCT14 U5D R42 U6C 6 74LS07 5 C 9 Logic 10k R43 8 74HCT14 U5E 11 10 SDA (short) SDA(ACK) 9 74HCT14 U5F 13 12 11 74HCT14 D5V +5V R44 JP9 L2 3 Logic D-A REG 10u B C37 C38 +C39 47u OUT IN 1 +12V C35 2 + + 0.1u 0.1u (short) C36 47u Logic (short) 1 4112B_3.3V C49 R14 5.1 0.1u JP10 C46 47u OUT IN + 2 VVD1 GND T2 LP2950A +5V A 3 C41 C42 C43 C44 C45 0.1u 0.1u 0.1u 0.1u 0.1u + C40 47u Logic C47 + C48 47u 0.1u for 74HCT14, 74HCU04, 74LS07, 74HCT541 VDD1 A VVD2 Title R13 JP11 (short) VDD2 Size VVD2 AKD4705-A POWER SUPPLY Document Number A Date: 5 B 47u R45 VVD1 C +12V T1 NJM78M05FA GND JP8 13 U6D 8 74LS07 U6E 10 74LS07 U6F 12 74LS07 4 3 Sheet 2 4 of 1 Rev 6 0 5 4 J13 ENCB R70 3 2 J14 VCRVIN C50 1 R77 C51 (short) 0.1u ENCB (short) R46 75 D VCRVIN R47 75 0.1u (VVSS2) (VVSS2) J15 ENCG (VVSS2) R71 (VVSS2) D J16 VCRFB C52 R78 ENCG R48 (short) VCRFB R49 75 0.1u 75 (VVSS2) (VVSS2) J17 ENCRC (VVSS2) R72 300 (VVSS2) JP12 J18 VCRRC C53 I R79 C54 (short) 0.1u ENCRC R50 75 (short) VCRRC I/O VCRRC R51 75 0.1u VCRCOUT C (VVSS2) (VVSS2) J19 ENCC (VVSS2) R73 J20 VCRG C55 C56 R80 ENCC R52 75 (VVSS2) (short) VCRG R53 75 0.1u (VVSS2) J21 ENCV (VVSS2) R74 C57 (short) 0.1u (short) 0.1u R81 C58 (short) 0.1u (VVSS2) J22 VCRB ENCV B R54 75 (VVSS2) VCRB R55 75 (VVSS2) (VVSS2) J23 ENCY R75 J24 VCRSB C59 (VVSS2) A (short) R56 VCRSB 0.1u (VVSS) R76 C60 (short) 0.1u (VVSS2) (VVSS) A TVVIN R59 75 300 R58 10K (VVSS2) J25 TVVIN Title Size A (VVSS2) Date: 5 B (VVSS2) ENCY R57 75 C (VVSS2) 4 3 AKD4705-A Document Number Rev Video Block Input Circuit 5 6 of Sheet 2 1 0 5 4 3 J27 R61 1 R67 VCRCOUT 75 300 VCRC D 2 J33 RFV RFV VCRCOUT D (VVSS2) (VVSS2) J29 R63 TVVOUT 75 R60 TVVOUT J26 75 TVFB R62 J28 TVFB (VVSS2) J30 R64 (VVSS2) TVRC 75 TVRC 300 TVSB TVSB C C (VVSS2) J31 R65 (VVSS2) TVG 75 TVG (VVSS2) J32 R66 TVB 75 TVB B B (VVSS2) J34 R68 VCRVOUT 75 VCRVOUT (VVSS2) A A Title Size A Date: 5 4 3 AKD4705-A Document Number Rev Video Block Output Circuit 6 6 of Sheet 2 1 0