AS1545 D a ta S he e t Dual, 12-Bit, 1MSPS, SAR ADC 1 General Description 2 Key Features The AS1545 is a dual, 12-bit, 6-channel, 1 MSPS, high speed, successive approximation (SAR) analog-todigital converters (ADCs). The AS1545 is designed to operate with a single +2.7V to +5.25V supply and a sampling rate of up to 1 MSPS. The device contains two ADCs, each preceded by a 6channel multiplexer and a high-bandwidth track/hold amplifier. Data access is made via standard control inputs in support of wide range of microprocessors and DSPs. The device requires very low supply-current at the 1MSPS maximum sampling speed, and features flexible power-down modes to reduce power consumption at slower throughput rate. The AS1545 contains an internal 2.5V reference and integrated reference buffer that can be over driven when an external reference is required. Superior AC characteristics, low power consumption, and highly reliable packaging makes the AS1545 perfect for portable battery-powered remote sensors and dataacquisition devices. ! Sampling Rate: 1MSPS per ADC ! Dual 12-bit serial interface ! Software Configurable Analog Input Types: ! - 12-Channel Single-Ended - 6-Channel Pseudo-Differential - 6-Channel Fully Differential Internal +2.5V Reference or External: 1V to VDD ! Rail to Rail Common Mode Input Range ! Low-Power Consumption ! - 15mW max. at 1MSPS with 2.7V supplies - 37mW max. at 1MSPS with 5.25V supplies Dual conversion with read at 20 MHz SCLK ! Single-Supply Operation: +2.7V to +5.25V ! Motor Control Registers: Difference of Inputs, Quadrature Signal Phases, Direction and Step Down Counter ! 32-lead TQFN Package 3 Applications The AS1545 is available in a 32-lead TQFN package. The device is ideal for motor control like encoder feedback or current sense, motion control such as robotics, sonar, or for any other radio frequency identification. Figure 1. Block Diagram REF_SELECT REF BUF MUX T/H DVDD System Control Registers AIN 0 AIN 1 AIN 2 AIN 3 AVDD REFA 12-Bit SAR and A/D Conversion Control OutPut Drivers AIN 4 AIN 5 DOUTA SCLK CSN RANGE SGL/DIFF A0 A1 A2 Control Logic and System Control Registers BIN 0 BIN 1 VDRIVE BIN 2 BIN 3 MUX 12-Bit SAR and A/D Conversion Control T/H OutPut Drivers DOUTB BIN 4 BIN 5 BUF AGND www.austriamicrosystems.com AGND AGND REFB Revision 1.00 DGND DGND 1 - 34 AS1545 Data Sheet - A p p l i c a t i o n s Contents 1 2 3 4 5 6 7 8 9 General Description ................................................................................................................................................ Key Features ........................................................................................................................................................... Applications ............................................................................................................................................................. Pinout ...................................................................................................................................................................... 1 1 1 3 Pin Assignment .................................................................................................................................................... 3 Pin Description 3 Absolute Maximum Ratings .................................................................................................................................... 5 Electrical Characteristics ......................................................................................................................................... 6 Timing Characteristics ..................................................................................................................................... 9 Typical Operating Characteristics ......................................................................................................................... 10 Terminology ........................................................................................................................................................... 15 Detailed Description .............................................................................................................................................. 18 Analog Input ....................................................................................................................................................... Acquisition Time ............................................................................................................................................ Analog Input Composition ............................................................................................................................. Analog Input Modes ...................................................................................................................................... Single-Ended Mode ....................................................................................................................................... Fully Differential Mode .................................................................................................................................. Pseudo Differential Mode .............................................................................................................................. Analog-to-Digital Conversion ............................................................................................................................. Output Coding ............................................................................................................................................... Transfer Functions ........................................................................................................................................ Digital Inputs ...................................................................................................................................................... VDRIVE Functionality..................................................................................................................................... 10 Application Information ....................................................................................................................................... 18 18 19 20 21 21 22 23 23 23 24 24 25 Operation Modes ............................................................................................................................................... 25 Full Power-Up Mode ..................................................................................................................................... 25 Full Power-Down Mode ................................................................................................................................. 25 Partial Power-Down Mode ............................................................................................................................ 26 Power-Up Times ........................................................................................................................................... 27 Power vs. Throughput Rate .......................................................................................................................... 28 Serial Interface ................................................................................................................................................... 28 Difference calculator and quadrature signals calculator ................................................................................ 29 Direction of the rotor based on DIR bit .......................................................................................................... 30 11 Application Hints .................................................................................................................................................. 31 Grounding and Layout ................................................................................................................................... 31 PCB Design Guidelines for TQFN ................................................................................................................. 31 12 Package Drawings and Markings ........................................................................................................................ 32 13 Ordering Information ........................................................................................................................................... 33 www.austriamicrosystems.com Revision 1.00 2 - 34 AS1545 Data Sheet - P i n o u t 4 Pinout Pin Assignment VDRIVE DOUTA DGND DOUTB CSN A0 32 31 30 29 28 27 26 25 SCLK DVDD Figure 2. Pin Assignments (Top View) 1 24 A1 REF_SELECT 2 23 A2 22 SGL/DIFF DGND AVDD 3 AS1545 REFA 4 AGND 5 20 REFB AGND 6 19 AGND BIN 5 18 BIN 0 17 BIN 1 BIN 2 13 14 15 16 BIN 3 11 12 BIN 4 10 AIN 5 9 AIN 4 33 Exp. Pad AIN 3 7 8 AIN 2 AIN 0 AIN 1 21 RANGE Pin Description Table 1. Pin Description Pin Number Pin Name 1, 29 DGND 2 REF_SELECT 3 AVDD Description Digital Ground. Ground reference point for the digital portion of the AS1545. Reference select pin. Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5V reference is used as the reference source for both ADC A and ADC B. In addition, Pin REFA and Pin REFB must be tied to decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AS1545 through the REFA or REFB pins. Analog Supply Voltage. 2.7V to 5.25V. 4, 20 REFA, REFB Reference Input/Output. These pins are connected to the internal reference through a series resistor and is the reference source for the AS1545. The nominal reference voltage is 2.5V and appears at the pin. This pin can be over-driven by an external reference or can be taken as high as AVDD. Decoupling capacitors (4.7 uF recommended) are connected to these pins to decouple the reference buffer for each respective ADC. 5 AGND Analog Ground. Decouple point for AVDD. Ground reference for track/hold, reference, and DAC circuits. 6, 19 AGND Analog Ground. Decouple point for VREF capacitors and analog input filters. Pin 6 is the decoupling point for REFA, pin 19 for REFB. Ground reference for track/hold, reference, and DAC circuits. 7 to 12 AIN0 to AIN5 www.austriamicrosystems.com Analog Inputs of ADC A. These may be programmed as six single-ended channels, three pseudo-differential or three true-differential analog input channel pairs. Revision 1.00 3 - 34 AS1545 Data Sheet - P i n o u t Table 1. Pin Description Pin Number Pin Name Description BIN0 to BIN5 Analog Inputs of ADC B. These may be programmed as six single-ended channels, three pseudo-differential or three true-differential analog input channel pairs. (see Table 5 on page 20). 21 RANGE Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input channels. If this pin is tied to a logic low, the analog input range is 0V to VREF. If this pin is tied to a logic high when CSN goes low, the analog input range is 2 × VREF. 22 SGL/DIFF 23 to 25 A2 to A0 Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and so on. 26 CSN Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AS1545 and framing the serial data transfer. 27 SCLK Serial Clock Input. A serial clock input provides the SCLK for accessing the data from the AS1545. This clock is also used as the clock source for the conversion process. DOUTB, DOUTA Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input and 15 SCLKs are required to access the data. The data simultaneously appears on both pins from the simultaneous conversions of both ADCs. The data stream consists of three leading zeros followed by the 12 bits of conversion data. The data is provided MSB first. If CSN is held low for 16 SCLK cycles rather than 15, then single trailing zero appears after the 12bits of data. If CSN is held low for a further 16 SCLK cycles on either DOUTA or DOUTB, futher data is clocked out according to the timing diagram. VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. This pin should be decoupled to DGND. The voltage at this pin may be different than that at AVDD and DVDD but should never exceed either by more than 0.3V. 32 DVDD Digital Supply Voltage. 2.7V to 5.25V. This is the supply voltage for all digital circuitry on the AS1545. The DVDD and AVDD voltages should ideally be at the same potential and must not be more than 0.3V apart even on a transient basis. This supply should be decoupled to DGND. 33 Exp. Pad 13 to 18 28, 30 31 www.austriamicrosystems.com Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A logic low selects differential operation while a logic high selects single-ended operation. Exposed Pad. This pin can be not connected or connected AGND. The exposed pad must not be connected to VDD. Revision 1.00 4 - 34 AS1545 Data Sheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical Characteristics on page 6 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Min Max Units VDD to AGND -0.3 +7 V DVDD to DGND -0.3 +7 V VDRIVE to DGND -0.3 DVDD V VDRIVE to AGND -0.3 AVDD V AVDD to DVDD -0.3 +0.3 V AGND to DGND -0.3 +0.3 V Analog Input Voltage to AGND -0.3 AVDD + 0.3 V Digital Input Voltage to DGND -0.3 +7 V Digital Output Voltage to DGND -0.3 VDRIVE + 0.3 V REFA, REFB to AGND -0.3 AVDD + 0.3 V ±10 mA Input Current to All Pins Except AVDD or DVDD Electro-Static Discharge 2 kV Operating Temperature Range -40 +85 ºC Storage Temperature Range -65 +150 ºC Package Body Temperature www.austriamicrosystems.com +260 Revision 1.00 ºC Comments The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Mount Devices”. The lead finish for Pb-free leaded packages is matte tin (100% Sn). 5 - 34 AS1545 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics AVDD = DVDD = 2.7V to 5.25V, VDRIVE = 2.7 V to AVDD/DVDD, fSCLK = 20 MHz, fSAMPLE = 1 MSPS, TAMB = -40 to +85°C, external reference = 2.5V, RANGE = 0, Typical values at 5.25V and 25°C with external reference; Unless otherwise specified. Table 3. Electrical Characteristics Symbol Parameter Condition Min Typ 70 72 71 72.5 Max Unit Dynamic Specifications 50kHz sinewave input SINAD Signal to Noise + Distortion Ratio SNR Signal-to-Noise Ratio THD Total Harmonic Distortion SFDR Spurious-Free Dynamic Range SINAD Signal to Noise + Distortion SNR Signal-to-Noise Ratio THD Total Harmonic Distortion SFDR Spurious-Free Dynamic Range IMD Intermodulation Distortion Fully Differential Mode Single Ended or Pseudo Differential Mode -81 -77 -83 -75 68 72 69 72.5 -81 -73 -83 -75 Second Order Terms -75 Third Order Terms -100 Channel-to-Channel Isolation dB dB dB -90 Sample and Hold Aperture Delay 13 Aperture Jitter 30 Aperture Delay Matching Full Power Bandwidth ns ps 200 3 dB, VDD = 5V 39 3 dB, VDD = 3V 35 0.1 dB, VDD = 5V 3.1 0.1 dB, VDD = 3V 2.9 Fully Differential Mode ±0.4 ±0.99 Single-Ended and Pseudo Differential Modes ±0.4 ±0.99 Differential mode ±0.25 ±0.99 Single-Ended and Pseudo Differential Modes ±0.25 ±0.99 ±0.5 ±6 ps MHz MHz DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity 12 Bits LSB LSB Straight Binary Output Coding Offset Error Offset Error Match Gain Error Single-Ended and PseudoDifferential Mode Gain Error Match www.austriamicrosystems.com ±0.5 ±0.75 ±0.5 Revision 1.00 ±2.5 LSB LSB 6 - 34 AS1545 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 3. Electrical Characteristics (Continued) Symbol Parameter Condition Min Typ Max Unit Twos Complement Output Coding Positive Gain Error ±2 Positive Gain Error Match Zero Code Error Zero Code Error Match ±0.5 ±0.5 Fully Differential Mode ±5 ±0.5 Negative Gain Error ±2 Negative Gain Error Match ±0.5 LSB LSB LSB Analog Input VINx Single Ended Input Voltage Ranges VINx - VINy Pseudo Differential Input Voltage Ranges VINx & VINy Differential Input Voltage Ranges VCM Common Mode Voltage Bit RANGE = 0 0 VREF Bit RANGE = 1 0 2xVREF Bit RANGE = 0 VCM VCM+VREF Bit RANGE = 1 VCM VCM+ 2xVREF Bit RANGE = 0 VCMVREF/2 VCM+ VREF/2 Bit RANGE = 1 VCMVREF VCM+ VREF 0 VDD V ±1 µA VDD V Leakage Current Absolute Analog Input Voltage Input Capacitance 0 V V V Track Mode 15 pF Hold Mode 8 pF Reference Input/Output REFIN Input Voltage Range 1 REFOUT Output Reference Voltage 2.475 ILEAK Leakage Current REFOUT TEMPCO 2.5 VDD V 2.525 V ±1 µA Input Capacitance 30 pF REFA, REFB Output Impedance 5 Ω Reference Temperature Coefficient 30 ppm/ºC Logic Inputs VIH Input High Voltage VIL Input Low Voltage IIN Input Current CIN Input Capacitance VDD < 5V 0.7x VDRIVE VDD > 5V 2.8 VIN = 0 V or VDRIVE V -1 0.4 V +1 µA 5 pF Logic Outputs VOH Output High Voltage ISOURCE = 200µA VOL Output Low Voltage ISINK = 200µA www.austriamicrosystems.com Revision 1.00 VDRIVE - 0.2 V 0.4 V 7 - 34 AS1545 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Table 3. Electrical Characteristics (Continued) Symbol Parameter Condition Floating State Leakage Current DOUT = GND or VDD Min Floating State Output Capacitance Output Coding Typ Max Unit ±1 µA 7 pF Straight binary (Single-Ended & Pseudo-Differential) Two’s complement (Fully Differential) Conversion Rate tCONV Conversion Time tACQ Track/Hold Acquisition Time Exclusive of tACQ 15tSCLK Full-scale step input; VDD = 5V 90 Full-scale step input; VDD = 3V 110 Throughput Rate ns 1 MSPS 2.7 5.25 V 2.7 AVDD/ DVDD V Power Requirements VDD Positive Supply Voltage VDRIVE Interface Supply Voltage Normal Mode (Static) Operational, fS = 1 MSPS IDDA+IDDD Partial Power-Down Mode AVDD = DVDD VDD = 5.25V, internal Ref. on 4 5 mA VDD = 5.25V, internal Ref. on 6.5 7 mA VDD = 2.7V, internal Ref. on 5.2 5.5 mA 500 µA 1 µA VDD = 5.25V, internal Ref. on, Static Full Power-Down Mode PD Operational, fS = 1 MSPS VDD = 5.25V, internal Ref. on 36.75 mW Partial Power-Down VDD = 5.25V, internal Ref. on 2.6 mW 5.25 µW Full Power-Down www.austriamicrosystems.com Revision 1.00 8 - 34 AS1545 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s Timing Characteristics AVDD = DVDD = 2.7V to 5.25V, VDRIVE = 2.7V to AVDD/DVDD, internal/external reference = 2.5V, TA = -40 to +85°C (unless otherwise specified). Table 4. Timing Characteristics 1 Parameter Symbol Master Clock Frequency fSCLK Conversion Time tCONVERT Conditions Min Typ Max Units 20 MHz tSCLK = 1/fSCLK 15 x tSCLK ns fSCLK = 20 MHz 750 1 Quiet Time tQUIET Minimum time between end of serial read and next falling edge of CSN 30 ns CSN Fall to SCLK Fall Setup Time tCSS VIL of CSN to VIL of SCLK 10 ns CSN Fall to DOUT Enable tCSDOE VIL of CSN to Corner of DOUT 15 VDD = 2.7V 40 VDD = 5.25V 10 2 tDOV SCLK Fall to DOUT Valid SCLK Fall to DOUT Hold 3 tDOH VDD = 2.7V 10 VDD = 5.25V 5 ns ns ns SCLK Low Pulse Width tCL VIL to VIL of SCLK 0.4 tSCLK 0.6 tSCLK SCLK High Pulse Width tCH VIH to VIH of SCLK 0.4 tSCLK 0.6 tSCLK CSN Rise to DOUT Disable tCSDOD VIH of CSN to corner of DOUT to Tristate CSN Minimum Pulse Width tCSPW VIH to VIH of CSN 30 SCLK Fall to DOUT Disable tDOD VIH of SCLK to corner of DOUT to Tristate 5 20 ns ns 50 ns 1. Based on simulation and characterised samples. 2. VIL of SCLK to VOH of DOUT (rising edge) / VOL of DOUT (falling edge) 3. VIL of SCLK to VOL of DOUT (rising edge) / VOH of DOUT (falling edge) Figure 3. Timing Diagram CSN tCSPW tCSS SCLK tCH 1 2 3 4 B 5 14 tCL tDOH tCSDOE DOUTA 0 0 DB11 0 DOUTB THREESTATE 3 LEADING ZEROES www.austriamicrosystems.com tCSDOD tDOV DB10 DB9 Revision 1.00 DB2 DB1 DB0 tQUIET THREE-STATE 9 - 34 AS1545 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s 7 Typical Operating Characteristics VDD = 5.25V, VREF = 2.5V, fSCLK = 20MHz (50% duty), fSAMPLE = 1MSPS, CREF = 4.7µF, RANGE = 0, SGL/DIFF = 1, TAMB = +25ºC (unless otherwise specified). Figure 4. Integral Nonlinearity vs. Digital Output Code; Figure 5. Diff. Nonlinearity vs. Digital Output Code; 1 1 External Reference 0.8 0.8 0.6 0.6 0.4 0.4 DNL (LSB) . INL (LSB) . External Reference 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1 -1 0 1024 2048 3072 4096 0 1024 Digital Output Code 2048 Figure 6. Integral Nonlinearity vs. Digital Output Code; 1 Internal Reference Internal Reference 0.8 0.8 0.6 0.6 0.4 0.4 DNL (LSB) . INL (LSB) . 4096 Figure 7. Diff. Nonlinearity vs. Digital Output Code; 1 0.2 0 -0.2 0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 -0.8 -0.8 -1 -1 0 1024 2048 3072 4096 0 1024 Digital Output Code 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 FFT (dBc) . 100 200 300 400 20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 500 Input Signal Frequency (kHz) www.austriamicrosystems.com 3072 4096 Figure 9. FFT @ 50kHz, Internal Reference; fSAMPLE = 1Msps NFFT = 65536 SNR=72.8dB THD = -84.6dB SFDR = 88.2dB SINAD = 72.5dB 0 2048 Digital Output Code Figure 8. FFT @ 50kHz, External Reference; FFT (dBc) . 3072 Digital Output Code fSAMPLE = 1Msps NFFT = 65536 SNR=72.2dB THD = -84.7dB SFDR = 87.9dB SINAD = 71.9dB 0 100 200 300 400 500 Input Signal Frequency (kHz) Revision 1.00 10 - 34 AS1545 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 10. Supply Current vs. Sampling Rate; Figure 11. Supply Current vs. Supply Voltage; 10 10 Vdd=5V 9 1M SPS 9 . 8 . 8 Supply Current (mA) 7 Supply Current (mA) Vdd=3V 7 6 5 4 3 2 1 st atic 6 5 4 3 2 1 0 0 0 200 400 600 800 1000 2.7 3 3.3 3.6 Sampling Rate (ksps) Figure 12. Supply Current vs. Temperature; . Full Power-Down Current (nA) . Supply Current (mA) 9 6 5 4 3 2 1 0 -45 -30 -15 8 7 6 5 4 3 2 1 0 0 15 30 45 60 75 90 2.7 3 3.3 3.6 Temperature (°C) 5.1 5.4 510 . Vdd=5V Vdd=3V Part. Power-Down Current (µA) . 4.5 4.8 Figure 15. Partitial Power-Down Current vs. Temp.; 20 Full Power-Down Current (nA) 3.9 4.2 Supply Voltage (V) Figure 14. Full Power-Down Current vs. Temperature; 18 5.1 5.4 10 Vdd=5V, 1M SPS Vdd=5V, stat ic Vdd=3V, 1M SPS Vdd=3V, st atic 9 7 4.5 4.8 Figure 13. Full Power-Down Current vs. VIN; 10 8 3.9 4.2 Supply Voltage (V) 16 14 12 10 8 6 4 2 0 -45 -30 -15 0 15 30 45 60 75 90 Vdd=5V 490 470 450 430 410 390 370 -45 -30 -15 Temperature (°C) www.austriamicrosystems.com Vdd=3V 0 15 30 45 60 75 90 Temperature (°C) Revision 1.00 11 - 34 AS1545 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 16. Part. Power-Down vs. Temperature; Figure 17. Dynamic Performance vs. Supply Voltage; 500 . 450 Dynamic Performance (dB) Part. Power-Down Current (µA) . 90 400 350 300 Int. Ref = OFF 250 Int. Ref = ON 200 150 100 50 85 80 75 70 SINAD SNR 65 THD SFDR 0 60 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 2.7 Supply Voltage (V) 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 Supply Voltage (V) Figure 18. Gain & Offset Error vs. Supply Voltage; Figure 19. SINAD vs. Input Frequency, Single-Ended; 74 3 Off set Error 2 72 1 SINAD (dB) . Offset/Gain Error (LSB) . Gain Error 0 -1 70 68 Rin=10Ohm Rin=50Ohm Rin=100Ohm Rin=1kOhm 66 -2 -3 64 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 10 Supply Voltage (V) 100 1000 Input Frequency (kHz) Figure 20. SINAD vs. Input Frequency, Single-Ended; Figure 21. SINAD vs. Input Frequency, Differential; 74 75 72 SINAD (dB) . SINAD (dB) . 70 65 68 66 64 Vdd=5.25V Vdd=4.5V Vdd=3.6V Vdd=2.7V 60 70 Vdd=5.25V Vdd=4.5V Vdd=3.6V Vdd=2.7V 62 55 60 10 100 1000 10 Input Frequency (kHz) www.austriamicrosystems.com 100 1000 Input Frequency (kHz) Revision 1.00 12 - 34 AS1545 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 22. ENOB vs. ReferenceVoltage; Figure 23. THD vs. Input Frequency, Single-Ended; 12 -65 -70 THD (dB) . ENOB (bit) . 11.8 Rin=10Ohm Rin=50Ohm Rin=100Ohm Rin=1kOhm 11.6 11.4 11.2 -75 -80 -85 Vdd=5V Vdd=3V 11 -90 1 1.5 2 2.5 3 3.5 4 4.5 5 10 Reference Voltage (V) Figure 24. THD vs. Input Frequency, Single-Ended; 1000 Figure 25. THD vs Input Frequency, Differential; -50 -60 Vdd=2.7V Vdd=3.6V Vdd=4.5V Vdd=5.25V -55 Vdd=2.7V Vdd=3.6V Vdd=4.5V Vdd=5.25V -65 THD (dB) . -60 THD (dB) . 100 Input Frequency (kHz) -65 -70 -75 -70 -75 -80 -80 -85 -85 -90 -90 10 100 1000 10 Input Frequency (kHz) 1000 Figure 27. ENOB vs. Input Frequency, Differential; 12 12 11.6 11.6 ENOB (bit) . ENOB (bit) . Figure 26. ENOB vs. Input Frequency, Single-Ended; 11.2 10.8 Vdd=5.25V Vdd=4.5V Vdd=3.6V Vdd=2.7V 10.4 100 Input Frequency (kHz) 11.2 10.8 Vdd=5.25V Vdd=4.5V Vdd=3.6V Vdd=2.7V 10.4 10 10 10 100 1000 Input Frequency (kHz) www.austriamicrosystems.com 10 100 1000 Input Frequency (kHz) Revision 1.00 13 - 34 AS1545 Data Sheet - Ty p i c a l O p e r a t i n g C h a r a c t e r i s t i c s Figure 28. SNR vs. Input Frequency, Single-Ended; Figure 29. SNR vs. Input Frequency, Differential; 75 74 72 70 SNR (dB) . SINAD (dB) . 70 65 66 64 Vdd=5.25V Vdd=4.5V Vdd=3.6V Vdd=2.7V 60 68 Vdd=5.25V Vdd=4.5V Vdd=3.6V Vdd=2.7V 62 55 60 10 100 1000 10 100 Input Frequency (kHz) Figure 31. INL/DNL vs. Reference Voltage, VDD = 5V; 1 1 0.8 0.8 0.6 0.6 INL/DNL (LSB) . INL/DNL (LSB) . Figure 30. INL/DNL vs. Reference Voltage, VDD = 3V; 0.4 0.2 0 -0.2 -0.4 INLmax -0.6 0.4 0.2 0 -0.2 -0.4 INLmax -0.6 INLmin DNLmax -0.8 1000 Input Frequency (kHz) INLmin DNLmax -0.8 DNLmin DNLmin -1 -1 1 1.5 2 2.5 3 Reference Voltage (V) www.austriamicrosystems.com 1 1.5 2 2.5 3 3.5 4 4.5 5 Reference Voltage (V) Revision 1.00 14 - 34 AS1545 Data Sheet - Te r m i n o l o g y 8 Terminology Acquisition Time The Acquisition time is the time needed by the ADC to accurately acquire the analog input voltage in the internal sampling capacitor. During this time the ADC is in track mode. Conversion Time The Conversion Time is the time that the ADC needs to convert an acquired analog input into a corresponding digital code. A Successive Approximation Register ADC usually needs a number of clocks dependant on the resolution. During this time the ADC is in hold mode. Throughput / Sample Rate The Throughput or Sample Rate is the number of conversions performed by an ADC per second. It is usually specified in Samples Per Second (SPS). The Throughput or Sample Rate is the reciprocal of the sum of Acquisition Time and Conversion Time. Aperture Delay The Aperture Delay defines the time between the falling edge of CSN and the actual Sampling Instant. The Aperture Delay Matching defines the maximum deviation of Aperture Delays across all 6 channels of one ADC. Aperture Jitter The Aperture Jitter is the deviation of the actual Sampling Instant. This deviation is totally random and the standard deviation of the distribution is calculated with one sigma. Differential Nonlinearity (DNL) The Differential Nonlinearity is the deviation between the actual code widths to the ideal code widths of 1 LSB, comparing all contiguous codes in the ADC. The ADC is specified according to its maximum and minimum DNL values across all codes. A DNL value equal to -1 indicates a missing code in the transfer function. Integral Nonlinearity (INL) The Integral Nonlinearity measures the deviation from the actual transfer function to the best straight line that minimizes the INL worst case values. Offset Error The Offset Error defines the absolute deviation of the first code transition (0x000h) to (0x001h) from the ideal input voltage (AGND + 0.5 LSB) in Single Ended and Pseudo Differential Mode (binary output coding). VIN VREF Offset Error = --------------- × 4096 – AVG ( MeasuredCodes ) Offset Error Match The Offset Error Match defines the maximum deviation of the Offset Errors across all 6 channels of VIN in Single Ended and Pseudo Differential Mode (binary output coding). Gain Error The Gain Error defines the absolute deviation of the last code transition (0xFFEh) to (0xFFFh) from the ideal input voltage (VREF – 1.5 LSB) in Single Ended and Pseudo Differential Mode. The Offset Error is compensated. VIN VREF Gain Error = OffsetError – AVG ( MeasuredCodes ) – --------------- × 4096 Gain Error Match The Gain Error Match defines the maximum deviation of the Gain Errors across all 6 channels of VIN in Single Ended and Pseudo Differential Mode (binary output coding). www.austriamicrosystems.com Revision 1.00 15 - 34 AS1545 Data Sheet - Te r m i n o l o g y Zero Code Error The Zero Code Error is the deviation of the midscale transition (all 0xFFFh to all 0x000h in 2’s complement output coding) from the ideal input voltage (VIN+ - VIN- = 0V) in Fully Differential Mode. VINP – VINN VREF Zero Code Error = ----------------------------------- × 4096 + 2048 – AVG ( MeasuredCodes ) Zero Code Error Match The Zero Code Error Match defines the maximum deviation of the Zero Code Errors across all 6 channels of VIN in Fully Differential Mode (2’s complement output coding). Positive Gain Error The Positive Gain Error is the deviation last code transition (0x7FEh) to (0x7FFh) in 2’s complement output coding from the ideal input voltage (VIN+ - VIN- = +VREF - 0.5LSB @ Range=1 and +VREF/2 - 0.5LSB @ Range=0) in Fully Differential Mode. ⎧ VINP – VINN VREF ⎩ ⎫ Positive Gain Error =Zero Code Error – ⎨ ----------------------------------- × 4096 + 2048 – AVG ( MeasuredCodes ) ⎬ ⎭ Negative Gain Error The Negative Gain Error is the deviation first code transition (0x800h) to (0xFFFh) in 2’s complement output coding from the ideal input voltage (VIN+ - VIN- = -VREF + 0.5LSB @ Range=1 and -VREF/2 + 0.5LSB @ Range=0) in Fully Differential Mode. ⎧ VINP – VINN VREF ⎩ ⎫ Negative Gain Error = ⎨ ----------------------------------- × 4096 + 2048 – AVG ( MeasuredCodes ) ⎬ – ZeroCodeError ⎭ Positive / Negative Gain Error Match The Positive / Negative Gain Error Match defines the maximum deviation of the Positive / Negative Gain Errors across all 6 channels of VIN in Fully Differential Mode (2’s complement output coding). Signal-to-Noise Plus Distortion (SINAD) The Signal to Noise Plus Distortion Ratio defines the ratio between the RMS value of the fundamental (input signal) and the equivalent RMS value of all other spectral components below one-half the sampling frequency, including harmonics but excluding DC. SINAD will be equal to SNR in an distortion free ADC. Effective Number of Bits (ENOB) The Effective Number of Bits indicates the actual resolution of the converter. The ENOB can be calculated from the Signal to Noise Plus Distortion Ratio (SINAD). SINAD – 1,76 6,02 ENOB = ---------------------------------- Signal-to-Noise Ratio (SNR) The Signal to Noise Ratio defines the ratio between the RMS value of the fundamental (input signal) to the RMS value of the sum of all other spectral components below one-half of the sampling frequency, excluding harmonics and DC. The theoretical SNR for an ideal N bit ADC is limited by the quantization error and is described by the formula: SNR = 6.02*N +1.76 (dB) Therefore, for a 12-bit ADC, the maximum SNR is 74dB. www.austriamicrosystems.com Revision 1.00 16 - 34 AS1545 Data Sheet - Te r m i n o l o g y Total Harmonic Distortion (THD) The Total Harmonic Distortion is the ratio between the RMS value of the fundamental (input signal) to the RMS value of the first five harmonics. 2 2 2 2 V2 + V3 + V4 + V5 + V6 V1 2 THD(dBc) = 20*log -----------------------------------------------------------------------Where: V1 is the RMS power of the input frequency (fundamental) V2 to V6 are the RMS values of the first five harmonics Spurious Free Dynamic Range (SFDR) The Spurious Free Dynamic Range defines the ratio between the RMS value of the fundamental to the RMS value of the largest peak off all spectral components below one-half of the sampling frequency, including harmonics but excluding DC. Channel to Channel Isolation The Channel to Channel Isolation (Crosstalk) defines the coupling of energy from one channel into the other channel in the ADC. It is measured by applying a 40kHz sine wave to all unselected channels and the attenuation to a 50kHz input sine wave is determined. Intermodulation Distortion (IMD) The Intermodulation Distortion measures the creations of additional spectral components that are caused by nonlinearities when applying a two tone sine wave on the input of the ADC. IMD is the ration of the RMS power in either the second or the third intermodulation products to the sum of both input frequencies. nd 2 order intermodulation products (IM2): f1+f2, f2-f1 rd 3 order intermodulation products (IM3): 2*f1-f2, 2*f2-f1, 2*f1+f2, 2*f2+f1 Full Power Bandwidth / Full Linear Bandwidth The Full Power Bandwidth defines the frequency at which the reconstructed input signal amplitude drops 3dB from the actual amplitude of the input signal, when applying a full scale signal. The Full Linear Bandwidth defines the frequency at which the reconstructed input signal amplitude drops 0.1dB from the actual amplitude of the input signal, when applying a full scale signal. www.austriamicrosystems.com Revision 1.00 17 - 34 AS1545 Data Sheet - D e t a i l e d D e s c r i p t i o n 9 Detailed Description The AS1545 is a dual, 6-channel (six single-ended, three pseudo-differential or three fully-differential for each multiplexer), 12-bit, 1 MSPS, high speed, successive approximation (SAR) analog-to-digital converter (ADC). The AS1545 is designed to operate with a single +2.7V to +5.25V supply and a sampling rate of up to 1 MSPS. The serial interface provides easy interfacing to microprocessors. The AS1545 feature two on-chip, differential track-and-hold amplifiers, two successive approximation ADCs, and a serial interface with two separate data output pins on a single die. The AS1545 is available in a 32-lead TQFN package, offering the user considerable space-saving advantage. The AS1545 can convert analog input signals in the range [0V to VREFIN] or [0V to 2 x VREFIN] in single-ended or pseudo-differential mode or [-VREFIN/2 to +VREFIN/2] or [-VREFIN to +VREFIN] in fully differential mode. The AS1545 has an on-chip 2.5V reference that can be overdriven when an external reference is preferred. If the internal reference is to be used then the output needs to be buffered first. The AS1545 also features power-down options to allow power saving between conversions. The power-down feature is implemented via the standard serial interface. Analog Input The AS1545 consists of successive approximation ADCs, each around two capacitive DACs and 12 analog inputs. Each on-board ADC has six analog inputs that can be configured as six single-ended channels, three pseudo differential channels, or three fully differential channels. Figure 32 and Figure 33 shows one of these ADCs in acquisition and conversion phase, respectively. The ADC consists of a control logic, a SAR, and two capacitive DACs. Figure 32. ADC Acquisition CH0 CH1 CH2 CH3 CH4 CH5 CAPACITIVE DAC B AIN+ COMPARATOR CS RIN + A SW1 11pF CONTROL LOGIC SW3 A CS SW2 AIN- RIN - 11pF B Analog Input Multiplexer CAPACITIVE DAC CSWITCH includes all parasitics VREF Acquisition Time During data acquisition time (tACQ) SW3 is closed, SW1 and SW2 are in track position, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. At the raising edge of the CSN signal, SW3 opens and SW1 and SW2 go into hold position, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. The output impedances of the sources driving the AIN+ and AIN- pins must be matched. Otherwise, the two inputs will have different settling times, resulting in errors. Figure 33. ADC Conversion Phase CH0 CH1 CH2 CH3 CH4 CH5 CAPACITIVE DAC B AIN+ COMPARATOR CS RIN + A SW1 11pF CONTROL LOGIC SW3 A SW2 AIN- CS RIN - 11pF B Analog Input Multiplexer CAPACITIVE DAC VREF www.austriamicrosystems.com CSWITCH includes all parasitics Revision 1.00 18 - 34 AS1545 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 34. Typical Application 10µF 10µF 1µF 1µF 100nF AVDD + 100nF DVDD DOUTA SCLK CSN RANGE SGL/DIFF DOUTB VDRIVE AIN 0 10nF 10Ω AIN 1 - + 10Ω 10nF 10Ω BIN 0 10nF BIN 1 10Ω 10nF µC AS1545 REFB REFA REFSEL 1µF 100nF 4.7µF 4.7µF A0 A1 A2 Analog Input Composition The equivalent circuit of analog input structure of the AS1545 in differential/pseudo differential modes is shown in the Figure 35. In single-ended mode, AIN- is internally tied to AGND. The four diodes provide ESD protection for the analog inputs. These diodes can conduct up to 10mA without causing irreversible damage to the part. Note: Make sure that the analog input signals never exceed the supply rails by more than 300mV. This causes the diodes to become forward-biased and starts conducting into the substrate. The C1 capacitors in Figure 35 are of 4pF and can be attributed to pin capacitance. The value of these resistors is typically about 100Ω. The C2 capacitors are the ADC’s sampling capacitors with a capacitance of 20pF typically. For ac applications, removing high frequency components from the analog input signal is recommended by the use of an RC low-pass filter on the relevant analog input pins with optimum values of 10Ω and 10nF. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC and may necessitate the use of an input buffer amplifier. The choice of the op amp is a function of the particular application. Figure 35. Equivalent Analog Input Circuit VDD VDD D R1 D C2 R1 C2 AIN- AIN+ C1 4pF C1 D Open for conversion, closed for tracking. 4pF D Open for conversion, closed for tracking. When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance depends on the amount of THD that can be tolerated. The THD increases as the source impedance increases and performance degrades. Figure 23 on page 13 shows a graph of the THD vs. the analog input signal frequency for various supplies in singleended mode, while Figure 25 shows the THD vs. the analog input signal frequency for various supplies in differential mode. Figure 22 on page 13 shows a graph of the THD vs. the analog input frequency for different source impedances. www.austriamicrosystems.com Revision 1.00 19 - 34 AS1545 Data Sheet - D e t a i l e d D e s c r i p t i o n Analog Input Modes Table 5. Address Map Address Map SGL/ DIFF A2 A1 A0 1 0 0 1 0 1 ADC A ADC B Comments AIN+ AIN- BIN+ BIN- 0 AIN0 GND BIN0 GND Single Ended 0 1 AIN1 GND BIN1 GND Single Ended 0 1 0 AIN2 GND BIN2 GND Single Ended 1 0 1 1 AIN3 GND BIN3 GND Single Ended 1 1 0 0 AIN4 GND BIN4 GND Single Ended 1 1 0 1 AIN5 GND BIN5 GND Single Ended 0 0 0 0 AIN0 AIN1 BIN0 BIN1 Fully Differential 0 0 0 1 AIN0 AIN1 BIN0 BIN1 Pseudo Differential 0 0 1 0 AIN2 AIN3 BIN2 BIN3 Fully Differential 0 0 1 1 AIN2 AIN3 BIN2 BIN3 Pseudo Differential 0 1 0 0 AIN4 AIN5 BIN4 BIN5 Fully Differential 0 1 0 1 AIN4 AIN5 BIN4 BIN5 Pseudo Differential 0 1 1 0 AIN0 AIN1 BIN0 BIN1 Pseudo Differential Difference – A/B Phases – Counter Table 6. Input Range SGL/DIFF Range Ain+ - AinRange Coding Example 1 0 0 to VREF Straight AIN+ - AIN- = 1.766 V Output Decimal = 2894 Output Binary = 1011 0100 1110 1 1 0 to 2VREF Straight AIN+ - AIN- = 1.766V Output Decimal = 1447 Output Binary = 0101 1010 0111 0 0 0 to VREF Straight AIN+ - AIN- = 1.666 V Output Decimal = 2703 Output Binary = 1010 1010 1010 0 1 0 to 2VREF Straight AIN+ - AIN- = 1.666 V Output Decimal = 1365 Output Binary = 0101 0101 0101 0 0 -VREF/2 to +VREF/2 2’s comp AIN+ - AIN- = 1.666 V Output Decimal = 4095 Output Binary = 0111 1111 1111 (its 2’s comp) 0 1 -VREF to +VREF 2’s comp AIN+ - AIN- = 1.666 V Output Decimal= 3413 Output Binary= 0101 0101 0101 (its 2’s comp) www.austriamicrosystems.com Revision 1.00 20 - 34 AS1545 Data Sheet - D e t a i l e d D e s c r i p t i o n Single-Ended Mode The AS1545 consists of 12 single-ended analog input channels with range that can be programmed to be either 0 to VREF or 0 to 2 × VREF. Note: In applications where the signal source has high impedance, it is recommended to buffer the analog input before applying it to the ADC. If the sampling analog input is bipolar, the internal reference of the ADC can be used to externally bias up this signal to make it correctly formatted for the ADC. Figure 36 shows the connecting diagram when operating the ADC in singleended mode. Figure 36. Single-Ended Mode Connection Diagram +2.5V +1.25V 0V -1.25V R VIN 0V R AIN0 to BIN5 3R 10Ω + 10nF REFA/ REFB R + 4.7µF - Figure 37. Definition of Single-Ended Input VIN RANGE = 0 VIN 0 < AIN < VDD RANGE = 1 0 < AIN < VDD VREF 2VREF t t Fully Differential Mode The AS1545 consists of six differential analog input pairs. Figure 38 defines the fully differential analog input of the AS1545. The amplitude of the differential signal is the difference between the signals applied to the AIN+ and AIN- pins in each differential pair (AIN+ - AIN-). These pins should be simultaneously driven by two signals each of amplitude VREF/2 (or VREF, depending on the range required) that are 180º out of phase. If RANGE = 1 is selected the amplitude of the differential signal is ±VREF regardless of the common mode (CM). The common mode is the average of the two signals and is therefore the voltage on which the two inputs are centered. (VIN+ + VIN-)/2 (EQ 1) Althought fully differential operation with phase between inputs of 180° is recommanded, non true differential signals can also be applied. Note: It is important to note that the absolute voltage of the analog inputs goes from AGND to VDD. www.austriamicrosystems.com Revision 1.00 21 - 34 AS1545 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 38. Definition of Fully Differential Input RANGE = 0 VIN AIN+ 0 < VCM < VDD 0 < AIN-, AIN+ < VDD RANGE = 1 VIN AIN+ ±VREF/2 VCM 0 < VCM < VDD 0 < AIN-, AIN+ < VDD ±VREF VCM AIN- AINt t Pseudo Differential Mode The AS1545 consists of six pseudo differential pairs. In pseudo differential mode, AIN+ is connected to the signal source with an amplitude of VREF or 2 × VREF (depending on the range selected) to make use of the full dynamic range of the part. A dc input is applied to the AIN- pin. The voltage applied to this input provides an offset from ground or a pseudo ground for the AIN+ input. The benefit of pseudo differential inputs is that they separate the analog input signal ground from the ADC’s ground allowing dc common-mode voltages to be cancelled. Figure 39 shows a connection diagram for pseudo differential mode. Figure 39. Pseudo Differential Mode Connection Diagram + VREF p-p VIN+ AS1545 VIN- REFA/ REFB - DC Input Voltage 4.7µF Figure 40. Definition of Pseudo Differential Input RANGE = 0 VIN AIN- + VREF 0 < AIN-, AIN+ < VDD RANGE = 1 VIN AIN+ AIN- + 2VREF 2VREF VREF AIN- AINt www.austriamicrosystems.com 0 < AIN-, AIN+ < VDD AIN+ Revision 1.00 t 22 - 34 AS1545 Data Sheet - D e t a i l e d D e s c r i p t i o n Analog-to-Digital Conversion The analog inputs of the AS1545 can be configured as single-ended pseudo-differential or fully differential via the SGL/ DIFF logic pin, as shown in Figure 41. If this pin is coupled to a logic low, the analog input channels to each on-chip ADC are set up as three fully differential pairs or 3 pseudo-differential inputs. If this pin is at logic high, the analog input channels to each on-chip ADC are set up as six single-ended analog inputs. The required logic level on this pin needs to be established prior to the acquisition time and remain unchanged during the conversion time until the track-andhold has returned to track. The track-and-hold returns to track on the 13th rising edge of SCLK after the CSN falling edge (see Figure 51). If the level on this pin is changed, it is recognized by the AS1545; therefore, keep the same logic level during acquisition and conversion to avoid corrupting the conversion in progress. The channels used for simultaneous conversions are selected via the multiplexer address input pins, A0 to A2. The logic states of these pins also need to be established prior to the acquisition time; however, they may change during the conversion time, provided that the mode is not changed. If the mode is changed from fully differential to pseudodifferential, for example, then the acquisition time would start again from this point. The selected input channels are decoded as shown in Table 5 on page 20. The analog input range of the AS1545 can be selected as [0V to VREF or -VREF/2 to +VREF/2] or [0V to 2×VREF or -VREF to +VREF] via the RANGE and MODE pin (see Table 5 on page 20). This selection is made in a similar fashion to that of the SGL/DIFF pin by setting the logic state of the RANGE pin a time tACQ prior to the falling edge of CSN. The logic level on this pin can be altered after the third falling edge of SCLK. If this pin is tied to a logic low, the analog input range selected is [0V to VREF or -VREF/2 to +VREF/2]. If this pin is tied to a logic high, the analog input range selected is [0V to 2×VREF or -VREF to +VREF]. Figure 41. Selecting Differential or Singe-Ended Configuration A CSN B tACQ 1 SCLK 14 1 14 SGL/ DIFF Output Coding The AS1545 output coding is set to either twos complement or straight binary, depending on which analog input configuration is selected for a conversion. Output coding scheme for each possible analog input configuration is show in the Table 7. Table 7. AS1545 Output Coding MODE Output Coding Differential Twos complement Single-Ended Straight binary Pseudo-Differential Straight binary Transfer Functions The designed code transitions occur at successive integer LSB values (1 LSB, 2 LSB, and so on). In single-ended mode, the LSB size is VREF/4096 when the 0V to VREF range is used, and the LSB size is 2 × VREF/4096 when the 0V to 2 × VREF range is used. In differential mode, the LSB size is 2 × VREF/4096 when the 0V to VREF. The ideal transfer characteristic for the AS1545 when straight binary coding is output is shown (with the 2 × VREF range) in Figure 42 & Figure 43 on page 24, and Figure 44 & Figure 45 on page 24 shows the twos complement. www.austriamicrosystems.com Revision 1.00 23 - 34 AS1545 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 42. Straight Binary Transfer Function for Single-Ended, RANGE = 0 Full Scale = VREF Zero Scale = 0 1LSB = VREF/4096 11...111 Figure 43. Straight Binary Transfer Function for Single-Ended, RANGE = 1 Full Scale (FS) Transition Full Scale = +2VREF Zero Scale = 0 1LSB = VREF/4096 11...111 11....101 11....101 Output Code 11...110 Output Code 11...110 00...011 00...011 00...010 00...010 00...001 00...001 00...000 00...000 0 1 2 3 FS - 3/2LSB 0 1 Input Voltage VINx (LSB) 011....111 011....111 011...110 000...010 000...010 Output Code 011...110 000...001 000...000 FS - 3/2LSB 111...111 Full Scale = +VREF Zero Scale = -VREF 1LSB = VREF/4096 000...001 000...000 111...111 111...110 111...110 111...101 111...101 100...001 100...001 100...000 100...000 ZS 3 Figure 45. Two’s Complement Transfer Function for Differential, RANGE = 1 Full Scale = VREF/2 Zero Scale = -VREF/2 1LSB = VREF/4096 -FS 2 Input Voltage VINx - VINy (LSB) Figure 44. Two’s Complement Transfer Function for Differential, RANGE = 0 Output Code Full Scale (FS) Transition +FS - 1LSB Input Voltage VINx (LSB) -FS ZS +FS - 1LSB Input Voltage VINx - VINy (LSB) Digital Inputs VDRIVE Functionality The AS1545 also has a VDRIVE feature to control the voltage at which the serial interface operates and allows the ADC to easily interface to both 3V and 5V processors. For example, if the AS1545 was operated with a VDD of 5V, the VDRIVE pin could be powered from a 3V supply, allowing a large dynamic range with low voltage digital processors. Therefore, the AS1545 could be used with the 2 × VREF input range, with a VDD of 5V while still being able to interface to 3V digital parts. www.austriamicrosystems.com Revision 1.00 24 - 34 AS1545 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n 10 Application Information Operation Modes The operation mode of the AS1545 is selected by controlling the (logic) state of the CSN signal during a conversion process. There are three possible modes of operation: Full Power-UP mode, Full Power-Down mode, and Partial Power-Down mode. After a conversion is initiated, the point at which CSN is pulled high determines which power-down mode, if any, the device enters. Similarly, in power-down mode, CSN can control whether the device returns to Full Power-Up mode or remains in power-down. These modes of operation provides flexible power management and can be selected to optimize the power dissipation/throughput rate ratio for differing application requirements. Full Power-Up Mode In this mode the AS1545 is fully powered all the time without any power-up time. This mode is suitable for applications that need the fastest throughput rates. Figure 46 shows the general diagram of the operation of the AS1545 in this mode. On the falling edge of CSN conversion is initiated. To ensure that the part remains fully powered up at all times, CSN must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CSN. The conversion is terminated and DOUTA and DOUTB go back into three-state, if CSN is brought high any time after the 10th SCLK falling edge but before the 15th SCLK falling edge. During this process the part remains powered up. Figure 46. Full Power-Up Mode Operation CSN 1 10 15 SCLK DOUTA DOUTB 3 LEADING ZEROS + CONVERSION RESULT 12bits Fiveteen serial clock cycles are required to complete the conversion and access the conversion result. The DOUT line does not return to three-state after 15 SCLK cycles have elapsed, but instead does so when CSN is brought high again. If CSN is left low for another SCLK cycle (for example, if only a 16 SCLK burst is available), one trailing zeros are clocked out after the data. If CSN is left low for a further 16 SCLK cycles, the result from the other ADC on board is also accessed on the same DOUT line, as shown in Figure 52 (see Serial Interface on page 28) Once 32 SCLK cycles have elapsed, the DOUT line returns to three-state on the 32nd SCLK falling edge. If CSN is brought high prior to this, the DOUT line returns to three-state at that point. Once a data transfer is complete and DOUTA and DOUTB have returned to three-state, another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CSN low again (assuming the required acquisition time is allowed). Full Power-Down Mode This mode is intended for applications where throughput rates are slower. In this mode the AS1545 will stay power down until the falling edge of CSN. The device continues to power-up when the CSN is held low till the falling edge of the 10th SCLK. When the AS1545 is in full power-down, all analog circuitry is powered down. Full power-down is entered in a similar way as partial power-down, except the timing sequence shown in Figure 50 must be executed twice. The conversion process must be interrupted in a similar fashion by bringing CSN high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK. The device enters partial power-down at this point. To reach full powerdown, the next conversion cycle must be interrupted in the same way, as shown in Figure 48. Once CSN is brought high in this window of SCLKs, the part completely powers down. Note: It is important to note, that the full power-down mode can only be established if both digital outputs, DOUTA and DOUTB are not left floating. Therefore a pulldown or pullup of >1GΩ is required. www.austriamicrosystems.com Revision 1.00 25 - 34 AS1545 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n Figure 47. Exiting Partial Power-Down Mode The part is fully powered-up The part begins to power-up tpower-up1 CSN 1 SCLK DOUTA DOUTB 1 15 10 15 VALID DATA INVALID DATA Figure 48. Entering Full Power-Down Mode The part enters fully powered down The part enters partial power down The part begins to power-up CSN SCLK 1 10 2 DOUTA DOUTB 15 1 2 15 10 Three-State Three-State INVALID DATA INVALID DATA Figure 49. Exiting Full Power-Down Mode The part is fully powered-up The part begins to power-up tpower-up1 CSN SCLK DOUTA DOUTB 1 10 15 1 15 VALID DATA INVALID DATA Note: It is not necessary to complete the 15 SCLKs once CSN is brought high to enter a power-down mode. The required power-up time must elapse before a conversion can be initiated, as shown in Figure 49. Partial Power-Down Mode This mode is intended for use in applications where slower throughput rates are required. Either the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate, and the ADC is then powered down for a relatively long duration between these bursts of several conversions. When the AS1545 is in partial power-down, all analog circuitry is powered down except for the on-chip reference and reference buffer. www.austriamicrosystems.com Revision 1.00 26 - 34 AS1545 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n To enter partial power-down mode, the conversion process must be interrupted by bringing CSN high anywhere after the second falling edge of SCLK and before the 10th falling edge of SCLK, as shown in Figure 50. Once CSN is brought high in this window of SCLKs, the part enters partial power-down, the conversion that was initiated by the falling edge of CSN is terminated, and DOUTA and DOUTB go back into three-state. If CSN is brought high before the second SCLK falling edge, the part remains in normal mode and does not power down. This avoids accidental powerdown due to glitches on the CSN line. Figure 50. Partial Power-Down Mode CSN 1 2 10 15 SCLK DOUTA DOUTB THREE-STATE To exit this mode of operation and power up the AS1545 again, a dummy conversion is performed. On the falling edge of CSN, the device begins to power up and continues to power up as long as CSN is held low until after the falling edge of the 10th SCLK. The device is fully powered up after approximately 1 µs has elapsed, and valid data results from the next conversion, as shown in Figure 47. If CSN is brought high before the second falling edge of SCLK, the AS1545 again goes into partial power-down. This avoids accidental power-up due to glitches on the CSN line. Although the device may begin to power up on the falling edge of CSN, it powers down again on the rising edge of CSN. If the AS1545 is already in partial power-down mode and CSN is brought high between the second and 10th falling edges of SCLK, the device enters full power-down mode. Power-Up Times As described in detail, the AS1545 has two power-down modes, partial power-down and full power-down. This section deals with the power-up time required when coming out of either of these modes. It should be noted that the power-up times, as explained in this section, apply with the recommended capacitors in place on the DCAPA and DCAPB pins. The power-up time is always 1µs, independent of the mode currently in. Note: It is important to note that, when using the internal reference, charging the external reference capacitance typically needs around 250µs but can take up to 1ms. When power supplies are first applied to the AS1545, the ADC may power up in either of the power-down modes or normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. Likewise, if it is intended to keep the part in the partial power-down mode immediately after the supplies are applied, then two dummy cycles must be initiated. The first dummy cycle must hold CSN low until after the 10th SCLK falling edge (see Figure 46); in the second cycle, CSN must be brought high before the 10th SCLK edge but after the second SCLK falling edge (see Figure 50). Alternatively, if it is intended to place the part in full power-down mode when the supplies are applied, then three dummy cycles must be initiated. The first dummy cycle must hold CSN low until after the 10th SCLK falling edge (see Figure 46); the second and third dummy cycles place the part in full power-down (see Figure 48). Once supplies are applied to the AS1545, enough time must be allowed for any external reference to power up and charge the various reference buffer decoupling capacitors to their final values. www.austriamicrosystems.com Revision 1.00 27 - 34 AS1545 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n Power vs. Throughput Rate The power consumption of the AS1545 varies with throughput rate. When using very slow throughput rates and as fast an SCLK frequency as possible, the various power-down options can be used to make significant power savings. However, the AS1545 quiescent current is low enough that even without using the power-down options, there is a noticeable variation in power consumption with sampling rate. This is true whether a fixed SCLK value is used or if it is scaled with the sampling rate. Figure 10 on page 11 shows plots of power vs. the throughput rate when operating in normal mode for a fixed maximum SCLK frequency, and an SCLK frequency that scales with the sampling rate with VDD = 3V and VDD = 5V, respectively. In all cases, the internal reference was used. Serial Interface The timing diagram for serial interfacing to the AS1545 is shown in Figure 51. The serial clock provides the conversion clock and controls the transfer of information from the AS1545 during conversion. The CSN signal initiates the data transfer and conversion process. The falling edge of CSN puts the track-and-hold into hold mode, at which point the analog input is sampled and the bus is taken out of three-state. The conversion is also initiated at this point and requires a minimum of 15 SCLKs to complete. Once 13 SCLK falling edges have elapsed, the track-and-hold goes back into track on the next SCLK rising edge, as shown in Figure 51 at Point B. If a 16-SCLK transfer is used, then two trailing zeros will appear after the final LSB. On the rising edge of CSN, the conversion is terminated and DOUTA and DOUTB go back into three-state. If CSN is not brought high but is instead held low for a further 15 SCLK cycles on DOUTA, the data from Conversion B is output on DOUTA (followed by 1 trailing zero). Likewise, if CSN is held low for a further 15 SCLK cycles on DOUTB, the data from Conversion A is output on DOUTB. This is illustrated in Figure 52 where the case for DOUTA is shown. In this case, the DOUT line in use goes back into three-state on the 32nd SCLK falling edge or the rising edge of CSN, whichever occurs first. A minimum of 15 serial clock cycles are required to perform the conversion process and to access data from one conversion on either data line of the AS1545. CSN going low provides the 3 leading zeros to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges. Therefore, the first falling clock edge on the serial clock has the leading zero provided and also clocks out the second leading zero. The 12-bit result then follows after a third leading zero with the final bit in the data transfer valid on the 15th falling edge, having being clocked out on the previous (14th) falling edge. It may also be possible to read in data on each SCLK rising edge depending on the SCLK frequency or the supply voltage. The secondrising edge of SCLK after the CSN falling edge would have the third leading zero provided, and the 14th rising SCLK edge would have DB0 provided. If a falling edge of SCLK is coincident with the falling edge of CSN, then this falling edge of SCLK is not acknowledged by the AS1545, and the next falling edge of SCLK will be the first registered after the falling edge of CSN. Figure 51. Timing Diagram CSN tCSPW tCSS SCLK tCH 1 2 3 4 B 5 14 tCL tDOH tCSDOE DOUTA 0 0 DB11 0 DOUTB THREESTATE 3 LEADING ZEROES www.austriamicrosystems.com tCSDOD tDOV DB10 DB9 Revision 1.00 DB2 DB1 DB0 tQUIET THREE-STATE 28 - 34 AS1545 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n Figure 52. Reading Data from Both ADCs on One DOUT Line with 32 SCLKs CSN tCSS tCH 1 SCLK 2 3 tDOV tCSDOE DOUTA THREESTATE 0 0 5 tCL 4 0 15 16 DB11A DB10A 0 0 1 TRAILING ZERO 3 LEADING ZEROES 32 tDOD 18 17 tDOH 0 0 DB11B DB0B 0 THREESTATE 1 TRAILING ZERO 3 LEADING ZEROES Figure 53. 32 SCLKs Data transfer for all modes in DOUTA, DOUTB CSN DOUTA 000 SDATA_A 0 00 0+SDATA_B 0 DOUTA* 000 SDATA_A 0 00 Counter + DIR + A + B 0 DOUTB 000 SDATA_A 0 00 DIF 0 16bit 16bit * only applicable when SGL/DIFF = 0 ; Α2=1, Α1=1, Α0=0 Difference calculator and quadrature signals calculator The AS1545 internally calculates the difference between the output codes of ADC A and ADC B. There are several requirements that need to be taken into account in order to work with the difference calculator. First off, the output data of both ADCs needs to be in straight binary coding. This means that the difference calculator will only give the correct results in single ended and pseudo differential modes. Also, it is important to note that in order to read the data from the difference calculator we must read all 32 bits of data of the ADC, therefore reducing the overall sampling rate of the ADC by half. The difference calculator will always give you a 13 bit two’s complement result. The first bit is the sign of the operation and the next 12 bits are the data. For simplicity in the design, an systematic error of 1 LSB can be expected from the difference calculator. Below we have an detailed example describing the operation of the difference calculator. Let’s assume that VINA = 1.667V VINB = 2V VREF = 2.5V and we are working in single ended mode. DOUT_A = 1010 1010 1010 or 2730 in decimal DOUT_B = 1100 1100 1100 or 3276 in decimal The difference should be 2730-3276=-546 in decimal In 2’s complement -546 is 1 1101 1101 1110 in binary. This is a 1 for the minus sign plus 4096-546=3550 in decimal which corresponds to 1101 1101 1110 in binary As stated before, there is a -1LSB error in the operation so the actual output should be -547 in decimal which corresponds to 1 1101 1101 1101 in binary which is the result that the difference calculator clocks out. www.austriamicrosystems.com Revision 1.00 29 - 34 AS1545 Data Sheet - A p p l i c a t i o n I n f o r m a t i o n On top of the difference calculator, the ADC also provide us with information regarding input signals in quadrature (90 degrees phase difference) like the ones we would get from a position calculation system of a motor control. In order for this mode to work, we must have SGL/DIFF=0, A2=1. A1=1. A0=0, according to what is specified in the channel addresses table. Also, it is important to note that in order to read the data from the quadrature inputs calculator we must read all 32 bits of data of the ADC, therefore reducing the overall sampling rate of the ADC by half. The ADC provides us with the following information: - Phase A and Phase B bits, dividing the period into four quadrants - DIR bit, which indicates the direction of the rotation of the rotor - Counter, this is a 10 bit word that, in the case of using a step down in the rotor indicates the number of times the step down has spun. The counter increases twice per period if DIR is equal zero and decreases twice per period if DIR equals one. Figure 54. A to B phase Code 4095 Cos Sinus Code 2048 Code 0 Direction = 0 Phase A Phase B Direction = 1 Direction of the rotor based on the DIR bit If the rotor is rotating as the above picture, the direction bit is low. If the rotor is rotating in the opposite direction to the above picture, the direction bit is high. Note: This mode works only for SGL/DIFF=0, A2=1. A1=1. A0=0. www.austriamicrosystems.com Revision 1.00 30 - 34 AS1545 Data Sheet - A p p l i c a t i o n H i n t s 11 Application Hints Grounding and Layout The analog and digital supplies to the AS1545 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The printed circuit board (PCB) that houses the AS1545 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This design facilitates the use of ground planes that can be easily separated. To provide optimum shielding for ground planes, a minimum etch technique is generally best. All three AGND pins of the AS1545 should be sunk in the AGND plane. Digital and analog ground planes should be joined in only one place. If the AS1545 is in a system where multiple devices require an AGND to DGND connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the ground pins on the AS1545. Avoid running digital lines under the device as this couples noise onto the die. However, the analog ground plane should be allowed to run under the AS1545 to avoid noise coupling. The power supply lines to the AS1545 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. To avoid radiating noise to other sections of the board, fast switching signals, such as clocks, should be shielded with digital ground, and clock signals should never run near the analog inputs. Avoid crossover of digital and analog signals. To reduce the effects of feedthrough within the board, traces on opposite sides of the board should run at right angles to each other. A microstrip technique is the best method but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. Good decoupling is also important. All analog supplies should be decoupled with 10 µF ceramic capacitors in parallel with 0.1 µF capacitors to GND. To achieve the best results from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. The 0.1 µF capacitors should have low effective series resistance (ESR) and effective series inductance (ESI), such as the common ceramic types or surface-mount types. These low ESR and ESI capacitors provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. PCB Design Guidelines for TQFN The lands on the TQFNpackage are rectangular. The PCB pad for these should be 0.1 mm longer than the package land length, and 0.05 mm wider than the package land width, thereby having a portion of the pad exposed. To ensure that the solder joint size is maximized, the land should be centered on the pad. The bottom of the chip scale package has a thermal pad. The thermal pad on the PCB should be at least as large as the exposed pad. On the PCB, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. To improve thermal performance of the package, use thermal via on the PCB incorporating them in the thermal pad at 1.2 mm pitch grid. The via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 oz. copper to plug the via. The user should connect the PCB thermal pad to AGND. www.austriamicrosystems.com Revision 1.00 31 - 34 AS1545 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 12 Package Drawings and Markings -A- Figure 55. 32-lead TQFN Package D INDEX AREA (D/2 xE/2) D2 D2/2 D/2 -B- aaa C 2x -BSEE DETAIL B TOP VIEW 4 6 SEE DETAIL B NXb -A- INDEX AREA (D/2 xE/2) 5 bbb ddd C A B C BTM VIEW 0.08 C NX A ccc C L1 SEATING PLANE -C- e/2 EVEN TERM INAL SIDE A1 SIDE VIEW e Terminal Tip 5 A3 Datum A or B 2 1 N N-1 aaa C 2x E2 E e E2/2 NXL E/2 4 Table 8. 32-lead TQFN Package Dimensions Symbol Min Nom Max Note Symbol Min Nom Max Note A 0.70 0.75 0.80 1,2 b 0.18 0.25 0.30 1,2,5 A1 0.00 0.02 0.05 1,2 L 0.30 0.40 0.50 L1 0.03 0.15 1,2 N 32 1,2,5 K 0.20 1,2 ND 8 1,2,5 NE 8 1,2,5 e 0.5 1,2,5 D2 3.30 3.45 3.55 1,2,5 aaa 0.10 1,2 E2 3.30 3.45 3.55 1,2,5 bbb 0.10 1,2 D BSC 5.00 1,2,5 ccc 0.10 1,2 E BSC 5.00 1,2,5 ddd 0.05 1,2 Note: 1. 2. 3. 4. Dimensioning and tolerancing conform to ASME Y14.5M-1994. All dimensions are in millimeters, angle is in degrees. N is the total number of terminals. Terminal #1 identifier and terminal numbering convention shall conform to JESD 95-1 SPP-012. Details of terminal #1 identifier are optional, but must be located within the area indicated. The terminal #1 identifier may be either a mold, embedded metal or mark feature. 5. Dimension b applies to metallized terminal and is measured between 0.15 and 0.30mm from terminal tip. 6. ND refers to the maximum number of terminals on D side. 7. Unilateral coplanarity zone applies to the exposed heat sink slug as well as the terminals. www.austriamicrosystems.com Revision 1.00 32 - 34 AS1545 Data Sheet - O r d e r i n g I n f o r m a t i o n 13 Ordering Information The device is available as the standard products shown in Table 9. Table 9. Ordering Information Model Description Marking Delivery Form Package AS1545-BQFT Dual, 12-Bit, 1MSPS, SAR ADC AS1545 T&R 32-lead TQFN www.austriamicrosystems.com Revision 1.00 33 - 34 AS1545 Data Sheet - O r d e r i n g I n f o r m a t i o n Copyrights Copyright © 1997-2007, austriamicrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG A-8141 Schloss Premstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com Revision 1.00 34 - 34