PRELIMINARY TECHNICAL DATA
a
Differential Input, 1MSPS,
12- & 10-Bit ADCs in 8-lead SOT-23
Preliminary Technical Data
FEATURES
Fast Throughput Rate: 1MSPS
Specified for VDD of 3 V and 5 V
Low Power at max Throughput Rate:
3.75 mW typ at 1MSPS with 3 V Supplies
9 mW typ at 1MSPS with 5 V Supplies
Fully Differential Analog Input
Wide Input Bandwidth:
70dB SINAD at 200kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
High Speed Serial Interface - SPI TM /QSPI TM /
MICROWIRE T M / DSP Compatible
Power-Down Mode: 1µA max
8 Lead SOT-23 and MSOP Packages
APPLICATIONS
Transducer Interface
Battery Powered Systems
Data Acquisition Systems
Portable Instrumentation
Motor Control
Communications
GENERAL DESCRIPTION
The AD7450A/AD7440 are respectively 12- and 10-bit,
high speed, low power, successive-approximation (SAR)
analog-to-digital converters that feature a fully differential
analog input. These parts operate from a single 3 V or 5 V
power supply and feature throughput rates up to 1MSPS.
The parts contains a low-noise, wide bandwidth, differential track and hold amplifier (T/H) which can handle
input frequencies in excess of 1MHz with the -3dB point
being 20MHz typically. The reference voltage is applied
externally to the VREF pin and can be varied from 100 mV
to 3.5 V depending on the power supply and what suits the
application. The value of the reference voltage determines
the common mode voltage range of the part. With this
truly differential input structure and variable reference
input, the user can select a variety of input ranges and bias
points.
The conversion process and data acquisition are controlled
using CS and the serial clock allowing the device to interface with Microprocessors or DSPs. The input signals are
sampled on the falling edge of CS and the conversion is
also initiated at this point.
AD7450A/AD7440
FUNCTIONAL BLOCK DIAGRAM
VDD
VIN+
T/H
VIN-
12-BIT SUCCESSIVE
APPROXIMATION
ADC
VREF
SCLK
AD7450A/
AD7440
CONTROL
LOGIC
SDATA
+5
GND
The SAR architecture of these parts ensures that there are
no pipeline delays.
The AD7450A and the AD7440 use advanced design techniques to achieve very low power dissipation at high
throughput rates.
PRODUCT HIGHLIGHTS
1.Operation with either 3 V or 5 V power supplies.
2.High Throughput with Low Power Consumption.
With a 3V supply, the AD7450A/AD7440 offer
3.75mW typ power consumption for 1MSPS throughput.
3.Fully Differential Analog Input.
4.Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. These
parts also feature a shutdown mode to maximize power
efficiency at lower throughput rates.
5.Variable Voltage Reference Input.
6.No Pipeline Delay.
7.Accurate control of the sampling instant via a CS input
and once off conversion control.
8. ENOB > 8 bits typically with 100mV reference.
MICROWIRE is a trademark of National Semiconductor Corporation.
SPI and QSPI are trademarks of Motorola, Inc.
REV. PrF 10 March 03
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL
DATA
( V = 2.7V to 3.6V, f = 18MHz, f
DD
SCLK
S = 1MSPS, VREF = 2.0 V;
VDD = 4.75V to 5.25V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.5 V;
VCM 3 = VREF; TA = TMIN to TMAX, unless otherwise noted.)
AD7450A - SPECIFICATIONS
Parameter
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion)
(SINAD) 2
F IN = 200kHz
Total Harmonic Distortion (THD) 2
Peak Harmonic or Spurious Noise2
Intermodulation Distortion (IMD) 2
Second Order Terms
Third Order Terms
Aperture Delay 2
Aperture Jitter 2
Full Power Bandwidth2
DC ACCURACY
Resolution
Integral Nonlinearity (INL) 2
Differential Nonlinearity (DNL) 2
Zero Code Error 2
Positive Gain Error 2
Negative Gain Error 2
ANALOG INPUT
Full Scale Input Span
Absolute Input Voltage
V IN+
V INDC Leakage Current
Input Capacitance
REFERENCE INPUT
V REF Input Voltage
VDD
VDD
VDD
VDD
VDD
VDD
=
=
=
=
=
=
4.75V to 5.25V
2.7 V to 3.6V
4.75V to 5.25V, -80dB typ
2.7V to 3.6V, -78dB typ
4.75V to5.25V, -82dB typ
2.7V to 3.6V, -80dB typ
@ -3 dB
@ -0.1 dB
Guaranteed No Missed Codes
to 12 Bits.
VDD = 4.75V to 5.25V
VDD = 2.7V to 3.6V
VDD = 4.75V to 5.25V
VDD = 2.7V to 3.6V
VDD = 4.75V to 5.25V
VDD = 2.7V to 3.6V
A Version1
B Version1
Unit
70
68
-75
-73
-75
-73
70
68
-75
-73
-75
-73
dB
dB
dB
dB
dB
dB
-85
-85
10
50
20
2.5
-85
-85
10
50
20
2.5
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
12
±2
12
±2
Bits
LSB max
-1/+2
±3
±6
±3
±6
±3
±6
±1
±3
±6
±3
±6
±3
±6
LSB
LSB
LSB
LSB
LSB
LSB
LSB
2 x VREF3
VIN+ - VIN -
VCM = VREF
VCM = VREF
VCM4 ± VREF/2 VCM4 ± VREF/2
VCM4 ± VREF/2 VCM4 ± VREF/2
±1
±1
20
20
6
6
When in Track
When in Hold
VDD = 4.75V to 5.25V
(±1% tolerance
for specified performance)
VDD = 2.7V to 3.6V
(±1% tolerance
for specified performance)
VIN+ - VIN
-
min
min
max
max
max
max
max
max
max
max
max
max
max
V
V
V
µA max
pF typ
pF typ
2.5 5
2.5 5
V
DC Leakage Current
VREF Input Capacitance
2.0 6
±1
15
2.0 6
±1
15
V
µA max
pF typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN7
2.4
0.8
±1
10
2.4
0.8
±1
10
V min
V max
µA max
pF max
2.8
2.8
V min
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance 7
Output Coding
REV. PrF
Typically 10nA, VIN = 0VorVDD
VDD = 4.75V to 5.25V
ISOURCE = 200µA
VDD = 2.7V to 3.6V
ISOURCE = 200µA
I SINK =200µA
–2–
2.4
0.4
±1
10
Two’s
Complement
2.4
0.4
±1
10
Two’s
Comlement
V min
V max
µA max
pF max
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
AD7450A - SPECIFICATIONS
Parameter
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time 2
Throughput Rate 8
POWER REQUIREMENTS
V DD
I DD9,10
Normal Mode(Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Full Power-Down
Test Conditions/Comments
A Version1 B Version1
Units
888ns with an 18MHz SCLK
16
16
SCLK cycles
Sine Wave Input
Step Input
200
TBD
1
200
TBD
1
ns max
ns max
MSPS max
Range: 3 V+20%/-10%;
5 V ± 5%
SCLK On or Off
VDD = 4.75V to 5.25V,
1.38mW typ for 100ksps9
VDD = 2.7V to 3.6V,
0.53mW typ for 100ksps9
SCLK On or Off
VDD
VDD
VDD
VDD
=5
=3
=5
=3
V.
V.
V. SCLK On or Off
V. SCLK On or Off
2.7V/5.25V
2.7V/5.25V
Vmin/max
0.5
0.5
mA typ
1.8
1.8
mA max
1.25
1
1.25
1
mA max
µA max
9
3.75
5
3
9
3.75
5
3
mW max
mW max
µW max
µW max
NOTES
1
Temperature ranges as follows: A and B Versions: –40°C to +85°C.
2
See ‘Terminology’ section.
3
Because the input spans of V IN+ and V IN- are both V REF, and they are 180° out of phase, the differential voltage is 2 x VREF .
4
Common Mode Voltage. The input signal can be centered on any choice of dc Common Mode Voltage as long as this value is in the range
specified in Figures 9 and 10.
5
The AD7450A is functional with a reference input from100mV and for V DD = 5V, the reference can range up to 3.5V.
6
The AD7450A is functional with a reference input from100mV and for V DD = 3V, the reference range up to 2.2V.
7
Sample tested @ +25°C to ensure compliance.
8
See ‘Serial Interface Section’.
9
See POWER VERSUS THROUGHPUT RATE section.
10
Measured with a midscale DC input.
Specifications subject to change without notice.
REV. PrF
–3–
PRELIMINARY TECHNICAL DATA
( VDD = 2.7V to 3.6V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.0 V;
VDD = 4.75V to 5.25V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.5 V;
VCM 3 = VREF; TA = TMIN to TMAX, unless otherwise noted.)
AD7440 - SPECIFICATIONS
Parameter
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion)
(SINAD) 2
FIN = 200kHz
Total Harmonic Distortion (THD) 2
Peak Harmonic or Spurious Noise2
Intermodulation Distortion (IMD) 2
Second Order Terms
Third Order Terms
Aperture Delay 2
Aperture Jitter 2
Full Power Bandwidth2
DC ACCURACY
Resolution
Integral Nonlinearity (INL) 2
Differential Nonlinearity (DNL) 2
Zero Code Error2
Positive Gain Error 2
Negative Gain Error 2
ANALOG INPUT
Full Scale Input Span
Absolute Input Voltage
V IN+
V INDC Leakage Current
Input Capacitance
REFERENCE INPUT
VREF Input Voltage
VDD
VDD
VDD
VDD
VDD
VDD
=
=
=
=
=
=
4.75V to 5.25V
2.7V to 3.6V
4.75V to 5.25V, -80dB typ
2.7V to 3.6V, -78dB typ
4.75V to 5.25V, -82dB typ
2.7V to 3.6V, -80dB typ
@ -3 dB
@ -0.1 dB
Guaranteed No Missed Codes
to 10 Bits.
VDD = 4.75V to 5.25V
VDD = 2.7V to 3.6V
VDD = 4.75V to 5.25V
VDD = 2.7V to 3.6V
VDD = 4.75V to 5.25V
VDD = 2.7V to 3.6V
B Version1
Unit
61
61
-73
-73
-73
-73
dB
dB
dB
dB
dB
dB
-78
-78
10
50
20
2.5
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
10
±0.5
Bits
LSB max
±0.5
±1.5
±3
±1.5
±3
±1.5
±3
LSB
LSB
LSB
LSB
LSB
LSB
LSB
min
min
max
max
max
max
max
max
max
max
max
max
max
2 x VREF3
VIN+ - VIN -
V
VCM = VREF
VCM = VREF
VCM4 ± VREF/2
VCM4 ± VREF/2
±1
20
6
V
V
µA max
pF typ
pF typ
When in Track
When in Hold
VDD = 4.75V to 5.25V
(±1% tolerance
for specified performance)
VDD = 2.7V to 3.6V
(±1% tolerance for specified
performance)
2.5 5
V
DC Leakage Current
VREF Input Capacitance
2.0 6
±1
15
V
µA max
pF typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN7
2.4
0.8
±1
10
V min
V max
µA max
pF max
2.8
V min
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance 7
Output Coding
REV. PrF
Typically 10nA, VIN = 0VorVDD
VDD = 4.75V to 5.25V
ISOURCE = 200µA
VDD = 2.7V to 3.6V
ISOURCE = 200µA
I SINK =200µA
–4–
2.4
0.4
±1
10
Two’s
Complement
V min
V max
µA max
pF max
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
AD7440 - SPECIFICATIONS
Parameter
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time 2
Test Conditions/Comments
888ns with an 18MHz SCLK
Sine Wave Input
Step Input
Throughput Rate 8
POWER REQUIREMENTS
V DD
I DD9,10
Normal Mode(Static)
Normal Mode (Operational)
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Full Power-Down
Range: 3 V+20%/-10%;
5 V ± 5%
SCLK On or Off
VDD = 4.75V to 5.25V,
1.38mW typ for 100ksps9
VDD = 2.7 V to 3.6V,
0.53mW typ for 100ksps9
SCLK On or Off
VDD
VDD
VDD
VDD
=5
=3
=5
=3
V.
V.
V. SCLK On or Off
V. SCLK On or Off
NOTES
1
Temperature ranges as follows: B Versions: –40°C to +85°C.
2
See ‘Terminology’ section.
3
Because the input spans of V IN+ and V IN- are both VREF, and they are 180°
4
Common Mode Voltage. The input signal can be centered on any choice
specified in Figures tbd and tbd.
5
The AD7440 is functional with a reference input from100mV and for V DD
6
The AD7440 is functional with a reference input from100mV and for V DD
7
Sample tested @ +25°C to ensure compliance.
8
See ‘Serial Interface Section’.
9
See POWER VERSUS THROUGHPUT RATE section.
10
Measured with a midscale DC input.
Specifications subject to change without notice.
REV. PrF
B Version1
16
200
TBD
1
2.7V/5.25V
Units
SCLK cycles
ns max
ns max
MSPS max
Vmin/max
0.5
mA typ
1.8
mA max
1.25
1
mA max
µA max
9
3.75
5
3
mW max
mW max
µW max
µW max
out of phase, the differential voltage is 2 x V REF.
of dc Common Mode Voltage as long as this value is in the range
= 5V, the reference can range up to 3.5V.
= 3V, the reference range up to 2.2V.
–5–
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
TIMING SPECIFICATIONS 1,2
Parameter
fSCLK
4
t CONVERT
t QUIET
t1
t2
t 35
t 45
t5
t6
t7
t 86
t POWER-UP 7
Limit at TMIN, TMAX
2.7V-3.6V
4.75V-5.25V
( VDD = 2.7V to 3.6V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.0 V;
VDD = 4.75V to 5.25V, fSCLK = 18MHz, fS = 1MSPS, VREF = 2.5 V;
VCM 3 = VREF; TA = TMIN to TMAX, unless otherwise noted.)
Units
Description
10
18
16 x tSCLK
888
25
10
18
16 x tSCLK
888
25
kHz min
MHz max
ns max
ns min
10
10
20
40
0.4 tSCLK
0.4 tSCLK
10
10
35
1
10
10
20
40
0.4 tSCLK
0.4 tSCLK
10
10
35
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tSCLK = 1/fSCLK
Minimum Quiet Time between the End of a Serial Read and the
Next Falling Edge of CS
Minimum CS Pulsewidth
CS falling Edge to SCLK Falling Edge Setup Time
Delay from CS Falling Edge Until SDATA 3-State Disabled
Data Access Time After SCLK Falling Edge
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Edge to Data Valid Hold Time
SCLK Falling Edge to SDATA 3-State Enabled
SCLK Falling Edge to SDATA 3-State Enabled
Power-Up Time from Full Power-Down
min
min
max
max
min
min
min
min
max
max
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts.
2
See Figure 1, Figure 2 and the ‘Serial Interface’ section.
3
Common Mode Voltage.
4
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
5
Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with V DD = 5 V and time for
an output to cross 0.4 V or 2.0 V for VDD = 3 V.
6
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the
timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
7
See ‘Power-up Time’ Section.
Specifications subject to change without notice.
t1
+5
t
t2
CONVERT
t5
SCLK
1
2
3
4
5
13
14
t6
t7
0
16
t8
t4
t3
SDATA
15
0
0
DB11
0
DB10
DB2
DB1
t QUIET
DB0
3-STATE
4 LEADING ZERO’S
Figure 1. AD7450A Serial Interface Timing Diagram
t1
+5
t CONVERT
t2
SCLK
1
2
3
4
0
0
0
0
4 LEADING ZERO’S
REV. PrF
5
t4
t3
SDATA
B
t5
DB9
13
14
t6
t7
DB8
15
DB0
16
t8
0
0
2 TRAILING ZEROS
Figure 2. AD7440 Serial Interface Timing Diagram
–6–
t QUIET
3-STATE
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
ABSOLUTE MAXIMUM RATINGS1
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V
VIN+ to GND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
–0.3 V to VDD + 0.3 V
VIN- to GND . . . . . . . . . . . . . . .
Digital Input Voltage to GND . . . . . . . . -0.3 V to +7 V
Digital Output Voltage to GND . -0.3 V to VDD + 0.3 V
VREF to GND . . . . . . . . . . . . . . . . . -0.3 V to VDD +0.3 V
Input Current to Any Pin Except Supplies2 . . . . ±10mA
Operating Temperature Range
Commercial (B Version) . . . . . . . . . . . -40oC to +85oC
Storage Temperature Range . . . . . . . . . -65oC to +150oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +150 o C
JA Thermal Impedance . . . . . . . . . . 205.9°C/W (MSOP)
211.5°C/W (SOT-23)
JC Thermal Impedance . . . . . . . . . 43.74°C/W (MSOP)
91.99°C/W (SOT-23)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . +215 o C
Infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . +220 o C
E S D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kV
IO L
1.6mA
TO
OUT PUT
PIN
+1.6V
CL
25pF
IO H
200µA
Figure 3. Load Circuit for Digital Output Timing
Specifications
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch up.
ORDERING GUIDE
Model
AD7450ABRT
AD7450AART
AD7450ABRM
AD7450AARM
AD7440BRT
AD7440BRM
TBD
EVAL-CONTROL BRD2 3
Linearity
Error (LSB)1
Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Evaluation Board
Controller Board
±1 LSB
±2 LSB
±1 LSB
±2 LSB
±0.5 LSB
±0.5 LSB
Package
Option 4
RT-8
RT-8
RM-8
RM-8
RT-8
RM-8
Branding Information
CSB
CSA
CSB
CSA
CTB
CTB
NOTES
1
Linearity error here refers to Integral Non-linearity Error.
2
This can be used as a stand-alone evaluation board or in conjunction with the EVALUATION BOARD CONTROLLER for evaluation/demonstration purposes.
3
EVALUATION BOARD CONTROLLER. This board is a complete unit allowing a PC to control and communicate with all Analog Devices
evaluation boards ending in the CB designators. To order a complete Evaluation Kit, you will need to order the ADC evaluation board i.e.
TBD, the EVAL-CONTROL BRD2 and a 12V AC transformer. See the TBD technote for more information.
4
RT = SOT-23; RM = MSOP
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the AD7450A/AD7440 features proprietary ESD protection
circuitry, permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REV. PrF
–7–
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
PIN FUNCTION DESCRIPTION
Pin Mnemonic
V REF
V IN+
V INGND
CS
SDATA
SCLK
VDD
Function
Reference Input for the AD7450A/AD7440. An external reference must be applied to this input. For a
5 V power supply, the reference is 2.5 V (±1%) and for a 3 V power supply, the reference is 2V (±1%)
for specified performance. This pin should be decoupled to GND with a capacitor of at least 0.1µF.
See the ‘Reference Section’ for more details.
Positive Terminal for Differential Analog Input.
Negative Terminal for Differential Analog Input.
Analog Ground. Ground reference point for all circuitry on the AD7450A/AD7440. All analog input
signals and any external reference signal should be referred to this GND voltage.
Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on
the AD7450A/AD7440 and framing the serial data transfer.
Serial Data. Logic Output. The conversion result from the AD7450A/AD7440 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data
stream of the AD7450A consists of four leading zeros followed by the 12 bits of conversion data which
are provided MSB first; the data stream of the AD7440 consists of four leading zeros, followed by the
10-bits of conversion data, followed by two trailing zeros. In both cases, the output coding is two’s
complement.
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock
input is also used as the clock source for the conversion process.
Power Supply Input. VDD is 3 V (+20%/-10%) or 5 V (±5%). This supply should be decoupled to
GND with a 0.1µF Capacitor and a 10µF Tantalum Capacitor in parallel.
PIN CONFIGURATION 8-LEAD SOT-23
VDD
1
SCLK
2
SDATA
3
AD7450A/AD7440
SOT-23
TOP VIEW
8
VREF
7
VIN +
6
VIN -
5
GND
(Not to Scale)
+5
4
PIN CONFIGURATION
VREF
1
VIN +
2
VIN -
3
AD7450A/AD7440
MSOP
TOP VIEW
8-LEAD MSOP
8
VDD
7
SCLK
6
SDATA
5
+5
(Not to Scale)
GND
4
–8–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
TERMINOLOGY
Aperture Delay
Signal to (Noise + Distortion) Ratio
This is the amount of time from the leading edge of the
sampling clock until the ADC actually takes the sample.
This is the measured ratio of signal to (noise + distortion)
at the output of the ADC. The signal is the rms amplitude
of the fundamental. Noise is the sum of all
nonfundamental signals up to half the sampling frequency
(fS/2), excluding dc. The ratio is dependent on the number
of quantization levels in the digitization process; the more
levels, the smaller the quantization noise. The theoretical
signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by:
Thus for a 12-bit converter, this is 74 dB and for a 10-bit
converter, this is 62dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms
sum of harmonics to the fundamental. For the AD7450, it
is defined as:
2
2
2
2
Full Power Bandwidth
The full power bandwidth of an ADC is that input frequency at which the amplitude of the reconstructed
fundamental is reduced by 0.1dB or 3dB for a full scale
input.
Common Mode Rejection Ratio (CMRR)
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
THD (dB ) = 20 log
Aperture Jitter
This is the sample to sample variation in the effective
point in time at which the actual sample is taken.
2
V2 +V3 +V 4 +V5 +V 6
V1
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, V5 and V6 are the rms amplitudes of the second to
the sixth harmonics.
The Common Mode Rejection Ratio is defined as the
ratio of the power in the ADC output at full-scale frequency, f, to the power of a 200mV p-p sine wave applied
to the Common Mode Voltage of VIN+ and VIN- of frequency fs:
CMRR (dB) = 10log(Pf/Pfs)
Pf is the power at the frequncy f in the ADC output; Pfs is
the power at frequency fs in the ADC output.
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1
LSB change between any two adjacent codes in the ADC.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of
the rms value of the next largest component in the ADC
output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried
in the noise floor, it will be a noise peak.
Zero Code Error
This is the deviation of the midscale code transition (111...111
to 000...000) from the ideal VIN+-VIN - (i.e., 0LSB).
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal VIN+-VIN- (i.e., +VREF - 1LSB), after
the Zero Code Error has been adjusted out.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities will create
distortion products at sum and difference frequencies of
mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation
distortion terms are those for which neither m nor n are
equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
The AD7450A/AD7440 is tested using the CCIF standard
where two input frequencies near the top end of the input
bandwidth are used. In this case, the second order terms
are usually distanced in frequency from the original sine
waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the
second and third order terms are specified separately. The
calculation of the intermodulation distortion is as per the
THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of
the sum of the fundamentals expressed in dBs.
REV. PrF
Negative Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal VIN+-VIN - (i.e., -VREF + 1LSB), after
the Zero Code Error has been adjusted out.
Track/Hold Acquisition Time
The track/hold acquisition time is the minimum time
required for the track and hold amplifier to remain in
track mode for its output to reach and settle to within 0.5
LSB of the applied input signal.
Power Supply Rejection
Ratio (PSRR)
The power supply rejection ratio is defined as the ratio of
the power in the ADC output at full-scale frequency, f, to
the power of a 200mV p-p sine wave applied to the ADC
VDD supply of frequency fs. The frequency of this input
varies from 1kHz to 1MHz.
PSRR (dB) = 10 log (Pf/Pfs)
Pf is the power at frequency f in the ADC output; Pfs is
the power at frequency fs in the ADC output.
–9–
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
PERFORMANCE CURVES
0
(Default Conditions: TA = 25°C, Fs = 1MSPS, FSCLK =
18MHz)
7%%7
TITLE
7%%7
6*,
0
SINAD - dB
7%%7
7%%7
0
0
0
0
0
TITLE
0
0
0
TPC 3. AD7450A PSRR vs. Supply Ripple Frequency
with Supply Decoupling of TBD
0
'3&26&/$:L)[
TITLE
TPC 1. AD7450A SINAD vs Analog Input Frequency for
Various Supply Voltages
TPC 2 shows the Common Mode Rejection Ratio versus
VDD supply ripple frequency for both VDD = 5V and 3 V.
Here a 200mV p-p sine wave is coupled onto the Common Mode Voltage of VIN+ and VIN-.
0
6*,
0
0
0
0
0
0
TITLE
0
0
0
TITLE
TPC 4. AD7450A PSRR vs. Supply Ripple Frequency
without Supply Decoupling
6*,
0
AD7450A PERFORMANCE CURVES
(Default Conditions: TA = 25°C, Fs = 1MSPS, FSCLK
= 18MHz)
0
0
0
0
0
TITLE
0
0
0
1PJOU''5
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'*/L414
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TPC 2. AD7450A CMRR versus Frequency for VDD = 5V
and 3 V
#E
3
/
4
TPC 3 and TPC 4 shows the Power Supply Rejection
Ratio (see Terminology) versus VDD supply ripple frequency for the AD7450A/AD7440 with and without
power supply decoupling respectively.
'3&26&/$:L);
TPC 5. AD7450A Dynamic Performance with VDD =5V
–10–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
T #4
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TPC 6. Typical DNL For the AD7450A for VDD = 5V
TPC 9. Change in DNL vs. VREF for the AD7450A
for VDD = 3 V
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0 3
3
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TPC 7. Typical INL For the AD7450A for VDD = 5V
TPC 10. Change in INL vs. VREF for the AD7450A
for VDD = 5V
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TPC 8. Change in DNL vs. VREF for the AD7450A
for VDD = 5V
REV. PrF
–11–
TPC 11. Change in INL vs. VREF for the AD7450A
for VDD = 3 V
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
AD7440 PERFORMANCE CURVES
(Default Conditions: TA = 25°C, Fs = 1MSPS, FSCLK
= 18MHz)
0
TITLE
6*,
0
T
#E
3
/
4
0
8192 Point FFT
FSAMPLE = 1MSPS
FIN = 200kHz
SINAD = 61.6dB
THD = -81.7dB
SFDR = -83.1dB
0
0
0
0
TITLE
0
0
0
TPC 12. Change in Zero Code Error vs Reference Voltage
VDD = 5V and 3 V for the AD7450A
'3&26&/$:L)[
TPC 15. AD7440 Dynamic Performance with VDD =5V
7%%7
7%%7
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0
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TPC 15. Typical DNL For the AD7440 for VDD = 5V
TPC 13 Change in ENOB vs Reference Voltage
VDD = 5V and 3 V for the AD7450A
0
TITLE
T
#
4
- 3
0
3
3
&
/
*
6*,
0
0
0
0
0
0
TITLE
0
0
0
TPC 14. Histogram of 10000 conversions of a DC Input for
the AD7450A with VDD = 5V
–12–
$0%&
TPC 16. Typical INL For the AD7440 for VDD = 5V
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
CIRCUIT INFORMATION
The AD7450A/AD7440 are 12- and 10- bit, fast, low
power, single supply, successive approximation analog-todigital converters (ADC). They can operate with a 5 V
and 3 V power supply and are capable of throughput rates
up to 1MSPS when supplied with an 18MHz SCLK. They
require an external reference to be applied to the VREF pin,
with the value of the reference chosen depending on the
power supply and what suits the application.
The AD7450A/AD7440 requires an external reference.
When operated with a 5 V supply, the maximum reference
that can be applied is 3.5 V and when operated with a 3 V
supply, the maximum reference that can be applied is 2.2
V. (See ‘Reference Section’).
disconnected once the conversion begins. The Control
Logic and the charge redistribution DACs are used to add
and subtract fixed amounts of charge from the sampling
capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the
ADC’s output code. The output impedances of the
sources driving the VIN+ and the VIN- pins must be
matched otherwise the two inputs will have different settling times, resulting in errors.
CAPACITIVE
DAC
The AD7450A/AD7440 has an on-chip differential track
and hold amplifier, a successive approximation (SAR)
ADC and a serial interface, housed in either an 8-lead
SOT-23 or MSOP package. The serial clock input accesses data from the part and also provides the clock source
for the successive-approximation ADC. The AD7450A/
AD7440 feature a power-down option for reduced power
consumption between conversions. The power-down feature is implemented across the standard serial interface as
described in the ‘Modes of Operation’ section.
CONVERTER OPERATION
V IN-
A SW1
A SW2
B
VREF
SW3
The output coding for the AD7450A/AD7440 is two’s
complement. The designed code transitions occur at successive LSB values (i.e. 1LSB, 2LSBs, etc.). The LSB
size of the AD7450A is 2xVREF/4096 and the LSB size of
the AD7440 is 2xVREF/1024. The ideal transfer characteristic of the AD7450A/AD7440 is shown in figure 6.
1LSB = 2xVREF/4096 (AD7450A)
011...111
iLSB = 2xVREF/1024 (AD7440)
011...110
000...001
000...000
111...111
100...010
100...001
100...000
Cs
-VREF + 1LSB
CAPACITIVE
DAC
0LSB
+VREF - 1LSB
ANALOG INPUT
(VIN+- VIN-)
Figure 6. AD7450A/AD7440 Ideal Transfer Characteristic
When the ADC starts a conversion (figure 5), SW3 will
open and SW1 and SW2 will move to position B, causing
the comparator to become unbalanced. Both inputs are
REV. PrF
Cs
ADC TRANSFER FUNCTION
CONTROL
LOGIC
Figure 4. ADC Acquisition Phase
CONTROL
LOGIC
Figure 5. ADC Conversion Phase
COMPARATOR
Cs
B
SW3
CAPACITIVE
DAC
CAPACITIVE
DAC
VIN+
A SW1
A SW2
B
VREF
V IN-
ADC CODE
The AD7450A/AD7440 is a successive approximation
ADC based around two capacitive DACs. Figures 4 and 5
show simplified schematics of the ADC in Acquisition and
Conversion phase respectively. The ADC comprises of
Control Logic, a SAR and two capacitive DACs.
In figure 4 (acquisition phase), SW3 is closed and SW1 and
SW2 are in position A, the comparator is held in a balanced condition and the sampling capacitor arrays acquire
the differential signal on the input
COMPARATOR
Cs
B
VIN+
–13–
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
TYPICAL CONNECTION DIAGRAM
Figure 7 shows a typical connection diagram for the
AD7450A/AD7440 for both 5 V and 3 V supplies. In this
setup the GND pin is connected to the analog ground
plane of the system. The VREF pin is connected to either
a 2.5 V or a 2 V decoupled reference source depending on
the power supply, to set up the analog input range. The
common mode voltage has to be set up externally and is
the value that the two inputs are centered on. The conversion result is output in a 16-bit word with four leading
zeros followed by the MSB of the 12-bit or 10-bit result.
The 10-bit result of the AD7440 is followed by two trailing zeros. For more details on driving the differential
inputs and setting up the common mode, see the ‘Driving
Differential Inputs’ section.
0.1µF
VDD
VREF
P-to-P
CM*
10µF
For ease of use, the common mode can be set up to be
equal to VREF, resulting in the differential signal being
±VREF centered on VREF. When a conversion takes place,
the common mode is rejected resulting in a virtually noise
free signal of amplitude -VREF to +VREF corresponding to
the digital codes of 0 to 4095 in the case of the AD7450A
and 0 to 1024 in the case of the AD7440.
SCLK
µC/µP
SDATA
VREF
P-to-P
Figures 9 and 10 show how the common mode range typically varies with VREF for both a 5 V and a 3 V power
supply. The common mode must be in this range to guarantee the functionality of the AD7450A/AD7440.
+3V/+5V
SUPPLY
SERIAL
INTERFACE
AD7450A/AD7440
VIN+
+5
CM*
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN- pins (i.e.
VIN+ - VIN-). VIN+ and VIN- are simultaneously driven by
two signals each of amplitude VREF that are 180° out of
phase. The amplitude of the differential signal is therefore
-VREF to +VREF peak-to-peak (i.e. 2 x VREF). This is regardless of the common mode (CM). The common mode
is the average of the two signals, i.e. (VIN+ + VIN-)/2 and
is therefore the voltage that the two inputs are centered on.
This results in the span of each input being CM ± VREF/2.
This voltage has to be set up externally and its range varies with VREF. As the value of VREF increases, the
common mode range decreases. When driving the inputs
with an amplfier, the actual common mode range will be
determined by the amplifier’s output voltage swing.
VINGND
VREF
2V/2.5V
VREF
0.1µF
* CM - COMMON MODE VOLTAGE
Figure 7. Typical Connection Diagram
THE ANALOG INPUT
The analog input of the AD7450A/AD7440 is fully differential. Differential signals have a number of benefits over
single ended signals including noise immunity based on
the device’s common mode rejection, improvements in
distortion performance, doubling of the device’s available
dynamic range and flexibility in input ranges and bias
points. Figure 8 defines the fully differential analog input
of the AD7450A/AD7440.
VREF
P-to-P
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7
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Figure 9. Input Common Mode Range versus VREF
(VDD = 5V and VREF (max) = 3.5V)
VIN+
AD7450A/
AD7440
COMMON
MODE
VOLTAGE
VREF
P-to-P
VIN-
Figure 8. Differential Input Definition
–14–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
7
7
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For ac applications, removing high frequency components
from the analog input signal is recommended by the use of
an RC low-pass filter on the relevant analog input pins.
In applications where harmonic distortion and signal to
noise ratio are critical, the analog input should be driven
from a low impedance source. Large source impedances
will significantly affect the ac performance of the ADC.
This may necessitate the use of an input buffer amplifier.
The choice of the opamp will be a function of the particular application.
7
VDD
D
R1
VIN+
C1
C2
D
VDD
73&'
D
Figure 10. Input Common Mode Range versus VREF
(VDD= 3V and VREF (max) = 2V)
C1
Figure 11 shows examples of the inputs to VIN+ and VINfor different values of VREF for VDD = 5 V. It also gives
the maximum and minimum common mode voltages for
each reference value according to figure 9.
Reference = 1.25 V (VREFmax/2)
VIN1.25 V peak to peak
Common Mode (CM)
CMmin = 0.625 V
CMmax = 4.42 V
VIN+
Reference = 2.5 V (VREFmax)
VIN-
Common Mode (CM)
CMmin = 1.25 V
CMmax = 3.75 V
2.5 V peak to peak
VIN+
R1
C2
VIND
Figure 12. Equivalent Analog Input Circuit.
Conversion Phase - Switches Open
Track Phase - Switches Closed
When no amplifier is used to drive the analog input, the
source impedance should be limited to low values. The
maximum source impedance will depend on the amount of
Total Harmonic Distortion (THD) that can be tolerated.
The THD will increase as the source impedance increases
and performance will degrade. Figure 13 shows a graph
of the THD versus analog input signal frequency for different source impedances for both VDD = 5 V and 3 V.
Figure 11. Examples of the Analog Inputs to VIN+ and VINfor Different Values of VREF for VDD = 5 V.
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Analog Input Structure
T
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5
Figure 12 shows the equivalent circuit of the analog input
structure of the AD7450A/AD7440. The four diodes
provide ESD protection for the analog inputs. Care must
be taken to ensure that the analog input signals never exceed the supply rails by more than 300mV. This will
cause these diodes to become forward biased and start
conducting into the substrate. These diodes can conduct
up to 10mA without causing irreversible damage to the
part. The capacitors C1, in figure 12 are typically 4pF
and can primarily be attributed to pin capacitance. The
resistors are lumped components made up of the on-resistance of the switches. The value of these resistors is
typically about 100. The capacitors, C2, are the ADC’s
sampling capacitors and have a capacitance of 16pF typically.
REV. PrF
3 Ω
3 LΩ
*/
*/
3 Ω
*/
3 Ω
*/
*/165'3&26&/$:L)[
Figure 13.THD vs Analog Input Frequency for Various
Source Impedances
–15–
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
Figure 14 shows a graph of THD versus analog input
frequency for VDD of 5 V ± 5% and 3 V +20/-10%, while
sampling at 1MSPS with a SCLK of 18 MHz. In this
case the source impedance is 10.
5"¡D
7%%7
balance this parallel impedance on the input and thus ensure
that both the positive and negative analog inputs have the
same gain (see figure 15). The outputs of the amplifier are
perfectly matched, balanced differential outputs of identical
amplitude and are exactly 180o out of phase.
The AD8138 is specified with 3 V, 5 V and ±5 V power
supplies but the best results are obtained when it is supplied
by ±5 V. A lower cost device that could also be used in this
configuration with slight differences in characteristics to the
AD8138 but with similar performance and operation is the
AD8132.
7%%7
T
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5
3.75V
2.5V
1.25V
Rf1
Rs*
Rg1
Vocm
+2.5V
GND
7%%7
51R
Rg2
C*
AD8138
Rs*
-2.5V
VINC*
Rf2
7%%7
VIN+
AD7450A/
AD7440
VREF
3.75V
2.5V
1.25V
*/165'3&26&/$:L)[
*Mount as close to the AD7450A/AD7440 as
possible and ensure high
precision Rs and Cs are used
EXTERNAL
VREF (2.5V)
.
Figure 14.THD vs Analog Input Frequency for 3V and 5V
Supply Voltages
Rs - 50R; C - 1nF;
Rg1=Rf1=Rf2= 499R; Rg2 = 523R
Figure 15. Using the AD8138 as a Single Ended to
Differential Amplifier
DRIVING DIFFERENTIAL INPUTS
Differential operation requires that VIN+ and VIN- be simultaneously driven with two equal signals that are 180o
out of phase. The common mode must be set up externally and has a range which is determined by VREF, the
power supply and the particular amplifier used to drive the
analog inputs (see figures 9 and 10). Differential modes
of operation with either an ac or dc input, provide the best
THD performance over a wide frequency range. Since
not all applications have a signal preconditioned for differential operation, there is often a need to perform single
ended to differential conversion.
Differential Amplifier
An ideal method of applying differential drive to the AD7450A/
AD7440 is to use a differential amplifier such as the AD8138.
This part can be used as a single ended to differential
amplifier or as a differential to differential amplifier. In both
cases the analog input needs to be bipolar. It also provides
common mode level shifting and buffering of the bipolar
input signal. Figure 15 shows how the AD8138 can be used
as a single ended to differential amplifier. The positive and
negative outputs of the AD8138 are connected to the respective inputs on the ADC via a pair of series resistors to
minimize the effects of switched capacitance on the front end
of the ADCs. The RC low pass filter on each analog input
is recommended in ac applications to remove high frequency
components of the analog input. The architecture of the
AD8138 results in outputs that are very highly balanced over
a wide frequency range without requiring tightly matched
external components.
Opamp Pair
An opamp pair can be used to directly couple a differential
signal to the AD7450A/AD7440. The circuit configurations shown in figures 16(a) and 16(b) show how a dual
opamp can be used to convert a single ended signal into a
differential signal for both a bipolar and a unipolar input
signal respectively.
The voltage applied to point A sets up the Common Mode
Voltage. In both diagrams, it is connected in some way to
the reference but any value in the common mode range
can be input here to setup the common mode. Examples
of suitable dual opamps that could be used in this configuration to provide differential drive to the AD7450A/
AD7440 are the AD8042, AD8056 and the AD8022.
Care must be taken when chosing the opamp used, as the
selection will depend on the required power supply and
the system performance objectives. The driver circuits in
figures 16(a) and 16(b) are optimized for dc coupling
applications requiring optimum distortion performance.
The differential op-amp driver circuit in figure 16(a) is
configured to convert and level shift a single ended,
ground referenced (bipolar) signal to a differential signal
centered at the VREF level of the ADC.
The circuit configuration shown in figure 16(b) converts a
unipolar, single ended signal into a differential signal.
If the analog input source being used has zero impedance then
all four resistors (Rg1, Rg2, Rf1, Rf2) should be the same. If
the source has a 50 impedance and a 50 termination for
example, the value of Rg2 should be increased by 25 to
–16–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
390Ω
GND
3.75V
2.5V
1.25V
220Ω
2 X VREF P-to-P
V+
VDD
R
R
27Ω
C
V220Ω
VIN+ AD7450A/
AD7440
220Ω
220Ω
VIN- V
REF
R
3.75V
2.5V
.
1.25V
V+
)
27Ω
VIN+
AD7450/
AD7440
VREF
VIN-
EXTERNAL
VREF (2.5V)
0.1µF
V20KΩ
Figure 17. Using an RF Transformer to Generate
Differential Inputs
10KΩ
EXTERNAL
VREF
.
.
REFERENCE SECTION
Figure 16(a). Dual Opamp Circuit to Convert a Single Ended
Bipolar Input into a Differential Input
220Ω
2 X VREF P-to-P
VREF
GND
390Ω
V+
VDD
27Ω
VIN+ AD7450A/
V-
AD7440
220Ω
220Ω
.
VIN- V
REF
V+
A
0.1µF
27Ω
An external reference source is required to supply the
reference to the AD7450A/AD7440. This reference input
can range from 100 mV to 3.5 V. With a 5 V power supply, the specified reference is 2.5 V and maximum
reference is 3.5 V. With a 3 V power supply, the specified
reference is 2 V and the maximum reference is 2.2 V. In
both cases, the reference is functional from 100mV.
It is important to ensure that, when chosing the reference
value for a particular application, the maximum analog
input range (VINmax) is never greater than VDD + 0.3V
to comply with the maximum ratings of the device. The
following two examples calculate the maximum VREF input that can be used when operating the AD7450A/
AD7440 at VDD of 5 V and 3.3 V respectively.
Example 1:
VINmax = VDD + 0.3
VINmax = VREF + VREF/2
V-
If VDD = 5 V
10KΩ
EXTERNAL
VREF
then VINmax = 5.3 V
Therefore 3xVREF/2 = 5.3 V
.
VREF max = 3.5 V
Figure 16(b). Dual Opamp Circuit to Convert a Single Ended
Unipolar Input into a Differential Input
RF Transformer
In systems that do not need to be dc-coupled, an RF transformer with a center tap offers a good solution for
generating differential inputs. Figure 17 shows how a
transformer is used for single ended to differential conversion. It provides the benefits of operating the ADC in the
differential mode without contributing additional noise
and distortion. An RF transformer also has the benefit of
providing electrical isolation between the signal source
and the ADC. A transformer can be used for most ac applications. The center tap is used to shift the differential
signal to the common mode level required, in this case it
is connected to the reference so the common mode level is
the value of the reference.
REV. PrF
Therefore, when operating at VDD = 5 V, the value of
VREF can range from 100mV to a maximum value of 3.5V.
When VDD = 4.75 V, VREF max = 3.17 V.
Example 2:
VINmax = VDD + 0.3
VINmax = VREF + VREF/2
If VDD = 3.3V
then VINmax = 3.6 V
Therefore 3xVREF/2 = 3.6 V
VREF max = 2.4 V
Therefore, when operating at VDD = 3.3 V, the value of
VREF can range from 100mV to a maximum value of 2.4V.
When VDD = 2.7 V, VREF max = 2 V.
These examples show that the maximum reference applied
to the AD7450A/AD7440 is directly dependant on the
value applied to VDD.
–17–
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
signals to comply with the input requirements. An
opamp can be configured to rescale and level shift the
ground based bipolar signal so it is compatible with the
selected input range of the AD7450A/AD7440 (see Figure
19).
The value of the reference sets the analog input span and
the common mode voltage range. Errors in the reference
source will result in gain errors in the AD7450A/AD7440
transfer function and will add to specified full scale errors
on the part. A capacitor of 0.1µF should be used to
decouple the VREF pin to GND.
+5V
R
Table I lists examples of suitable voltage references that
could be used that are available from Analog Devices and
Figure 18 shows a typical connection diagram for the
VREF pin.
+2.5V
+2.5V
0V
0V
R
V IN
-2.5V
R
R
0.1µF
Table I Examples of Suitable Voltage References
VIN+
AD7450/
AD7440
VINVREF
EXTERNAL
VREF (2.5V)
Reference Output
Voltage
Initial
Accuracy
(% max)
REF192
REF43
AD780
0.08-0.4
0.06-0.1
0.04-0.2
2.5
2.5
2.5
Operating
Current
(µA)
45
600
1000
AD780
NC
VDD
1
OpSel
0.1µF
NC
Temp
Vout
NC
6 2.5 V
4 GND
Trim
5
3
10nF
8
SERIAL INTERFACE
Figures 1 and 2 show detailed timing diagrams for the
serial interface of the AD7450A and the AD7440 respectively. The serial clock provides the conversion clock and
also controls the transfer of data from the device during
conversion. CS initiates the conversion process and frames
the data transfer. The falling edge of CS puts the track
and hold into hold mode and takes the bus out of threestate. The analog input is sampled and the conversion
initiated at this point. The conversion will require 16
SCLK cycles to complete.
VDD
AD7450/
AD7440*
VREF
7
2 VIN
0.1µF
Figure 19. Applying a Bipolar Single Ended Input to the
AD7450A/AD7440
0.1µF
NC
*ADDITIONAL PINS OMITTED FOR CLARITY
Once 13 SCLK falling edges have occurred, the track and
hold will go back into track on the next SCLK rising edge
as shown at point B in Figures 1 and 2. On the 16th
SCLK falling edge the SDATA line will go back into
three-state. If the rising edge of CS occurs before 16
SCLKs have elapsed, the conversion will be terminated
and the SDATA line will go back into three-state.
Figure 18. Typical VREF Connection Diagram for VDD = 5 V
When supplied with a 5 V power supply, the AD7450A/
AD7440 can handle a single ended input. The design of
this part is optimized for differential operation so with a
single ended input, performance will degrade. Linearity
will degrade by typically 0.2 LSBs, Zero Code and the
Full Scale Errors will degrade by typically 2 LSBs and
AC performance is not guaranteed.
The conversion result from the AD7450A/AD7440 is provided on the SDATA output as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input. The
data stream of the AD7450A consists of four leading zeros,
followed by 12 bits of conversion data which is provided MSB
first; the data stream of the AD7440 consists of four leading
zeros, followed by the 10 bits of conversion data, followed
by two trailing zeros, which is also provided MSB first. In
both cases, the output coding is twos complement.
To operate the AD7450A/AD7440 in single ended mode,
the VIN+ input is coupled to the signal source while the
VIN- input is biased to the appropriate voltage corresponding to the mid-scale code transition. This voltage is the
Common Mode, which is a fixed dc voltage (usually the
reference). The VIN+ input swings around this value and
should have voltage span of 2 x VREF to make use of the
full dynamic range of the part. The input signal will therefore have peak to peak values of Common Mode ±VREF.
If the analog input is unipolar then an opamp in a noninverting unity gain configuration can be used to drive the
VIN+ pin. Because the ADC operates from a single supply,
it will be necessary to level shift ground based bipolar
16 serial clock cycles are required to perform a conversion
and to access data from the AD7450A/AD7440. CS going
low provides the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out
on the subsequent SCLK falling edges beginning with the
second leading zero. Thus the first falling clock edge on the
serial clock provides the second leading zero. The final bit
in the data transfer is valid on the 16th falling edge, having
been clocked out on the previous (15th) falling edge. Once
the conversion is complete and the data has been accessed
after the 16 clock cycles, it is important to ensure that, before
the next conversion is initiated, enough time is left to meet
the acquisition and quiet time specifications - see the Timing
SINGLE ENDED OPERATION
–18–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
Examples. To achieve 1MSPS with an 18MHz clock for
VDD = 3 V and 5 V, an 18 clock burst will perform the
conversion and leave enough time before the next conversion
for the acquisition and quiet time.
In applications with a slower SCLK, it may be possible to
read in data on each SCLK rising edge i.e. the first rising
edge of SCLK after the CS falling edge would have the
leading zero provided and the 15th SCLK edge would have
DB0 provided.
Timing Example 1
Having FSCLK = 18MHz and a throughput rate of
1MSPS gives a cycle time of:
1/Throughput = 1/1,000,000 = 1µs
A cycle consists of:
t2 + 12.5 (1/FSCLK) + tACQ = 1µs.
Therefore if t2 = 10ns then:
10ns + 12.5(1/18MHz) + tACQ = 1µs
tACQ = 296ns
This 296ns satisfies the requirement of 200ns for tACQ.
As in this example and with other slower clock values, the
signal may already be acquired before the conversion is
complete but it is still necessary to leave 25ns minimum
tQUIET between conversions. In example 2 the signal should
be fully acquired at approximately point C in Figure 20.
MODES OF OPERATION
The mode of operation of the AD7450A/AD7440 is selected
by controlling the logic state of the CS signal during a
conversion. There are two possible modes of operation,
Normal Mode and Power-Down Mode. The point at which
CS is pulled high after the conversion has been initiated will
determine whether or not the AD7450A/AD7440 will enter
the power-down mode. Similarly, if already in power-down,
CS controls whether the devices will return to normal
operation or remain in power-down. These modes of
operation are designed to provide flexible power management options. These options can be chosen to optimize the
power dissipation/throughput rate ratio for differing application requirements.
Normal Mode
This mode is intended for fastest throughput rate performance. The user does not have to worry about any
power-up times with the AD7450A/AD7440 remaining
fully powered up all the time. Figure 21 shows the general diagram of the operation of the AD7450A/AD7440 in
this mode. The conversion is initiated on the falling edge
of CS as described in the ‘Serial Interface Section’. To
ensure the part remains fully powered up, CS must remain
low until at least 10 SCLK falling edges have elapsed after
the falling edge of CS.
From Figure 20, tACQ comprises of:
2.5(1/FSCLK) + t8 + tQUIET
where t8 = 35ns. This allows a value of 122ns for tQUIET
satisfying the minimum requirement of 25ns.
Timing Example 2
Having FSCLK = 5MHz and a throughput rate of
315kSPS gives a cycle time of :
1/Throughput = 1/315000 = 3.174µs
A cycle consists of:
t2 + 12.5 (1/FSCLK) + tACQ = 3.174µs.
Therefore if t2 is 10ns then:
10ns + 12.5(1/5MHz) + tACQ = 3.174µs
tACQ = 664ns
This 664ns satisfies the requirement of 200ns for tACQ.
From Figure 20, tACQ comprises of:
2.5(1/FSCLK) + t8 + tQUIET
where t8 = 35ns. This allows a value of 129ns for tQUIET
satisfying the minimum requirement of 25ns.
If CS is brought high any time after the 10th SCLK falling edge, but before the 16th SCLK falling edge, the part
will remain powered up but the conversion will be terminated and SDATA will go back into three-state. Sixteen
serial clock cycles are required to complete the conversion
and access the complete conversion result. CS may idle
high until the next conversion or may idle low until sometime prior to the next conversion. Once a data transfer is
complete, i.e. when SDATA has returned to three-state,
another conversion can be initiated after the quiet time,
tQUIET has elapsed by again bringing CS low.
+5 t CONVERT
SCLK
t
10ns 2
1
2
3
4
C
B
t5
5
13
14
t6
15
16
t8
t ACQUISITION
12.5(1/fSCLK )
1/Throughput
Figure 20. Serial Interface Timing Example
REV. PrF
tQUIET
–19–
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
Power up Time
+5
SCLK
1
10
SDATA
The power up time of the AD7450A/AD7440 is typically
1µsec, which means that with any frequency of SCLK up
to 18MHz, one dummy cycle will always be sufficient to
allow the device to power-up. Once the dummy cycle is
complete, the ADC will be fully powered up and the input
signal will be acquired properly. The quiet time tQUIET
must still be allowed from the point at which the bus goes
back into three-state after the dummy conversion, to the
next falling edge of CS.
16
4 LEADING ZEROS + CONVERSION RESULT
Figure 21. Normal Mode Operation
Power Down Mode
This mode is intended for use in applications where
slower throughput rates are required; either the ADC is
powered down between each conversion, or a series of
conversions may be performed at a high throughput rate
and the ADC is then powered down for a relatively long
duration between these bursts of several conversions.
When the AD7450A/AD7440 is in the power down mode,
all analog circuitry is powered down. To enter power
down mode, the conversion process must be interrupted by
bringing CS high anywhere after the second falling edge
of SCLK and before the tenth falling edge of SCLK as
shown in Figure 22.
+5
1
2
10
SCLK
THREE STATE
SDATA
Figure 22. Entering Power Down Mode
Once CS has been brought high in this window of
SCLKs, the part will enter power down and the conversion that was initiated by the falling edge of CS will be
terminated and SDATA will go back into three-state.
The time from the rising edge of CS to SDATA threestate enabled will never be greater than t8 (see the
‘Timing Specifications’). If CS is brought high before
the second SCLK falling edge, the part will remain in
normal mode and will not power-down. This will avoid
accidental power-down due to glitches on the CS line.
In order to exit this mode of operation and power the
AD7450A/AD7440 up again, a dummy conversion is performed. On the falling edge of CS the device will begin
to power up, and will continue to power up as long as CS
is held low until after the falling edge of the 10th SCLK.
The device will be fully powered up after 1µsec has
elapsed and, as shown in Figure 23, valid data will result
from the next conversion.
If CS is brought high before the 10th falling edge of
SCLK, the AD7450A/AD7440 will again go back into
power-down. This avoids accidental power-up due to
glitches on the CS line or an inadvertent burst of eight
SCLK cycles while CS is low. So although the device
may begin to power up on the falling edge of CS, it will
again power-down on the rising edge of CS as long as it
occurs before the 10th SCLK falling edge.
When running at the maximum throughput rate of
1MSPS, the AD7450A/AD7440 will power up and acquire a signal within ±0.5LSB in one dummy cycle, i.e.
1µs. When powering up from the power-down mode with
a dummy cycle, as in Figure 23, the track and hold, which
was in hold mode while the part was powered down, returns to track mode after the first SCLK edge the part
receives after the falling edge of CS. This is shown as
point A in Figure 23.
Although at any SCLK frequency one dummy cycle is
sufficient to power the device up and acquire VIN, it does
not necessarily mean that a full dummy cycle of 16
SCLKs must always elapse to power up the device and
acquire VIN fully; 1µs will be sufficient to power the device up and acquire the input signal.
For example, if a 5MHz SCLK frequency was applied to
the ADC, the cycle time would be 3.2µs (i.e. 1/(5MHz) x
16). In one dummy cycle, 3.2µs, the part would be powered up and VIN acquired fully. However after 1µs with a
5MHz SCLK only 5 SCLK cycles would have elapsed. At
this stage, the ADC would be fully powered up and the
signal acquired. So, in this case the CS can be brought
high after the 10th SCLK falling edge and brought low
again after a time tQUIET to initiate the conversion.
When power supplies are first applied to the AD7450A/
AD7440, the ADC may either power up in the powerdown mode or normal mode. Because of this, it is best to
allow a dummy cycle to elapse to ensure the part is fully
powered up before attempting a valid conversion. Likewise, if the user wishes the part to power up in
power-down mode, then the dummy cycle may be used to
ensure the device is in power-down by executing a cycle
such as that shown in Figure 22.
Once supplies are applied to the AD7450A/AD7440, the
power up time is the same as that when powering up from
the power-down mode. It takes approximately 1µs to
power up fully if the part powers up in normal mode. It is
not necessary to wait 1µs before executing a dummy cycle
to ensure the desired mode of operation. Instead, the
dummy cycle can occur directly after power is supplied to
the ADC. If the first valid conversion is then performed
directly after the dummy conversion, care must be taken to
ensure that adequate acquisition time has been allowed.
As mentioned earlier, when powering up from the powerdown mode, the part will return to track upon the first
–20–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
tPOWERUP
THE PART BEGINS
TO POWER UP
+5
SCLK
A
1
SDATA
THE PART IS FULLY POWERED
UP WITH VIN FULLY ACQUIRED
10
16
10
1
INVALID DATA
16
VALID DATA
Figure 23. Exiting Power Down Mode
SCLK edge applied after the falling edge of CS. However, when the ADC powers up initially after supplies are
applied, the track and hold will already be in track. This
means if (assuming one has the facility to monitor the
ADC supply current) the ADC powers up in the desired
mode of operation and thus a dummy cycle is not required
to change mode, then neither is a dummy cycle required
to place the track and hold into track.
For throughput rates above 320kSPS, it is recommended
that for optimum power performance, the serial clock
frequency is reduced.
100
For example, if the AD7450A/AD7440 is operated in
continuous sampling mode with a throughput rate of
100kSPS and an SCLK of 18MHz and the device is
placed in the power down mode between conversions, then
the power consumption is calculated as follows:
POWER (mW)
By using the power-down mode on the AD7450A/AD7440
when not converting, the average power consumption of
the ADC decreases at lower throughput rates. Figure 24
shows how, as the throughput rate is reduced, the device
remains in its power-down state longer and the average
power consumption reduces accordingly. It shows this for
both 5V and 3V power supplies.
VDD = 5V
10
POWER VERSUS THROUGHPUT RATE
1
VDD = 3V
0.1
0.01
0
50
100
150
200
250
300
350
THROUGHPUT (kSPS)
Power dissipation during normal operation = 9mW typ
(for VDD = 5V).
Figure 24. Power versus Throughput Rate for Power Down
Mode
If the power up time is 1 dummy cycle i.e. 1µsec, and the
remaining conversion time is another cycle i.e. 1µsec, then
the AD7450A/AD7440 can be said to dissipate 9mW for
2µsec* during each conversion cycle.
*This figure assumes a very short time used to enter the power down
mode. This will increase as the burst of clocks used to enter the
power down mode is increased.
If the throughput rate = 100kSPS then the cycle time =
10µsec and the average power dissipated during each cycle
is:
(2/10) x 9mW = 1.8mW
For the same scenario, if VDD = 3V, the power dissipation
during normal operation is 3.75mW max.
The AD7450A/AD7440 can now be said to dissipate
3.75mW for 2µsec* during each conversion cycle.
The average power dissipated during each cycle with a
throughput rate of 100kSPS is therefore:
(2/10) x 3.75mW = 0.75mW
This is how the power numbers in Figure 24 are calculated.
REV. PrF
MICROPROCESSOR AND DSP INTERFACING
The serial interface on the AD7450A/AD7440 allows the
part to be directly connected to a range of different microprocessors. This section explains how to interface the
AD7450A/AD7440 with some of the more common
microcontroller and DSP serial interface protocols.
AD7450A/AD7440 to ADSP21xx
The ADSP21xx family of DSPs are interfaced
the AD7450A/AD7440 without any glue logic
The SPORT control register should be set up
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data words
ISCLK = 1, Internal serial clock
TFSR = RFSR = 1, Frame every word
IRFS = 0,
–21–
directly to
required.
as follows:
Signal
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
ITFS = 1.
To implement the power-down mode SLEN should be set
to 1001 to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 25. The
ADSP21xx has the TFS and RFS of the SPORT tied
together, with TFS set as an output and RFS set as an
input. The DSP operates in Alternate Framing Mode and
the SPORT control register is set up as described. The
Frame Synchronisation signal generated on the TFS is
tied to CS and as with all signal processing applications
equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling
rate of the ADC and under certain conditions, equidistant
sampling may not be acheived.
serial port of the TMS320C5x/C54x is set up to operate
in burst mode with internal CLKX (TX serial clock) and
FSX (TX frame sync). The serial port control register
(SPC) must have the following setup: FO = 0, FSM = 1,
MCM = 1 and TXM = 1. The format bit, FO, may be set
to 1 to set the word length to 8-bits, in order to implement the power-down mode on the AD7450A/AD7440.
The connection diagram is shown in Figure 26. It should
be noted that for signal processing applications, it is imperative that the frame synchronisation signal from the
TMS320C5x/C54x will provide equidistant sampling.
AD7450A/AD7440*
TMS320C5x/C54x*
SCLK
CLKX
CLKR
ADSP21xx*
AD7450A/AD7440*
SCLK
SCLK
SDATA
DR
+5
RFS
SDATA
+5
DR
FSX
FSR
*ADDITIONAL PINS OMITTED FOR CLARITY
TFS
Figure 26. Interfacing to the TMS320C5x/C54x
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7450A/AD7440 to DSP56xxx
Figure 25. Interfacing to the ADSP 21xx
The timer registers etc., are loaded with a value which
will provide an interrupt at the required sample interval.
When an interrupt is received, a value is transmitted with
TFS/DT (ADC control word). The TFS is used to control the RFS and hence the reading of data. The frequency
of the serial clock is set in the SCLKDIV register. When
the instruction to transmit with TFS is given, (i.e.
AX0=TX0), the state of the SCLK is checked. The DSP
will wait until the SCLK has gone High, Low and High
before transmission will start. If the timer and SCLK values are chosen such that the instruction to transmit occurs
on or near the rising edge of SCLK, then the data may be
transmitted or it may wait until the next clock edge.
For example, the ADSP-2111 has a master clock frequency of 16MHz. If the SCLKDIV register is loaded
with the value 3 then a SCLK of 2MHz is obtained, and 8
master clock periods will elapse for every 1 SCLK period.
If the timer registers are loaded with the value 803, then
100.5 SCLKs will occur between interrupts and subsequently between transmit instructions. This situation will
result in non-equidistant sampling as the transmit instruction is occuring on a SCLK edge. If the number of
SCLKs between interrupts is a whole integer figure of N
then equidistant sampling will be implemented by the
DSP.
The connection diagram in figure 27 shows how the
AD7450A/AD7440 can be connected to the SSI (Synchronous Serial Interface) of the DSP56xxx family of DSPs
from Motorola. The SSI is operated in Synchronous
Mode (SYN bit in CRB =1) with internally generated 1word frame sync for both Tx and Rx (bits FSL1 =0 and
FSL0 =0 in CRB). Set the word length to 16 by setting
bits WL1 =1 and WL0 = 0 in CRA. To implement the
power-down mode on the AD7450A/AD7440 then the
word length can be changed to 8 bits by setting bits WL1
= 0 and WL0 = 0 in CRA. It should be noted that for
signal processing applications, it is imperative that the
frame synchronisation signal from the DSP56xxx will
provideequidistant sampling.
AD7450A/AD7440*
DSP56xxx*
SCLK
SCLK
SDATA
SRD
+5
*
SR2
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 27. Interfacing to the DSP56xx
AD7450A/AD7440 to TMS320C5x/C54x
The serial interface on the TMS320C5x/C54x uses a
continuous serial clock and frame synchronization signals
to synchronize the data transfer operations with peripheral
devices like the AD7450A/AD7440. The CS input allows
easy interfacing between the TMS320C5x/C54x and the
AD7450A/AD7440 without any glue logic required. The
–22–
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
APPLICATION HINTS
Grounding and Layout
The printed circuit board that houses the AD7450A/
AD7440 should be designed so that the analog and digital
sections are separated and confined to certain areas of the
board. This facilitates the use of ground planes that can
be easily separated. A minimum etch technique is generally best for ground planes as it gives the best shielding.
Digital and analog ground planes should be joined in only
one place and the connection should be a star ground
point established as close to the GND pin on the
AD7450A/AD7440 as possible. Avoid running digital
lines under the device as this will couple noise onto the
die. The analog ground plane should be allowed to run
under the AD7450A/AD7440 to avoid noise coupling.
The power supply lines to the AD7450A/AD7440 should
use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
Fast switching signals like clocks should be shielded with
digital ground to avoid radiating noise to other sections
of the board, and clock signals should never run near the
analog inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at
right angles to each other. This will reduce the effects of
feedthrough through the board. A microstrip technique is
by far the best but is not always possible with a doublesided board.
In this technique the component side of the board is dedicated to ground planes while signals are placed on the
solder side. Good decoupling is also important. All analog supplies should be decoupled with 10µF tantalum
capacitors in parallel with 0.1µF capacitors to GND. To
achieve the best from these decoupling components, they
must be placed as close as possible to the device.
EVALUATING THE AD7450A/AD7440 PERFORMANCE
The evaluation board package includes a fully assembled
and tested evaluation board, documentation and software
for controlling the board from a PC via the Evaluation
Board Controller. The Evaluation Board Controller can
be used in conjunction with the AD7450A/40 Evaluation
board as well as many other Analog Devices evaluation
boards ending with the CB designator, to demonstrate/
evaluate the ac and dc performance of the AD7450A/40.
The software allows the user to perform ac (fast Fourier
Transform) and dc (Histogram of codes) tests on the
AD7450A/40. See the evaluation board technical note for
more information.
REV. PrF
–23–
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
OUTLINE DIMENSIONS
Dimensions shown in inches (millimeters)
8-LEAD SOT-23 (RT-8)
0.122 (3.10)
0.110 (2.80)
8
7
6
5
0.118 (3.0)
0.098 (2.50)
0.071 (1.80)
0.059 (1.50)
1
2
3
4
PIN 1
0.026 (0.65) BSC
0.077 (1.95)
BSC
0.051 (1.30)
0.035 (0.90)
0.057 (1.45)
0.035 (0.90)
0.015 (0.38)
0.009 (0.22)
0.006 (0.15)
0.000 (0.00)
SEATING
PLANE
10°
0.009 (0.23) 0°
0.003 (0.08)
0.022 (0.55)
0.014 (0.35)
8-LEAD MSOP (RM-8)
0.122 (3.10)
0.114 (2.90)
1
5
0.199 (5.05)
0.187 (4.75)
4
0.120 (3.05)
0.112 (2.84)
0.006 (0.15)
0.002 (0.05)
0.043 (1.09)
0.037 (0.94)
0.018 (0.46)
0.008 (0.20)
0.011 (0.28)
0.003 (0.08)
–24–
0.120 (3.05)
0.112 (2.84)
33°
27°
PRINTED IN U.S.A.
8
0.122 (3.10)
0.114 (2.90)
0.028 (0.71)
0.016 (0.41)
REV. PrF