AMCC CS1202

Part Number S1202
Revision 3.8 - May 2000
NILE
SUMMARY DATASHEET
STS-12 ATM/DS3 SONET MAPPER
General Description
Features
• Processes valid combinations of SONET/SDH
STS-12c/AU-4-4c, STS-3c/AU-4, or STS-1 tributaries
within an STS-12/STM-4.
The S1202 is a highly integrated chip that implements
SONET/SDH processing and ATM mapping functions for
STS-12/STM-4 data streams. In addition, it supports DS3
tributaries, in an STS-1 SPE, with provisionable support for
M23 or C-bit parity OH, as well as clear channel
pass-through, direct mapping of ATM cells, or ATM PLCP
mapping. The S1202 is SONET and SDH standards compliant with Bellcore GR-253 and ANSI T1.105, and ITU G.707,
respectively. The S1202 is also DS3 standards compliant
with Bellcore GR-499 and ANSI T1.107-1995 and ATM standards compliant with Utopia Specification Level 2.
• Terminates and generates SONET/SDH section, line, and
path layers.
• Provides DS3 mapping and demapping for 12 STS-1s and
supports clear channel DS3.
• Supports ATM payload mapping into STS-12c/AU-4-4c &
STS-3c/AU-4, as well as direct ATM or ATM PLCP for DS3
tributaries.
The S1202 supports full-duplex processing of SONET/SDH
data streams with section, line, & path overhead processing.
The device supports framing, scrambling/descrambling,
alarm signal insertion/detection, and bit interleaved parity
(B1/B2/B3) processing. Serial interfaces for E1, E2, F1 and
Line and Section DCC are also provided.
• Supports M23 and C-Bit parity clear channel DS3 mapping, as well as clear channel DS3 transparent
passthrough mode.
• Provides a 77.76 MHz 8-bit bus interface on the
SONET/SDH side in both the TX and RX directions.
• Provides a 50 MHz 16-bit Utopia Lvl 2 interface on the system side in both the TX and RX directions.
A general purpose 8-bit microprocessor interface is provided
for device initialization, control, and monitoring. The interface
supports both Intel and Motorola type microprocessors, and
is capable of operating in either an interrupt driven or
polled-mode configuration.
• Programmable Utopia addresses to support multi-PHY
operation.
• Generic 8-bit microprocessor interface for configuration
and status monitoring.
Applications
• Supports IEEE 1149.1 JTAG testing.
• Packaged in a 388 pin BGA.
• Implemented in 3.3V with 5V tolerant I/O.
• Loopback capability for SONET/SDH, DS3 and ATM.
•
ATM switches
•
Packet over SONET Routers and Switches
•
SONET/SDH Add Drop Multiplexers, Terminal
Multiplexers and Digital Cross Connects
•
Test equipment
DL
Insert
MICROPROCESSOR I/F
FRAMER
TOH
MONITOR
RX
POH
MONITOR
FRAMER
POINTER
INTERPRET
TOH DROP
RX_EXTLOS
GPIO REG
DS3
Map
Clear Channel DS3
DS3
FR
PRBS
Gen
PLCP
Proc
ATM
Proc
1
12
1
12
1
12
1
12
FEBE
DS3
Dmap
DS3
FR
PRBS
Det
PLCP
Proc
1
12
1
12
1
12
JTAG PORT
DL Drop
TX
FIFO
1
ATM
Proc
1
12
RX
FIFO
Clear Channel DS3
1
RX
Utopia
I/F
TX_DS3[1:4][1:3]DATA
TX_DS3[1:4][1:3]CLK
TX_DS3[1:4][1:3]FIFO
TX_DS3[1:4][1:3]X1_IN
TX_ATM_DAT[15:0]
TX_PRTY
TX_SOC
TX_CLK
TX_ADR[4:0]
TX_ENB
TX_CLAV[3:0]
RX_ATM_DAT[15:0]
RX_PRTY
RX_SOC
RX_CLK
RX_ADR[4:0]
RX_ENB
RX_CLAV[3:0]
RX_DS3[1:4][1:3]DATA
RX_DS3_x_y_GAP_CLK
RX_DS3_x_y_CLK
RX_DS3[1:4][1:3]X1_OUT
RX_DS3[1:4][1:3]FIFO[1:0]
TS_EN
TRTSB
RX_DL_DATA
RX_DL_ENB
DL_CLK
DL_SYNC
RX_LOF_OUT
RX_LAIS_OUT
RX_OOF_OUT
TDO
TDI
TCK
TMS
AMCC
TX
Utopia
I/F
12
12
GPPIO[15:0]
RX_CLK78
RX_FRAME_OUT
SPE/VC
GENERATE
RX_SDCC_DATA
RX_SDCC_CLK
RX_LDCC_DATA
RX_LDCC_CLK
RX_E1E2F1_DATA
RX_E1E2F1_CLK
RX_FRAME_IN
RX_DATA[7:0]
LINE SIDE INTERFACE
TX_CLK78
TX_FRAME_IN
TOH INSERT
TX
TX_DATA[7:0]
TX_DL_DATA
TX_DL_ENB
CSN
WRB(RWB)
RDB(DSB)
RDYB(DTACKB)
BUSMODE
APS_INTB
D[7:0]
ADDR[11:0]
RSTB
INTB
TX_E1E2F1_CLK
TX_E1E2F1_DATA
TX_SDCC_CLK
TX_LDCC_DATA
TX_LDCC_CLK
TX_SDCC_DATA
TX_8K_CLK
TX_FRAME_OUT
S1202 Block Diagram
Production Information - The information contained in this
document is about a product in its fully tested and characterized phase. All features described herein are supported. Contact AMCC for updates to this document and the latest product
status.
Revision 3.8 - May 2000
S1202 STS-12 ATM/DS3 SONET MAPPER
SUMMARY DATASHEET
Overview and Applications
SONET Processing
The S1202 implements SONET/SDH processing and ATM
mapping functions for STS-12/STM-4 data streams. It can
support any combination of STS-12c, STS-3c, or STS-1 signals within an STS-12, or any combination of AU-4-4c or
AU-4 signals within an STM-4. In addition, it can support DS3
tributaries, in SONET, with provisionable support for clear
channel passthrough, direct mapping of ATM cells, or ATM
PLCP mapping. A TOH/SOH interface provides direct
add/drop capability for E1, E2, F1, and both Section and Line
DCC channels.
On the transmit side the S1202 generates section, line, &
path overhead. It performs framing pattern insertion (A1, A2),
scrambling, alarm signal insertion, and generates section,
line and path Bit Interleaved Parity (B1/B2/B3) for far-end
performance monitoring.
On the receive side the S1202 processes section, line, & path
overhead. It performs payload framing (A1, A2), descrambling, alarm detection, Bit Interleaved Parity monitoring
(B1/B2/B3), and error count accumulation for performance
monitoring.
ATM Processing
When configured for ATM cell processing, the S1202 transmit
ATM processor will perform all necessary cell encapsulation
including HEC generation, cell level scrambling (X43+1), and
idle cell insertion to adapt the cell rate to the SPE. When
receiving data from the line side, it performs cell delineation,
Rx header control, descrambling, and receive cell rate adaptation.
The DS3 mapper accepts data from an external DS3 input,
from looped-back DS3 tributaries, or from internal DS3 frame
generators. The internal DS3 frame generators are used for
ATM, PLCP, or PRBS data. The S1202 maps the data into
STS-1 SONET payloads.
The S1202 DS3 de-mapper support includes the ability to
extracts DS3 or ATM data from the SONET signal. DS3 signals can contain ATM, PLCP, or clear channel DS3 data. For
ATM or PLCP data, the S1202 frames on the DS3 and
extracts these signals from the DS3 payload. For clear channel DS3 data, the S1202 generates RX serial (NRZ) data signals smoothed to match a DS3 clock input that is provided to
the device, as well as a FIFO Fill Indication, provided for
phase lock loop adjustment. The S1202 also provides full
DS3 framing, monitoring, and extraction for full DS3 support.
Line-side Interface
On the line-side, the S1202 supports an 8-bit parallel interface which operates at 77.76 MHz. The device is typically
connected to a parallel-to-serial converter, which is in turn
connected to an electrical-to-optical converter for interfacing
to the fiber optic interface. (See figure below.)
System Interface
The S1202 supports a UTOPIA Level 2 interface, operating at
50 Mb/s, for providing ATM cell transfers to/from the system
interface. The S1202 also supports up to 12 DS3 tributaries.
For clear channel DS3 data, the S1202 generates RX serial
(NRZ) data signals smoothed to match a DS3 clock input that
is provided to the device, as well as a FIFO Fill Indication,
provided for phase lock loop adjustment.
DS3 Processing
The S1202 provides DS3 mapper and de-mapper functions.
Microprocessor
Control
TYPICAL APPLICATIONS
Reference
Clock
Control
Addr
12
Data
TX_CLK78
SerTxD±
SONET
Line Side
Interface
Fiber Optic
Transceiver
HP HFCT5208
Sumitomo SDM7202
SerRxD±
P/S & S/P
SONET XCVR
with
Clk Recovery
U
T
O
P
I
A
TX_DATA[7:0]
RX_LOS
RX_CLK78
RX_DATA[7:0]
AMCC
S1202
8
Channelized 622 Mb/s ATM Application
TX_CLK
TX_SYS_DAT[15:0]
Utopia Level-2
System Interface
RX_CLK
RX_SYS_DAT[15:0]
ATM Switch
OR
IP ROUTER
AMCC S3032
TX_DS3_[1:12]_DATA
DS3
TX_DS3_[1:12]_CLK
RX_DS3_[1:12]_DATA
RX_DS3_[1:12]_GAP/SM_CLK
RX_DS3_[1:12]_FIFO_[1:0]
TOH Insertion
and Extraction
Multi
Channel
HDLC
Processor
Switching/
Routing
Logic
DS3 Clear Channel for
Packet over SONET Application
AMCC
200 Brickstone Square, Andover, MA 01810 Ph: 978/623-0009 Fax:978/623-0024