áç XRT95L51 PRELIMINARY OC-48 ATM UNI/POS/MAPPER IC JULY 2000 REV. P1.0.1 GENERAL DESCRIPTION The XRT95L51 is an ATM/PPP physical layer processor with integrated SONET OC-48/STM-16 framing controller. ATM direct mapping and cell delineation are supported, as are PPP mapping and frame processing. The XRT95L51 contains an integral SONET framer which provides framing and error accumulation in accordance with ANSI/ITU-T specifications. The configuration of this device is done through internal registers accessible via 8-bit parallel, memory mapped, microprocessor interface. The XRT95L51 provides full section, line and path overhead processing and supports scrambling/descrambling, alarm signal insertion/detection and bit interleaved parity processing. The SONET/SDH transmit and receive blocks are used to transmit/receive an OC-48c/STM-16c signal or compose and decompose four OC-12/12c signals.The blocks operate at a peak internal clock speed of 77 MHz and support 32-bit internal data paths. The transmit and receive blocks are compliant with both SONET and SDH standards. APPLICATIONS • Digital Cross Connect Systems • ATM Switches • Routers • SONET/SDH Add Drop Multiplexers • Multiplexers FEATURES • Single chip for ATM UNI and Packet over SONET. • Generates and terminates SONET section, line and path layers. • Provides SONET frame scrambling and descrambling. • Provides 32-bit data UTOPIA level II and III multiPHY interface and POS-PHY interface. • 8-bit microprocessor interface • Includes ATM cell or PPP packet mapping • Single +3.3V power supply with +5V input tolerance • -40°C to +85°C Operating Temperature Range • Available in a 388 pin PBGA package 7&. 706 7', 7'2 JTAG Test Port 32 Tx ATM Cell Processor Tx Cell Buffer Tx POS Cell Processor Tx Control Rx Framer SOH Processor POH Processor Descrambler Rx POS Cell Processor Rx Control Overhead Extraction Block Rx ATM Cell Processor Rx OC-12 MapperX4 Rx Cell Buffer 7[8&ON 7[8(1%/ 7[862& 7[8&/$9 7[8$''5>7=3@ 7[8'$7$>64=3@ 7[8357< 7[3(23 7[3(55 5[8&ON 5[8(1B/ 5[862& 5[8&/$9 5[8$''5>7=3@ 5[8'$7$>64=3@ 5[8357< 5[3(23 5[3(55 5[3'9$/ POH Extract & Interpret 5[32+ 5[32+&ON 5[6%&ON 5[32+)3 5[32+9$/,' *3225[6%4'$7$>:=3@ 5[6%5'$7$>:=3@ 5[6%6'$7$>:=3@ 5[6%7'$7$>:=3@2 5[&3/ 5[*)&&ON/ 5[*)&06%/ 5[*)&/ 7[&3/ 7[*)&&ON/ 7[*)&06% /&' Serial to Parallel Rx XCVR I/F & Byte Align 32 POH Generation & Insertion Scrambler POH Processor SOH Processor Tx Framer 5[72+&ON 5[72+9$/,' 5[72+>6=3@ 5[72+)3 Line Interface 5[/&ON#.20 5[/'$7$>48=3@#.20 5[/357<#.20 5[/)3#.20 5[/&ON3#.20 5[5()&ON /26 Parallel to Serial Tx XCVR I/F Tx OC-12 Mapper X4 Utopia III ATM & POS I/F Overhead Insertion Block Microprocessor Interface 7[/&ON#.20 7[/'$7$>48=3@#.20 7[/357<#.20 7[/)3#.20 7[/567B/#.20 7[/&ON2#.20 7[5()&ON 7[32+ 7[32+&ON 7[32+)3 7[32+,16 *3,27[6%4'$7$>:=3@ 7[6%5'$7$>:=3@ 7[6%6'$7$>:=3@ 7[*)&27[6%7'$7$>:=3@ 7[72+&ON 7[72+(1% 7[72+ 7[72+,16 7[72+)3 S$''5>7=3@ S'$7$>:=3@ S$/(2$6 S:5B/ S5'B/ S&6B/ S'%(1B/ S$&.>4=3@ S5'<B/ S5(4B/>4=3@ S7<3(>5=3@ S&/. S,17B/ FIGURE 1. BLOCK DIAGRAM OF THE 95L51 OC-48 ATM UNI/POS/MAPPER IC Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com áç XRT95L51 OC-48 ATM UNI/POS/MAPPER IC PRELIMINARY REV. P1.0.1 SONET/SDH RECEIVER FUNCTIONAL OVERVIEW XRT95L51 implements the SONET/SDH framing function with full duplex ATM/POS interface for the STS-48/STM-16 data streams.The XRT95L51 is functionally and architecturally, divided into the following blocks and modules: • Performs standard STS-48c/STM-16c receive processing • Provides fully programmable threshold detection for SD and SF condition • Provides 155.52MHz 16-bit parallel interface LINE SIDE INTERFACE • Provides section trace buffer with mis-match detection and invalid message detection • Differential inputs/outputs for high speed chip-tochip communication using Pseudo ECL logic. • Performs SONET/SDH frame synchronization • Programmable parity bit for both incoming and outgoing data paths. • Supports NDF, positive stuff and negative stuff pointer processor • Monitors the Loss of Optical Carrier. • Performs receive data de-scrambling • The transmit line side provides the direct looped back version of the line clock, framing pulse and parity. • Performs POH,TOH interpretation/extraction • The reference signal derived from the receive clock input can be programmed to be 77.76 MHz,38.88 MHz,19.44 MHz or 8 kHz. • Extracts data communication channels from D1-D3 and D4-D12 • Interprets payload pointer (H1,H2) • Detects out of frame (OOF), loss of frame (LOF), loss of signal (LOS), APS failure • The reference signal derived from the transmit clock input can be programmed to be 77.76 MHz,38.88 MHz, 19.44 MHz and 8 kHz. • Detects Line Alarm Indication (L-AIS), Line remote Defect Indication (L-RDI), Loss of Pointer • 8 kHz reference signal can be phase locked to either incoming or outgoing SONET/SDH frame. • Detects Path Alarm Indication, Path remote Defect Indication, Path extended RDI • Supports Local and Remote Line Loopback. • Provides signal label monitor with PLM detection • Provides 155.52 MHz 16-bit parallel interface • Supports path travel buffer with TIM-P and invalid message detection SONET/SDH TRANSMITTER • Computes and compare B3,REI-L and REI-P errors • Performs standard OC-48c/STM-16c transmit processing • Computes and compare BIP-8 (B1,B2) and counts the errors • Conforms to IYU-T I.432,ANSI.105 and Bellcore GR-253 • Performs payload extraction. ATM CELL PROCESSOR • Performs SONET/SDH frame insertion and accepts external frame synchronization • Performs optional transmit data scrambling • Implements the ATM physical layer for Broadband ISDN according to ITU-T Recommendation I.432 • Performs POH,TOH generation/insertion • Supports SDH mapping • Generates transmit payload pointer (H1,H2) (fixed at 522) with NDF insertion • Provides selectable on-going HEC insertion and verification • Inserts A1/A2 with optional error mask • Provides selectable Coset addition and removal • Computes and inserts BIP-8 (B1,B2) with optional error mask • Provides single bit error correction and multiple bit error detection for HEC processing • Generates AIS-L,REI-L and RDI-L according to receiver state with option of SW/HW insertion • Provides HEC correctable and uncorrectable indications • Inserts LOS, forces SEF by software • Provides HEC correction selectability • Generates RDI-P and REI-P automatically with optional SW/HW override • Supports external cell GFC insertion and extraction • Provides the functions of cell rate de-coupling; idle cell insertion and detection, 16-cell FIFO cell buffering, programmable idle cell header and payload and idle cell HEC generation • Inserts fixed stuff columns, calculates and inserts B3 error code • Performs payload insertion from cell processor 2 áç XRT95L51 OC-48 ATM UNI/POS/MAPPER IC PRELIMINARY REV. P1.0.1 • Optional transmit FCS insertion • Offers cell delineation with three states (hunt, presync and sync) synchronization algorithm and provides LCD (Loss of Cell Delineation) indication and interrupt UTOPIA / POS-PHY INTERFACE • Complies with ATM forum Utopia Level 2 and 3 Specification • Supports multiple programmable VPI/VCI filters on Transmit and Receive • Supports 32-bit 100MHz Transmit and Receive interface • Provides self-synchronizing SDH cell scrambling/ de-scrambling, x43+1 • Provides up to total 16 cell buffers for transmit and receive • Supports OAM cell insertion and extraction with dedicated cell store via microprocessor interface. Transmission is enabled through semaphore • Transmits and receives both 52 and 54 byte cell • Generates and checks data parity of Utopia interface • Provides TXCell and TXCell indication signals • Supports programmable Transmit CLAV (transmit cell available) signal for 0,1,2,3 cell look ahead • Provides test cell generation and verification PACKET OVER SONET (POS) PROCESSOR • Supports programmable Receive CLAV (receive cell available) signal for 0,1,2,3 byte look ahead • Supports packet based link protocols by using byte synchronous HDLC framing like PPP,HDLC and frame relay • Provides 32-bit up to 100 MHz industrial standard POS-PHY interface • 32-bit extended Saturn POS-PHY host interface clocked to 100 MHz PERFORMANCE MONITORING • Supports line path performance monitoring • Performs transmit HDLC frame insertion and receive data extraction • Provides 32-bit saturating counter of idle cells transmitted • Performs self-synchronous data scrambling and descrambling using1+X43 polynomial • Provides 32-bit saturating counter of assigned cells transmitted • Performs transmit flag sequence insertion and receive synchronization • Provides 32-bit saturating counter of valid cells received • Performs byte stuffing and de-stuffing for transparency processing • Provides 32-bit saturating counter of idle cells received • Performs optional CRC-CCITT and CRC-32 FCS generation and error checking • Provides 32-bit saturating counter of cells received with HEC error • Supports optionally flow-through mode • Provides 32-bit saturating counter of cells discarded • Performs abort sequence insertion and detection • Arbitrary packet length (1 or more octets) and flag sharing (single flag between frames) • Provides 32-bit saturating counter of REI-L errors • Provides 32-bit saturating counter of REI-P errors • Provide minimum and maximum packet length checking, removing and reporting • Provides 32-bit saturating counter of BIP-8 (B1,B2 and B3) errors • Transparency by octet stuffing of flag (0x7E), control escape (0x7D) and abort sequence • Provides 32-bit saturating counter of POS frame check sequence errors • Automatic transfer halt on receive FIFO host-side at end of packet • Provides 32-bit saturating PPP good frame counter • Provides 32-bit saturating PPP bad FCS counter • Error detection for Underflow of transmit FIFO, Overflow of receive FIFO, parity error on transmit • Provides 32-bit saturating PPP aborted frame counter • Optional removal of FCS from receive frames • Provides 32-bit saturating PPP Runt frame counter 3 áç XRT95L51 OC-48 ATM UNI/POS/MAPPER IC PRELIMINARY REV. P1.0.1 INTERRUPT, STATUS AND TEST FIFO under-run, change of cell alignment, HEC errors, LCD status change • Provides individually maskable interrupts • Provides Local and Remote Line Loopback • Provides one second interrupt generations • Provides SONET Remote Loopback • Generates interrupts from the following causes: OOF status change, LOS status change, AIS status change, COFA, Utopia/PPP-PHY parity error, Utopia/PPP-PHY FIFO overrun, Utopia/PPP-PHY • Provides local ATM/PPP and UTOPIA Loopback • Supports IEEE 1149.1 JTAG testing FIGURE 2. TYPICAL APPLICATION Microprocessor SONET Transmit Interface Fiber Optic XCVR SONET/SDH Line Interface 2.48Mb/s Utopia Level 3/ PPP 32-Bit Interface Transmit Receive XRT95L51 OC-48/ STM-16 LIU EXAR OC-48/STM-16C Framer/Mapper SONET Receive Interface 4 IP Router or ATM Switch áç XRT95L51 OC-48 ATM UNI/POS/MAPPER IC PRELIMINARY REV. P1.0.1 FIGURE 3. PIN OUT OF THE XRT95L51 IN THE 388 PIN PBGA PACKAGE 4 $ *1'$3 5 9&&$3 6 7$''59 7 7$''55 % QF 7;/&/.3 & 7;/567 /3 7;/&/. 23 ' 7;/ 357<3 7;/567 B/1 7;/&/. 21 QF ( 7;/'481 7;/567 357<1 7;/)33 ) 7;/'471 7;/'91 * 7;/'463 7;/'81 + 7;/'73 - 7;/'441 7;/'443 7;/'71 . 7;/'431 7;/'433 / 7;/'51 0 8 9 75()3// 7;5() &/. : *347 ; < 43 44 45 46 47 48 49 4: 4; *344 7;6%5 '5 7;6%5 '5 7;72+ &/. 7;6%6 '5 7;6%6 '4 7;6'&& 7;(4)4 (5)3 7;6%7 '6 7;6%6 '7 7;6%6 '4 7;*)& 7;/'&& (1% 7;6%6 '9 7;6%7 ': 7;6%6 '9 53 54 7;6%7'7 7;6%6 '8 7;8'48 7;8'< 55 57 58 59 7;8'4; 7;8'8 7'08;( 14 *1'$3 $ 7;843 7;8'9 7'08; (15 7:(1 9&&$3 % 7;8'; 56 7;6%6': 7;72+ 7;(4)4 7;6%7 '5 7;6%5 '7 7;6%5 '3 7;72+)3 7;6'&& 7;(4)4(5 (1% (1% 7;6%6 '8 7;32+ &/. 7;32+ ,16 7;32+ 7;8'46 7;8'49 7;8'4: 7;8'4< 7;8&/. 75(1 1& 7;8'53 & *345 7;6%5 '4 7;6%5 '6 7;72+ ,16 7;6%6 '3 7;32+ (1% 7;32+)3 7;8'47 7;8'45 7;8'44 7;8': 7;8' &/.3 7'08; (13 1& 7;8'7 7;862& ' QF 7;8'5: 7;8(1B/ 7;8'5; 7;8'6 ( 7;/'483 7;/)31 7;8&/$9 7;8'59 7;8357< 7;8$3 ) 7;/'473 7;/'93 7;8'54 7;8$7 7;8'5 7;8'4 * 7;/'453 7;/'461 7;/'83 7;8'5< 7;3(23 7;8'55 7;8$6 + 7;/'451 7;8'58 7;8'63 7;8$4 7;8'3 - 7;/'61 7;/'63 7;8'57 7;3(55 7;8$56 7;8$5 . 7;/'<3 7;/'<1 7;/'53 96 96 96 96 96 96 7;8'64 1& 1& 5;8'< / 7;/';1 7;/';3 7;/'41 7;/'43 94 94 * * 95 95 5;8'43 5;8'; 5;8'46 5;8'45 0 1 7;/'31 7;/':3 7;/':1 7;/'33 94 94 * * 95 95 5;8'44 5;8$6 5;8$7 5;862& 1 3 5;/'483 5;/'481 5;/'331 5;/'31 94 94 * * 95 95 5;8&/$9 5;8': 5;8'47 5;8'59 3 5 5;/'473 5;/'471 5;/'41 5;/'43 94 94 * * 95 95 5;8'48 5;8(1B/ 5;8'5: 5;8'58 5 7 5;/'463 5;/'461 5;/'53 5;/'453 * * * * * * 5;8$5 5;8'57 5;8'9 5;8'49 7 8 5;/'63 5;/'61 5;/'51 5;/'443 5;8'8 1& 9 5;/'451 5;/'443 5;/'73 5;/'71 5;8'4: : 7$''5< 7$''58 7;/&/.1 7$''5; 7$''54 7;6%&/. *349 *343 7;6%5'9 7;6%6'6 7$''57 7$''53 1& *348 7;6%5 ': 7$''5: 7$''56 733// *34: *346 7;72+ (1% 4< 7;/'&& 723#9,(: ;57<8/84#+6;;#3,16, 5;8'5; 5;3'9$/ 8 5;8'56 5;8$4 5;8'4; 9 5;3(55 : 5;3 (23 < 5;/'431 5;/'433 5;/'<1 5;/'81 5;8$3 5;8'4< 5;8 '5< < 5;/'<3 5;/'83 5;/';1 5;/':3 5;8'53 1& 5;8' 55 $$ 5;/';3 5;/'93 5;/':1 5;/)33 5;8'5 $% 5;/'91 5;/ 35<73 5;/)31 5;/ &/.1 $& 5;/357< 1 1& 1& *1'$3 $' 5;/&/.3 5;/ &/.23 9&&$3 $( 5;/ &/.21 5;5() &/. 5;6' &&9$/ $) 1& 4 5;6'&& 5;32+)3 /23& 5;6%&/. 5;/'&& 5 5;/'&& 9$/ 6 5;32+ 9$/ /2) /26 5;32+ 5;32+ &/. 5;72+ 5;72+ 9$/ 5(6(7B/ 5;72+)3 3$''57 7(67 02'( *325 35(4B/4 *327 *328 *323 6() 1& *32: *326 *329 *324 5;72+ &/. 7 8 9 : ; < 43 3$''56 5;6%5'6 5;6%5'5 3,17B/ 3'$7$: 3:5B/ 3'$7$9 3$''54 5;6%5'3 3$''53 3$/( 37<3(5 3'$7$7 3&/. 3&6B/ 5;6%6'8 5;6%6'7 35(4B/3 3$''55 3$&.B/4 5;6%5'4 5;6%5'7 5;6%5'6 5;6%6'5 5;6%6'4 5;6%5': 5;6%5'9 5;6%5'8 3$&.B/3 44 45 46 47 35'B/ 3'$7$8 48 49 3'$7$6 5;6%6': 5;6%6'9 4: 4; 37<3(4 7;*)& &/. 35'<B/ 37<3(3 5;8'64 5;8357< 5;8'63 $$ 5;8'&/ . 5;8'3 5;8'6 5;8'54 $% 7567B/ 5;8&/.3 5;8'4 $& 7;*)& 06% /&' 706 3'$7$5 3%/$67B / 5;(4)4 (5)3 7&. 7'2 1& $' 3'$7$3 3'%(1B/ 5;(4)4 (59$/ 5;(4 )4(5 5;*)& 7', $( 5;*)& 06% 9&&$3 *1'$3 $) 57 58 59 3'$7$4 5;6%6'3 7;&3 5;&3 5;*)& &/. 4< 53 54 55 56 ORDERING INFORMATION PART NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE XRT95L51IB 388 Pin PBGA 35x35 mm, 26x26 Ball Matrix -40°C to +85°C 5 áç XRT95L51 OC-48 ATM UNI/POS/MAPPER IC PRELIMINARY REV. P1.0.1 FIGURE 4. SIGNAL DIAGRAM OF XRT95L51 4 4 7;/&/.#.20 7;/'$7$>48=3@#.20 7;/357<#.20 7;/)3#.20 7;/567B/#.20 7;/&/.2#.20 7;5()&/. 5 65 5 5 5 5 4 5;/&/.#.20 5;/'$7$>48=3@#.20 6()/#/2)/#/26 5;5()&/. 5;/357<#.20 5;/)3#.20 /23& 5 65 4/4/4 75$16&(,9(5 5 5; 5 ,17(5)$&( 5 4 7;72+&/. 7;72+(1% 7;72+ 7;72+,16 7;72+)3 7;32+ 7;32+&/. 7;32+)3 7;32+,16 7;6'&&/7;/'&&/7;(4)4(5 7;6'&&(1%/7;/'&&(1%/#7;(4)4(5(1%/7;(4)4(5)3 *3,27;6%4'$7$>:=3@ 7;6%5'$7$>:=3@ 7;6%6'$7$>:=3@ 7;*)&27;6%7'$7$>:=3@ 7;8&/. 7;8(1B/ 7;862& 7;8&/$9 7;8$''5>7=3@ 7;8'$7$>64=3 7;8357< 7;3(23 7;3(55 75$16&(,9(5 7; ,17(5)$&( 4 4 7 4 4 4 7;#,13872 4 29(5+($' 4 ,17(5)$&( 4 4/4/4 4/4/4/4 ; ; ; ; 4 4 4 4 8 65 4 4 4 5;#8723,$ ,17(5)$&( 4 4 4 4 8 65 4 4 4 4 5;8&/. 5;8(1%B/ 5;862& 5;8&/$9 5;8$''5>7=3@ 5;8'$7$>64=3@ 5;8357< 5;3(23 5;3(55 5;3'9$/ 5(&(,9( ,17(5)$&( 4 4 4 4 4 4 4 4 4/4 ; ; ; ; X3 ,17(5)$&( 8 ; 4 4 4 4 4 4 6 4 4 4 5;72+&/. 5;72+9$/,' 5;72+ 5;72+)3 5;32+ 5;32+&/.25;6%&/. 5;32+)325;6%)3 5;32+9$/,' 5;5()&/./#5;7)32 *3225;6%4'$7$>:=3@ 5;6%5'$7$>:=3@ 5;6%6'$7$>:=3@ 5;6%7'$7$>:=3@2/&'/#5;*)&&/./#5;*)&06%/ 5;*)&/#7;*)&&/./7;*)&06% S$''5>7=3@ S'$7$>:=3@ S:5B/25:B/ S5'B/ S&6B/ S$/( S'%(1B/ S5'<B/ S7<3(>5=3@ S&/. S%/$67B/ S,17B/ '0$ &21752/ 5 5 S5(4B/>4=3@ S$&.B/>4=3@ 7; 8723,$ ,17(5)$&( 6 5(6(7B/ 7(6702'( áç XRT95L51 OC-48 ATM UNI/POS/MAPPER IC PRELIMINARY REV. P1.0.1 ORDERING INFORMATION PART NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE XRT95L51IB 388 Pin PBGA 35x35 mm, 26x26 Ball Matrix -40°C to +85°C PACKAGE DIMENSIONS 388 Ball Plastic Ball Grid Array (35 x 35 mm PBGA) Rev. 1.0 26 24 25 22 23 20 21 18 19 16 14 17 12 15 13 10 11 8 6 9 7 4 5 2 3 Chamfer Optional 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF b D D1 e e D1 D D2 C b A2 A A1 Symbol Inches Millimeters MIN MAX MIN MAX A A1 0.075 0.020 0.106 0.028 1.90 0.50 2.70 0.70 A2 b 0.039 0.024 0.051 0.035 1.00 0.60 1.30 0.90 C D 0.016 1.370 0.028 1.386 0.40 34.80 0.70 35.20 D1 D2 1.250BSC 1.177 1.185 31.75BSC 29.90 30.10 e 0.050BSC 1.27BSC Note: The control dimension is the millimeter column 7 XRT95L51 áç OC-48 ATM UNI/POS/MAPPER IC PRELIMINARY REV. P1.0.1 REVISION HISTORY NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2000 EXAR Corporation Datasheet July 2000. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 8