1.8 V to 5.5 V single supply 4 Ω (max) on resistance Low on resistance flatness −3 dB bandwidth >200 MHz Tiny package options 8-lead MSOP 3 mm × 2 mm LFCSP (A grade) Fast switching times tON, 20 ns tOFF, 10 ns Low power consumption (<0.1 μW) TTL/CMOS compatible FUNCTIONAL BLOCK DIAGRAMS ADG722 ADG721 S1 S1 IN1 IN1 D1 D1 D2 D2 IN2 IN2 S2 S2 Figure 1. 00045-002 FEATURES 00045-001 Data Sheet CMOS, Low Voltage, 4 Ω Dual SPST Switches in 3 mm × 2 mm LFCSP ADG721/ADG722/ADG723 Figure 2. ADG723 S1 IN1 D1 APPLICATIONS D2 IN2 USB 1.1 signal switching circuits Cell phones PDAs Battery-powered systems Communication systems Sample hold systems Audio signal routing Video switching Mechanical reed relay replacement SWITCHES SHOWN FOR A LOGIC "0" INPUT 00045-003 S2 Figure 3. GENERAL DESCRIPTION The ADG721, ADG722, and ADG723 are monolithic CMOS SPST switches. These switches are designed on an advanced submicron process that provides low power dissipation yet gives high switching speed, low on resistance, and low leakage currents. The devices are packaged in both a tiny 3 mm × 2 mm LFCSP and an MSOP, making them ideal for space-constrained applications. and normally closed, respectively. In the ADG723, Switch 1 is normally open and Switch 2 is normally closed. The ADG721, ADG722, and ADG723 are designed to operate from a single 1.8 V to 5.5 V supply, making them ideal for use in battery-powered instruments and with the new generation of DACs and ADCs from Analog Devices, Inc. 1. 2. 3. 4. 5. The ADG721, ADG722, and ADG723 contain two independent single-pole/single-throw (SPST) switches. The ADG721 and ADG722 differ only in that both switches are normally open 6. Each switch of the ADG721, ADG722, and ADG723 conducts equally well in both directions when on. The ADG723 exhibits break-before-make switching action. PRODUCT HIGHLIGHTS 1.8 V to 5.5 V single-supply operation. Very low RON (4 Ω max at 5 V, 10 Ω max at 3 V). Low on resistance flatness. −3 dB bandwidth >200 MHz. Low power dissipation. CMOS construction ensures low power dissipation. 8-lead MSOP and 3 mm × 2 mm LFCSP. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2004-2011 Analog Devices, Inc. All rights reserved. ADG721/ADG722/ADG723 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Terminology .......................................................................................7 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................8 Functional Block Diagrams ............................................................. 1 Test Circuits ..................................................................................... 10 General Description ......................................................................... 1 Applications..................................................................................... 12 Product Highlights ........................................................................... 1 ADG721/ADG722/ADG723 Supply Voltages ....................... 12 Revision History ............................................................................... 2 On Response vs. Frequency ...................................................... 12 Specifications..................................................................................... 3 Off Isolation ................................................................................ 12 Absolute Maximum Ratings............................................................ 5 Outline Dimensions ....................................................................... 13 ESD Caution .................................................................................. 5 Ordering Guide .......................................................................... 14 Pin Configuration and Pin Descriptions ....................................... 6 REVISION HISTORY 10/11—Rev. D to Rev. E Changes to Ordering Guide ............................................................... 4/11—Rev. C to Rev. D Changes to Ordering Guide .......................................................... 14 1/11—Rev. B to Rev. C Changes to Table 4 ............................................................................ 6 Changes to Ordering Guide .......................................................... 14 2/07—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Specifications ................................................................ 3 Changes to Absolute Maximum Ratings ....................................... 5 Change to Figure 4 ........................................................................... 6 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 13 3/04—Rev. 0 to Rev. A Additions to Applications ................................................................ 1 Changes to Ordering Guide ............................................................ 4 Updated Outline Dimensions ....................................................... 10 Rev. E | Page 2 of 16 Data Sheet ADG721/ADG722/ADG723 SPECIFICATIONS VDD = 5 V ± 10%, GND = 0 V. All specifications −40°C to +85°C, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON A, B Grade 1 +25°C −40°C to +85°C 0 to VDD On Resistance Match Between Channels, ∆RON 2.5 4 0.3 On Resistance Flatness, RFLAT(ON) 0.85 5 1.0 1.5 LEAKAGE CURRENTS – A Grade Source off Leakage, IS (OFF) Drain off Leakage, ID (OFF) Channel on Leakage, ID, IS (ON) LEAKAGE CURRENTS – B Grade Source off Leakage, IS (OFF) Drain off Leakage, ID (OFF) Channel on Leakage, ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS 2 tON ±0.01 ±0.01 ±0.01 ±0.01 ±0.25 ±0.01 ±0.25 ±0.01 ±0.25 7 Charge Injection Off Isolation 2 −60 −80 −77 −97 200 7 7 18 μA typ μA max VIN = VINL or VINH ±0.1 ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ dB typ dB typ MHz typ pF typ pF typ pF typ RL = 300 Ω, CL = 35 pF VS = 3 V, see Figure 15 RL = 300 Ω, CL = 35 pF VS = 3 V, see Figure 15 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 3 V, see Figure 16 VS = 2 V, RS = 0 Ω, CL = 1 nF, see Figure 17 RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 18 RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 19 RL = 50 Ω, CL = 5 pF, see Figure 20 0.001 1.0 1 2 VDD = 5.5 V VS = 4.5 V/1 V, VD = 1 V/4.5 V, see Figure 13 VS = 4.5 V/1 V, VD = 1 V/4.5 V, see Figure 13 VS = VD = 1 V or VS = VD = 4.5 V, see Figure 14 VDD = 5.5 V VS = 4.5 V/1 V, VD = 1 V/4.5 V Test Circuit 2 VS = 4.5 V/1 V, VD = 1 V/4.5 V See Figure 13 VS = VD = 1 V or VS = VD = 4.5 V See Figure 14 V min V max 1 Bandwidth −3 dB CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD VS = 0 V to VDD, IS = −10 mA 2.4 0.8 10 Channel-to-Channel Crosstalk VS = 0 V to VDD, IS = −10 mA See Figure 12 VS = 0 V to VDD, IS = −10 mA ±0.35 ±0.35 20 Break-Before-Make Time Delay, tD (ADG723 Only) Test Conditions/Comments nA typ nA max nA typ nA max nA typ nA max ±0.35 14 6 V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA typ nA typ 0.005 tOFF Unit μA typ μA max Temperature range: A, B grades, −40°C to +85°C. All specifications apply to both grades unless otherwise stated. Guaranteed by design; not subject to production test. Rev. E | Page 3 of 16 VDD = 5.5 V Digital inputs = 0 V or 5 V ADG721/ADG722/ADG723 Data Sheet VDD = 3 V ± 10%, GND = 0 V. All specifications −40°C to +85°C, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON A, B Grades 1 +25°C −40°C to +85°C 0 to VDD 3.5 V Ω typ Ω max Ω typ Ω max Ω typ ±0.01 ±0.01 ±0.01 nA typ nA typ nA typ 6.5 10 On Resistance Match Between Channels, ∆RON 0.3 1.0 On Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS – A Grade Source off Leakage, IS (OFF) Drain off Leakage, ID (OFF) Channel on Leakage, ID, IS (ON) LEAKAGE CURRENTS – B Grade Source off Leakage, IS (OFF) Drain off Leakage, ID (OFF) Channel on Leakage, ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH DYNAMIC CHARACTERISTICS 2 tON ±0.01 ±0.25 ±0.01 ±0.25 ±0.01 ±0.25 Break-Before-Make Time Delay, tD (ADG723 Only) 7 Charge Injection Off Isolation 2 −60 −80 −77 −97 200 7 7 18 V min V max μA typ μA max VIN = VINL or VINH ±0.1 ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ dB typ dB typ MHz typ pF typ pF typ pF typ RL = 300 Ω, CL = 35 pF VS = 2 V, see Figure 15 RL = 300 Ω, CL = 35 pF VS = 2 V, see Figure 15 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 2 V, see Figure 16 VS = 1.5 V, RS = 0 Ω, CL = 1 nF, see Figure 17 RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 18 RL = 50 Ω, CL = 5 pF, f = 10 MHz RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 19 RL = 50 Ω, CL = 5 pF, see Figure 20 11 1 Bandwidth −3 dB CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD 0.001 1.0 1 2 VS = 0 V to VDD, IS = −10 mA VDD = 3.3 V VS = 3 V/1 V, VD = 1 V/3 V, see Figure 13 VS = 3 V/1 V, VD = 1 V/3 V, see Figure 13 VS = VD = 1 V or 3 V, Figure 14 VDD = 3.3 V VS = 3 V/1 V, VD = 1 V/3 V See Figure 13 VS = 3 V/1 V, VD = 1 V/3 V See Figure 13 VS = VD = 1 V or 3 V See Figure 14 2.0 0.4 16 7 VS = 0 V to VDD, IS = −10 mA See Figure 12 VS = 0 V to VDD, IS = −10 mA ±0.35 ±0.35 0.005 tOFF Test Conditions/Comments nA typ nA max nA typ nA max nA typ nA max ±0.35 24 Channel-to-Channel Crosstalk Unit μA typ μA max Temperature range: A, B Grades, −40°C to +85°C. All specifications apply to both grades unless otherwise stated. Guaranteed by design; not subject to production test. Rev. E | Page 4 of 16 VDD = 3.3 V Digital inputs = 0 V or 3 V Data Sheet ADG721/ADG722/ADG723 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Table 3. Parameter VDD to GND Analog, Digital Inputs1 Continuous Current, S or D Operating Temperature Range Industrial (A, B Grade) Storage Temperature Range Junction Temperature 8-Lead MSOP θJA Thermal Impedance θJC Thermal Impedance 8-Lead LFCSP (4-Layer Board) θJA Thermal Impedance1 Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Lead-Free Temperature, Soldering IR Reflow, Peak Temperature Time at Peak Temperature ESD Rating −0.3 V to +7 V −0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 30 mA −40°C to +85°C −65°C to +150°C +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 206°C/W 44°C/W 50.8°C/W 215°C 220°C 260°C (+0/−5°C) 10 sec to 40 sec 2 kV Assumes exposed paddle is tied to ground. 1 Rev. E | Page 5 of 16 ADG721/ADG722/ADG723 Data Sheet PIN CONFIGURATION AND PIN DESCRIPTIONS S1 1 D1 2 IN2 3 ADG721/ ADG722/ ADG723 8 VDD 7 IN1 NOTES 1. EXPOSED PADDLE OF LFCSP SHOULD BE TIED TO GROUND. 00045-004 TOP VIEW 6 D2 GND 4 (Not to Scale) 5 S2 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic S1 D1 IN2 GND S2 D2 IN1 VDD Descriptions Source Pin 1. May be an input or an output. Drain Pin 1. May be an input or an output. Logic Control Input for Switch S2D2. Ground (0 V) Reference. Source Pin 2. May be an input or an output. Drain Pin 2. May be an input or an output. Logic Control Input for Switch S1D1. Positive Power Supply Input. Table 5. Truth Table (ADG721/ADG722) Table 6. Truth Table (ADG723) ADG721 In 0 1 Logic 0 1 ADG722 In 1 0 Switch Condition Off On Rev. E | Page 6 of 16 Switch 1 Off On Switch 2 On Off Data Sheet ADG721/ADG722/ADG723 TERMINOLOGY VDD Most positive power supply potential. VD (VS) Analog voltage on the D and S terminals. GND Ground (0 V) reference. CS (OFF) Off switch source capacitance. S Source terminal. May be an input or output. CD (OFF) Off switch drain capacitance. D Drain terminal. May be an input or output. CD, CS (ON) On switch capacitance. IN Logic control input. tON Delay between applying the digital control input and the output switching on. RON Ohmic resistance between D and S. tOFF Delay between applying the digital control input and the output switching off. ∆RON On resistance match between any two channels, that is, RON max − RON min. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. tD Off time or on time measured between the 90% points of both switches, when switching from one address state to another (ADG723 only). IS (OFF) Source leakage current with the switch off. Crosstalk A measure of unwanted signal that is the result of parasitic capacitance. ID (OFF) Drain leakage current with the switch off. Off Isolation A measure of unwanted signal coupling through an off switch. ID, IS (ON) Channel leakage current with the switch on. Charge Injection A measure of the glitch impulse transferred during switching. Rev. E | Page 7 of 16 ADG721/ADG722/ADG723 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1m 6.0 TA = 25°C 5.5 VDD = 5V VDD = 2.7V 5.0 100µ 4.5 VDD = 4.5V 4.0 10µ RON (Ω) ISUPPLY (A) VDD = 3.0V 3.5 3.0 2.5 VDD = 5.0V 2.0 1µ 100n 1.5 10n 1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VD OR VS – DRAIN OR SOURCE VOLTAGE (V) 1n 10 00045-005 0 10k 100k FREQUENCY (Hz) 1M 10M –30 6 VDD = 3V +85°C VDD = 3V, 5V –40 OFF ISOLATION (dB) 5 4 +25°C 3 –40°C 2 1 –50 –60 –70 –80 –90 –100 10k 0 0.5 1.0 1.5 2.0 2.5 3.0 VD OR VS – DRAIN OR SOURCE VOLTAGE (V) 00045-006 0 Figure 6. On Resistance as a Function of a VD (VS) for Different Temperatures, VDD = 3 V 100k 1M 10M FREQUENCY (Hz) 100M 00045-009 RON (Ω) 1k Figure 8. Supply Current vs. Input Switching Frequency Figure 5. On Resistance as a Function of VD (VS), Single Supplies Figure 9. Off Isolation vs. Frequency 6.0 –30 VDD = 3V, 5V VDD = 5V 5.5 –40 5.0 4.5 +25°C CROSSTALK (dB) –50 4.0 RON (Ω) 100 00045-008 0.5 +85°C 3.5 3.0 2.5 2.0 –40°C 1.5 –60 –70 –80 –90 1.0 –100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VD OR VS – DRAIN OR SOURCE VOLTAGE (V) 4.5 5.0 –110 10k 00045-007 0 Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures, VDD = 5 V Rev. E | Page 8 of 16 100k 1M FREQUENCY (Hz) 10M Figure 10. Crosstalk vs. Frequency 100M 00045-010 0.5 Data Sheet ADG721/ADG722/ADG723 –6 VDD = 5V –8 –9 –10 –11 –12 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 00045-011 ON RESPONSE (dB) –7 Figure 11. On Response vs. Frequency Rev. E | Page 9 of 16 ADG721/ADG722/ADG723 Data Sheet TEST CIRCUITS IDS V1 RON = V1/IDS D ID (OFF) ID (ON) S A VS VD Figure 12. On Resistance D A VS VD Figure 13. Off Leakage Figure 14. On Leakage VDD 0.1µF VIN ADG721 50% 50% VIN 50% 50% VDD S VS VOUT D CL 35pF RL 300Ω IN ADG722 90% 90% VOUT tON tOFF 00045-015 GND Figure 15. Switching Times VDD 0.1µF VIN VDD S2 D2 VOUT1 VOUT2 RL2 300Ω IN1, IN2 50% RL1 300Ω VOUT1 CL1 35pF 90% 90% 0V CL2 35pF GND VIN 50% 0V 90% VOUT2 90% 00045-016 VS2 D1 0V tD tD Figure 16. Break-Before-Make Time Delay, tD (ADG723 Only) VDD SW ON SW OFF VDD RS S D VOUT VIN CL 1nF VS IN VOUT ΔVOUT GND QINJ = CL × ΔVOUT Figure 17. Charge Injection Rev. E | Page 10 of 16 00045-017 VS1 S1 00045-014 S A 00045-013 VS IS (OFF) D 00045-012 S Data Sheet ADG721/ADG722/ADG723 VDD VDD 0.1µF 0.1µF VDD VDD D S VOUT D RL 50Ω IN VS GND VIN IN GND Figure 19. Channel-to-Channel Crosstalk Figure 18. Off Isolation VDD 0.1µF VDD S VS NC 50Ω D VIN1 VIN2 S D GND CHANNEL-TO-CHANNEL CROSSTALK = 20 × log |VS/VOUT| Figure 20. Bandwidth Rev. E | Page 11 of 16 VOUT RL 50Ω 00045-020 VIN 00045-018 VS VOUT RL 50Ω 00045-019 S ADG721/ADG722/ADG723 Data Sheet APPLICATIONS The ADG721/ADG722/ADG723 belong to a new family of Analog Devices CMOS switches. This series of general-purpose switches has improved switching times, lower on resistance, higher bandwidths, low power consumption, and low leakage currents. ADG721/ADG722/ADG723 SUPPLY VOLTAGES Functionality of the ADG721/ADG722/ADG723 extends from a 1.8 V to a 5.5 V single supply, which makes it ideal for batterypowered instruments, where important design parameters are power efficiency and performance. It is important to note that the supply voltage affects the input signal range, the on resistance, and the switching times of the part. The typical performance characteristics and the specifications clearly show the effects of the power supplies. The signal transfer characteristic is dependent on the switch channel capacitance, CDS. This capacitance creates a frequency zero in the numerator of the transfer function A(s). Because the switch on resistance is small, this zero usually occurs at high frequencies. The bandwidth is a function of the switch output capacitance combined with CDS and the load capacitance. The frequency pole corresponding to these capacitances appears in the denominator of A(s). The dominant effect of the output capacitance, CD, causes the pole breakpoint frequency to occur first. Therefore, in order to maximize bandwidth, a switch must have a low input and output capacitance and low on resistance (see Figure 11). OFF ISOLATION Off isolation is a measure of the input signal coupled through an off switch to the switch output. The capacitance, CDS, couples the input signal to the output load, when the switch is off, as shown in Figure 22. ON RESPONSE VS. FREQUENCY Figure 21 illustrates the parasitic components that affect the ac performance of CMOS switches (the switch is shown surrounded by a box). Additional external capacitances further degrade some aspects of performance. These capacitances affect feedthrough, crosstalk, and system bandwidth. CDS S VOUT VIN S D VOUT CD CLOAD RLOAD 00045-021 VIN CD CLOAD RLOAD Figure 22. Off Isolation Is Affected by External Load Resistance and Capacitance CDS RON D 00045-022 For VDD = 1.8 V, on resistance is typically 40 Ω over the temperature range. Figure 21. Switch Represented by Equivalent Parasitic Components The transfer function that describes the equivalent diagram of the switch (Figure 21) is of the form (A)s, as shown in the following equation: s (RON CDS ) + 1 A(s) = RT s (RON CT RT ) + 1 The larger the value of CDS, the larger the value of feedthrough produced. Figure 9 illustrates the drop in off isolation as a function of frequency. From dc to roughly 1 MHz, the switch shows better than −80 dB isolation. Up to frequencies of 10 MHz, the off isolation remains better than −60 dB. As the frequency increases, more and more of the input signal is coupled through to the output. Off isolation can be maximized by choosing a switch with the smallest CDS possible. The values of load resistance and capacitance also affect off isolation because they contribute to the coefficients of the poles and zeros in the transfer function of the switch when open. s (RLOAD CDS ) A(s) = s (RLOAD ) (CLOAD + CD + CDS ) + 1 where: CT = CLOAD + CD + CDS RT = RLOAD/(RLOAD + RON) Rev. E | Page 12 of 16 Data Sheet ADG721/ADG722/ADG723 OUTLINE DIMENSIONS 3.20 3.00 2.80 8 3.20 3.00 2.80 5.15 4.90 4.65 5 1 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 6° 0° 0.40 0.25 0.80 0.55 0.40 0.23 0.09 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 23. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters 1.75 1.65 1.50 2.00 BSC 5 3.00 BSC 8 1.90 1.80 1.65 EXPOSED PAD 0.20 MIN 4 INDEX AREA 0.50 0.40 0.30 TOP VIEW 0.80 0.75 0.70 0.50 0.30 0.25 0.20 COPLANARITY 0.08 0.05 MAX 0.02 NOM PIN 1 INDICATOR BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 081806-A SEATING PLANE 0.15 REF SIDE VIEW 1 Figure 24. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 2 mm Body, Very Very Thin, Dual Lead (CP-8-4) Dimensions shown in millimeters Rev. E | Page 13 of 16 ADG721/ADG722/ADG723 Data Sheet ORDERING GUIDE Model 1 ADG721BRM ADG721BRM-REEL ADG721BRM-REEL7 ADG721BRMZ ADG721BRMZ-REEL ADG721BRMZ-REEL7 ADG721ACPZ-REEL ADG721ACPZ-REEL7 ADG722BRM ADG722BRM-REEL7 ADG722BRMZ ADG722BRMZ-REEL ADG722BRMZ-REEL7 ADG722ACPZ-REEL ADG722ACPZ-REEL7 ADG723BRM ADG723BRM-REEL ADG723BRM-REEL7 ADG723BRMZ ADG723BRMZ-REEL ADG723BRMZ-REEL7 ADG723ACPZ-REEL ADG723ACPZ-REEL7 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead LFCSP_WD 8-Lead LFCSP_WD Z = RoHS Compliant Part; # denotes lead-free product may be top or bottom marked. Branding = due to package size limitations, these three characters represent the part number. Rev. E | Page 14 of 16 Package Option RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 CP-8-4 CP-8-4 RM-8 RM-8 RM-8 RM-8 RM-8 CP-8-4 CP-8-4 RM-8 RM-8 RM-8 RM-8 RM-8 RM-8 CP-8-4 CP-8-4 Branding 2 S6B S6B S6B #S6B #S6B #S6B 17 17 S7B S7B #S7B #S7B #S7B 0U 0U S8B S8B S8B #S8B #S8B #S8B S2N S2N Data Sheet ADG721/ADG722/ADG723 NOTES Rev. E | Page 15 of 16 ADG721/ADG722/ADG723 Data Sheet NOTES ©2004-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00045-0-10/11(E) Rev. E | Page 16 of 16