1 Ω Typical On Resistance, ±5 V, +12 V, +5 V, and +3.3 V Dual SPDT Switches ADG1636 FEATURES FUNCTIONAL BLOCK DIAGRAMS 1 Ω typical on resistance 0.2 Ω on resistance flatness ±3.3 V to ±8 V dual supply operation 3.3 V to 16 V single supply operation No VL supply required 3 V logic-compatible inputs Rail-to-rail operation Continuous current per channel LFCSP package: 385 mA TSSOP package: 238 mA 16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP ADG1636 S1A D1 S1B IN1 IN2 S2A D2 NOTES 1. SWITCHES SHOWN FOR A LOGIC 1 INPUT. APPLICATIONS 07983-001 S2B Figure 1. 16-Lead TSSOP Communication systems Medical systems Audio signal routing Video signal routing Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Relay replacements ADG1636 S1A S2A D1 D2 S1B S2B IN1 IN2 EN NOTES 1. SWITCHES SHOWN FOR A 1 INPUT LOGIC. 07983-002 LOGIC Figure 2. 16-Lead LFCSP GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG1636 is a monolithic CMOS device containing two independently selectable single-pole/double-throw (SPDT) switches. An EN input is used to enable or disable the device. When disabled, all channels are switched off. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. Both switches exhibit break-before-make switching action for use in multiplexer applications. 1. 2. 3. 4. 5. 6. 1.6 Ω maximum on resistance over temperature. Minimum distortion: THD + N = 0.007%. 3 V logic-compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V. No VL logic power supply required. Ultralow power dissipation: <16 nW. 16-lead TSSOP and 16-lead 4 mm × 4 mm LFCSP. The ultralow on resistance of these switches make them ideal solutions for data acquisition and gain switching applications where low on resistance and distortion is critical. The on resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching audio signals. The CMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and batterypowered instruments. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. ADG1636 TABLE OF CONTENTS Features .............................................................................................. 1 3.3 V Single Supply........................................................................6 Applications ....................................................................................... 1 Continuous Current per Channel, S or D ..................................7 General Description ......................................................................... 1 Absolute Maximum Ratings ............................................................8 Functional Block Diagrams ............................................................. 1 ESD Caution...................................................................................8 Product Highlights ........................................................................... 1 Pin Configurations and Function Descriptions ............................9 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 10 Specifications..................................................................................... 3 Test Circuits ..................................................................................... 13 ±5 V Dual Supply ......................................................................... 3 Terminology .................................................................................... 15 12 V Single Supply ........................................................................ 4 Outline Dimensions ....................................................................... 16 5 V Single Supply .......................................................................... 5 Ordering Guide .......................................................................... 16 REVISION HISTORY 9/09—Rev. 0 to Rev. A Changes to Table 4 ............................................................................ 6 1/09—Revision 0: Initial Version Rev. A | Page 2 of 16 ADG1636 SPECIFICATIONS ±5 V DUAL SUPPLY VDD = +5 V ± 10%, VSS = −5 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT(ON)) 25°C −40°C to +85°C −40°C to +125°C VDD to VSS 1 1.2 0.04 0.08 0.2 0.25 1.4 1.6 0.09 0.1 0.29 0.34 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) ±0.1 ±1 Drain Off Leakage, ID (Off ) ±0.25 ±0.1 ±0.25 ±0.3 ±0.6 ±2 ±10 ±2 ±12 Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH ±4 2.0 0.8 0.005 5 VS = ±4.5 V, VD = ∓4.5 V; see Figure 24 VS = ±4.5V, VD = ∓4.5 V; see Figure 24 nA max nA typ nA max VS = VD = ±4.5 V; see Figure 25 V min V max μA typ μA max pF typ VIN = VGND or VDD Break-Before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise (THD + N) 130 70 90 0.007 25 68 127 220 MHz typ pF typ pF typ pF typ 245 273 166 176 259 281 17 −3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD VDD/VSS VS = ±4.5 V, IS = −10 mA nA max nA typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ tOFF (EN) VS = ±4.5 V, IS = −10 mA; see Figure 23 VDD = ±4.5 V, VSS = ±4.5 V VS = ±4.5 V, IS = −10 mA nA typ 130 209 119 148 182 228 30 tON (EN) 1 V Ω typ Ω max Ω typ Ω max Ω typ Ω max Test Conditions/Comments VDD = +5.5 V, VSS = −5.5 V ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION Unit 0.001 1.0 ±3.3/±8 Guaranteed by design, not subject to production test. Rev. A | Page 3 of 16 μA typ μA max V min/max RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 2.5 V; see Figure 31 VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 Ω, CL = 5 pF; see Figure 27 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +5.5 V, VSS = −5.5 V Digital inputs = 0 V or VDD ADG1636 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C −40°C to +125°C 0 V to VDD 0.95 1.1 0.03 0.06 0.2 0.23 ±0.1 ±0.25 ±0.1 ±0.25 ±0.3 ±0.6 1.25 1.45 0.07 0.08 0.27 0.32 ±1 ±4 ±2 ±10 ±2 ±12 2.0 0.8 0.001 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 5 V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ Break-Before-Make Time Delay, tD 100 153 80 95 133 161 25 Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise (THD + N) 150 70 90 0.013 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ 27 65 120 216 MHz typ pF typ pF typ pF typ tON (EN) tOFF (EN) 183 206 103 110 187 210 17 −3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD 0.001 1 IDD VDD 1 Unit 230 360 3.3/16 Guaranteed by design, not subject to production test. Rev. A | Page 4 of 16 μA typ μA max μA typ μA max V min/max Test Conditions/Comments VS = 0 V to 10 V, IS = −10 mA; see Figure 23 VDD = 10.8 V, VSS = 0 V VS = 10 V, IS = −10 mA VS = 0 V to 10 V, IS = −10 mA VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VS = 10 V/1 V; see Figure 24 VS = 1 V/10 V, VS = 10 V/1 V; see Figure 24 VS = VD = 1 V or 10 V; see Figure 25 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 8 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 8 V; see Figure 31 VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28 RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz; see Figure 29 RL = 50 Ω, CL = 5 pF; see Figure 27 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 12 V Digital inputs = 0 V or VDD Digital inputs = 5 V ADG1636 5 V SINGLE SUPPLY VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C −40°C to +85°C −40°C to 125°C 0 V to VDD 1.7 2.15 0.05 0.09 0.4 0.53 ±0.05 ±0.25 ±0.05 ±0.25 ±0.1 ±0.6 2.4 2.7 0.12 0.15 0.55 0.6 ±1 ±4 ±2 ±10 ±2 ±12 2.0 0.8 0.001 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 5 V Ω typ Ω max Ω typ Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max μA typ μA max pF typ Break-Before-Make Time Delay, tD 160 271 132 172 210 268 30 Charge Injection Off Isolation 70 70 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ Channel-to-Channel Crosstalk 90 dB typ Total Harmonic Distortion + Noise (THD + N) 0.09 % typ 26 76 145 237 MHz typ pF typ pF typ pF typ tON (EN) tOFF (EN) 319 355 185 201 313 345 17 −3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD 0.001 1.0 VDD 1 Unit 1.0 3.3/16 Guaranteed by design, not subject to production test. Rev. A | Page 5 of 16 μA typ μA max V min/max Test Conditions/Comments VS = 0 V to 4.5 V, IS = −10 mA; see Figure 23 VDD = 4.5 V, VSS = 0 V VS = 0 V to 4.5 V, IS = −10 mA VS = 0 V to 4.5 V, IS = −10 mA VDD = 5.5 V, VSS = 0 V VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 24 VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 24 VS = VD = 1 V or 4.5 V; see Figure 25 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 2.5 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 2.5 V; see Figure 31 VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 28 RL = 110 Ω, f = 20 Hz to 20 kHz, VS = 3.5 V p-p; see Figure 29 RL = 50 Ω, CL = 5 pF; see Figure 27 VS = 2.5 V, f = 1 MHz VS = 2.5 V, f = 1 MHz VS = 2.5 V, f = 1 MHz VDD = 5.5 V Digital inputs = 0 V or VDD ADG1636 3.3 V SINGLE SUPPLY VDD = 3.3 V, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) 25°C −40°C to +85°C −40°C to +125°C Unit 3.2 3.4 0 V to VDD 3.6 V Ω typ On Resistance Match Between Channels (∆RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) 0.06 1.2 0.07 1.3 0.08 1.4 Ω typ Ω typ ±1 ±4 ±2 ±10 ±2 ±12 Drain Off Leakage, ID (Off ) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH ±0.02 ±0.25 ±0.02 ±0.25 ±0.05 ±0.6 2.0 0.8 0.001 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 5 V min V max μA typ μA max pF typ Break-Before-Make Time Delay, tD 275 449 225 306 340 454 50 Charge Injection Off Isolation Channel-to-Channel Crosstalk 50 70 90 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ Total Harmonic Distortion + Noise (THD + N) 0.19 % typ 26 80 153 243 MHz typ pF typ pF typ pF typ tON (EN) tOFF (EN) 506 550 327 338 512 553 28 −3 dB Bandwidth CS (Off ) CD (Off ) CD, CS (On) POWER REQUIREMENTS IDD 0.001 1.0 VDD 1 nA typ nA max nA typ nA max nA typ nA max 1.0 3.3/16 Guaranteed by design, not subject to production test. Rev. A | Page 6 of 16 μA typ μA max V min/max Test Conditions/Comments VS = 0 V to VDD, IS = −10 mA; see Figure 23 VDD = 3.3 V, VSS = 0 V VS = 0 V to VDD, IS = −10 mA VS = 0 V to VDD, IS = −10 mA VDD = 3.6 V, VSS = 0 V VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 24 VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 24 VS = VD = 0.6 V or 3 V; see Figure 25 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 1.5 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 1.5 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS = 1.5 V; see Figure 30 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 31 VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 32 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 26 RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 28 RL = 33 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p; see Figure 29 RL = 50 Ω, CL = 5 pF; see Figure 27 VS = 1.5 V, f = 1 MHz VS = 1.5 V, f = 1 MHz VS = 1.5 V, f = 1 MHz VDD = 3.6 V Digital inputs = 0 V or VDD ADG1636 CONTINUOUS CURRENT PER CHANNEL, S OR D Table 5. Parameter CONTINUOUS CURRENT, S OR D VDD = +5 V, VSS = −5 V TSSOP (θJA = 150.4°C/W) LFCSP (θJA = 48.7°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 150.4°C/W) LFCSP (θJA = 48.7°C/W) VDD = 5 V, VSS = 0 V TSSOP (θJA = 150.4°C/W) LFCSP (θJA = 48.7°C/W) VDD = 3.3 V, VSS = 0 V TSSOP (θJA = 150.4°C/W) LFCSP (θJA = 48.7°C/W) 25°C 85°C 125°C Unit 238 385 151 220 88 105 mA maximum mA maximum 280 469 175 259 98 119 mA maximum mA maximum 189 301 126 182 77 98 mA maximum mA maximum 189 305 130 189 84 105 mA maximum mA maximum Rev. A | Page 7 of 16 ADG1636 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs 1 Digital Inputs1 Peak Current, S or D Continuous Current, S or D 2 Operating Temperature Range Industrial (Y Version) Storage Temperature Range Junction Temperature 16-Lead TSSOP, θJA Thermal Impedance (2-Layer Board) 16-Lead LFCSP, θJA Thermal Impedance (4-Layer Board) Reflow Soldering Peak Temperature, Pb free 1 2 Rating 18 V −0.3 V to +18 V +0.3 V to −18 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 850 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 150.4°C/W 48.7°C/W 260°C Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given. See Table 5. Rev. A | Page 8 of 16 ADG1636 D1 1 D1 3 14 EN S1B 2 13 VDD 12 S2B 11 D2 7 10 S2A NC 8 9 IN2 GND 6 NC NC = NO CONNECT GND 4 14 NC 13 NC 12 EN ADG1636 11 VDD TOP VIEW (Not to Scale) 9 D2 NC 5 VSS 5 TOP VIEW (Not to Scale) VSS 3 10 S2B NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD TIED TO SUBSTRATE, VSS. 07983-003 ADG1636 S1B 4 PIN 1 INDICATOR 07983-004 NC S2A 8 NC 15 NC 7 16 IN2 6 IN1 1 S1A 2 15 IN1 16 S1A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. 16-Lead LFCSP Pin Configuration Figure 3. 16-Lead TSSOP Pin Configuration Table 7. Pin Function Descriptions TSSOP 1 2 3 4 5 6 7, 8, 15, 16 9 10 11 12 13 14 N/A Pin No. LFCSP 15 16 1 2 3 4 5, 7, 13, 14 6 8 9 10 11 12 17 (EPAD) Mnemonic IN1 S1A D1 S1B VSS GND NC IN2 S2A D2 S2B VDD EN EP (EPAD) Description Logic Control Input. Source Terminal. This pin can be an input or output. Drain Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Most Negative Power Supply Potential. Ground (0 V) Reference. No Connection. Logic Control Input. Source Terminal. This pin can be an input or output. Drain Terminal. This pin can be an input or output. Source Terminal. This pin can be an input or output. Most Positive Power Supply Potential. Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When this pin is high, the Ax logic inputs determine the on switches. Exposed Pad. Tied to substrate, VSS. Table 8. ADG1636 TSSOP Truth Table EN 0 1 1 INx X 0 1 SxA Off Off On SxB Off On Off SxA Off Off On SxB Off On Off Table 9. ADG1636 LFCSP Truth Table EN 0 1 1 INx X 0 1 Rev. A | Page 9 of 16 ADG1636 TYPICAL PERFORMANCE CHARACTERISTICS 1.4 TA = 25°C 1.2 ON RESISTANCE (Ω) 1.0 VDD = +5V VSS = –5V VDD = +8V VSS = –8V 0.4 –8 –6 –4 –2 0 0.8 0.6 2 4 6 8 VS OR VD VOLTAGE (V) 0.4 07983-014 0.6 1.0 0 2 4 TA = 25°C ON RESISTANCE (Ω) VDD = 3.3V VSS = 0V 2.5 2.0 VDD = 5V VSS = 0V VDD = 12V VSS = 0V 1.0 0 2 4 6 8 10 2.0 1.5 VDD = 16V VSS = 0V 12 14 16 VS OR VD VOLTAGE (V) 1.0 07983-015 1.5 Figure 6. On Resistance as a Function of VD (VS) for Single Supply 3.5 ON RESISTANCE (Ω) 1.2 1.0 0.8 –4 –2 0 2 VS OR VD VOLTAGE (V) 4 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD = 3.3V VSS = 0V 3.0 TA = +125°C TA = +85°C TA = +25°C TA = –40°C 2.5 2.0 TA = +125°C TA = +85°C TA = +25°C TA = –40°C 6 1.5 07983-012 0.4 –6 0.5 Figure 9. On Resistance as a Function of VD (VS) for Different Temperatures, 5 V Single Supply 4.0 VDD = +5V VSS = –5V 0 VS OR VD VOLTAGE (V) 1.4 0.6 12 VDD = 5V VSS = 0V TA = +125°C TA = +85°C TA = +25°C TA = –40°C 3.0 ON RESISTANCE (Ω) 10 2.5 3.5 ON RESISTANCE (Ω) 8 Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures, 12 V Single Supply Figure 5. On Resistance as a Function of VD (VS) for Dual Supply 0.5 6 VS OR VD VOLTAGE (V) 07983-011 0.8 TA = +125°C TA = +85°C TA = +25°C TA = –40°C 07983-013 1.2 ON RESISTANCE (Ω) VDD = 12V VSS = 0V VDD = +3.3V VSS = –3.3V Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures, ±5 V Dual Supply 0 0.5 1.0 1.5 2.0 VS OR VD VOLTAGE (V) 2.5 3.0 3.5 07983-007 1.4 Figure 10. On Resistance as a Function of VD (VS) for Different Temperatures, 3.3 V Single Supply Rev. A | Page 10 of 16 ADG1636 18 5 16 ID (OFF) –, + 14 LEAKAGE CURRENT (nA) IS (OFF) +, – 0 IS (OFF) –, + ID, IS (ON) –, – –5 ID (OFF) +, – ID, IS (OFF) +, + 12 10 8 ID, IS (OFF) –, – 6 ID (OFF) –, + 4 IS (OFF) +, – 2 0 –10 IS (OFF) –, + –2 0 20 40 60 80 100 120 TEMPERATURE (°C) –4 07983-033 40 100 120 10 IS (OFF) +, – IDD (µA) 300 0 ID, IS (ON) –, – IS (OFF) –, + –5 200 40 60 80 100 IDD = +5V ISS = 0V 0 120 TEMPERATURE (°C) –100 07983-032 20 IDD = +5V ISS = –5V 100 ID (OFF) +, – 0 IDD = +12V ISS = 0V 400 ID (OFF) –, + 5 IDD PER CHANNEL TA = 25°C 500 ID, IS (ON) +, + –10 IDD = +3.3V ISS = 0V 0 2 4 6 8 10 12 14 LOGIC (V) Figure 15. IDD vs. Logic Level Figure 12. Leakage Currents as a Function of Temperature, 12 V Single Supply 300 20 250 CHARGE INJECTION (pC) 15 ID, IS (OFF) +, + 10 ID, IS (OFF) –, – 5 ID (OFF) –, + 0 0 20 40 60 80 VDD = +5V VSS = –5V 200 150 VDD = +12V VSS = 0V 100 VDD = +5V VSS = 0V 50 IS (OFF) +, – IS (OFF) –, + ID (OFF) +, – 100 120 TEMPERATURE (°C) 07983-030 LEAKAGE CURRENT (nA) 80 600 15 –5 60 Figure 14. Leakage Currents as a Function of Temperature, 3.3 V Single Supply 20 LEAKAGE CURRENT (nA) 20 TEMPERATURE (°C) Figure 11. Leakage Currents as a Function of Temperature, ±5 V Dual Supply –15 ID (OFF) +, – 0 07983-006 –15 Figure 13. Leakage Currents as a Function of Temperature, 5 V Single Supply 0 –6 VDD = +3.3V VSS = 0V –4 –2 0 2 4 6 8 10 VS (V) Figure 16. Charge Injection vs. Source Voltage Rev. A | Page 11 of 16 12 14 07983-010 LEAKAGE CURRENT (nA) 10 ID, IS (ON) +, + 07983-031 15 ADG1636 450 TA = 25°C VDD = +5V VSS = –5V –1 400 VDD = +3.3V, VSS = 0V –3 INSERTION LOSS (dB) 350 VDD = +5V, VSS = 0V 250 200 150 VDD = +5V, VSS = –5V 20 40 60 80 100 –11 120 TEMPERATURE (°C) –15 1k 0 10M 100M 1G TA = 25°C VDD = +5V VSS = –5V –20 NO DECOUPLING CAPACITORS ACPSRR (dB) –40 –60 DECOUPLING CAPACITORS –80 –100 100k 1M 10M 100M 1G –120 1k 07983-008 OFF ISOLATION (dB) 1M Figure 20. On Response vs. Frequency FREQUENCY (Hz) 10k 100k 1M 10M 25k FREQUENCY (Hz) Figure 18. Off Isolation vs. Frequency Figure 21. ACPSRR vs. Frequency 0 0.20 TA = 25°C VDD = +5V –20 VSS = –5V 0.18 ADJACENT –40 VDD = +3.3V VS = 2V p-p RL = 110Ω TA = 25°C 0.16 THD + N (%) 0.14 –60 –80 NON-ADJACENT VDD = +5V VS = 3.5V p-p 0.12 0.10 0.08 0.06 –100 VDD = +5V VSS = –5V VS = 5V p-p VDD = +12V VS = 5V p-p 0.04 –120 0.02 –140 1k 10k 100k 1M 10M FREQUENCY (Hz) 100M 1G 07983-018 CROSSTALK (dB) 100k FREQUENCY (Hz) Figure 17. tON/tOFF Times vs. Temperature –10 –15 TA = 25°C –20 VDD = +5V –25 VSS = –5V –30 –35 –40 –45 –50 –55 –60 –65 –70 –75 –80 –85 –90 –95 –100 –105 –110 1k 10k 10k 07983-009 0 07983-019 –20 –9 –13 VDD = +12V, VSS = 0V 50 –40 –7 07983-005 100 –5 07983-017 TIME (ns) 300 0 0 5k 10k 15k FREQUENCY (Hz) Figure 22. THD + N vs. Frequency Figure 19. Crosstalk vs. Frequency Rev. A | Page 12 of 16 20k ADG1636 TEST CIRCUITS VDD VSS 0.1µF 0.1µF VDD SxA INx NETWORK ANALYZER VSS NC SxB 50Ω 50Ω VS Dx V VIN SxA/SxB Dx RL 50Ω GND VOUT 07983-020 OFF ISOLATION = 20 log Figure 23. On Resistance 07983-027 IDS VS VOUT VS Figure 26. Off Isolation VDD VSS 0.1µF 0.1µF VDD SxA INx NETWORK ANALYZER VSS NC SxB 50Ω 50Ω VS Dx VIN Dx RL 50Ω GND A VS VD INSERTION LOSS = 20 log VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 27. Bandwidth Figure 24. Off Leakage VDD VSS 0.1µF 0.1µF NETWORK ANALYZER VOUT VDD SxA VSS RL 50Ω SxB VS NC = NO CONNECT RL 50Ω GND A VD CHANNEL-TO-CHANNEL CROSSTALK = 20 log 07983-022 NC Dx Dx INx ID (ON) SxA/SxB VOUT 07983-028 SxA/SxB 07983-021 A ID (OFF) VOUT VS Figure 28. Channel-to-Channel Crosstalk Figure 25. On Leakage Rev. A | Page 13 of 16 07983-029 IS (OFF) ADG1636 VDD VSS 0.1µF 0.1µF AUDIO PRECISION VDD VSS RS SxA/SxB INx VS V p-p Dx VIN VOUT RL 110Ω 07983-034 GND Figure 29. THD + Noise VDD VSS VIN 50% 50% VIN 50% 50% VSS VDD SxB VS 0.1µF Dx SxA VOUT RL 300Ω INx CL 35pF 90% VOUT GND VIN 90% tON tOFF 07983-023 0.1µF Figure 30. Switching Times 0.1µF VDD VSS VDD VSS SxB VS 0.1µF VIN Dx VOUT SxA RL 300Ω INx VOUT CL 35pF 80% tBBM GND tBBM 07983-024 VIN Figure 31. Break-Before-Make Time Delay VS VDD VSS VDD VSS VIN (NORMALLY CLOSED SWITCH) SxB Dx SxA INx VIN 0.1µF GND ON OFF NC VOUT CL 1nF VIN (NORMALLY OPEN SWITCH) VOUT ΔVOUT Figure 32. Charge Injection Rev. A | Page 14 of 16 QINJ = CL × ΔVOUT 07983-026 0.1µF ADG1636 TERMINOLOGY tTRANSITION The delay time between the 50% and 90% points of the digital input and switch on condition when switching from one address state to another. IDD The positive supply current. ISS The negative supply current. tON (EN) The delay between applying the digital control input and the output switching on. See Figure 30. VD (VS) The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between Terminal D and Terminal S. RFLAT(ON) Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. tOFF (EN) The delay between applying the digital control input and the output switching off. See Figure 30. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. ID (Off) The drain leakage current with the switch off. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. ID, IS (On) The channel leakage current with the switch on. Bandwidth The frequency at which the output is attenuated by 3 dB. VINL The maximum input voltage for Logic 0. On Response The frequency response of the on switch. VINH The minimum input voltage for Logic 1. Insertion Loss The loss due to the on resistance of the switch. IINL (IINH) The input current of the digital input. Total Harmonic Distortion + Noise (THD + N) The ratio of the harmonic amplitude plus noise of the signal to the fundamental. CS (Off) The off switch source capacitance, which is measured with reference to ground. CD (Off) The off switch drain capacitance, which is measured with reference to ground. CD, CS (On) The on switch capacitance, which is measured with reference to ground. AC Power Supply Rejection Ratio (ACPSRR) The ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the ability of the part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. CIN The digital input capacitance. Rev. A | Page 15 of 16 ADG1636 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC 0.20 0.09 SEATING PLANE COPLANARITY 0.10 0.75 0.60 0.45 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 33. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters 4.00 BSC SQ 0.60 MAX 12 13 3.75 BSC SQ TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING 0.30 PLANE 0.23 0.18 1 16 EXPOSED PAD 0.65 BSC 4 9 8 PIN 1 INDICATOR 2.65 2.50 SQ 2.35 5 0.25 MIN 1.95 BCS 0.80 MAX 0.65 TYP BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.20 REF 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGC. 031006-A PIN 1 INDICATOR 0.50 0.40 0.30 Figure 34. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-13) Dimensions shown in millimeters ORDERING GUIDE Model ADG1636BRUZ 1 ADG1636BRUZ-REEL1 ADG1636BRUZ-REEL71 ADG1636BCPZ- REEL1 ADG1636BCPZ-REEL71 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16- Lead Thin Shrink Small Outline Package [TSSOP] 16- Lead Thin Shrink Small Outline Package [TSSOP] 16- Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07983-0-9/09(A) Rev. A | Page 16 of 16 Package Option RU-16 RU-16 RU-16 CP-16-13 CP-16-13