CYPRESS CYRF7936

CYRF7936
2.4 GHz CyFi™ Transceiver
Features
■
Battery Voltage Monitoring Circuitry
2.4 GHz Direct Sequence Spread Spectrum (DSSS) radio
transceiver
■
Supports coin-cell operated applications
■
Operating voltage from 1.8V to 3.6V
■
Operates in the unlicensed worldwide Industrial, Scientific,
and Medical (ISM) band (2.400 GHz – 2.483 GHz)
■
Operating temperature from 0 to 70°C
21 mA operating current (Transmit at –5 dBm)
■
Space saving 40-pin QFN 6x6 mm package
■
■
Transmit power up to +4 dBm
■
Receive sensitivity up to –97 dBm
■
Wireless Sensor Networks
■
Sleep Current <1 μA
■
Wireless Actuator Control
■
DSSS data rates up to 250 kbps, GFSK data rate of 1 Mbps
■
Home Automation
■
Low external component count
■
White Goods
■
Auto Transaction Sequencer (ATS) - no MCU intervention
■
Commercial Building Automation
■
Framing, Length, CRC16, and Auto ACK
■
Automatic Meter Readers
■
Power Management Unit (PMU) for MCU
■
Precision Agriculture
■
Fast Startup and Fast Channel Changes
■
Remote Controls
■
Separate 16-byte Transmit and Receive FIFOs
■
Consumer Electronics
■
Dynamic data rate reception
■
Personal Health and Fitness
■
Receive Signal Strength Indication (RSSI)
■
Toys
■
Serial Peripheral Interface (SPI) control while in sleep mode
Applications Support
■
4 MHz SPI microcontroller interface
■
Applications
See www.cypress.com for development tools, reference
designs, and application notes.
Logic Block Diagram
VREG
L/D
VBAT
PMU
VIO
IRQ
SS
SCK
MISO
MOSI
VCC
VDD
PACTL
CyFi Radio Modem
Data
Interface
and
Sequencer
SPI
GFSK
Modulator
DSSS
Baseband
& Framer
RFN
RFBIAS
GFSK
Demodulator
RSSI
Xtal Osc
RFP
Synthesizer
RST
XTAL XOUT
Cypress Semiconductor Corporation
Document #: 001-48013 Rev. **
•
GND
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 10, 2008
[+] Feedback
CYRF7936
Functional Description
The CYRF7936 CyFi™ Transceiver is a Radio IC designed for low-power embedded wireless applications. Combined with
Cypress’s PSoC programmable system-on-chip and a CyFi network protocol stack, CYRF7936 can be used to implement a
complete CyFi wireless system.
Figure 1. Pin Diagram - CYRF7936 40-Pin QFN
NC 31
NC 32
VIO 33
RST 34
NC 36
VDD 35
L/D 37
VBAT0 38
NC 39
VREG 40
Corner
tabs
30
PACTL / GPIO
NC
2
29
XOUT / GPIO
VCC
3
28
MISO / GPIO
NC
4
27
MOSI / SDAT
NC
5
26
IRQ / GPIO
VBAT1
6
XTAL 1
CYRF7936
CyFi Transciever
40 lead QFN
25 SCK
VCC
7
24 SS
VBAT2
8
23 NC
NC
9
22 NC
* E- PAD Bottom Side
21 NC
RFBIAS 10
20 NC
19 RESV
18 NC
17 NC
16 VCC
15 NC
14 NC
13 RFN
12 GND
11 RFP
Table 1. Pin Description - CYRF7936 40-Pin QFN
Pin Number
Name
Type
Default
Description
13
RFN
IO
I
Differential RF signal to and from antenna.
11
RFP
IO
I
Differential RF signal to and from antenna.
10
RFBIAS
O
O
RF IO 1.8V reference voltage.
30
PACTL
IO
O
Control signal for external PA, T/R switch, or GPIO.
1
XTAL
I
I
12 MHz crystal.
29
XOUT
IO
O
Buffered 0.75, 1.5, 3, 6, or 12 MHz clock, PACTL, or GPIO.
Tri-states in sleep mode (configure as GPIO drive LOW).
25
SCK
I
I
SPI clock.
28
MISO
IO
Z
SPI data output pin (Master In Slave Out), or GPIO (in SPI 3-pin mode).
Tri-states when SPI 3PIN = 0 and SS# is deasserted.
27
MOSI
IO
I
SPI data input pin (Master Out Slave In), or SDAT.
24
SS#
I
I
SPI enable, active LOW assertion. Enables and frames transfers.
26
IRQ
IO
O
Interrupt output (configurable active HIGH or LOW), or GPIO.
34
RST
I
I
Device reset. Internal 10 kohm pull down resistor. Active HIGH, typically
connect through a 0.47 μF capacitor to VBAT. Must have RST = 1 event the
first time power is applied to the radio. Otherwise the state of the radio control
registers is unknown.
37
LVD
O
40
VREG
Pwr
PMU boosted output voltage feedback.
35
VDD
Pwr
Decoupling pin for 1.8V logic regulator, connect through a 0.47 μF capacitor
to GND.
6, 8, 38
VBAT(0-2)
Pwr
VBAT = 1.8V to 3.6V. Main supply.
3, 7, 16
VCC
Pwr
VCC = 2.4V to 3.6V. Typically connected to VREG.
Document #: 001-48013 Rev. **
PMU inductor/diode connection, when used. If not used, connect to GND.
Page 2 of 21
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CYRF7936
Table 1. Pin Description - CYRF7936 40-Pin QFN (continued)
Pin Number
Name
33
VIO
19
RESV
2, 4, 5, 9, 14, 15, NC
18, 17, 20, 21, 22,
23, 32, 36, 39, 31
Type
Pwr
I
NC
Default
Description
IO interface voltage, 1.8–3.6V.
Must be connected to GND.
Connect to GND.
12
GND
GND
Ground.
E-PAD
GND
GND
Must be soldered to Ground.
Corner Tabs
NC
NC
Do Not solder the tabs and keep other signal traces clear. All tabs are
common to the lead frame or paddle which is grounded after the pad is
grounded. While they are visible to the user, they do not extend to the bottom.
Functional Overview
The CYRF7936 IC is designed to implement wireless device
links operating in the worldwide 2.4 GHz ISM frequency band.
It is intended for systems compliant with worldwide regulations
covered by ETSI EN 301 489-1 V1.41, ETSI EN 300 328-1
V1.3.1 (Europe), FCC CFR 47 Part 15 (USA and Industry
Canada), and TELEC ARIB_T66_March, 2003 (Japan).
Data Transmission Modes
The CyFi radio transceiver supports two different data transmission modes:
■
In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
■
In 8DR mode, DSSS is enabled and eight bits are encoded
in each derived code symbol transmitted.
The CYRF7936 contains a 2.4 GHz CyFi radio modem which
features a 1 Mbps GFSK radio front-end, packet data buffering,
packet framer, DSSS baseband controller, and Received
Signal Strength Indication (RSSI). CYRF7936 features a SPI
interface for data transfer and device configuration.
Both 64 chip and 32 chip Pseudo Noise (PN) codes are
supported in 8DR mode. In general, lower data rates reduce
packet error rate in any given environment.
The CyFi radio modem supports 98 discrete 1 MHz channels
(regulations may limit the use of some of these channels in
certain jurisdictions).
The CYRF7936 IC device supports the following data packet
framing features:
The baseband performs DSSS spreading/despreading, Start
of Packet (SOP), End of Packet (EOP) detection, and CRC16
generation and checking. The baseband may also be
configured to automatically transmit Acknowledge (ACK)
handshake packets whenever a valid packet is received.
When in receive mode, with packet framing enabled, the
device is always ready to receive data transmitted at any of the
supported bit rates. This enables the implementation of
mixed-rate systems in which different devices use different
data rates. This also enables the implementation of dynamic
data rate systems that use high data rates at shorter distances
or in a low-moderate interference environment or both. It
changes to lower data rates at longer distances or in high interference environments or both.
In addition, the CYRF7936 IC has a Power Management Unit
(PMU), which allows direct connection of the device to any
battery voltage in the range 1.8V to 3.6V. The PMU conditions
the battery voltage to provide the supply voltages required by
the device, and may supply external devices.
Document #: 001-48013 Rev. **
Packet Framing
SOP
Packets begin with a two-symbol Start-of-Packet (SoP)
marker. The SOP_CODE_ADR PN code used for the SOP is
different from that used for the “body” of the packet, and if
desired may be a different length. SOP must be configured to
be the same length on both sides of the link.
Length
This is the first eight bits after the SOP symbol, and is transmitted at the payload data rate. An EoP condition is inferred
after reception of the number of bytes defined in the length
field, plus two bytes for the CRC16.
CRC16
The device may be configured to append a 16 bit CRC16 to
each packet. The CRC16 uses the USB CRC polynomial with
the added programmability of the seed. If enabled, the receiver
verifies the calculated CRC16 for the payload data against the
received value in the CRC16 field. The seed value for the
CRC16 calculation is configurable, and the CRC16 transmitted
may be calculated using either the loaded seed value or a zero
seed; the received data CRC16 is checked against both the
configured and zero CRC16 seeds.
Page 3 of 21
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CYRF7936
CRC16 detects the following errors:
■
Any odd number of bits in error (irrespective of the location).
An error burst as wide as the checksum itself.
■
Any one bit in error.
■
■
Any two bits in error (irrespective of how far apart, which
column, and so on).
Figure 2 shows an example packet with SOP, CRC16, and
lengths fields enabled, and Figure 3 shows a standard ACK
packet.
Figure 2. Example Packet Format
P re a m b le
n x 16us
P
2 n d F ra m in g
S y m b o l*
SOP 1
SOP 2
L e n g th
P a y lo a d D a ta
Packet
le n g th
1 B y te
P e rio d
1 s t F ra m in g
S y m b o l*
C R C 16
*N o te :3 2 o r 6 4 u s
Figure 3. Example ACK Packet Format
P r e a m b le
n x 16us
P
2 n d F r a m in g
S y m b o l*
SO P 1
SO P 2
1 s t F r a m in g
S y m b o l*
C RC 16
C R C fie ld fr o m
r e c e iv e d p a c k e t.
2 B y te p e r io d s
Packet Buffers
All data transmission and reception use the 16 byte packet
buffers - one for transmission and one for reception.
The transmit buffer allows loading a complete packet of up to 16
bytes of payload data in one burst SPI transaction. This is then
transmitted with no further MCU intervention. Similarly, the
receive buffer allows receiving an entire packet of payload data
up to 16 bytes with no firmware intervention required until the
packet reception is complete.
The CYRF7936 IC supports packets up to 255 bytes. However,
the actual maximum packet length depends on the accuracy of
the clock on each end of the link and the data mode. Interrupts
are provided to allow an MCU to use the transmit and receive
buffers as FIFOs. When transmitting a packet longer than 16
bytes, the MCU can load 16 bytes initially, and add further bytes
to the transmit buffer as transmission of data creates space in
the buffer. Similarly, when receiving packets longer than 16
bytes, the MCU must fetch received data from the FIFO
periodically during packet reception to prevent it from
overflowing.
Auto Transaction Sequencer (ATS)
The CYRF7936 IC provides automated support for transmission
and reception of acknowledged data packets.
When transmitting in transaction mode, the device automatically:
■
starts the crystal and synthesizer
■
enters transmit mode
■
transmits the packet in the transmit buffer
■
transitions to receive mode and waits for an ACK packet
■
transitions to the transaction end state when an ACK packet is
received or a timeout period expires
Document #: 001-48013 Rev. **
*N o te :3 2 o r 6 4 u s
Similarly, when receiving in transaction mode, the device
automatically:
■
waits in receive mode for a valid packet to be received
■
transitions to transmit mode, transmits an ACK packet
■
transitions to the transaction end state (receive mode to await
the next packet, and so on.)
The contents of the packet buffers are not affected by the
transmission or reception of ACK packets.
In each case, the entire packet transaction takes place without
any need for MCU firmware action (as long as packets of 16
bytes or less are used). To transmit data, the MCU must load the
data packet to be transmitted, set the length, and set the TX GO
bit. Similarly, when receiving packets in transaction mode,
firmware must retrieve the fully received packet in response to
an interrupt request indicating reception of a packet.
Data Rates
The CYRF7936 IC supports the following data rates by
combining the PN code lengths and data transmission modes
described in the previous sections:
■
1000 kbps (GFSK)
■
250 kbps (32 chip 8DR)
■
125 kbps (64 chip 8DR)
Page 4 of 21
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CYRF7936
Functional Block Overview
SPI communication may be described as the following:
2.4 GHz CyFi Radio Modem
■
Command Direction (bit 7) = ‘1’ enables SPI write transaction.
When it equals a ‘0’, it enables SPI read transactions.
■
Command Increment (bit 6) = ‘1’ enables SPI auto address
increment. When set, the address field automatically
increments at the end of each data byte in a burst access.
Otherwise the same address is accessed.
■
Six bits of address
■
Eight bits of data
The CyFi radio Modem is a dual conversion low IF architecture
optimized for power, range, and robustness. The CyFi radio
modem employs channel-matched filters to achieve high performance in the presence of interference. An integrated Power
Amplifier (PA) provides up to +4 dBm transmit power, with an
output power control range of 34 dB in seven steps. The supply
current of the device is reduced as the RF output power is
reduced.
Table 2. Internal PA Output Power Step Table
PA Setting
7
6
5
4
3
2
1
0
Typical Output Power (dBm)
+4
0
–5
–13
–18
–24
–30
–35
Frequency Synthesizer
Before transmission or reception may begin, the frequency
synthesizer must settle. The settling time varies depending on
channel; 25 fast channels are provided with a maximum settling
time of 100 μs.
The ‘fast channels’ (less than 100 μs settling time) are every third
channel, starting at 0 up to and including 72 (for example, 0, 3,
6, 9 …. 69, 72).
Baseband and Framer
The device receives SCK from an application MCU on the SCK
pin. Data from the application MCU is shifted in on the MOSI pin.
Data to the application MCU is shifted out on the MISO pin. The
active LOW Slave Select (SS#) pin must be asserted to initiate
an SPI transfer.
The application MCU can initiate SPI data transfers using a
multi-byte transaction. The first byte is the Command/Address
byte, and the following bytes are the data bytes shown in
Figure 4 through Figure 7 on page 6.
The SPI communications interface has a burst mechanism,
where the first byte can be followed by as many data bytes as
required. A burst transaction is terminated by deasserting the
slave select (SS# = 1).
The SPI communications interface single read and burst read
sequences are shown in Figure 5 and Figure 6 on page 6,
respectively.
The SPI communications interface single write and burst write
sequences are shown in Figure 7 and Figure 8 on page 6,
respectively.
This interface may be optionally operated in a 3-pin mode with
the MISO and MOSI functions combined in a single bidirectional
data pin (SDAT). When using 3-pin mode, user firmware must
ensure that the MOSI pin on the MCU is in a high impedance
state except when MOSI is actively transmitting data.
Packet Buffers and Radio Configuration Registers
The device registers may be written to or read from one byte at
a time, or several sequential register locations may be written or
read in a single SPI transaction using incrementing burst mode.
In addition to single byte configuration registers, the device
includes register files. Register files are FIFOs written to and
read from using nonincrementing burst SPI transactions.
Packet data and configuration registers are accessed through
the SPI interface. All configuration registers are directly
addressed through the address field in the SPI packet. Configuration registers allow configuration of DSSS PN codes, data rate,
operating mode, interrupt masks, interrupt status, and so on.
The IRQ pin function may be optionally multiplexed onto the
MOSI pin. When this option is enabled, the IRQ function is not
available while the SS# pin is LOW. When using this configuration, user firmware must ensure that the MOSI pin on the MCU
is in a high impedance state whenever the SS# pin is HIGH.
SPI Interface
The SPI interface is not dependent on the internal 12 MHz clock.
Registers may therefore be read from or written to when the
device is in sleep mode, and the 12 MHz oscillator disabled.
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception, CRC16
generation and checking, and EOP detection and length field.
The CYRF7936 IC has an SPI interface supporting
communication between an application MCU and one or more
slave devices (including the CYRF7936). The SPI interface
supports single-byte and multi-byte serial transfers using either
4-pin or 3-pin interfacing. The SPI communications interface
consists of Slave Select (SS#), Serial Clock (SCK), Master
Out-Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data
(SDAT).
Document #: 001-48013 Rev. **
The SPI interface and the IRQ and RST pins have a separate
voltage reference pin (VIO). This enables the device to interface
directly to MCUs operating at voltages below the CYRF7936 IC
supply voltage.
Page 5 of 21
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CYRF7936
Figure 4. SPI Transaction Format
Byte 1
Byte 1+N
Bit #
7
6
[5:0]
[7:0]
Bit Name
DIR
INC
Address
Data
Figure 5. SPI Single Read Sequence
SCK
SS
cmd
MOSI
DIR
0
INC
addr
A5
A4
A3
A2
A1
A0
data to mcu
MISO
D7
D6
D5
D4
D3
D2
D1
D0
Figure 6. SPI Incrementing Burst Read Sequence
SCK
SS
MOSI
cmd
DIR
0
INC
addr
A5
A4
A3
A2
A1
A0
data to mcu1+N
data to mcu1
MISO
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
Figure 7. SPI Single Write Sequence
SCK
SS
cmd
MOSI
DIR
1
INC
addr
A5
A4
A3
A2
data from mcu
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
MISO
Figure 8. SPI Incrementing Burst Write Sequence
SCK
SS
cmd
MOSI
DIR
1
INC
addr
A5
A4
A3
A2
data from mcu1
A1
A0
D7
D6
D5
D4
D3
D2
data from mcu1+N
D1
D0
D7
D6
D5
D4
D3
D2
MISO
Document #: 001-48013 Rev. **
Page 6 of 21
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CYRF7936
Interrupts
The device provides an interrupt (IRQ) output, which is
configurable to indicate the occurrence of various different
events. The IRQ pin may be programmed to be either active
HIGH or active LOW, and be either a CMOS or open drain output.
The available interrupts are described in the section Register
Descriptions on page 12.
The CYRF7936 IC features three sets of interrupts: transmit,
receive, and system interrupts. These interrupts all share a
single pin (IRQ), but can be independently enabled or disabled.
The contents of the enable registers are preserved when
switching between transmit and receive modes.
If more than one interrupt is enabled at any time, it is necessary
to read the relevant status register to determine which event
caused the IRQ pin to assert. Even when a given interrupt source
is disabled, the status of the condition that would otherwise
cause an interrupt can be determined by reading the appropriate
status register. It is therefore possible to use the devices without
the IRQ pin, by polling the status registers to wait for an event,
rather than using the IRQ pin.
Clocks
A 12 MHz crystal (30 ppm or better) is directly connected
between XTAL and GND without the need for external
capacitors. A digital clock out function is provided, with
selectable output frequencies of 0.75, 1.5, 3, 6, or 12 MHz. This
output may be used to clock an external microcontroller (MCU)
or ASIC. This output is enabled by default, but may be disabled.
The requirements to directly connect the crystal to the XTAL pin
and GND are:
■
Nominal Frequency: 12 MHz
■
Operating Mode: Fundamental Mode
■
Resonance Mode: Parallel Resonant
■
Frequency Initial Stability: ±30 ppm
■
Series Resistance: <60 ohms
■
Load Capacitance: 10 pF
■
Drive Level: 100 µW
Power Management
The operating voltage of the device is 1.8V to 3.6V DC, which is
applied to the VBAT pin. The device can be shut down to a fully
static sleep mode by writing to the FRC END = 1 and
END STATE = 000 bits in the XACT_CFG_ADR register over the
SPI interface. The device enters sleep mode within 35 µs after
the last SCK positive edge at the end of this SPI transaction.
Alternatively, the device may be configured to automatically
enter sleep mode after completing the packet transmission or
reception. When in sleep mode, the on-chip oscillator is stopped,
but the SPI interface remains functional. The device wakes from
sleep mode automatically when the device is commanded to
enter transmit or receive mode. When resuming from sleep
mode, there is a short delay while the oscillator restarts. The
device can be configured to assert the IRQ pin when the
oscillator has stabilized.
Document #: 001-48013 Rev. **
The output voltage (VREG) of the Power Management Unit
(PMU) is configurable to several minimum values between 2.4V
and 2.7V. VREG may be used to provide up to 15 mA (average
load) to external devices. It is possible to disable the PMU and
provide an externally regulated DC supply voltage to the device’s
main supply in the range 2.4V to 3.6V. The PMU also provides a
regulated 1.8V supply to the logic.
The PMU is designed to provide high boost efficiency (74–85%
depending on input voltage, output voltage, and load) when
using a Schottky diode and power inductor, eliminating the need
for an external boost converter in many systems where other
components require a boosted voltage. However, reasonable
efficiencies (69–82% depending on input voltage, output voltage,
and load) may be achieved when using low cost components
such as SOT23 diodes and 0805 inductors.
The PMU also provides a configurable low battery detection
function, which may be read over the SPI interface. One of seven
thresholds between 1.8V and 2.7V may be selected. The
interrupt pin may be configured to assert when the voltage on the
VBAT pin falls below the configured threshold. LV IRQ is not a
latched event. Battery monitoring is disabled when the device is
in sleep mode.
Low Noise Amplifier and Received Signal Strength
Indication
The gain of the receiver can be controlled directly by clearing the
AGC EN bit and writing to the Low Noise Amplifier (LNA) bit of
the RX_CFG_ADR register. Clearing the LNA bit reduces the
receiver gain approximately 20 dB, allowing accurate reception
of very strong received signals (for example, when operating a
receiver very close to the transmitter). Approximately 30 dB of
receiver attenuation can be added by setting the Attenuation
(ATT) bit. This limits data reception to devices at very short
ranges. Disabling AGC and enabling LNA is recommended,
unless receiving from a device using external PA.
When the device is in receive mode the RSSI_ADR register
returns the relative signal strength of the on-channel signal
power.
When receiving, the device automatically measures and stores
the relative strength of the signal being received as a five bit
value. An RSSI reading is taken automatically when the SoP is
detected. In addition, a new RSSI reading is taken every time the
previous reading is read from the RSSI_ADR register, allowing
the background RF energy level on any given channel to be
easily measured when RSSI is read while no signal is being
received. A new reading can occur as fast as once every 12 µs.
Page 7 of 21
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CYRF7936
Application Examples
CYRF7936
Figure 9. Recommended Circuit for Systems where VBAT ≤ 2.4V
Document #: 001-48013 Rev. **
Page 8 of 21
[+] Feedback
CYRF7936
Table 3. Recommended BoM for Systems where VBAT ≤ 2.4V
Item Qty
CY Part Number
Reference
ANT1
Description
Manufacturer
2.5GHZ H-STUB WIGGLE ANTENNA NA
FOR 32MIL PCB
Mfr Part Number
1
1
NA
2
1
730-10012
C1
CAP 15PF 50V CERAMIC NPO 0402 Panasonic
ECJ-0EC1H150J
3
1
730-11955
C3
CAP 2.0 PF 50V CERAMIC NPO 0402 Kemet
C0402C209C5GAC
TU
4
1
730-11398
C4
CAP 1.5PF 50V CERAMIC NPO 0402 PANASONIC
SMD
ECJ-0EC1H1R5C
5
1
730R-13322
C5
CAP CER .47UF 6.3V X5R 0402
Murata
GRM155R60J474K
E19D
6
2
730-13037
C12,C7
CAP CERAMIC 10UF 6.3V X5R 0805 Kemet
C0805C106K9PAC
TU
7
1
730-13400
C8
CAP 1 uF 6.3V CERAMIC X5R 0402 Panasonic
ECJ-0EB0J105M
8
6
730-13404
C9,C10,C11, CAP 0.047 uF 50V CERAMIC X5R
C13,C15,C1 0402
6
9
1
730R-11952
C17
CAP .10UF 10V CERAMIC X5R 0402 Kemet
C0402C104K8PAC
TU
10
1
800-13317
D1
DIODE SCHOTTKY 0.5A 40V SOT23 DIODES INC
BAT400D-7-F
11
1
420-11976
J1
CONN HEADER 12 PIN 2MM GOLD Hirose Electric
Co. LTD.
DF11-12DP-2DSA(0
1)
12
1
800-13401
L1
INDUCTOR 22NH 2% FIXED 0603
SMD
Panasonic - ECG ELJ-RE22NGF2
13
1
800-11651
L2
INDUCTOR 1.8NH +-.3NH FIXED
0402 SMD
Panasonic - ECG ELJ-RF1N8DF
Newark
AVX
NA
0402YD473KAT2A
14
1
800-10594
L3
COIL 10UH 1100MA CHOKE 0805
15
1
630-11356
R1
RES 1.00 OHM 1/8W 1% 0805 SMD Yageo
16
1
610-13402
R2
RES 47 OHM 1/16W 5% 0402 SMD
17
1
CYRF7936-40LFXC
U1
IC, LP 2.4 GHz RADIO SoC QFN-40 Cypress
Semiconductor
CYRF7936-40LFXC
18
1
800-13259
Y1
CRYSTAL 12.00MHZ HC49 SMD
eCERA
GF-1200008
19
1
PDCR-9515 REV01
PCB
PRINTED CIRCUIT BOARD
Cypress
Semiconductor
PDCR-9515 REV01
20
1
920-11206
LABEL1
Serial Number
21
1
920-51500 REV01
LABEL2
PCA #
Document #: 001-48013 Rev. **
30K5421
9C08052A1R00FK
HFT
Panasonic - ECG ERJ-2GEJ470X
121R-51500 REV01
Page 9 of 21
[+] Feedback
VBUS
DM
DP
GND
S1
S2
1
2
3
4
5
6
USB A RA PLUG
J1
R4
zero
VBUS
DM
DP
0805
5V
4.7 uFd
C13
R1
R2
24
24
0603
0603
5V
5V
R9
R8
3
1
EN
VIN
U3
100
100
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
DM
DP
CY8C24794-24LFXI
25
18
25
17
22
16
28
15
21
20
U2
S1
2
1
D1
4
5
TPS79133
PYBASS
VOUT
KR
KG
2A
2B
0402
0.01 uFd
C15
4
3
SW1
LED Green Red
RD
GR
SW PUSHBUTTON
1A
1B
620
620
0805
VCC
2.2 uFd
C14
nLED2
nLED1
RED
= USB ACTIVITY
GREEN = RF ACTIVITY
Power Supply
5V
R10
R11
LP_nSS R6
LP_IRQ
1K
R5
SCK
MISO
1K
CLKOUT
R7
MOSI
1K
0402
0402
GND
0402
0402
0402
2
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P0_0
P0_1
P0_2
P0_3
P0_4
P0_5
P0_6
P0_7
40
2
42
1
43
56
45
54
46
53
47
52
40
51
TP1
NO LOAD
R3
nLED2
nLED1
SW1
P0_1
RST
TP3
TP4
0402
VCC
0402
VCC
0402
2
4
5
9
14
15
17
18
37
26
24
25
27
28
34
C6
0.047 uFd
LP_IRQ
LP_nSS
SCK
MOSI
MISO
RST
C17
0.47 uFd
U1
CYRF7936
0402
C7
0.047 uFd
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
L/D
IRQ
SS
SCK
MOSI
MISO
RST
0402
C8
0.047 uFd
RFn
RFp
19
20
21
22
23
31
32
36
39
29
1
30
13
11
10
0402
C10
0.047 uFd
RESV
NC9
NC10
NC11
NC12
NC13
NC14
NC15
NC16
XOUT
XTAL
PACTL
0402
C9
0.047 uFd
C5
0402
0.47 uFd
RFbias
8
6
38
0402
1500 pFd
33
VIO
VCC
TP2
C11
0.047 uFd
CLKOUT TV1
PACTL
L2
L1
1.8 nH
IND0402
22 nH
IND0603
0402
12 MHz Crystal
Y1
2.0 pFd
C3
C1
15 pFd
0402
1.5 pFd
C4
ANT1
WIGGLE 32
1
2
C12
0402
VCC
22
49
VDD
VSS
VSS
19
50
40
VREG
VBAT2
VBAT1
VBAT0
GND1
12
3
7
16
VCC1
VCC2
VCC3
E-PAD
35
VDD
41
0402
0402
Document #: 001-48013 Rev. **
0402
5V
CYRF7936
Figure 10. Recommended Circuit for Systems where VBAT is 2.4V - 3.6V (PMU Disabled)
Page 10 of 21
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0402
CYRF7936
Table 4. Recommended BoM for Systems where VBAT is 2.4V - 3.6V (PMU disabled)
Item Qty CY Part Number Reference
Description
Manufacturer
Mfr Part Number
1
1
NA
ANT1
2.5GHZ H-STUB WIGGLE ANTENNA
FOR 32MIL PCB
NA
NA
2
1
730-10012
C1
CAP 15PF 50V CERAMIC NPO 0402
Panasonic
ECJ-0EC1H150J
3
1
730-11955
C3
CAP 2.0 PF 50V CERAMIC NPO 0402
Kemet
C0402C209C5GACTU
4
1
730-11398
C4
CAP 1.5PF 50V CERAMIC NPO 0402
SMD
PANASONIC
ECJ-0EC1H1R5C
5
1
730-13322
C5
CAP 0.47 uF 6.3V CERAMIC X5R 0402
Murata
GRM155R60J474KE19D
6
6
730-13404
C6,C7,C8, CAP 0.047 uF 16V CERAMIC X5R 0402
C9,C10,
C11
AVX
0402YD473KAT2A
7
1
730-11953
C12
CAP 1500PF 50V CERAMIC X7R 0402
Kemet
C0402C152K5RACTU
8
1
730-13040
C13
CAP CERAMIC 4.7UF 6.3V XR5 0805
Kemet
C0805C475K9PACTU
9
1
730-12003
C14
CAP CER 2.2UF 10V 10% X7R 0805
Murata
GRM21BR71A225KA01L
Electronics North
America
10
1
800-13333
D1
LED GREEN/RED BICOLOR 1210 SMD
LITEON
LTST-C155KGJRKT
11
1
420-13046
J1
CONN USB PLUG TYPE A PCB SMT
ACON
UAR72-4N5J10
12
1
800-13401
L1
INDUCTOR 22NH 2% FIXED 0603 SMD
Panasonic - ECG ELJ-RE22NGF2
13
1
800-11651
L2
INDUCTOR 1.8NH +-.3NH FIXED 0402
SMD
Panasonic - ECG ELJ-RF1N8DF
14
2
610-10037
R1, R2
RES 24 OHM 1/16W 5% 0603 SMD
Panasonic - ECG ERJ-3GEYJ240V
15
1
610-10343
R4
RES ZERO OHM 1/16W 0402 SMD
Panasonic - ECG ERJ-2GE0R00X
16
3
610-10016
R5, R6, R7 RES CHIP 1K OHM 1/16W 5% 0402 SMD Panasonic - ECG ERJ-2GEJ102X
17
2
610-13472
R9,R8
RES CHIP 620 OHM 1/16W 5% 0402 SMD Panasonic - ECG ERJ-2GEJ621X
18
2
610-10684
R10, R11
RES CHIP 100 OHM 1/16W 5% 0402 SMD Phycomp USA
Inc
19
1
200-13471
S1
SWITCH LT 3.5MMX2.9MM 160GF SMD Panasonic - ECG EVQ-P7J01K
20
1
CYRF7936-40LFC U1
IC, 2.4 GHz CyFi Transceiver QFN-40
Cypress
Semiconductor
CYRF7936 Rev A5
21
1
CY8C24794-24LF U2
XI
PSoC Mixed Signal Array
Cypress
Semiconductor
CY8C24794-24LFXI
22
1
800-13259
Y1
CRYSTAL 12.00MHZ HC49 SMD
eCERA
GF-1200008
23
1
LABEL1
Serial Number
XXXXXX
Document #: 001-48013 Rev. **
9C1A04021000FLHF3
Page 11 of 21
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CYRF7936
Register Descriptions
All registers are read and writable, except where noted. Registers may be written to or read from individually or in sequential groups.
Table 5. Register Map Summary
Address
Mnemonic
b7
b6
0x00
0x01
CHANNEL_ADR
TX_LENGTH_ADR
0x02
TX_CTRL_ADR
TX GO
TX CLR
0x03
TX_CFG_ADR
0x04
TX_IRQ_STATUS_ADR
Not Used
OS
IRQ
Not Used
LV
IRQ
b5
Not Used
0x05
0x06
RX_CTRL_ADR
RX GO
RSVD
TXB15
IRQEN
DATA CODE
LENGTH
TXB15
IRQ
RXB16
IRQEN
RX_CFG_ADR
0x07
0x08
0x09
0x0A
0x0B
RX_IRQ_STATUS_ADR
RX_STATUS_ADR
RX_COUNT_ADR
RX_LENGTH_ADR
PWR_CTRL_ADR
AGC EN
RXOW
IRQ
RX ACK
LNA
SOPDET
IRQ
PKT ERR
ATT
RXB16
IRQ
EOP ERR
PMU EN
LVIRQ EN
0x0C
0x0D
XTAL_CTRL_ADR
IO_CFG_ADR
XOUT FN
IRQ OD
IRQ POL
PMU Mode
Force
XSIRQ EN
MISO OD
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
GPIO_CTRL_ADR
XACT_CFG_ADR
FRAMING_CFG_ADR
DATA32_THOLD_ADR
DATA64_THOLD_ADR
RSSI_ADR
EOP_CTRL_ADR
CRC_SEED_LSB_ADR
CRC_SEED_MSB_ADR
TX_CRC_LSB_ADR
TX_CRC_MSB_ADR
RX_CRC_LSB_ADR
RX_CRC_MSB_ADR
TX_OFFSET_LSB_ADR
TX_OFFSET_MSB_ADR
MODE_OVERRIDE_ADR
XOUT OP
ACK EN
SOP EN
Not Used
Not Used
SOP
HEN
MISO OP
Not Used
SOP LEN
Not Used
Not Used
Not Used
PACTL OP
FRC END
LEN EN
Not Used
Not Used
LNA
HINT
Not Used
RSVD
Not Used
RSVD
Not Used
FRC SEN
0x1E
RX_OVERRIDE_ADR
ACK RX
RXTX DLY
MAN RXACK
0x1F
0x26
0x27
0x28
0x29
0x32
0x35
TX_OVERRIDE_ADR
XTAL_CFG_ADR
CLK_OVERRIDE_ADR
CLK_EN_ADR
RX_ABORT_ADR
AUTO_CAL_TIME_ADR
AUTO_CAL_OFFSET_AD
R
ANALOG_CTRL_ADR
ACK TX
RSVD
RSVD
RSVD
RSVD
FRC PRE
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
ABORT EN
RSVD
RSVD
RSVD
0x39
Register Files
0x20
0x21
0x22
0x23
0x24
0x25
TX_BUFFER_ADR
RX_BUFFER_ADR
SOP_CODE_ADR
DATA_CODE_ADR
PREAMBLE_ADR
MFG_ID_ADR
b4
b3
Channel
TX Length
TXB8
TXB0
IRQEN
IRQEN
b2
TXBERR
IRQEN
b1
TXC
IRQEN
b0
TXE
IRQEN
DATA MODE
PA SETTING
TXB8
TXB0
TXBERR
TXC
TXE
IRQ
IRQ
IRQ
IRQ
IRQ
RXB8
RXB1
RXBERR
RXC
RXE
IRQEN
IRQEN
IRQEN
IRQEN
IRQEN
FAST TURN
HILO
EN
Not Used
RXOW EN
VLD EN
RXB8
RXB1
RXBERR
RXC
RXE
IRQ
IRQ
IRQ
IRQ
IRQ
CRC0
Bad CRC
RX Code
RX Data Mode
RX Count
RX Length
PFET
LVI TH
PMU OUTV
disable
Not Used
Not Used
FREQ
XOUT OD PACTL OD
PACTL
SPI 3PIN
IRQ GPIO
GPIO
IRQ OP
XOUT IP
MISO IP
PACTL IP
IRQ IP
END STATE
ACK TO
SOP TH
Not Used
TH32
TH64
RSSI
EOP
CRC SEED LSB
CRC SEED MSB
CRC LSB
CRC MSB
CRC LSB
CRC MSB
STRIM LSB
Not Used
STRIM MSB
FRC AWAKE
Not Used
Not Used
RST
FRC
RXDR
DIS CRC0 DIS RXCRC
ACE
Not Used
MAN
TXACK
OVRD ACK DIS TXCRC
RSVD
TX INV
RSVD
START DLY
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RXF
RSVD
RSVD
RSVD
RSVD
RXF
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
AUTO_CAL_TIME
AUTO_CAL_OFFSET
RSVD
RSVD
TX Buffer File
RX Buffer File
SOP Code File
Data Code File
Preamble File
MFG ID File
RSVD
RX INV
ALL SLOW
Default[1] Access[1]
-1001000
00000000
00000011
-bbbbbbb
bbbbbbbb
bbbbbbbb
--000101
--bbbbbb
--------
rrrrrrrr
00000111
bbbbbbbb
10010-10
bbbbb-bb
--------
brrrrrrr
-------00000000
00000000
10100000
rrrrrrrr
rrrrrrrr
rrrrrrrr
bbb-bbbb
000--100
00000000
bbb--bbb
bbbbbbbb
0000---1-000000
10100101
----0100
---01010
0-100000
10100100
00000000
00000000
--------------11111111
11111111
00000000
----0000
00000--0
0000000-
bbbbrrrr
b-bbbbbb
bbbbbbbb
----bbbb
---bbbbb
r-rrrrrr
bbbbbbbb
bbbbbbbb
bbbbbbbb
rrrrrrrr
rrrrrrrr
rrrrrrrr
rrrrrrrr
bbbbbbbb
----bbbb
wwwww--w
bbbbbbb-
00000000
bbbbbbbb
00000000
00000000
00000000
00000000
00000011
00000000
wwwwwwww
wwwwwwww
wwwwwwww
wwwwwwww
wwwwwwww
wwwwwwww
00000000
wwwwwwww
--------------Note 2
Note 3
Note 4
NA
wwwwwwww
rrrrrrrr
bbbbbbbb
bbbbbbbb
bbbbbbbb
rrrrrrrr
Notes
1. b = read/write; r = read only; w = write only; ‘-’ = not used, default value is undefined.
2. SOP_CODE_ADR default = 0x17FF9E213690C782.
3. DATA_CODE_ADR default = 0x02F9939702FA5CE3012BF1DB0132BE6F.
4. PREAMBLE_ADR default = 0x333302. The count value must be great than 4 for DDR and greater than 8 for SDR
5. Registers must be configured or accessed only when the radio is in IDLE or SLEEP mode. The PMU, GPIOs, and RSSI registers can be accessed in Active Tx and
Rx mode.
6. EOP_CTRL_ADR[6:4] must never have the value of “000”, that is, EOP Hint Symbol count must never be “0”
7. PFET Bit: Setting this bit to "1" disables the FET, therefore safely allowing Vbat to be connected to a separate reference from Vcc when the PMU is disabled to the radio.
Document #: 001-48013 Rev. **
Page 12 of 21
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CYRF7936
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature .................................. –65°C to +150°C
Ambient Temperature with Power Applied.. –55°C to +125°C
Supply Voltage on any power supply pin
relative to VSS .................................................–0.3V to +3.9V
DC Voltage to Logic Inputs[8] ................... –0.3V to VIO +0.3V
DC Voltage applied to Outputs
in High-Z State......................................... –0.3V to VIO +0.3V
DC Characteristics
Static Discharge Voltage (Digital)[9] ........................... >2000V
Static Discharge Voltage (RF)[9] ................................. 1100V
Latch-Up Current .....................................+200 mA, –200 mA
Operating Conditions
VCC .....................................................................2.4V to 3.6V
VIO ......................................................................1.8V to 3.6V
VBAT ....................................................................1.8V to 3.6V
TA (Ambient Temperature Under Bias) ............. 0°C to +70°C
Ground Voltage.................................................................. 0V
FOSC (Crystal Frequency)............................ 12MHz ±30 ppm
(T = 25°C, VBAT = 2.4V, PMU disabled, fOSC = 12.000000 MHz)
Parameter
VBAT
VREG[10]
VREG[10]
Description
Conditions
Battery Voltage
0–70°C
PMU Output Voltage
2.4V mode
PMU Output Voltage
2.7V mode
VIO[11]
VIO Voltage
Min
1.8
2.4
2.7
1.8
2.4[12]
VIO – 0.2
VIO – 0.4
Typ
Max
3.6
2.43
2.73
3.6
VCC
VCC Voltage
0–70°C
VOH1
Output High Voltage Condition 1
At IOH = –100.0 µA
VOH2
Output High Voltage Condition 2
At IOH = –2.0 mA
VOL
Output Low Voltage
At IOL = 2.0 mA
VIH
Input High Voltage
0.7VIO
VIO
VIL
Input Low Voltage
0
0.3VIO
IIL
Input Leakage Current
0 < VIN < VIO
0.26
+1
CIN
Pin Input Capacitance
3.5
10
ICC (GFSK)[13]
except XTAL, RFN, RFP, RFBIAS
Average TX ICC, 1 Mbps, slow channel
PA = 5, 2 way, 4 bytes/10 ms
0.87
ISB[14]
Sleep Mode ICC
ICC (32-8DR)[13] Average TX ICC, 250 kbps, fast channel PA = 5, 2 way, 4 bytes/10 ms
ISB[14]
3.6
VIO
VIO
0
–1
0.45
1.2
0.8
10
31.4
Unit
V
V
V
V
V
V
V
V
V
V
µA
pF
mA
mA
µA
µA
mA
mA
mA
mA
mA
mA
mA
%
Sleep Mode ICC
PMU enabled
IDLE ICC
Radio off, XTAL Active
XOUT disabled
Isynth
ICC during Synth Start
TX ICC
ICC during Transmit
PA = 5 (–5 dBm)
20.8
TX ICC
ICC during Transmit
PA = 6 (0 dBm)
26.2
TX ICC
ICC during Transmit
PA = 7 (+4 dBm)
34.1
RX ICC
ICC during Receive
LNA off, ATT on
18.4
RX ICC
ICC during Receive
LNA on, ATT off
21.2
Boost Eff
PMU Boost Converter Efficiency
VBAT = 2.5V, VREG = 2.73V,
ILOAD = 20 mA
ILOAD_EXT
Average PMU External Load current
VBAT = 1.8V, VREG = 2.73V,
0–50°C, RX Mode
15
mA
ILOAD_EXT
Average PMU External Load current
VBAT = 1.8V, VREG = 2.73V, 50–70°C,
RX Mode
10
mA
1.0
8.4
81
Notes
8. It is permissible to connect voltages above VIO to inputs through a series resistor limiting input current to 1 mA. AC timing not guaranteed.
9. Human Body Model (HBM).
10. VREG depends on battery input voltage.
11. In sleep mode, the IO interface voltage reference is VBAT.
12. In sleep mode, VCC min. can be as low as 1.8V.
13. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including SOP and CRC16), changing to receive mode, and receiving ACK
handshake. Device is in sleep except during this transaction.
14. ISB is not guaranteed if any IO pin is connected to voltages higher than VIO.
Document #: 001-48013 Rev. **
Page 13 of 21
[+] Feedback
CYRF7936
AC Characteristics
The AC Characteristics of CYRF7936 follow[12]
Table 6. SPI Interface[16]
Parameter
Description
tSCK_CYC
SPI Clock Period
tSCK_HI
tSCK_LO
Min
Typ
Max
Unit
238.1
ns
SPI Clock High Time
100
ns
SPI Clock Low Time
100
ns
tDAT_SU
SPI Input Data Setup Time
25
ns
tDAT_HLD
SPI Input Data Hold Time
10
tDAT_VAL
SPI Output Data Valid Time
0
tDAT_VAL_TRI
SPI Output Data Tri-state (MOSI from Slave Select Deassert)
[17]
ns
50
ns
20
ns
tSS_SU
SPI Slave Select Setup Time before first positive edge of SCK
10
ns
tSS_HLD
SPI Slave Select Hold Time after last negative edge of SCK
10
ns
tSS_PW
SPI Slave Select Minimum Pulse Width
20
ns
tSCK_SU
SPI Slave Select Setup Time
10
ns
tSCK_HLD
SPI SCK Hold Time
10
ns
tRESET
Minimum RST Pin Pulse Width
10
ns
Figure 11. SPI Timing
tSCK_CYC
tSCK_HI
SCK
tSCK_LO
tSCK_HLD
tSCK_SU
nSS
tSS_SU
tDAT_SU
tSS_HLD
tDAT_HLD
MOSI input
tDAT_VAL
tDAT_VAL_TRI
MISO
MOSI output
Notes
15. AC values are not guaranteed if voltage on any pin exceeding VIO.
16. CLOAD = 30 pF
17. SCK must start low at the time SS# goes LOW, otherwise the success of SPI transactions are not guaranteed.
Document #: 001-48013 Rev. **
Page 14 of 21
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CYRF7936
RF Characteristics
Table 7. Radio Parameters
Parameter Description
Conditions
RF Frequency Range
Note 18
Receiver (T = 25°C, VCC = 3.0V, fOSC = 12.000000 MHz, BER < 1E-3)
Sensitivity 125 kbps 64-8DR
BER 1E-3
Sensitivity 250 kbps 32-8DR
Min
BER 1E-3
Sensitivity
CER 1E-3
Sensitivity GFSK
BER 1E-3, ALL SLOW = 1
Typ
2.400
–80
Max
Unit
2.497
GHz
–97
dBm
–93
dBm
–87
dBm
–84
dBm
LNA Gain
22.8
dB
ATT Gain
–31.7
dB
Maximum Received Signal
LNA On
RSSI Value for PWRin –60 dBm
LNA On
–15
RSSI Slope
–6
dBm
21
Count
1.9
dB/Count
9
dB
Interference Performance (CER 1E-3)
Co-channel Interference rejection
Carrier-to-Interference (C/I)
C = –60 dBm
Adjacent (±1 MHz) channel selectivity C/I 1 MHz
C = –60 dBm
3
dB
Adjacent (±2 MHz) channel selectivity C/I 2 MHz
C = –60 dBm
–30
dB
Adjacent (> 3 MHz) channel selectivity C/I > 3 MHz
C = –67 dBm
–38
dB
Out-of-Band Blocking 30 MHz–12.75 MHz[19]
C = –67 dBm
–30
dBm
Intermodulation
C = –64 dBm, Δf = 5,10 MHz
–36
dBm
Receive Spurious Emission
800 MHz
100 kHz ResBW
–79
dBm
1.6 GHz
100 kHz ResBW
–71
dBm
3.2 GHz
100 kHz ResBW
–65
dBm
Transmitter (T = 25°C, VCC = 3.0V)
Maximum RF Transmit Power
PA = 7
+2
4
+6
dBm
Maximum RF Transmit Power
PA = 6
–2
0
+2
dBm
Maximum RF Transmit Power
PA = 5
–7
–5
–3
Maximum RF Transmit Power
PA = 0
–35
39
dB
RF Power Range Control Step Size
Seven steps, monotonic
5.6
dB
Frequency Deviation Min
PN Code Pattern 10101010
270
kHz
Frequency Deviation Max
PN Code Pattern 11110000
323
kHz
Error Vector Magnitude (FSK error)
>0 dBm
Occupied Bandwidth
–6 dBc, 100 kHz ResBW
RF Power Control Range
dBm
dBm
10
%rms
876
kHz
In-band Spurious Second Channel Power (±2 MHz)
–38
dBm
In-band Spurious Third Channel Power (>3 MHz)
–44
dBm
500
Transmit Spurious Emission (PA = 7)
Notes
18. Subject to regulation.
19. Exceptions F/3 & 5C/3.
Document #: 001-48013 Rev. **
Page 15 of 21
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CYRF7936
Table 7. Radio Parameters (continued)
Parameter Description
Conditions
Min
Typ
Max
Unit
Non-Harmonically Related Spurs (800 MHz)
–38
dBm
Non-Harmonically Related Spurs (1.6 GHz)
–34
dBm
Non-Harmonically Related Spurs (3.2 GHz)
–47
dBm
Harmonic Spurs (Second Harmonic)
–43
dBm
Harmonic Spurs (Third Harmonic)
–48
dBm
Fourth and Greater Harmonics
–59
dBm
Power Management (Crystal PN# eCERA GF-1200008)
Crystal Start to 10ppm
0.7
1.3
0.6
ms
Crystal Start to IRQ
XSIRQ EN = 1
Synth Settle
Slow channels
270
ms
µs
Synth Settle
Medium channels
180
µs
Synth Settle
Fast channels
100
µs
Link Turnaround Time
GFSK
30
µs
Link Turnaround Time
250 kbps
62
µs
Link Turnaround Time
125 kbps
94
µs
Link Turnaround Time
<125 kbps
31
µs
Max Packet Length
<60 ppm crystal-to-crystal
40
bytes
Document #: 001-48013 Rev. **
Page 16 of 21
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CYRF7936
Typical Operating Characteristics
The typical operating characteristics of CYRF7936 follow[20]
Transmit Power vs. Temperature
(Vcc = 2.7v)
Transmit Power vs. Channel
Transmit Power vs. Vcc
(PMU off)
6
6
-2
-4
PA5
-6
-8
-10
PA4
-12
2
20
PA6
0
-2
-4
PA5
-6
-8
-10
PA4
-12
-14
0
40
Output Power (dBm)
PA6
0
-14
2.4
60
2.6
2.8
3
3.2
3.4
PA4
0
20
40
LNA OFF
ATT ON
LNA OFF
80
Average RSSI vs. Vcc
(Rx signal = -70dBm)
20
19
18
RSSI Count
LNA ON
60
Channel
17
RSSI Count
RSSI Count
-8
-10
3.6
19
24
16
15
17
16
15
14
13
14
12
13
0
-120
11
10
2.4
12
-100
-80
-60
-40
0
-20
20
40
60
RSSI vs. Channel
(Rx signal = -70dBm)
12
10
8
6
4
2
0
40
60
-82
-84
-86
CER
-88
-90
8DR32
-92
-94
2.4
80
3.4
3.6
-82
-84
-86
CER
-88
-90
8DR32
-92
-94
2.6
2.8
Channel
3
3.2
3.4
3.6
0
20
Vcc
40
60
Temp (deg C)
Receiver Sensitivity vs Channel
(3.0v, Room Temp)
Receiver Sensitivity vs. Frequency Offset
-80
3.2
-80
Receiver Sensitivity (dBm)
Receiver Sensitivity (dBm)
14
3
Rx Sensitivity vs. Temperature
(1Mbps CER)
-80
16
20
2.8
Vcc
Rx Sensitivity vs. Vcc
(1Mbps CER)
18
0
2.6
Temp (deg C)
Input Power (dBm)
Carrier to Interferer
(Narrow band, LP modulation)
-81
Receiver Sensitivity (dBm)
-82
-84
GFSK
-86
-88
-90
-92
-94
8DR64
10.0
0.0
-85
CER
-87
-89
-50
0
50
100
Crystal Offset (ppm)
150
-20.0
-30.0
-50.0
8DR32
-60.0
-10
-95
-100
-10.0
-40.0
-91
-93
-96
20.0
GFSK
-83
C/I (dB)
RSSI Count
PA5
-6
-12
18
Receiver Sensitivity (dBm)
-4
Average RSSI vs. Temperature
(Rx signal = -70dBm)
32
-98
-150
PA6
0
-2
Vcc
Typical RSSI Count vs Input Power
8
2
-14
Temp (deg C)
16
PA7
4
PA7
4
Output Power (dBm)
2
Output Power (dBm)
6
PA7
4
0
10
20
30
40
50
60
70
80
-5
0
5
10
Channel Offset (MHz)
Channel
Note
20. With LNA on, ATT off, above -2dBm erroneous RSSI values may be read. Cross-checking RSSI with LNA off/on is recommended for accurate readings.
Document #: 001-48013 Rev. **
Page 17 of 21
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CYRF7936
Typical Operating Characteristics (continued)
GFSK vs. BER
(SOP Threshold = 5, C38 slow)
BER vs. Data Threshold (32-8DR)
(SOP Threshold = 5, C38 slow)
10
100
0 Thru 7
10
1
1
0.1
%BER
0.01
0.01
0.001
0.001
0.0001
0.0001
0.00001
-100
-95
-90
-85
-80
-75
GFSK
0.00001
-100
-70
Input Power (dBm)
-80
-60
-40
-20
0
Input Power (dBm)
ICC RX
(LNA ON)
ICC RX
(LNA OFF)
ICC RX SYNTH
25
21
19.5
19
18.5
18
17.5
3.3V
3.0V
2.7V
2.4V
24
23.5
23
22.5
22
21.5
21
20.5
20
19.5
19
17
0
5
0
10 15 20 25 30 35 40 45 50 55 60 65 70
5
10 15 20 25 30 35 40 45 50 55 60 65 70
5
16
15.5
15
14.5
OPERATING CURRENT (mA)
17.5
3.3V
3.0V
2.7V
2.4V
16.5
10 15 20 25 30 35 40 45 50 55 60 65 70
16.5
16
15.5
15
14.5
5
0
10 15 20 25 30 35 40 45 50 55 60 65 70
ICC TX @ PA4
20.5
16
15.5
OPERATING CURRENT (mA)
19
16.5
3.3V
3.0V
2.7V
2.4V
18.5
18
17.5
17
16.5
16
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
Document #: 001-48013 Rev. **
3.3V
3.0V
2.7V
2.4V
20
19.5
19
18.5
18
17.5
17
15.5
15
10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
ICC TX @ PA3
18
17
5
TEMPERATURE (C)
ICC TX @ PA2
3.3V
3.0V
2.7V
2.4V
3.3V
3.0V
2.7V
2.4V
17
14
0
TEMPERATURE (C)
17.5
10 15 20 25 30 35 40 45 50 55 60 65 70
ICC TX @ PA1
14
0
5
TEMPERATURE (C)
17
3.3V
3.0V
2.7V
2.4V
OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
0
ICC TX @ PA0
ICC TX SYNTH
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
7.9
7.8
3.3V
3.0V
2.7V
2.4V
TEMPERATURE (C)
TEMPERATURE (C)
OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
3.3V
3.0V
2.7V
2.4V
20
OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
24.5
20.5
9.2
9.1
9
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8
7.9
7.8
OPERATING CURRENT (mA)
%BER
0.1
16.5
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
Page 18 of 21
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CYRF7936
Typical Operating Characteristics (continued)
ICC TX @ PA5
29.5
3.3V
3.0V
2.7V
2.4V
22.5
22
21.5
21
20.5
20
3.3V
3.0V
2.7V
2.4V
29
28.5
28
OPERATING CURRENT (mA)
23
OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
ICC TX @ PA7
ICC TX @ PA6
30
23.5
27.5
27
26.5
26
25.5
25
19.5
24.5
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
0
40.5
40
39.5
39
38.5
38
37.5
37
36.5
36
35.5
35
34.5
34
33.5
33
32.5
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
3.3V
3.0V
2.7V
2.4V
5 10 15 20 25 30 35 40 45 50 55 60 65 70
TEMPERATURE (C)
TEMPERATURE (C)
AC Test Loads and Waveforms for Digital Pins
Figure 12. AC Test Loads and Waveforms for Digital Pins
AC Test Loads
DC Test Load
OUTPUT
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
VCC
5 pF
R1
OUTPUT
INCLUDING
JIG AND
Typical
SCOPE
Max
R2
ALL INPUT PULSES
Parameter
R1
R2
RTH
VTH
VCC
1071
937
500
1.4
3.00
Unit
Ω
Ω
Ω
V
V
VCC
GND
90%
10%
OUTPUT
10%
Fall time: 1 V/ns
Rise time: 1 V/ns
Equivalent to:
90%
THÉVENIN EQUIVALENT
RTH
VTH
Ordering Information
Table 8. Ordering Information
Part Number
CYRF7936-40LFXC
Radio
Transceiver
Document #: 001-48013 Rev. **
Package Name
Package Type
40 QFN
40 Quad Flat Package No Leads Pb-Free
CYRF7936
Operating Range
Commercial
Page 19 of 21
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CYRF7936
Package Description
Figure 13. 40-Pin Pb-Free QFN 6 x 6 mm LY40
SOLDERABLE
EXPOSED
PAD
NOTES:
1.
HATCH IS SOLDERABLE EXPOSED AREA
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.086g
4. ALL DIMENSIONS ARE IN MM [MIN/MAX]
(SUBCON Punch Type PKG WITH 3.50X3.50 EPAD)
5. PACKAGE CODE
UNLESS OTHERWISE SPECIFIED
PART #
DESCRIPTION
LF40A
LY40A
STANDARD
PB-FREE
ALL DIMENSIONS ARE IN INCHES [MILLIMETERS]
STANDARD TOLERANCES ON:
DECIMALS
ANGLES
.XX
-+
-+
.XXX -+
.XXXX +
-
DESIGNED BY
DRAWN
CHK BY
DATE
MLA
DATE
CYPRESS
COMPANY CONFIDENTIAL
07/10/08
DATE
TITLE
APPROVED BY
DATE
APPROVED BY
DATE
MATERIAL
SIZE
40LD QFN 6 X 6MM PACKAGE OUTLINE
(SUBCON PUNCH TYPE PKG with 3.50 X 3.50 EPAD)
PART NO.
SEE NOTES
DWG NO
001-12917 *AREV
001-12917
*A
The recommended dimension of the PCB pad size for the E-PAD underneath the QFN is 3.5 mm × 3.5 mm (width x length).
Document #: 001-48013 Rev. **
Page 20 of 21
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CYRF7936
Document History Page
Description Title: CYRF7936 2.4 GHz CyFi™ Transceiver
Document #: 001-48013 Rev. **
REV.
ECN
Orig. of
Change
Submission
Date
**
2557501
KKU/AESA
09/10/08
Description of Change
New Data Sheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
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psoc.cypress.com
clocks.cypress.com
General
Low Power/Low Voltage
psoc.cypress.com/solutions
psoc.cypress.com/low-power
Wireless
wireless.cypress.com
Precision Analog
Memories
memory.cypress.com
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psoc.cypress.com/lcd-drive
image.cypress.com
CAN 2.0b
psoc.cypress.com/can
USB
psoc.cypress.com/usb
Image Sensors
psoc.cypress.com/precision-analog
© Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-48013 Rev. **
Revised September 10, 2008
Page 21 of 21
CyFi, WirelessUSB, PSoC, and enCoRe are trademarks of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
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