50 CY7C150 1Kx4 Static RAM Features Separate I/O paths eliminates the need to multiplex data in and data out, providing for simpler board layout and faster system performance. Outputs are three-stated during write, reset, deselect, or when output enable (OE) is held HIGH, allowing for easy memory expansion. • Memory reset function • 1024 x 4 static RAM for control store in high-speed computers • CMOS for optimum speed/power • High speed — 10 ns (commercial) Reset is initiated by selecting the device (CS = LOW) and taking the reset (RS) input LOW. Within two memory cycles all bits are internally cleared to zero. Since chip select must be LOW for the device to be reset, a global reset signal can be employed, with only selected devices being cleared at any given time. — 12 ns (military) • Low power — 495 mW (commercial) • • • • Writing to the device is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the four data inputs (D0−D3) is written into the memory location specified on the address pins (A0 through A9). — 550 mW (military) Separate inputs and outputs 5-volt power supply ±10% tolerance in both commercial and military Capable of withstanding greater than 2001V static discharge TTL-compatible inputs and outputs Reading the device is accomplished by taking chip select (CS) and output enable (OE) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the four output pins (O0 through O3). Functional Description The output pins remain in high-impedance state when chip enable (CE) or output enable (OE) is HIGH, or write enable (WE) or reset (RS) is LOW. The CY7C150 is a high-performance CMOS static RAM designed for use in cache memory, high-speed graphics, and data-acquisition applications. The CY7C150 has a memory reset feature that allows the entire memory to be reset in two memory cycles. A die coat is used to insure alpha immunity. Logic Block Diagram Pin Configuration RS D0 D1 D2 D3 64 x 64 ARRA Y Top View A3 A4 A5 A6 A7 A8 A9 D0 D1 O0 O1 GND WE SENSE AMPS ROW DECODER DATAINPUT CONTROL A0 A1 A2 A3 A4 A5 DIP/SOIC CS OE O0 O1 O2 O3 1 2 3 4 5 24 23 22 21 20 6 7C150 19 18 7 8 17 9 16 10 15 14 11 13 12 VCC A2 A1 A0 RS CS WE OE D3 D2 O3 O2 COLUMN COLUMN DECODER DECODER A6 C150-2 C150–1 A7 A8 A9 Selection Guide Maximum Access Time (ns) Commercial 7C150−10 7C150−12 7C150−15 7C150−25 10 12 15 25 12 15 25 35 90 90 90 90 100 100 100 100 Military Maximum Operating Current (mA) Commercial 90 Military Cypress Semiconductor Corporation Document #: 38-05024 Rev. ** • 3901 North First Street • San Jose • 7C150−35 CA 95134 • 408-943-2600 Revised August 24, 2001 CY7C150 Maximum Ratings Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current.................................................... >200 mA Storage Temperature ......................................−65°C to+150°C Operating Range Ambient Temperature with Power Applied................................................... −55°C to+125°C Supply Voltage to Ground Potential (Pin 24 to Pin 12)..................................................−0.5V to+7.0V Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% −55°C to +125°C 5V ± 10% [1] Military DC Voltage Applied to Outputs in High Z State ......................................................−0.5V to+7.0V Note: 1. TA is the “instant on” case temperature. DC Input Voltage .................................................−3.0V to +7.0V Output Current into Outputs (LOW) .............................20 mA Electrical Characteristics Over the Operating Range[2] 7C150 Parameter Description Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = − 0.4 mA VOL Output LOW Current VCC = Min., IOL = 12 mA VIH Input HIGH Level VIL Input LOW Level −3.0 0.8 V IIX Input Load Current GND < VI < VCC −10 +10 µA IOZ Output Current (High Z) VOL < VOUT < VOH, Output Disabled −50 +50 µA IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA 2.4 2.0 V 0.4 V VCC V −300 mA Commercial 90 mA Military 100 mA Notes: 2. See the last page of this specification for Group A subgroup testing information. 3. Not more than 1 output should be shorted at a time. Duration of the short circuit should not exceed 30 seconds. Capacitance[4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 10 pF 10 pF Note: 4. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms R1329 Ω R1329 Ω 5V OUTPUT 5V OUTPUT R2 202Ω 30 pF INCLUDING JIG AND SCOPE Equivalent to: ALL INPUT PULSES INCLUDING JIG AND SCOPE (a) R2 202Ω 5 pF 3.0V 10% C150–3 90% 10% GND < 3 ns (b) 90% < 3 ns C150–4 THÉVENIN EQUIVALENT OUTPUT Document #: 38-05024 Rev. ** 125Ω 1.9V Page 2 of 11 CY7C150 Switching Characteristics Over the Operating Range[2,5] Parameter Description 7C150−10 7C150−12 7C150−15 7C150−25 7C150−35 Min. Min. Min. Min. Min. Max. Max. Max. Max. Max. Unit READ CYCLE tRC Read Cycle Time 10 tAA Address to Data Valid tOHA Output Hold from Address Change tACS CS LOW to Data Valid tLZCS CS LOW to Low Z[6] 12 10 2 15 12 2 8 0 25 15 2 10 0 35 25 2 12 0 ns 35 2 15 0 ns ns 20 0 ns ns tHZCS CS HIGH to High Z [6,7] 6 8 11 20 25 ns tDOE OE LOW to Data Valid 6 8 10 15 20 ns [6] tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[6,7] WRITE CYCLE 0 Write Cycle Time 10 tSCS CS LOW to Write End 6 tAW Address Set-Up to Write End 8 tHA Address Hold from Write End 2 tSA Address Set-Up to Write Start tPWE tSD tHD tHZWE 0 8 0 9 0 20 ns 25 ns [8] tWC tLZWE 0 6 15 25 35 ns 8 11 15 20 ns 10 13 20 30 ns 2 2 5 5 ns 2 2 2 5 5 ns WE Pulse Width 6 8 11 15 20 ns Data Set-Up to Write End 6 8 11 15 20 ns Data Hold from Write End 2 2 2 5 5 ns 0 0 0 0 0 ns [6] WE HIGH to Low Z WE LOW to High Z [6,7] 12 6 8 12 20 25 ns RESET CYCLE tRRC Reset Cycle Time 20 24 30 50 70 ns tSAR Address Valid to Beginning of Reset 0 0 0 0 0 ns tSWER Write Enable HIGH to Beginning of Reset 0 0 0 0 0 ns tSCSR Chip Select LOW to Beginning of Reset 0 0 0 0 0 ns tPRS Reset Pulse Width 10 12 15 20 30 ns tHCSR Chip Select Hold After End of Reset 0 0 0 0 0 ns tHWER Write Enable Hold After End of Reset 8 12 15 30 40 ns tHAR Address Hold After End of Reset 10 12 15 30 40 ns tLZRS Reset HIGH to Output in Low Z tHZRS Reset LOW to Output in High Z[6,7] [6] 0 0 6 0 8 0 12 0 20 ns 25 ns Notes: 5. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZ is less than tLZ for any given device. 7. tHZCS, tHZOE, tHZR, and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be reference to the rising edge of the signal that terminates the write. Document #: 38-05024 Rev. ** Page 3 of 11 CY7C150 Switching Waveforms Read Cycle No.1 [9,10] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID C150-5 Read Cycle No. 2 [9,11] tRC CE tACS OE DATA OUT tHZOE tHZCS tDOE tLZOE HIGH IMPEDANCE DATA VALID HIGH IMPEDANCE tLZCS C150-6 Write CycleNo.1 (WE Controlled) [8] tWC ADDRESS tSCS CE tSA tAW tHA tPWE WE tSD DATA IN VALID DATA IN tHZWE DATA I/O tHD DATA UNDEFINED tLZWE HIGH IMPEDANCE C150-7 Notes: 9. WE is HIGH for read cycle. 10. Device is continuously selected, CS and OE = VIL. 11. Address prior to or coincident with CS transition LOW. Document #: 38-05024 Rev. ** Page 4 of 11 CY7C150 Switching Waveforms (continued) Write Cycle No.2 (CS Controlled) [8,12] tWC ADDRESS tSA tSCS CE tAW tHA tPWE WE tHD tSD DATA IN VALID DATA IN tHZWE HIGH IMPEDANCE DATA I/O DATA UNDEFINED C150-8 Reset Cycle [13] tRRC ADDRESS tSAR WE tSWER CS tSCSR tHAR tHWER tHCSR tPRS RESET tLZRS tHZRS DATA I/O HIGH IMPEDANCE OUTPUT VALID ZERO C150-9 Notes: 12. If CS goes HIGH with WE HIGH, the output remains in a high-impedance state. 13. Reset cycle is defined by the overlap of RS and CS for the minimum reset pulse width. Document #: 38-05024 Rev. ** Page 5 of 11 CY7C150 NORMALIZED SUPPLY CURRENT vs.AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs.SUPPLY VOLTAGE SB 1.2 1.2 ICC 0.8 0.6 0.4 4.5 5.0 0.8 0.6 0.4 VCC =5.0V VIN =5.0V 5.5 ISB 0.0 −55 6.0 NORMALIZED ACCESS TIME vs.AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs.SUPPLY VOLTAGE 1.4 1.6 1.3 1.4 NORMALIZED t AA NORMALIZED t AA 125 1.2 1.1 TA =25°C 1.0 1.2 1.0 VCC =5.0V 0.8 0.9 0.8 4.0 4.5 5.0 5.5 0.6 −55 6.0 TYPICAL POWER–ONCURRENT vs.SUPPLYVOLTAGE 25 DELTA tAA (ns) 2.0 1.5 1.0 20 10 VCC =4.5V TA =25°C 0.5 3.0 4.0 SUPPLY VOLTAGE(V) Document #: 38-05024 Rev. ** 40 VCC =5.0V TA =25°C 30 20 10 0 0.0 5.0 0 0 200 400 600 800 1000 CAPACITANCE (pF) 1.0 2.0 3.0 4.0 OUTPUT SINK CURRENT vs.OUTPUT VOLTAGE 150 125 VCC =5.0V TA =25°C 100 75 50 25 0 0.0 125 2.5 2.0 50 OUTPUT VOLTAGE(V) 1.0 2.0 3.0 4.0 5.0 OUTPUT VOLTAGE(V) TYPICAL ACCESS TIME CHANGE vs.OUTPUT LOADING 30 3.0 1.0 60 AMBIENT TEMPERATURE(°C) SUPPLY VOLTAGE(V) 0.0 0.0 OUTPUT SOURCE CURRENT vs.OUTPUT VOLTAGE AMBIENT TEMPERATURE(°C) SUPPLY VOLTAGE(V) NORMALIZED I PO 25 OUTPUT SINK CURRENT (mA) 0.0 4.0 ICC 0.2 ISB 0.2 1.0 NORMALIZED I CC vs.CYCLE TIME 1.1 NORMALIZED ICC 1.0 NORMALIZED I,CC I NORMALIZED I,CC I SB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics VCC =5.0V TA =25°C VCC =0.5V 1.0 0.9 0.8 10 20 30 40 CYCLE FREQUENCY (MHz) Page 6 of 11 CY7C150 Truth Table Inputs CS WE OE RS H X X X High Z Outputs Not Selected Mode L H X L High Z Reset L L X H High Z Write L H L H O0−O3 Read L X H H High Z Output Disable Ordering Information Speed (ns) 10 12 15 Ordering Code CY7C150−10PC 35 Package Type Operating Range P13A 24-Lead (300-Mil) Molded DIP Commercial CY7C150−10SC S13 CY7C150−12PC P13A 24-Lead Molded SOIC 24-Lead (300-Mil) Molded DIP Commercial CY7C150−12SC S13 24-Lead Molded SOIC CY7C150−12DMB D14 24-Lead (300-Mil) CerDIP Military 24-Lead (300-Mil) Molded DIP Commercial CY7C150−15PC P13A CY7C150−15SC S13 24-Lead Molded SOIC D14 24-Lead (300-Mil) CerDIP Military 24-Lead (300-Mil) Molded DIP Commercial CY7C150−15DMB 25 Package Name CY7C150−25PC P13A CY7C150−25SC S13 24-Lead Molded SOIC CY7C150−25DMB D14 24-Lead (300-Mil) CerDIP Military CY7C150−35DMB D14 24-Lead (300-Mil) CerDIP Military Document #: 38-05024 Rev. ** Page 7 of 11 CY7C150 MILITARY SPECIFICATIONS Group A Subgroup Testing Switching Characteristics Parameter DC Characteristics Parameter Subgroups Subgroups READ CYCLE tRC 7, 8, 9, 10, 11 VOH 1, 2, 3 tAA 7, 8, 9, 10, 11 VOL 1, 2, 3 tOHA 7, 8, 9, 10, 11 VIH 1, 2, 3 tACS 7, 8, 9, 10, 11 VIL Max. 1, 2, 3 IIX 1, 2, 3 tWC 7, 8, 9, 10, 11 IOZ 1, 2, 3 tSCS 7, 8, 9, 10, 11 ICC 1, 2, 3 tAW 7, 8, 9, 10, 11 tHA 7, 8, 9, 10, 11 tSA 7, 8, 9, 10, 11 tPWE 7, 8, 9, 10, 11 tSD 7, 8, 9, 10, 11 tHD 7, 8, 9, 10, 11 WRITE CYCLE RESET CYCLE Document #: 38-05024 Rev. ** tRRC 7, 8, 9, 10, 11 tSAR 7, 8, 9, 10, 11 tSWER 7, 8, 9, 10, 11 tSCSR 7, 8, 9, 10, 11 tPRS 7, 8, 9, 10, 11 tHCSR 7, 8, 9, 10, 11 tHWER 7, 8, 9, 10, 11 tHAR 7, 8, 9, 10, 11 Page 8 of 11 CY7C150 Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9Config.A 24-Lead (300-Mil) Molded DIP P13/P13A Document #: 38-05024 Rev. ** Page 9 of 11 CY7C150 Package Diagrams (continued) 24-Lead Molded SOIC S13 Document #: 38-05024 Rev. ** Page 10 of 11 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C150 Document Title: Cy7C150 1K x4 Static RAM Document Number: 38-05024 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106810 09/10/01 SZV Change from Spec number: 38-00028 to 38-05024 Document #: 38-05024 Rev. ** Page 11 of 11