ONSEMI NCP1523

NCP1523
3 MHz, 600 mA,
High−Efficiency, Adjustable
Output Voltage Stepdown
Converter
The NCP1523 stepdown PWM DC−DC converter is optimized for
portable applications powered from 1−cell Li−ion or 3−cell
Alkaline/NiCd/NiMH batteries. The device is available in an
adjustable output voltage from 0.9 V to 2.3 V. It uses synchronous
rectification to increase efficiency and reduce external part count. The
device also has a built−in 3 MHz (nominal) oscillator which reduces
component size by allowing a small inductor and capacitors.
Automatic switching PWM/PFM mode offers improved system
efficiency.
Finally, it includes an integrated soft−start, cycle−by−cycle current
limiting, and thermal shutdown protection. The NCP1523 is available
in a space saving, 8 pin chip scale package.
http://onsemi.com
MARKING
DIAGRAM
FLIP−CHIP−8
CASE 766AE
A
Y
WW
G
Features
•
•
•
•
•
•
•
•
•
•
Up to 93% Efficiency
Sources up to 600 mA
3 MHz Switching Frequency
Adjustable Output Voltage from 0.9 V to 2.3 V
60 mA Quiescent Current
Synchronous Rectification for Higher Efficiency.
2.7 V to 5.5 V Input Voltage Range
Thermal Limit Protection
Shutdown Current Consumption of 0.3 mA
This is a Pb−Free Device*
•
•
•
•
•
Cellular Phones, Smart Phones and PDAs
Digital Still Cameras
MP3 Players and Portable Audio Systems
Wireless and DSL Modems
Portable Equipment
A2
CIN
C1
A1
VIN
GND
GND
A1
= Assembly Location
= Year
= Work Week
= Pb−Free Package
A1
A2
B1
B2
C1
C3
D1
D2
PIN:
A1 − GND
A2 − VIN
B1 − SW
B2 − EN
C1 − GND
C2 − ADJ
D1 − VOUT
D2 − FB
Top View
(Bumps Below)
Typical Applications
VIN
NCP1523G
AYWW
A1
ORDERING INFORMATION
Device
Package
NCP1523FCT2G FLIP−CHIP−8
(Pb−Free)
3000 /
Tape * Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
VOUT Brochure, BRD8011/D.
L
SW B1
Shipping†
COUT
VOUT D1
ADJ C2
R1
OFF
ON
B2
EN
FB
D2
R2
Figure 1. NCP1523 Typical Applications
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 0
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
1
Publication Order Number:
NCP1523/D
NCP1523
100
EFFICIENCY (%)
90
VIN = 2.7 V
80
VIN = 4.2 V
70
VIN = 3.6 V
60
50
40
30
1
10
100
IOUT, OUTPUT CURRENT (mA)
1000
Figure 2. Efficiency vs. Output Current
(VOUT = 2.0 V, Temperature = 25°C)
TYPICAL APPLICATIONS
SW
VIN
VBATTERY
A2
B1
Q1
2.2 mH
Q2
4.7 mF
4.7 mF
PWM/PFM
Control
VOUT
GND
C1
D1
ILIMIT
Comp
GND
A1
ADJ
C2
R1
Reference Voltage
Enable
EN
B2
Logic Control &
Thermal Shutdown
FB
D2
R2
Figure 3. Simplified Block Diagram
http://onsemi.com
2
NCP1523
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Type
A1
GND
Power Ground
Description
B2
VIN
Power Input
B1
SW
Analog Output
B2
EN
Digital Input
C1
GND
Power Ground
C2
ADJ
Analog Input
This pin is the compensation input. R1 is connected to this pin.
D1
VOUT
Analog Input
This pin is connected of the converter’s output. This is the sense of the output voltage.
D2
FB
Analog Input
Feedback voltage from the output of the power supply. This is the input to the error
amplifier.
Ground connection for the NFET Power Stage and the analog sections.
Power Supply Input for the PFET Power stage and the Analog Sections of the IC.
Connection from Power MOSFETs to the Inductor.
Enable for Switching Regulator. This pin is active high. This pin contains an internal
pulldown resistor.
Ground connection for the NFET Power Stage and the analog sections.
MAXIMUM RATINGS
Rating
Minimum Voltage All Pins
Symbol
Value
Unit
VMIN
−0.3
V
VMAX
7
V
VMAX
VIN + 0.3
V
Thermal Resistance, Junction−to−Air (Note 2)
RJA
159
°C/W
Operating Ambient Temperature Range
TA
−40 to 85
°C
TSTG
−55 to 150
°C
Junction Operating Temperature
TJ
−40 to 125
°C
Latchup Current maximum Rating TA = 85°C (Note 4)
LU
"100
mA
2.0
200
kV
V
Maximum Voltage All Pins (Note 1)
Maximum Voltage Enable, FB, SW
Storage Temperature Range
ESD Withstand Voltage (Note 3)
Human Body Model
Machine Model
VESD
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. According to JEDEC standard JESD22−A108B
2. For the 8−Pin Chip scale package, the RJA is highly dependent of the PCB heatsink area. RJA = 159°C/W with 50 mm2 PCB heatsink area.
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) $2.0 kV per JEDEC standard: JESD22−A114
Machine Model (MM) $200 V per JEDEC standard: JESD22−A115
4. Latchup current maximum rating per JEDEC standard: JESD78.
http://onsemi.com
3
NCP1523
ELECTRICAL CHARACTERISTICS
(Typical values are referenced to TA = +25°C, Minimum and Maximum values are referenced −40°C to +85°C ambient temperature,
unless otherwise noted, operating conditions VIN = 3.6 V, VOUT = 1.8 V unless otherwise noted)
Rating
Symbol
Min
Typ
Unit
5.5
V
Input Voltage Range
VUVLO
Under voltage Lockout (VIN Falling)
2.4
Iq
Quiescent Current
PFM no load
60
95
ISTB
Standby Current, EN Low
0.3
1.2
mA
FOSC
Oscillator Frequency
3
3.600
MHz
ILIM
Peak Inductor Current
VREF
Feedback Reference Voltage
VFBtol
FB Pin Tolerance Overtemperature
DVFB
Reference Voltage Line Regulation
VOUT
Output Voltage Accuracy (Note 5)
VOUT
Minimum Output Voltage
0.9
V
VOUT
Maximum Output Voltage
2.3
V
DVOUT
Output Voltage Line Regulation (VIN = 2.7 – 5.5)
IO = 100 mA
0.1
%
VLOA-
Voltage Load Regulation
(IO = 150 mA to 300 mA)
(IO = 150 mA to 600 mA)
0.0005
0.001
%/mA
%/mA
DREG
2.7
Max
VIN
2.400
V
1200
mA
0.6
V
−3
3
0.1
−3%
mA
Vnom
Duty Cycle
%
%
+3%
100
V
%
RSWH
P−Channel On−Resistance
300
mW
RSWL
N−Channel On−Resistance
300
mW
ILeakH
P−Channel Leakage Current
0.05
mA
ILeakL
N−Channel Leakage Current
0.01
mA
VENH
Enable Pin High
VENL
Enable Pin Low
TSTART
Soft−Start Time
1.2
V
350
5. The overall output voltage tolerance depends upon the accuracy of the external resistor (R1, R2).
http://onsemi.com
4
0.4
V
450
ms
100
100
90
90
IQ, QUIESCENT CURRENT (mA)
IQ, QUIESCENT CURRENT (mA)
NCP1523
80
70
60
50
40
30
20
EN = VIN
IOUT = 0 mA
10
0
2.5
3.0
3.5
4.0
4.5
5.0
80
70
60
50
VIN = 5.5 V
40
30
20
10
0
−40
5.5
10
VIN, INPUT VOLTAGE (V)
100
−40°C
90
0.8
0.7
EFFICIENCY (%)
SHUTDOWN CURRENT (mA)
0.9
0.6
0.5
0.4
0.3
0.2
3.0
3.5
4.0
4.5
5.0
80
105°C
70
25°C
60
50
40
EN = GND
IOUT = 0 mA
0.1
30
5.5
1
10
100
1000
VIN, INPUT VOLTAGE (V)
IOUT, OUTPUT CURRENT (mA)
Figure 6. Shutdown Current vs. Supply
Voltage
Figure 7. Efficiency vs. Output Current
(VOUT = 1.8 V, VIN = 3.6 V)
100
100
90
90
−40°C
80
70
EFFICIENCY (%)
EFFICIENCY (%)
110
Figure 5. Quiescent Current vs. Temperature
1.0
25°C
60
105°C
50
−40°C
80
25°C
70
105°C
60
50
40
40
30
1
60
TEMPERATURE (°C)
Figure 4. Quiescent Current vs. Supply
Voltage
0
2.5
VIN = 2.7 V
10
100
1000
30
1
10
100
IOUT, OUTPUT CURRENT (mA)
IOUT, OUTPUT CURRENT (mA)
Figure 8. Efficiency vs. Output Current
(VOUT = 0.9 V, VIN = 3.6 V)
Figure 9. Efficiency vs. Output Current
VOUT = 2.0 V, VIN = 3.6 V)
http://onsemi.com
5
1000
3.6
3.6
3.4
3.4
FREQUENCY (MHz)
FREQUENCY (MHz)
NCP1523
IOUT = 400 mA
3.2
IOUT = 600 mA
3.0
2.8
IOUT = 400 mA
3.2
3.0
2.8
2.6
2.6
2.4
2.8
3.3
3.8
4.3
VIN, INPUT VOLTAGE (V)
4.8
2.4
−40
5.3
Figure 10. Frequency vs. Input Voltage
−20
0
20
40
TEMPERATURE (°C)
60
80
Figure 11. Frequency vs. Temperature
300
3.0
IOUT, OUTPUT CURRENT (mA)
5.0
LOAD REGULATION (%)
IOUT = 600 mA
VOUT = 0.9 V
1.0
−1.0
VOUT = 2.0 V
−3.0
−5.0
0
100
200
300
400
500
VOUT, OUTPUT VOLTAGE (V)
250
200
150
100
50
0
2.7
600
Figure 12. Load Regulation
3.2
3.7
4.2
VIN, INPUT VOLTAGE (V)
4.7
Figure 13. PFM/PWM Threshold vs. Input
Voltage
Figure 14. Stepdown Converter PFM Mode
Operation
Figure 15. Stepdown Converter PWM Mode
Operation
http://onsemi.com
6
5.2
NCP1523
Figure 16. Load Transient Response in PFM
Operation (10 mA to 100 mA)
Figure 17. Load Transient Response Between
PFM and PWM Operation (100 mA to 200 mA)
Figure 18. Soft−Start Time (VIN = 3.6 V)
http://onsemi.com
7
NCP1523
OPERATION DESCRIPTION
Overview
Q1 remains ON until the peak inductor current reaches
200 mA (nom). Then ILIM comparator goes high to switch
off Q1. After a short dead time delay, switch rectifier Q2 is
turn ON. The Negative current detector (NCD) will detect
when the inductor current drops below zero and send the
signal to turn off Q2. The output voltage continues to
decrease through discharging the output capacitor. When the
output voltage falls below the threshold of the PFM
comparator, a new cycle starts immediately.
The NCP1523 uses a constant frequency, voltage mode
stepdown architecture. Both the main (P−Channel
MOSFET) and synchronous (N−Channel MOSFET)
switches are internal.
It delivers a constant voltage from either a single Li−Ion
or three cell NiMH/NiCd battery to portable devices such as
cell phones and PDA. The output voltage is sets by external
resistor divider. The NCP1523 sources up to 600 mA
depending on external components chosen.
The NCP1523 works with two mode of operation
PWM/PFM depending on the current required. The device
operates in PWM mode at load currents of approximately
130 mA or higher, having voltage tolerance of ±3% with
90% efficiency or better. Lighter load currents cause the
device to automatically switch into PFM mode for reduced
current consumption (IQ = 60 mA typ) and a longer battery
life.
Additional features include soft−start, under voltage
protection, current overload protection, and thermal
shutdown protection. As shown in Figure 1, only six
external components are required for implementation. The
part uses an internal reference voltage of 0.6 V. It is
recommended to keep the part in shutdown until the input
voltage is 2.7 V or higher.
Cycle−by−Cycle Current Limitation
From the block diagram (Figure 3), an ILIM comparator is
used to realize cycle−by−cycle current limit protection. The
comparator compares the SW pin voltage with the reference
voltage, which is biased by a constant current. If the inductor
current reaches the limit, the ILIM comparator detects the
SW voltage falling below the reference voltage and releases
the signal to turn off the switch Q1. The cycle−by−cycle
current limit is set at 1200 mA (nom).
Soft−Start
The NCP1523 uses soft−start to limit the inrush current
when the device is initially powered up or enabled.
Soft−start is implemented by gradually increasing the
reference voltage until it reaches the full reference voltage.
During startup, a pulsed current source charges the internal
soft−start capacitor to provide gradually increasing
reference voltage. When the voltage across the capacitor
ramps up to the nominal reference voltage, the pulsed
current source will be switched off and the reference voltage
will switch to the regular reference voltage.
PWM Operating Mode
In this mode, the output voltage of the NCP1523 is
regulated by modulating the on−time pulse width of the
main switch Q1 at a fixed frequency of 3 MHz. The
switching of the PMOS Q1 is controlled by a flip−flop
driven by the internal oscillator and a comparator that
compares the error signal from an error amplifier with the
PWM ramp. At the beginning of each cycle, the main switch
Q1 is turned ON by the rising edge of the internal oscillator
clock. The inductor current ramps up until the sum of the
current sense signal and compensation ramp becomes higher
than the error voltage amplifier. Once this has occurred, the
PWM comparator resets the flip−flop, Q1 is turned OFF and
the synchronous switch Q2 is turned ON. Q2 replaces the
external Schottky diode to reduce the conduction loss and
improve the efficiency. To avoid overall power loss, a
certain amount of dead time is introduced to ensure Q1 is
completely turned OFF before Q2 is being turned ON.
Shutdown Mode
When the EN pin has a voltage applied of less than 0.4 V,
the NCP1523 will be disabled. In shutdown mode, the
internal reference, oscillator and most of the control
circuitries are turned off. Therefore, the typical current
consumption will be 0.3 mA (typical value). Applying a
voltage above 1.2 V to EN pin will enable the device for
normal operation. The device will go through soft−start to
normal operation. EN pin should be activated after the input
voltage is applied.
Thermal Shutdown
circuitry is provided to protect the integrated circuit in the
event that the maximum junction Temperature is exceeded.
If the junction temperature exceeds 160°C, the device shuts
down. In this mode switch Q1 and Q2 and the control circuits
are all turned off. The device restarts in soft start after the
temperature drops below 135°C. This feature is provided to
prevent catastrophic failures from accidental device
overheating and it is not intended as a substitute for proper
heatsinking.
PFM Operating Mode
Under light load conditions, The NCP1523 enters in low
current PFM mode operation to reduce power consumption.
The output regulation is implemented by pulse frequency
modulation. If the output voltage drops below the threshold
of PM comparator (typically Vnom − 2%), a new cycle will
be initiated by the PM comparator to turn on the switch Q1.
http://onsemi.com
8
NCP1523
APPLICATION INFORMATION
Output Voltage Selection
The device operates with inductance value between 1 mH
and maximum of 4.7 mH.
If the corner frequency is moved, it is recommended to
check the loop stability depending of the output ripple
voltage accepted and output current required. For lower
frequency, the stability will be increase; a larger output
capacitor value could be chosen without critical effect on the
system. On the other hand, a smaller capacitor value
increases the corner frequency and it should be critical for
the system stability. Take care to check the loop stability.
The phase margin is usually higher than 45°.
The output voltage is programmed through an external
resistor divider connected from ADJ to FB then to GND. For
low power consumption and noise immunity, the resistor
from FB to GND (R2) should be in the [100 kW − 600 kW]
range. If R2 is 200 kW given the VFB is 0.6 V, the current
through the divider will be 3 mA.
The formula below gives the value of VOUT, given the
desired R1 and the R1 value,
VOUT + VFB
•
•
•
•
ǒ1 ) R1Ǔ
(eq. 1)
R2
VOUT: output voltage (volts)
VFB: feedback voltage = 0.6 V
R1: feedback resistor from VOUT to FB
R2: feedback resistor from FB to GND
Table 2. L−C FILTER EXAMPLE
Inductance (L)
Input Capacitor Selection
In PWM operating mode, the input current is pulsating
with large switching noise. Using an input bypass capacitor
can reduce the peak current transients drawn from the input
supply source, thereby reducing switching noise
significantly. The capacitance needed for the input bypass
capacitor depends on the source impedance of the input
supply.
The maximum RMS current occurs at 50% duty cycle
with maximum output current, which is IO, max/2.
For NCP1523, a low profile ceramic capacitor of 4.7 mF
should be used for most of the cases. For effective bypass
results, the input capacitor should be placed as close as
possible to the VIN Pin.
The NCP1523 is built in 3 MHz frequency and uses
voltage mode architecture. The correct selection of the
output filter ensures good stability and fast transient
response.
Due to the nature of the buck converter, the output
L−C filter must be selected to work with internal
compensation. For NCP1523, the internal compensation is
internally fixed and it is optimized for an output filter of L
= 2.2 mH and COUT = 4.7 mF
The corner frequency is given by:
Cout
+
1
2p Ǹ2.2 mH
4.7 mF
L
fSW
ǒ1 * VVOUTǓ
IN
(eq. 3)
DIL
2
(eq. 4)
IL(MAX) Maximum Inductor Current
IO(MAX) Maximum Output Current
The inductor’s resistance will factor into the overall
efficiency of the converter. For best performances, the DC
resistance should be less than 0.3 W for good efficiency.
JMK212BY475MG
C2012X5ROJ475KB
1
VOUT
IL(MAX) + IO(MAX) )
Output L−C Filter Design Considerations:
2p ǸL
2.2 mF
DIL peak to peak inductor ripple current
L inductor value
fSW Switching frequency
The Saturation current of the inductor should be rated
higher than the maximum load current plus half the ripple
current:
C1632X5ROJ475KT
fc +
4.7 mH
DIL +
GRM21BR71C475KA
TDK
10 mF
4.7 mF
The inductor parameters directly related to device
performances are saturation current and DC resistance and
inductance value. The inductor ripple current (DIL)
decreases with higher inductance:
GRM188R60J475KE
Taiyo Yuden
1 mH
2.2 mH
Inductor Selection
Table 1. LIST OF INPUT CAPACITOR
Murata
Output Capacitor (COUT)
Table 3. LIST OF INDUCTOR
FDK
MIPW3226 Series
TDK
VLF3010AT Series
Taiyo Yuden
Coil Craft
LQ CBL2012
DO1605−T Series
LPO3010
+ 49.5 kHz
(eq. 2)
http://onsemi.com
9
NCP1523
Output Capacitor Selection
Table 4. LIST OF OUTPUT CAPACITOR ROHS
Selecting the proper output capacitor is based on the
desired output ripple voltage. Ceramic capacitors with low
ESR values will have the lowest output ripple voltage and
are strongly recommended. The output capacitor requires
either an X7R or X5R dielectric.
The output ripple voltage in PWM mode is given by:
DVOUT + DIL
ǒ4
1
fSW
COUT
) ESR
Ǔ
Murata
GRM188R60J475KE
4.7 mF
GRM21BR71C475KA
Taiyo Yuden
(eq. 5)
TDK
GRM188R60OJ106ME
10 mF
JMK212BY475MG
4.7 mF
JMK212BJ106MG
10 mF
C2012X5ROJ475KB
4.7 mF
C1632X5ROJ475KT
In PFM mode (at light load), the output voltage is
regulated by pulse frequency modulation. The output
voltage ripple is independent of the output capacitor value.
It is set by the threshold of PM comparator.
C2012X5ROJ106K
10 mF
APPLICATION BOARD
PCB Layout Recommendations
possible for best performance. All connecting
traces must be short, direct, and wide to reduce
voltage errors caused by resistive losses through
the traces.
3. Separate the feedback path of the output voltage
from the power path. Keep this path close to the
NCP1523 circuit. And also route it away from
noisy components. This will prevent noise from
coupling into the voltage feedback trace.
4. Place the DC−DC converter away from noise
sensitive circuitry, such as RF circuits.
The following shows the NCP1523 demo board
schematic and layout and bill of materials:
Good PCB layout plays an important role in switching
mode power conversion. Careful PCB layout can help to
minimize ground bounce, EMI noise and unwanted
feedback that can affect the performance of the converter.
Hints suggested below can be used as a guideline in most
situations.
1. Use star−ground connection to connect the IC
ground nodes and capacitor GND nodes together
at one point. Keep them as close as possible, and
then connect this to the ground plane through
several vias. This will reduce noise in the ground
plane by preventing the switching currents from
flowing through the ground plane.
2. Place the power components (i.e., input capacitor,
inductor and output capacitor) as close together as
VBATTERY
U2
A2
OFF
B2
ON
NCP1523
GND
VIN
A1
SW D1
EN
L1
C1
C2
D2
R1
ADJ
GND1 C1
FB
R2
VOUT
D1
C2
Figure 19. NCP1523 Board Schematic
http://onsemi.com
10
NCP1523
Figure 20. NCP1523 Board Layout
U1
VIN
A2
EN
B2
ADJ
C2
R1
220k
D2
FB
VIN
EN
ADJ
FB
NCP1523
B2
VOUT
A1
GND
L1
SW
SW D1
2.2 mH
GND C1
D1
VOUT
TP3
VOUT
C2
4.7 mF
R2
220k
TP1
VIN
B1
VIN
1
2
VOUT
VIN
C1
4.7 mF
J1
S1
TP2
EN
G1
EN
VIN
1
EN
2
3
Figure 21. NCP1523 Board Schematic
http://onsemi.com
11
1
1
JMP1
JMP
2
JMP2
JMP
2
NCP1523
Figure 22. NCP1523 Assembly Layer
Figure 23. NCP1523 Top Layer Routing
http://onsemi.com
12
NCP1523
Figure 24. NCP1523 Bottom Layer Routing
BILL OF MATERIALS
Designator
Qty
Description
Value
Tolerance
Footprint
Manufacturer
Manufacturer
Part Number
U1
1
IC, Converter,
DC/DC
NA
NA
8−Pin Flip
Chip
ON Semiconductor
NCP1523
C1, C2
2
Ceramic
Capacitor
4.7 mF, 10 V,
X5R
0,1
0805
Murata
GRM219R61A475
KE19D
R1, R2
2
SMD resistor
220k
0.05
0805
Standard
Standard
L1
1
Inductor
2.2 mH
0.2
1605
Coilcraft
DO1605T−222MLB
B1, B2
2
Male
SL5.08/2/90B +
Female
BLZ5.08/2/90B
Connector I/O
NA
NA
NA
Weidmuller
1510360000
+
1555060000
J1
1
3 Pin Jumper
Header
NA
NA
2.54 mm
TYCO/AMP
5−826629−0
JMP1, JMP2
2
Jumper for GND
NA
NA
10.16 mm
Harwin
D3082−01
TP1, TP2,
TP3
3
Test point
NA
NA
NA
Standard
Standard
G1
0*
SMB Connector
NA
NA
NA
Radiall
R114665000
PCB
1
88.9 x 61.1 x
1.6 mm
4 Layers
NA
NA
NA
Any
TLS−P−001−A−050
6−DA
http://onsemi.com
13
NCP1523
PACKAGE DIMENSIONS
FLIP−CHIP−8
CASE 766AE−01
ISSUE A
0.10 C
2X
TERMINAL A1
LOCATOR
ÈÈ
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
A B
E
MILLIMETERS
DIM MIN
MAX
A
−−− 0.655
A1 0.210 0.270
A2 0.335 0.385
b
0.290 0.340
D
2.050 BSC
D1
1.500 BSC
E
1.050 BSC
e
0.500 BSC
0.10 C TOP VIEW
2X
A2
A1
0.10 C
A
0.05 C
8X
SEATING
PLANE
SIDE VIEW
NOTE 3
D1
b
0.05 C A B
8X
0.03 C
C
e/2
e
2
1
A
B
C
D
e
BOTTOM VIEW
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
14
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP1523/D