CY7C1021BNV33 64K x 16 Static RAM Functional Description[1] Features • 3.3V operation (3.0V–3.6V) The CY7C1021BNV is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. • High speed — tAA = 10, 12, 15 ns • CMOS for optimum speed/power Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). • Low Active Power (L version) — 576 mW (max.) • Low CMOS Standby Power (L version) — 1.80 mW (max.) • Automatic power-down when deselected • Independent control of upper and lower bits • Available in 44-pin TSOP II and 400-mil SOJ • Available in a 48-Ball Mini BGA package Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021BNV is available in 400-mil-wide SOJ, standard 44-pin TSOP Type II, and 48-ball mini BGA packages. Logic Block Diagram Pin Configurations SOJ / TSOP II Top View SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 64K x 16 RAM Array 512 X 2048 I/O1–I/O8 I/O9–I/O16 COLUMN DECODER A8 A9 A10 A11 A12 A13 A14 A15 BHE WE CE OE BLE A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com Cypress Semiconductor Corporation Document #: 001-06433 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 1, 2006 [+] Feedback CY7C1021BNV33 Selection Guide -10 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) -12 -15 10 12 15 Commercial 160 150 140 Industrial 180 170 160 5 5 5 0.5 0.5 0.5 Commercial/Industrial L Pin Configurations Mini BGA (Top View) 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O9 BHE A3 A4 CE I/O1 B I/O10 I/O11 A5 A6 I/O2 I/O3 C VSS I/O12 NC A7 I/O4 VCC D VCC I/O13 NC NC I/O5 VSS E I/O15 I/O14 A14 A15 I/O6 I/O7 F I/O16 NC NC Document #: 001-06433 Rev. ** A8 A12 A13 WE I/O8 G A9 A10 A11 H NC Page 2 of 10 [+] Feedback CY7C1021BNV33 DC Input Voltage[1] .................................. –0.5V to VCC+0.5V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V Range DC Voltage Applied to Outputs in High Z State[1] ......................................–0.5V to VCC+0.5V Ambient Temperature VCC 0°C to +70°C 3.3V ± 10% –40°C to +85°C 3.3V ± 10% Commercial Industrial Electrical Characteristics Over the Operating Range -12 -10 Parameter Description Test Conditions Min. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage[1] IIX Input Load Current GND < VI < VCC IOZ Output Leakage Current GND < VI < VCC, Output Disabled ICC VCC Operating Supply Current VCC = Max., IOUT=0mA Com’l f = fMAX = 1/tRC Ind’l Max. 2.4 Min. -15 Max. Min. 2.4 Max. 2.4 0.4 Unit V 0.4 V 2.2 VCC+0.3V 2.2 VCC+0.3V 0.4 2.2 VCC+0.3V V −0.3 0.8 –0.3 0.8 –0.3 0.8 V −1 +1 –1 +1 –1 +1 µA −1 +1 –1 +1 –1 +1 µA 160 150 140 mA 120 170 160 mA ISB1 Automatic CE Max. VCC, CE > VIH, Powerdown Current VIN > VIH or VIN < VIL, —TTL Inputs f = fMAX 40 40 40 mA ISB2 Automatic CE Power Down Current —CMOS Inputs 5 5 5 mA 500 500 500 µA Max. VCC, CE > VCC–0.3V, L VIN > VCC –0.3V or VIN <0.3V, f = 0 Capacitance[2] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz Max. Unit 6 pF 8 pF AC Test Loads and Waveforms R 317Ω R 317Ω 3.3V 3.3V OUTPUT 90% OUTPUT 30 pF R2 351Ω INCLUDING JIG AND SCOPE (a) 5 pF R2 351 Ω INCLUDING JIG AND SCOPE (b) 167 OUTPUT Equivalent to: THÉVENIN EQUIVALENT ALL INPUT PULSES 3.0V GND Rise Time: 1 V/ns 10% 90% 10% Fall Time: 1 V/ns 1.73V 30 pF Note: 1. Minimum voltage is –2.0V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-06433 Rev. ** Page 3 of 10 [+] Feedback CY7C1021BNV33 Switching Characteristics[3] Over the Operating Range -10 Parameter Description Min. -12 Max. Min. -15 Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE 10 OE HIGH to High Z 12 10 3 12 6 0 5 Z[5] 3 12 4 0 ns 15 ns 7 ns 0 6 ns 7 3 ns CE LOW to Low tHZCE CE HIGH to High Z[4, 5] tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 12 12 15 ns tDBE Byte Enable to Data Valid 5 6 7 ns tLZBE Byte Enable to Low Z tHZBE Byte Disable to High Z 5 0 3 ns tLZCE WRITE 3 ns 15 3 10 [4, 5] 15 6 0 0 0 0 5 ns 7 ns 0 6 ns ns 7 ns CYCLE[6] tWC Write Cycle Time 10 12 15 ns tSCE CE LOW to Write End 8 9 10 ns tAW Address Set-Up to Write End 7 8 10 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 ns tPWE WE Pulse Width 8 8 10 ns tSD Data Set-Up to Write End 6 6 8 ns tHD Data Hold from Write End 0 0 0 ns Z[5] tLZWE WE HIGH to Low tHZWE WE LOW to High Z[4, 5] tBW Byte Enable to End of Write 3 3 5 8 3 6 ns 7 8 9 ns ns Data Retention Characteristics Over the Operating Range (L version only) Parameter Conditions[7] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[8] Chip Deselect to Data Retention Time tR [9] Operation Recovery Time Min. Max. 2.0 Com’l VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Unit V 100 µA 0 ns tRC ns Notes: 3. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 4. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 7. No input may exceed VCC + 0.5V. 8. Tested initially and after any design or process changes that may affect these parameters. 9. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds. Document #: 001-06433 Rev. ** Page 4 of 10 [+] Feedback CY7C1021BNV33 Data Retention Waveform DATA RETENTION MODE 3.0V VCC VDR > 2V 3.0V tR tCDR CE Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[11, 12] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% IICC CC 50% IISB SB Notes: 10. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. Document #: 001-06433 Rev. ** Page 5 of 10 [+] Feedback CY7C1021BNV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[13, 14] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA I/O Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes: 13. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 001-06433 Rev. ** Page 6 of 10 [+] Feedback CY7C1021BNV33 Switching Waveforms (continued) Write Cycle No. 2 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE OE WE H X L L L X BLE BHE X X X High Z High Z Power-Down Standby (ISB) H L L Data Out Data Out Read - All bits Active (ICC) L H Data Out High Z Read - Lower bits only Active (ICC) H L High Z Data Out Read - Upper bits only Active (ICC) L L Data In Data In Write - All bits Active (ICC) L H Data In High Z Write - Lower bits only Active (ICC) H L High Z Data In Write - Upper bits only Active (ICC) L I/O1–I/O8 I/O9–I/O16 Mode Power L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Document #: 001-06433 Rev. ** Page 7 of 10 [+] Feedback CY7C1021BNV33 Ordering Information Speed (ns) 10 12 15 Ordering Code Package Diagram Operating Range Package Type CY7C1021BNV33L-10VXC 51-85082 44-Lead (400-Mil) Molded SOJ (Pb-free) CY7C1021BNV33L-10ZXC 51-85087 44-Lead TSOP Type II (Pb-free) CY7C1021BNV33L-12ZC 51-85087 44-Lead TSOP Type II CY7C1021BNV33L-12ZXC 51-85087 44-Lead TSOP Type II (Pb-free) CY7C1021BNV33L-15ZC 51-85087 44-Lead TSOP Type II CY7C1021BNV33L-15ZXC 51-85087 44-Lead TSOP Type II (Pb-free) CY7C1021BNV33L-15VXC 51-85082 44-Lead (400-Mil) Molded SOJ (Pb-free) CY7C1021BNV33L-15BAI 51-85096 48-ball Mini Ball Grid Array (7 mm x 7 mm) CY7C1021BNV33L-15VXI 51-85082 44-Lead (400-Mil) Molded SOJ (Pb-free) CY7C1021BNV33L-15ZXI 51-85087 44-Lead TSOP Type II (Pb-free) CY7C1021BNV33L-15ZI 51-85087 44-Lead TSOP Type II Commercial Industrial Please contact local sales representative regarding availability of these parts. Package Diagrams 48-ball FBGA (7 mm x 7 mm x 1.2 mm) (51-85096) BOTTOM VIEW TOP VIEW PIN 1 CORNER Ø0.05 M C PIN 1 CORNER (LASER MARK) Ø0.25 M C A B Ø0.30±0.05(48X) 1 2 3 4 5 6 6 4 3 2 1 C C F G D E F 2.625 E 0.75 B 5.25 A B 7.00±0.10 A D 7.00±0.10 5 G H H A A 1.875 0.75 B 7.00±0.10 3.75 7.00±0.10 0.15(4X) 0.10 C 0.21±0.05 0.53±0.05 0.25 C B 51-85096-*F 0.36 SEATING PLANE C Document #: 001-06433 Rev. ** 1.20 MAX. Page 8 of 10 [+] Feedback CY7C1021BNV33 Package Diagrams (continued) 44-Lead (400-Mil) Molded SOJ (51-85082) 51-85082-*B 44-Pin TSOP Type II (51-85087) 51-85087-*A All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06433 Rev. ** Page 9 of 10 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1021BNV33 Document History Page Document Title: CY7C1021BNV33 64K x 16 Static RAM Document Number: 001-06433 REV. ** ECN NO. 423847 Issue Date See ECN Document #: 001-06433 Rev. ** Orig. of Change NXR Description of Change New Data Sheet Page 10 of 10 [+] Feedback