021BV33 CY7C1021BV33 64K x 16 Static RAM Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15). Features • 3.3V operation (3.0V–3.6V) • High speed — tAA = 10/12/15 ns • CMOS for optimum speed/power • Low Active Power (L version) — 576 mW (max.) • Low CMOS Standby Power (L version) — 1.80 mW (max.) • Automatic power-down when deselected • Independent control of upper and lower bits • Available in 44-pin TSOP II and 400-mil SOJ • Available in a 48-Ball Mini BGA package Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. Functional Description[1] The CY7C1021BV is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021BV is available in 400-mil-wide SOJ, standard 44-pin TSOP Type II, and 48-ball mini BGA packages. Logic Block Diagram Pin Configurations SOJ / TSOP II Top View SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 64K x 16 RAM Array 512 X 2048 A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A15 A14 A13 A12 NC I/O1–I/O8 I/O9–I/O16 COLUMN DECODER A8 A9 A10 A11 A12 A13 A14 A15 BHE WE CE OE BLE 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 37 36 35 34 33 32 31 30 29 28 27 13 14 15 16 17 18 19 20 21 22 26 25 24 23 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC Selection Guide 7C1021BV-8 7C1021BV-10 7C1021BV-12 7C1021BV-15 8 10 12 15 Commercial 170 160 150 140 Industrial 190 180 170 160 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Commercial L 5 5 5 5 0.500 0.500 0.500 0.500 Shaded areas contain advance information. Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05148 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 13, 2002 CY7C1021BV33 Pin Configurations Mini BGA (Top View) 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O9 BHE A3 A4 CE I/O1 B I/O10 I/O11 A5 A6 I/O2 I/O3 C VSS I/O12 NC A7 I/O4 VCC D VCC I/O13 NC NC I/O5 VSS E I/O15 I/O14 A14 A15 I/O6 I/O7 F I/O16 NC NC A8 A12 A13 WE I/O8 G A9 A10 A11 H Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[2] ......................................–0.5V to VCC+0.5V DC Input Voltage[2]...................................–0.5V to VCC+0.5V NC Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature VCC 0°C to +70°C 3.3V ± 10% –40°C to +85°C 3.3V ± 10% Note: 2. Mimimum voltage is–2.0V for pulse durations of less than 20 ns. Document #: 38-05148 Rev. *A Page 2 of 11 CY7C1021BV33 Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 7C1021BV-8 7C1021BV-10 7C1021BV-12 Min. Min. Min. Max. 2.4 Max. 2.4 Max. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC+ 0.3V 2.2 VCC+ 0.3V 2.2 VCC+ 0.3V VIL Input LOW Voltage[2] −0.3 0.8 −0.3 0.8 –0.3 IIX Input Load Current GND < VI < VCC −1 +1 −1 +1 IOZ Output Leakage Current GND < VI < VCC, Output Disabled −1 +1 −1 +1 ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC ISB1 Automatic CE Power-Down Current —TTL Inputs ISB2 Automatic CE Power-Down Current —CMOS Inputs 0.4 7C1021BV-15 Min. Max. 2.4 0.4 0.4 Unit V 0.4 V 2.2 VCC+ 0.3V V 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –1 +1 –1 +1 µA Com 170 160 150 140 mA Ind 190 120 170 160 mA Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 40 40 40 40 mA Max. VCC, CE > VCC – 0.3V, L VIN > VCC – 0.3V, or VIN < 0.3V, f=0 5 5 5 5 mA 500 500 500 500 µA Shaded areas contain advance information. Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz Max. Unit 6 pF 8 pF Note: 3. Tested initially and after any design or process changes that may affect these parameters. AC Test Loads and Waveforms R 317Ω R 317Ω 3.3V 3.3V OUTPUT 90% OUTPUT 30 pF R2 351Ω INCLUDING JIG AND SCOPE (a) Document #: 38-05148 Rev. *A R2 351Ω 5 pF INCLUDING JIG AND SCOPE 167 OUTPUT Equivalent to: THÉVENIN EQUIVALENT ALL INPUT PULSES 3.0V GND Rise Time: 1 V/ns (b) 10% 90% 10% Fall Time: 1 V/ns 1.73V 30 pF Page 3 of 11 CY7C1021BV33 Switching Characteristics[4] Over the Operating Range Parameter Description 7C1021BV-8 7C1021BV-10 7C1021BV-12 7C1021BV-15 Min. Min. Min. Min. Max. Max. Max. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid 8 tOHA Data Hold from Address Change tACE CE LOW to Data Valid 8 10 12 15 ns tDOE OE LOW to Data Valid 4 4 6 7 ns tLZOE OE LOW to Low Z 3 OE HIGH to High Z tLZCE CE LOW to Low Z[6] 4 tHZCE CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down tDBE Byte Enable to Data Valid 4 tLZBE Byte Enable to Low Z 0 tHZBE Byte Disable to High Z 3 6 3 12 ns ns 7 ns 0 12 12 5 4 ns 7 6 0 6 0 ns 3 5 0 ns 0 5 4 ns 15 3 0 3 0 15 12 0 3 [5, 6] 12 10 3 0 [5, 6] tHZOE WRITE 10 8 0 ns 15 ns 7 ns 0 5 6 ns 7 ns CYCLE[7] tWC Write Cycle Time 8 10 12 15 ns tSCE CE LOW to Write End 7 8 9 10 ns tAW Address Set-Up to Write End 6 7 8 10 ns tHA Address Hold from Write End 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 ns tPWE WE Pulse Width 6 8 8 10 ns tSD Data Set-Up to Write End 4 6 6 8 ns tHD Data Hold from Write End 0 0 0 0 ns tLZWE WE HIGH to Low Z[6] 3 3 3 3 ns Z[5, 6] tHZWE WE LOW to High tBW Byte Enable to End of Write 4 8 5 8 6 8 7 ns 9 ns Shaded areas contain advance information. Data Retention Characteristics Over the Operating Range (L version only) Parameter Conditions[8] Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[9] Chip Deselect to Data Retention Time tR[10] Operation Recovery Time Min. Max. 2.0 Com’l VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Unit V 100 µA 0 ns tRC ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. No input may exceed VCC + 0.5V. 9. Tested initially and after any design or process changes that may affect these parameters. 10. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds. Document #: 38-05148 Rev. *A Page 4 of 11 CY7C1021BV33 Data Retention Waveform DATA RETENTION MODE 3.0V VCC VDR > 2V 3.0V tR tCDR CE Switching Waveforms Read Cycle No. 1 [11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID Read Cycle No. 2 (OE Controlled) DATA VALID [12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% IICC CC 50% IISB SB Notes: 11. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 38-05148 Rev. *A Page 5 of 11 CY7C1021BV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) [14, 15] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA I/O Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes: 14. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05148 Rev. *A Page 6 of 11 CY7C1021BV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE OE WE BLE BHE H X X X X High Z High Z Power-Down Standby (ISB) L L H L L Data Out Data Out Read - All bits Active (ICC) L H Data Out High Z Read - Lower bits only Active (ICC) H L High Z Data Out Read - Upper bits only Active (ICC) L L Data In Data In Write - All bits Active (ICC) L H Data In High Z Write - Lower bits only Active (ICC) H L High Z Data In Write - Upper bits only Active (ICC) L X L I/O1–I/O8 I/O9–I/O16 Mode Power L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Document #: 38-05148 Rev. *A Page 7 of 11 CY7C1021BV33 Ordering Information Speed (ns) 8 Ordering Code CY7C1021BV33-8BAC 12 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) V34 44-Lead (400-Mil) Molded SOJ CY7C1021BV33L-8VC V34 44-Lead (400-Mil) Molded SOJ CY7C1021BV33-8ZC Z44 44-Lead TSOP Type II Z44 44-Lead TSOP Type II CY7C1021BV33-10BAC BA48A 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) CY7C1021BV33-10VC V34 44-Lead (400-Mil) Molded SOJ CY7C1021BV33L-10VC V34 44-Lead (400-Mil) Molded SOJ CY7C1021BV33-10ZC Z44 44-Lead TSOP Type II CY7C1021BV33L-10ZC Z44 44-Lead TSOP Type II CY7C1021BV33-12BAC BA48A 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) CY7C1021BV33-12VC V34 CY7C1021BV33L-12VC V34 44-Lead (400-Mil) Molded SOJ CY7C1021BV33-12ZC Z44 44-Lead TSOP Type II CY7C1021BV33L-12ZC Z44 44-Lead TSOP Type II CY7C1021BV33-12BAI BA48A CY7C1021BV33-12VI 15 BA48A Package Type CY7C1021BV33-8VC CY7C1021BV33L-8ZC 10 Package Name V34 Operating Range Commercial Commercial Commercial 44-Lead (400-Mil) Molded SOJ 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) Industrial 44-Lead (400-Mil) Molded SOJ CY7C1021BV33-15BAC BA48A 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) CY7C1021BV33L-15BAC BA48A 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) CY7C1021BV33-15VC V34 CY7C1021BV33L-15VC V34 44-Lead (400-Mil) Molded SOJ CY7C1021BV33-15ZC Z44 44-Lead TSOP Type II CY7C1021BV33L-15VC Z44 44-Lead TSOP Type II CY7C1021BV33-15BAI BA48A 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) CY7C1021BV33L-15BAI BA48A 48-Ball Mini Ball Grid Array (7.00 mm x 7.00 mm) Commercial 44-Lead (400-Mil) Molded SOJ CY7C1021BV33-15VI V34 44-Lead (400-Mil) Molded SOJ CY7C1021BV33L-15ZI Z44 44-Lead TSOP Type II Industrial Shaded areas contain advance information. Document #: 38-05148 Rev. *A Page 8 of 11 CY7C1021BV33 Package Diagrams 48-Ball (7.00 mm x 7.00 mm x 1.2 mm) FBGA BA48A 51-85096-*E Document #: 38-05148 Rev. *A Page 9 of 11 CY7C1021BV33 Package Diagrams (continued) 44-Lead (400-Mil) Molded SOJ V34 51-85082-*B 44-Pin TSOP II Z44 51-85087-A All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05148 Rev. *A Page 10 of 11 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1021BV33 Document History Page Document Title: CY7C1021BV33 64K x 16 Static RAM Document Number: 38-05148 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109892 09/22/01 SZV Change from Spec number: 38-00954 to 38-05148 *A 116474 09/16/02 CEA Add applications foot note to data sheet, page 1. Document #: 38-05148 Rev. *A Page 11 of 11