PLDC20G10B PLDC20G10 USE ULTRA37000™ FOR ALL NEW DESIGNS CMOS Generic 24-Pin Reprogrammable Logic Device Features • CMOS EPROM technology for reprogrammability • Highly reliable • Fast — Commercial: tPD = 15 ns, tCO = 10 ns, tS = 12 ns — Military: tPD = 20 ns, tCO = 15 ns, tS = 15 ns • Low power — ICC max.: 70 mA, commercial — ICC max.: 100 mA, military • Commercial and military temperature range • User-programmable output cells — Selectable for registered or combinatorial operation — Output polarity control — Output enable source selectable from pin 13 or product term • Generic architecture to replace standard logic functions including: 20L10, 20L8, 20R8, 20R6, 20R4, 12L10, 14L8, 16L6, 18L4, 20L2, and 20V8 • Eight product terms and one OE product term per output — Uses proven EPROM technology — Fully AC and DC tested — Security feature prevents logic pattern duplication — ±10% power supply voltage and higher noise immunity Functional Description Cypress PLD devices are high-speed electrically programmable logic devices. These devices utilize the sum-of-products (AND-OR) structure providing users the ability to program custom logic functions for unique requirements. In an unprogrammed state the AND gates are connected via EPROM cells to both the true and complement of every input. By selectively programming the EPROM cells, AND gates may be connected to either the true or complement or disconnected from both true and complement inputs. Logic Block Diagram VSS I I I I I I I I I I CP/I 12 11 10 9 8 7 6 5 4 3 2 1 PROGRAMMABLE AND ARRAY 8 OUTPUT CELL OUTPUT CELL 8 OUTPUT CELL OUTPUT CELL OE OUTPUT CELL 8 OE OUTPUT CELL 8 OE OUTPUT CELL 8 OE OUTPUT CELL 8 OE OUTPUT CELL 8 OE 8 OE 8 OE 8 OUTPUT CELL 13 14 15 16 17 18 19 20 21 22 23 24 I/OE I/O 9 I/O 8 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 I/O 0 V CC STD PLCC Top View NC I I NC I I NC 5 6 7 8 9 10 11 25 24 23 PLDC20G10 PLDC20G10B 22 21 20 121314 1516 1718 19 4 3 2 1 2827 26 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 NC I I I NC I I I 5 6 7 8 9 10 11 25 24 23 CG7C323–A CG7C323B–A 22 21 20 121314 1516 1718 19 I/O 2 I/O 3 I/O 4 NC I/O 5 I/O 6 I/O 7 I I I I I I I NC I/OE I/O 9 I/O 8 4 3 2 1 2827 26 NC I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 VSS I/OE I/O 9 I/O 8 4 3 2 1 282726 25 24 23 PLDC20G10 22 PLDC20G10B 21 20 19 12131415161718 [1] I I CP/I NC V CC I/O0 I/O 1 NC I I CP/I VCC I/O 0 I/O 1 5 6 7 8 9 10 11 V SS I/OE I/O9 I/O8 NC I I I I I I NC JEDEC PLCC Top View I I I CP/I V CC I/O0 I/O1 LCC Top View VSS Pin Configurations Note: 1. The CG7C323 is the PLDC20G10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The difference is in the location of the “no connect” or NC pins. Cypress Semiconductor Corporation Document #: 38-03010 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised April 20, 2004 USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Selection Guide ICC (mA) Generic Part Number Com/Ind 20G10B–15 70 20G10B–20 70 20G10B–25 20G10–25 Mil Com/Ind 100 20 100 Com/Ind 20 12 Cypress PLDC20G10 uses an advanced 0.8-micron CMOS technology and a proven EPROM cell as the programmable element. This technology and the inherent advantage of being able to program and erase each cell enhances the reliability and testability of the circuit. This reduces the burden on the customer to test and to handle rejects. A preload function allows the registered outputs to be preset to any pattern during testing. Preload is important for testing the functionality of the Cypress PLD device. 20G10 Functional Description The PLDC20G10 is a generic 24-pin device that can be programmed to logic functions that include but are not limited to: 20L10, 20L8, 20R8, 20R6, 20R4, 12L10, 14L8, 16L6, 18L4, 20L2, and 20V8. Thus, the PLDC20G10 provides significant design, inventory and programming flexibility over dedicated 24-pin devices. It is executed in a 24-pin 300-mil molded DIP and a 300-mil windowed cerDIP. It provides up to 22 inputs and 10 outputs. When the windowed cerDIP is exposed to UV light, the 20G10 is erased and then can be reprogrammed. The programmable output cell provides the capability of defining the architecture of each output individually. Each of the 10 output cells may be configured with registered or combinatorial outputs, active HIGH or active LOW outputs, and product term or Pin 13 generated output enables. Three architecture bits determine the configurations as shown in the Com/Ind 15 12 15 15 15 20 30 40 Mil 10 18 30 Functional Description Mil 15 35 80 tCO (ns) 12 25 80 Document #: 38-03010 Rev. *A Mil 25 55 20G10–40 tS (ns) 15 55 20G10–30 20G10–35 tPD (ns) 20 25 35 25 Configuration Table and in Figures 1 through 8. A total of eight different configurations are possible, with the two most common shown in Figure 3 and Figure 5. The default or unprogrammed state is registered/active/LOW/Pin 11 OE. The entire programmable output cell is shown in the next section. The architecture bit ‘C1’ controls the registered/combinatorial option. In either combinatorial or registered configuration, the output can serve as an I/O pin, or if the output is disabled, as an input only. Any unused inputs should be tied to ground. In either registered or combinatorial configuration, the output of the register is fed back to the array. This allows the creation of control-state machines by providing the next state. The register is clocked by the signal from Pin 1. The register is initialized on power up to Q output LOW and Q output HIGH. In both the combinatorial and registered configurations, the source of the output enable signal can be individually chosen with architecture bit ‘C2’. The OE signal may be generated within the array, or from the external OE (Pin 13). The Pin 13 allows direct control of the outputs, hence having faster enable/disable times. Each output cell can be configured for output polarity. The output can be either active HIGH or active LOW. This option is controlled by architecture bit ‘C0’. Along with this increase in functional density, the Cypress PLDC20G10 provides lower-power operation through the use of CMOS technology and increased testability with a register preload feature. Page 2 of 14 USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Programmable Output Cell OE PRODUCT TERM OUTPUT ENABLE MUX C2 10 11 00 D Q Q CP 01 OUTPUT SELECT MUX C1 C0 0 INPUT/ FEED– BACK MUX C3 1 C2 C1 C0 PIN 13 Configuration Table Figure C2 C1 C0 Configuration 1 0 0 0 Product Term OE/Registered/Active LOW 2 0 0 1 Product Term OE/Registered/Active HIGH 5 0 1 0 Product Term OE/Combinatorial/Active LOW 6 0 1 1 Product Term OE/Combinatorial/Active HIGH 3 1 0 0 Pin 13 OE/Registered/Active LOW 4 1 0 1 Pin 13 OE/Registered/Active HIGH 7 1 1 0 Pin 13 OE/Combinatorial/Active LOW 8 1 1 1 Pin 13 OE/Combinatorial/Active HIGH Registered Output Configurations D Q C2 = 0 C1 = 0 C0 = 0 Figure 1. Product Term OE/Active LOW D CP Q Figure 3. Pin 13 OE/Active LOW Document #: 38-03010 Rev. *A Figure 2. Product Term OE/Active HIGH C2 = 1 C1 = 0 C0 = 0 Q Q Q CP Q CP D C2 = 0 C1 = 0 C0 = 1 D CP Q C2 = 1 C1 = 0 C0 = 1 Q Figure 4. Pin 13 OE/Active HIGH Page 3 of 14 USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Combinatorial Output Configurations[2] C2 = 0 C1 = 1 C0 = 0 Figure 5. Product Term OE/Active LOW C2 = 0 C1 = 1 C0 = 1 Figure 6. Product Term OE/Active HIGH C2 = 1 C1 = 1 C0 = 0 C2 = 1 C1 = 1 C0 = 1 PIN 13 Figure 7. Pin 13 OE/Active Low PIN 13 Figure 8. Pin 13 OE/Active HIGH Note: 2. Bidirectional I/O configurations are possible only when the combinatorial output option is selected Document #: 38-03010 Rev. *A Page 4 of 14 USE ULTRA37000™ FOR ALL NEW DESIGNS Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +7.0V PLDC20G10B PLDC20G10 DC Programming Voltage PLDC20G10B and CG7C323B–A ............................... 13.0V PLDC20G10 and CG7C323–A.................................... 14.0V Latch-Up Current ..................................................... >200 mA Static Discharge Voltage.............................................. >500V (per MIL-STD-883, Method 8015) Operating Range Range Ambient Temperature VCC 0°C to +75°C 5V ±10% DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V Commercial DC Input Voltage............................................ –3.0V to +7.0V Military[3] –55°C to +125°C 5V ±10% Output Current into Outputs (LOW) .............................16 mA Industrial –40°C to +85°C 5V ±10% Electrical Characteristics Over the Operating Range (Unless Otherwise Noted)[4] Parameter VOH Description Output HIGH Voltage VOL Output LOW Voltage Test Conditions Min. VCC = Min., VIN = VIH or VIL IOH = –3.2 mA Com’l/Ind IOH = –2 mA Military VCC = Min., VIN = VIH or VIL IOL = 24 mA Com’l/Ind IOL = 12 mA Military VIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs[5] VIL Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs[5] IIX Input Leakage Current VSS ≤ VIN ≤ VCC ISC Output Short Circuit Current VCC = Max., VOUT = 0.5V[6, 7] ICC Power Supply Current IOZ Output Leakage Current Unit 2.4 V 0.5 V 0.8 V 2.0 V +10 µA –90 mA Com’l/Ind–15, –20 70 mA Com’l/Ind–25, –35 55 mA Military–20, –25 100 mA Military–30, –40 80 mA 100 µA –10 0 ≤ VIN ≤ VCC VCC = Max., IOUT = 0 mA Unprogrammed Device Max. VCC = Max., VSS ≤ VOUT ≤ VCC –100 Capacitance[7] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit TA = 25°C, f = 1 MHz 10 pF VIN = 2.0V, VCC = 5.0V 10 pF Notes: 3. TA is the “instant on” case temperature. 4. See the last page of this specification for Group A subgroup testing information. 5. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 7. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-03010 Rev. *A Page 5 of 14 USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 AC Test Loads and Waveforms (Commercial) R1 238 Ω (319Ω MIL) R1 238Ω (319Ω MIL) 5V 5V OUTPUT OUTPUT 50pF INCLUDING JIG AND SCOPE R2 170Ω (236Ω MIL) 5 pF INCLUDING JIG AND SCOPE (a) Equivalent to: THÉVENIN EQUIVALENT (Commercial) 99Ω OUTPUT 2.08V=Vthc R2 170Ω (236Ω MIL) (b) Equivalent to: THÉVENIN EQUIVALENT (Military/Industrial) 136 Ω OUTPUT 2.13V=V thm Switching Characteristics Over Operating Range[3, 8, 9] Commercial B–15 Parameter Description B–20 –25 –35 Min. Max. Min. Max. Min. Max. Min. Max. Unit tPD Input or Feedback to Non-Registered Output tEA Input to Output Enable 15 20 25 35 ns tER Input to Output Disable 15 20 25 35 ns tPZX Pin 11 to Output Enable 12 15 20 25 ns tPXZ Pin 11 to Output Disable 12 15 20 25 ns tCO Clock to Output 25 ns tS Input or Feedback Set-up Time tH Hold Time 0 0 0 0 ns tP[10] Clock Period 22 24 30 55 ns tWH Clock High Time 8 10 12 17 ns tWL Clock Low Time 8 10 12 17 ns fMAX[11] Maximum Frequency 45.4 41.6 33.3 18.1 MHz 15 20 10 12 25 12 12 35 15 15 30 ns ns Switching Characteristics Over Operating Range [3, 8, 9] Military/Industrial B–20 Parameter Description B–25 –30 –40 Min. Max. Min. Max. Min. Max. Min. Max. Unit tPD Input or Feedback to Non-Registered Output 20 25 30 40 ns tEA Input to Output Enable 20 25 30 40 ns tER Input to Output Disable 20 25 30 40 ns tPZX Pin 11 to Output Enable 17 20 25 25 ns tPXZ Pin 11 to Output Disable 17 20 25 25 ns tCO Clock to Output 15 15 20 25 ns tS Input or Feedback Set-Up Time 15 18 20 35 ns tH Hold Time 0 0 0 0 ns Notes: 8. Part (a) of AC Test Loads and Waveforms used for all parameters except tER, tPZX, and tPXZ. Part (b) of AC Test Loads and Waveforms used for tER, tPZX, and tPXZ. 9. The parameters tER and tPXZ are measured as the delay from the input disable logic threshold transition to VOH – 0.5V for an enabled HIGH output or VOL + 0.5V for an enabled LOW input. 10. tP, minimum guaranteed clock period is that guaranteed for state machine operation and is calculated from tP = tS + tCO. The minimum guaranteed period for registered data path operation (no feedback) can be calculated as the greater of (tWH + tWL) or (tS + tH). 11. fMAX, minimum guaranteed operating frequency, is that guaranteed for state machine operation and is calculated from fMAX = 1/(tS + tCO). The minimum guaranteed fMAX for registered data path operation (no feedback) can be calculated as the lower of 1/(tWH + tWL) or 1/(tS + tH). Document #: 38-03010 Rev. *A Page 6 of 14 USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Switching Characteristics Over Operating Range (continued)[3, 8, 9] Military/Industrial B–20 Parameter Description B–25 –30 –40 Min. Max. Min. Max. Min. Max. Min. Max. Unit tP[10] Clock Period tWH Clock High Time 12 14 16 22 ns tWL Clock Low Time 12 14 16 22 ns fMAX[11] Maximum Frequency 33.3 30.3 25.0 16.6 MHz 30 33 40 60 ns Switching Waveform INPUTS I/O, REGISTERED FEEDBACK tH tS tW tW CP tP OE tPXZ tCO tPZX REGISTERED OUTPUTS tPD t ER t EA COMBINATORIAL OUTPUTS Document #: 38-03010 Rev. *A Page 7 of 14 USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Functional Logic Diagram 1 0 4 8 12 16 20 24 28 32 36 40 OE 0 •• • OUTPUT CELL 7 23 OE 0 •• • OUTPUT CELL 22 7 2 OE 0 •• • 7 OUTPUT CELL 21 3 OE 0 •• • OUTPUT CELL 7 20 4 OE 0 •• • OUTPUT CELL 19 7 5 OE 0 •• • OUTPUT CELL 18 7 6 OE 0 •• • OUTPUT CELL 7 17 7 OE 0 •• • OUTPUT CELL 16 7 8 OE 0 •• • OUTPUT CELL 15 7 9 OE 0 •• • 7 OUTPUT CELL 14 10 11 Document #: 38-03010 Rev. *A 13 Page 8 of 14 USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Ordering Information tPD (ns) tS (ns) tCO (ns) ICC (mA) 15 12 10 70 20 15 15 100 25 15 15 55 30 35 20 30 20 25 80 55 Ordering Code Package Name Operating Range Package Type PLDC20G10B–15PC P13 24-Lead (300-Mil) Molded DIP Commercial PLDC20G10B–15WC W14 24-Lead (300-Mil) Windowed CerDIP PLDC20G10B–20DMB D14 24-Lead (300-Mil) CerDIP Military PLDC20G10–25JC J64 28-Lead Plastic Leaded Chip Carrier Commercial PLDC20G10–25PC/PI P13 24-Lead (300-Mil) Molded DIP Commercial/ Industrial PLDC20G10–25WC W14 24-Lead (300-Mil) Windowed CerDIP Commercial Military PLDC20G10–30DMB D14 24-Lead (300-Mil) CerDIP PLDC20G10–30LMB L64 28-Square Leadless Chip Carrier PLDC20G10–30WMB W14 24-Lead (300-Mil) Windowed CerDIP PLDC20G10–35JC J64 28-Lead Plastic Leaded Chip Carrier PLDC20G10–35PC P13 24-Lead (300-Mil) Molded DIP MILITARY SPECIFICATIONS Group A Subgroup Testing Commercial Switching Characteristics Parameter DC Characteristics Subgroups tPD 9, 10, 11 tPZX 9, 10, 11 1, 2, 3 tCO 9, 10, 11 VOL 1, 2, 3 tS 9, 10, 11 VIH 1, 2, 3 tH 9, 10, 11 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC 1, 2, 3 Parameter VOH Document #: 38-03010 Rev. *A Subgroups Page 9 of 14 USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9 Config.A 51-80031-** 28-Lead Plastic Leaded Chip Carrier J64 51-85001-*A Document #: 38-03010 Rev. *A Page 10 of 14 USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Package Diagrams (continued) 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 51-80051-** Document #: 38-03010 Rev. *A Page 11 of 14 USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Package Diagrams (continued) 28-Pin Windowed Leaded Chip Carrier H64 51-80077-** Document #: 38-03010 Rev. *A Page 12 of 14 PLDC20G10B PLDC20G10 USE ULTRA37000™ FOR ALL NEW DESIGNS Package Diagrams (continued) 24-Lead (300-Mil) PDIP P13 51-85013-*B 24-Lead (300-Mil) Windowed CerDIP W14 MIL-STD-1835 D-9 Config. A 51-80086-** Ultra37000 is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-03010 Rev. *A Page 13 of 14 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. USE ULTRA37000™ FOR ALL NEW DESIGNS PLDC20G10B PLDC20G10 Document History Page Document Title: PLDC20G10B/PLDC20G10 CMOS Generic 24-Pin Reprogrammable Logic Device Document Number: 38-03010 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106292 04/25/01 SZV Change from Spec number: 38-00019 to 38-03010 *A 213375 See ECN FSG Added note to title page: “Use Ultra37000 For All New Designs” Document #: 38-03010 Rev. *A Page 14 of 14