CY14B101KA CY14B101MA 1-Mbit (128 K × 8/64 K × 16) nvSRAM with Real Time Clock 1-Mbit (128 K × 8/64 K × 16) nvSRAM with Real Time Clock Features 1-Mbit nonvolatile static random access memory (nvSRAM) ❐ 25 ns and 45 ns access times ❐ Internally organized as 128 K × 8 (CY14B101KA) or 64 K × 16 (CY14B101MA) ❐ Hands off automatic STORE on power-down with only a small capacitor ❐ STORE to QuantumTrap nonvolatile elements is initiated by software, hardware, or AutoStore on power-down ❐ RECALL to SRAM initiated on power-up or by software ■ High reliability ❐ Infinite Read, Write, and RECALL cycles ❐ 1 million STORE cycles to QuantumTrap ❐ 20 year data retention ■ Real time clock (RTC) ❐ Full featured real time clock ❐ Watchdog timer ❐ Clock alarm with programmable interrupts ❐ Capacitor or battery backup for RTC ❐ Backup current of 0.35 µA (Typ) ■ Industry standard configurations ❐ Single 3 V +20%, –10% operation ❐ Industrial temperature ■ Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-pin shrink small outline package (SSOP) ■ Pb-free and restriction of hazardous substances (RoHS) compliant ■ Functional Description The Cypress CY14B101KA/CY14B101MA combines a 1-Mbit nvSRAM with a full featured real time clock in a monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM is read and written an infinite number of times, while independent nonvolatile data resides in the nonvolatile elements. The real time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The alarm function is programmable for periodic minutes, hours, days, or months alarms. There is also a programmable watchdog timer for process control. Logic Block Diagram[1, 2, 3] Quatrum Trap 1024 X 1024 A5 A6 A7 R O W A8 A9 A12 A13 A14 A15 A 16 D E C O D E R STORE VCA VCC P VRTCbat POWER CONTROL VRTCcap RECALL STATIC RAM ARRAY 1024 X 1024 STORE/RECALL CONTROL SOFTWARE DETECT HSB A14 - A2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 RTC I N P U T B U F F E R S Xout Xin INT COLUMN I/O MUX A 16- A0 OE COLUMN DEC WE DQ12 DQ13 CE DQ14 BLE A0 A1 A 2 A3 A 4 A10 A 11 DQ15 BHE Notes 1. Address A0–A16 for × 8 configuration and Address A0–A15 for × 16 configuration. 2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration. 3. BHE and BLE are applicable for × 16 configuration only. Cypress Semiconductor Corporation Document #: 001-42880 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 22, 2011 [+] Feedback CY14B101KA CY14B101MA Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 4 Device Operation .............................................................. 5 SRAM Read ....................................................................... 5 SRAM Write ....................................................................... 5 AutoStore Operation ........................................................ 5 Hardware STORE (HSB) Operation ................................. 5 Hardware RECALL (Power-Up) ....................................... 6 Software STORE ............................................................... 6 Software RECALL ............................................................. 6 Preventing AutoStore ....................................................... 7 Data Protection ................................................................. 8 Noise Considerations ....................................................... 8 Real Time Clock Operation .............................................. 8 nvTIME Operation ....................................................... 8 Clock Operations ......................................................... 8 Reading the Clock ....................................................... 8 Setting the Clock ......................................................... 8 Backup Power ............................................................. 8 Stopping and Starting the Oscillator ............................ 9 Calibrating the Clock ................................................... 9 Alarm ........................................................................... 9 Watchdog Timer .......................................................... 9 Power Monitor ........................................................... 10 Interrupts ................................................................... 10 Flags Register ........................................................... 11 Best Practices ................................................................. 16 Maximum Ratings ........................................................... 17 Operating Range ............................................................. 17 Document #: 001-42880 Rev. *I DC Electrical Characteristics ........................................ 17 Data Retention and Endurance ..................................... 18 Capacitance .................................................................... 18 Thermal Resistance ........................................................ 18 AC Test Loads ................................................................ 18 AC Test Conditions ........................................................ 18 RTC Characteristics ....................................................... 19 AC Switching Characteristics ....................................... 20 SRAM Read Cycle .................................................... 20 SRAM Write Cycle ..................................................... 20 Switching Waveforms .................................................... 20 AutoStore/Power-Up RECALL ....................................... 23 Switching Waveforms .................................................... 23 Software Controlled STORE/RECALL Cycle ................ 24 Switching Waveforms .................................................... 24 Hardware STORE Cycle ................................................. 25 Switching Waveforms .................................................... 25 Truth Table For SRAM Operations ................................ 26 Ordering Information ...................................................... 27 Package Diagrams .......................................................... 28 Acronyms ........................................................................ 30 Document Conventions ............................................. 30 Units of Measure ....................................................... 30 Document History Page ................................................. 31 Sales, Solutions, and Legal Information ...................... 34 Worldwide Sales and Design Support ....................... 34 Products .................................................................... 34 PSoC Solutions ......................................................... 34 Page 2 of 34 [+] Feedback CY14B101KA CY14B101MA Pinouts Figure 1. Pin Diagram – 44-pin, 54-pin TSOP II, and 48-pin SSOP INT 1 [7] NC 2 A0 3 A1 4 A2 5 A3 6 A4 7 CE 8 DQ0 9 DQ1 10 VCC 11 12 VSS DQ2 13 DQ3 14 WE 15 A5 16 A6 17 A7 18 A8 19 A9 20 Xout 21 Xin 22 44-pin TSOP II (× 8) Top View (not to scale) VCAP 44 43 42 41 40 39 38 37 36 35 34 33 32 31 HSB NC [6] NC [5] NC[4] NC A16 A15 OE DQ7 DQ6 VSS VCC DQ5 DQ4 30 29 28 27 26 25 24 23 VCAP A14 A13 DQ0 A3 A2 A12 A11 A10 A1 A0 DQ1 DQ2 Xout Xin VRTCcap VRTCbat A16 A14 A12 A7 A6 A5 INT A4 NC NC NC VSS NC VRTCbat 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-pin SSOP (× 8) Top View (not to scale) 48 47 VCC 46 45 44 43 42 41 40 HSB WE A13 A8 A9 39 38 37 36 NC NC NC VSS NC 35 34 33 32 31 30 29 28 27 26 25 A15 NC A11 VRTCcap DQ6 OE A10 CE DQ7 DQ5 DQ4 DQ3 VCC INT [7] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 NC Xout Xin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 54-pin TSOP II (× 16) Top View (not to scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 HSB [6] NC [5] NC [4] NC A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ 11 DQ 10 DQ 9 DQ 8 VCAP A14 A13 A12 A11 A10 NC VRTCcap VRTCbat Notes 4. Address expansion for 2-Mbit. NC pin not connected to die. 5. Address expansion for 4-Mbit. NC pin not connected to die. 6. Address expansion for 8-Mbit. NC pin not connected to die. 7. Address expansion for 16-Mbit. NC pin not connected to die. Document #: 001-42880 Rev. *I Page 3 of 34 [+] Feedback CY14B101KA CY14B101MA Pin Definitions Pin Name A0–A16 A0–A15 DQ0–DQ7 DQ0–DQ15 NC I/O Type Input Input/Output No connect Description Address inputs. Used to select one of the 131,072 Bytes of the nvSRAM for × 8 configuration. Address inputs. Used to select one of the 65,536 Words of the nvSRAM for × 16 configuration. Bidirectional data I/O Lines for × 8 configuration. Used as input or output lines depending on operation. Bidirectional data I/O Lines for × 16 configuration. Used as input or output lines depending on operation. No connects. This pin is not connected to the die. Input Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. Input Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tristate. BHE Input Byte High Enable, Active LOW. Controls DQ15–DQ8. BLE Xout Input Byte Low Enable, Active LOW. Controls DQ7–DQ0. WE CE OE Xin Output Input Crystal connection. Drives crystal on start up. Crystal connection. For 32.768 kHz crystal. VRTCcap Power supply Capacitor supplied backup RTC supply voltage. Left unconnected if VRTCbat is used. VRTCbat Power supply Battery supplied backup RTC supply voltage. Left unconnected if VRTCcap is used. INT Output Interrupt output. Programmable to respond to the clock alarm, the watchdog timer, and the power monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain). VSS Ground Ground for the device. Must be connected to the ground of the system. VCC HSB VCAP Power supply Power supply inputs to the device. 3.0 V +20%, –10% Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. After each Hardware and Software STORE operation HSB is driven HIGH for short time (tHHHD) with standard output high current and then weak internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection optional). Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements. Document #: 001-42880 Rev. *I Page 4 of 34 [+] Feedback CY14B101KA CY14B101MA The CY14B101KA/CY14B101MA nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations SRAM read and write operations are inhibited. The CY14B101KA/CY14B101MA supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 1 million STORE operations. Refer Truth Table For SRAM Operations on page 26 for a complete description of read and write modes. SRAM Read The CY14B101KA/CY14B101MA performs a read cycle whenever CE and OE are LOW, and WE and HSB are HIGH. The address specified on pins A0–16 or A0–15 determines which of the 131,072 data bytes or 65,536 words of 16 bits each are accessed. Byte enables (BHE, BLE) determine which bytes are enabled to the output, in the case of 16-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle #1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle #2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. SRAM Write A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins IO0–7 are written into the memory if it is valid tSD before the end of a WE-controlled write, or before the end of an CE-controlled write. The Byte Enable inputs (BHE, BLE) determine which bytes are written, in the case of 16-bit words. It is recommended that OE be kept HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. AutoStore Operation The CY14B101KA/CY14B101MA stores data to the nvSRAM using one of three storage operations. These three operations are: Hardware STORE, activated by the HSB; Software STORE, activated by an address sequence; AutoStore, on device power-down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B101KA/CY14B101MA. During a normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Note If the capacitor is not connected to VCAP pin, AutoStore must be disabled using the soft sequence specified in Preventing AutoStore on page 7. In case AutoStore is enabled without a capacitor on VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the Store. This corrupts the data stored in nvSRAM. Figure 2. AutoStore Mode VCC 0.1 uF 10 kOhm Device Operation VCC WE VCAP VSS VCAP Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic STORE operation. Refer to DC Electrical Characteristics on page 17 for the size of the VCAP. The voltage on the VCAP pin is driven to VCC by a regulator on the chip. A pull-up should be placed on WE to hold it inactive during power-up. This pull-up is only effective if the WE signal is tristate during power-up. Many MPUs tristate their controls on power-up. This should be verified when using the pull-up. When the nvSRAM comes out of power-on-RECALL, the MPU must be active or the WE held inactive until the MPU comes out of reset. To reduce unnecessary nonvolatile stores, AutoStore and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. Hardware STORE (HSB) Operation The CY14B101KA/CY14B101MA provides the HSB pin to control and acknowledge the STORE operations. The HSB pin is used to request a Hardware STORE cycle. When the HSB pin is driven LOW, the CY14B101KA/CY14B101MA conditionally initiates a STORE operation after tDELAY. An actual STORE cycle begins only if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver (internal 100 k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high Document #: 001-42880 Rev. *I Page 5 of 34 [+] Feedback CY14B101KA CY14B101MA current and then remains HIGH by internal 100 k pull-up resistor. SRAM write operations that are in progress when HSB is driven LOW by any means are given time (tDELAY) to complete before the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. In case the write latch is not set, HSB is not driven LOW by the CY14B101KA/CY14B101MA. But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or other external source. During any STORE operation, regardless of how it is initiated, the CY14B101KA/CY14B101MA continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. Leave the HSB unconnected if it is not used. Hardware RECALL (Power-Up) During power-up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the VSWITCH on powerup, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, the HSB pin is driven LOW by the HSB driver and all reads and writes to nvSRAM are inhibited. Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14B101KA/CY14B101MA Software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8FC0 Initiate STORE cycle The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation. Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A Software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation. To initiate the RECALL cycle, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4C63 Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared. Next, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements. Because a sequence of reads from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. To initiate the Software STORE cycle, the following read sequence must be performed: Document #: 001-42880 Rev. *I Page 6 of 34 [+] Feedback CY14B101KA CY14B101MA Table 1. Mode Selection OE X BHE, BLE[8] X A15–A0[9] X Mode I/O Power Not selected Output high Z Standby H L L X Read SRAM Output data Active L X L X Write SRAM Input data Active L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Output data Output data Output data Output data Output data Output data Active[10] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Output data Output data Output data Output data Output data Output data Active[10] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output data Output data Output data Output data Output data Output high Z Active ICC2[10] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output data Output data Output data Output data Output data Output high Z Active[10] CE H WE X L L Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable To initiate the AutoStore enable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or reenabled, a manual STORE operation (Hardware or Software) issued to save the AutoStore state through subsequent power-down cycles. The part comes from the factory with AutoStore enabled. The AutoStore is reenabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the Software RECALL initiation. Notes 8. BHE and BLE are applicable for × 16 configuration only. 9. While there are 17 address lines on the CY14B101KA (16 address lines on the CY14B101MA), only the 13 address lines (A14–A2) are used to control software modes. The remaining address lines are don’t care. 10. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. Document #: 001-42880 Rev. *I Page 7 of 34 [+] Feedback CY14B101KA CY14B101MA Data Protection The CY14B101KA/CY14B101MA protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY14B101KA/CY14B101MA is in a write mode (both CE and WE are LOW) at power-up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power-up or brown out conditions. Noise Considerations Refer to CY application note AN1064. Real Time Clock Operation nvTIME Operation The CY14B101KA/CY14B101MA offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. RTC registers use the last 16 address locations of the SRAM. Internal double buffering of the clock and timer information registers prevents accessing transitional internal clock data during a read or write operation. Double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data. Clock and alarm registers store data in BCD format. RTC functionality is described with respect to CY14B101KA in the following sections. The same description applies to CY14B101MA, except for the RTC register addresses. The RTC register addresses for CY14B101KA range from 0x1FFF0 to 0x1FFFF, while those for CY14B101MA range from 0x0FFF0 to 0x0FFFF. Refer to Table 3 on page 12 and Table 4 on page 13 for a detailed Register Map description. Clock Operations The clock registers maintain time up to 9,999 years in one second increments. The time can be set to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and century transitions. There are eight registers dedicated to the clock functions, which are used to set time with a write cycle and to read time during a read cycle. These registers contain the time of day in BCD format. Bits defined as ‘0’ are currently not used and are reserved for future use by Cypress. Setting the Clock Setting the write bit ‘W’ (in the flags register at 0x1FFF0) to a ‘1’ stops updates to the time keeping registers and enables the time to be set. The correct day, date, and time is then written into the registers and must be in 24-hour BCD format. The time written is referred to as the “Base Time”. This value is stored in nonvolatile registers and used in the calculation of the current time. Resetting the write bit to ‘0’ transfers the values of timekeeping registers to the actual clock counters, after which the clock resumes normal operation. If the time written to the timekeeping registers is not in the correct BCD format, each invalid nibble of the RTC registers continue counting to 0xF before rolling over to 0x0 after which RTC resumes normal operation. Note After ‘W’ bit is set to ‘0’, values written into the timekeeping, alarm, calibration, and interrupt registers are transferred to the RTC time keeping counters in tRTCp time. These counter values must be saved to nonvolatile memory either by initiating a Software/Hardware STORE or AutoStore operation. While working in AutoStore disabled mode, perform a STORE operation after tRTCp time while writing into the RTC registers for the modifications to be correctly recorded. Backup Power The RTC in the CY14B101KA is intended for permanently powered operation. The VRTCcap or VRTCbat pin is connected depending on whether a capacitor or battery is chosen for the application. When the primary power, VCC, fails and drops below VSWITCH the device switches to the backup power supply. The clock oscillator uses very little current, which maximizes the backup time available from the backup source. Regardless of the clock operation with the primary source removed, the data stored in the nvSRAM is secure, having been stored in the nonvolatile elements when power was lost. During backup operation, the CY14B101KA consumes 0.35 µA (Typical) at room temperature. The user must choose capacitor or battery values according to the application. Backup time values based on maximum current specifications are shown in the following table. Nominal backup times are approximately two times longer. Table 2. RTC Backup Time Capacitor Value Backup Time Reading the Clock 0.1 F 72 hours 0.47 F 14 days The double buffered RTC register structure reduces the chance of reading incorrect data from the clock. Stop internal updates to the CY14B101KA time keeping registers before reading clock data, to prevent reading of data in transition. Stopping the register updates does not affect clock accuracy. 1.0 F 30 days The updating process is stopped by writing a ‘1’ to the read bit ‘R’ (in the flags register at 0x1FFF0), and does not restart until a ‘0’ is written to the read bit. The RTC registers are then read while the internal clock continues to run. After a ‘0’ is written to the read bit (‘R’), all RTC registers are simultaneously updated within 20 ms. Document #: 001-42880 Rev. *I Using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up. If a battery is used, a 3 V lithium is recommended and the CY14B101KA sources current only from the battery when the primary power is removed. However, the battery is not recharged at any time by the CY14B101KA. The battery capacity must be chosen for total anticipated cumulative down time required over the life of the system. Page 8 of 34 [+] Feedback CY14B101KA CY14B101MA Stopping and Starting the Oscillator The OSCEN bit in the calibration register at 0x1FFF8 controls the enable and disable of the oscillator. This bit is nonvolatile and is shipped to customers in the “enabled” (set to 0) state. To preserve the battery life when the system is in storage, OSCEN must be set to ‘1’. This turns off the oscillator circuit, extending the battery life. If the OSCEN bit goes from disabled to enabled, it takes approximately one second (two seconds maximum) for the oscillator to start. While system power is off, if the voltage on the backup supply (VRTCcap or VRTCbat) falls below their respective minimum level, the oscillator may fail.The CY14B101KA has the ability to detect oscillator failure when system power is restored. This is recorded in the oscillator fail bit (OSCF) of the flags register at the address 0x1FFF0. When the device is powered on (VCC goes above VSWITCH) the OSCEN bit is checked for “enabled” status. If the OSCEN bit is enabled and the oscillator is not active within the first 5 ms, the OSCF bit is set to ‘1’. The system must check for this condition and then write ‘0’ to clear the flag. Note that in addition to setting the OSCF flag bit, the time registers are reset to the “Base Time” (see Setting the Clock on page 8), which is the value last written to the timekeeping registers. The control or calibration registers and the OSCEN bit are not affected by the ‘oscillator failed’ condition. Reset the value of OSCF to ‘0’ when the time registers are written for the first time. This initializes the state of this bit which may have become set when the system was first powered on. To reset OSCF, set the write bit ‘W’ (in the flags register at 0x1FFF0) to a ‘1’ to enable writes to the Flag register. Write a ‘0’ to the OSCF bit and then reset the write bit to ‘0’ to disable writes. Calibrating the Clock The RTC is driven by a quartz controlled crystal with a nominal frequency of 32.768 kHz. Clock accuracy depends on the quality of the crystal and calibration. The crystals available in market typically have an error of +20 ppm to +35 ppm. However, CY14B101KA employs a calibration circuit that improves the accuracy to +1/–2 ppm at 25 °C. This implies an error of +2.5 seconds to –5 seconds per month. The calibration circuit adds or subtracts counts from the oscillator divider circuit to achieve this accuracy. The number of pulses that are suppressed (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in calibration register at 0x1FFF8. The calibration bits occupy the five lower order bits in the calibration register. These bits are set to represent any value between ‘0’ and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates positive calibration and a ‘0’ indicates negative calibration. Adding counts speeds the clock up and subtracting counts slows the clock down. If a binary ‘1’ is loaded into the register, it corresponds to an adjustment of 4.068 or –2.034 ppm offset in oscillator error, depending on the sign. Calibration occurs within a 64-minute cycle. The first 62 minutes in the cycle may, once per minute, have one second shortened by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is loaded into the register, only the first two minutes of the 64-minute cycle are modified. If a binary 6 is loaded, the first 12 are affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every Document #: 001-42880 Rev. *I 125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. To determine the required calibration, the CAL bit in the flags register (0x1FFF0) must be set to ‘1’. This causes the INT pin to toggle at a nominal frequency of 512 Hz. Any deviation measured from the 512 Hz indicates the degree and direction of the required correction. For example, a reading of 512.01024 Hz indicates a +20 ppm error. Hence, a decimal value of –10 (001010b) must be loaded into the calibration register to offset this error. Note Setting or changing the calibration register does not affect the test output frequency. To set or clear CAL, set the write bit ‘W’ (in the flags register at 0x1FFF0) to ‘1’ to enable writes to the flags register. Write a value to CAL, and then reset the write bit to ‘0’ to disable writes. Alarm The alarm function compares user programmed values of alarm time and date (stored in the registers 0x1FFF1-5) with the corresponding time of day and date values. When a match occurs, the alarm internal flag (AF) is set and an interrupt is generated on INT pin if alarm interrupt enable (AIE) bit is set. There are four alarm match fields - date, hours, minutes, and seconds. Each of these fields has a match bit that is used to determine if the field is used in the alarm match logic. Setting the match bit to ‘0’ indicates that the corresponding field is used in the match process. Depending on the match bits, the alarm occurs as specifically as once a month or as frequently as once every minute. Selecting none of the match bits (all 1s) indicates that no match is required and therefore, alarm is disabled. Selecting all match bits (all 0s) causes an exact time and date match. There are two ways to detect an alarm event: by reading the AF flag or monitoring the INT pin. The AF flag in the flags register at 0x1FFF0 indicates that a date or time match has occurred. The AF bit is set to ‘1’ when a match occurs. Reading the flags register clears the alarm flag bit (and all others). A hardware interrupt pin may also be used to detect an alarm event. To set, clear or enable an alarm, set the ‘W’ bit (in flags register - 0x1FFF0) to ‘1’ to enable writes to alarm registers. After writing the alarm value, clear the ‘W’ bit back to ‘0’ for the changes to take effect. Note CY14B101KA requires the alarm match bit for seconds (0x1FFF2–D7) to be set to ‘0’ for proper operation of alarm flag and Interrupt. Watchdog Timer The watchdog timer is a free running down counter that uses the 32 Hz clock (31.25 ms) derived from the crystal oscillator. The oscillator must be running for the watchdog to function. It begins counting down from the value loaded in the watchdog timer register. The timer consists of a loadable register and a free running counter. On power-up, the watchdog time out value in register 0x1FFF7 is loaded into the counter load register. Counting begins on power-up and restarts from the loadable value any time the watchdog strobe (WDS) bit is set to ‘1’. The counter is compared to the terminal value of ‘0’. If the counter reaches this value, it causes an internal flag and an optional interrupt output. Page 9 of 34 [+] Feedback CY14B101KA CY14B101MA You can prevent the time out interrupt by setting WDS bit to ‘1’ prior to the counter reaching ‘0’. This causes the counter to reload with the watchdog time out value and to be restarted. As long as the user sets the WDS bit prior to the counter reaching the terminal value, the interrupt and WDT flag never occur. New time out values are written by setting the watchdog write bit to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out value bits D5–D0 are enabled to modify the time out value. When WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function enables a user to set the WDS bit without concern that the watchdog timer value is modified. A logical diagram of the watchdog timer is shown in Figure 3. Note that setting the watchdog time out value to ‘0’ disables the watchdog function. The output of the watchdog timer is the flag bit WDF that is set if the watchdog is allowed to time out. If the watchdog interrupt enable (WIE) bit in the interrupt register is set, a hardware interrupt on INT pin is also generated on watchdog timeout. The flag and the hardware interrupt are both cleared when user reads the flags registers. Figure 3. Watchdog Timer Block Diagram Clock Divider Oscillator 32,768 KHz Zero Compare The CY14B101KA has flags register, interrupt register and interrupt logic that can signal interrupt to the microcontroller. There are three potential sources for interrupt: watchdog timer, power monitor, and alarm timer. Each of these can be individually enabled to drive the INT pin by appropriate setting in the Interrupt register (0x1FFF6). In addition, each has an associated flag bit in the flags register (0x1FFF0) that the host processor uses to determine the cause of the interrupt. The INT pin driver has two bits that specify its behavior when an interrupt occurs. An interrupt is raised only if both a flag is raised by one of the three sources and the respective interrupt enable bit in interrupts register is enabled (set to ‘1’). After an interrupt source is active, two programmable bits, H/L and P/L, determine the behavior of the output pin driver on INT pin. These two bits are located in the interrupt register and can be used to drive level or pulse mode output from the INT pin. In pulse mode, the pulse width is internally fixed at approximately 200 ms. This mode is intended to reset a host microcontroller. In the level mode, the pin goes to its active polarity until the flags register is read by the user. This mode is used as an interrupt to a host microcontroller. The control bits are summarized in the following section. Interrupts are only generated while working on normal power and are not triggered when system is running in backup power mode. 1 Hz 32 Hz Counter Interrupts WDF Note CY14B101KA generates valid interrupts only after the Power-up RECALL sequence is completed. All events on INT pin must be ignored for tHRECALL duration after powerup. Interrupt Register Load Register WDS D Q WDW Q write to Watchdog Register Watchdog Register Power Monitor The CY14B101KA provides a power management scheme with power fail interrupt capability. It also controls the internal switch to backup power for the clock and protects the memory from low VCC access. The power monitor is based on an internal band gap reference circuit that compares the VCC voltage to VSWITCH threshold. As described in the AutoStore Operation on page 5, when VSWITCH is reached as VCC decays from power loss, a data STORE operation is initiated from SRAM to the nonvolatile elements, securing the last SRAM data state. Power is also switched from VCC to the backup supply (battery or capacitor) to operate the RTC oscillator. When operating from the backup source, read and write operations to nvSRAM are inhibited and the RTC functions are not available to the user. The RTC clock continues to operate in the background. The updated RTC time keeping registers data are available to the user after VCC is restored to the device (see AutoStore/Power-Up RECALL on page 23). Document #: 001-42880 Rev. *I Watchdog Interrupt Enable (WIE). When set to ‘1’, the watchdog timer drives the INT pin and an internal flag when a watchdog time out occurs. When WIE is set to ‘0’, the watchdog timer only affects the WDF flag in flags register. Alarm Interrupt Enable (AIE). When set to ‘1’, the alarm match drives the INT pin and an internal flag. When AIE is set to ‘0’, the alarm match only affects the AF flag in flags register. Power Fail Interrupt Enable (PFE). When set to ‘1’, the power fail monitor drives the pin and an internal flag. When PFE is set to ‘0’, the power fail monitor only affects the PF flag in flags register. High/Low (H/L). When set to a ‘1’, the INT pin is active HIGH and the driver mode is push pull. The INT pin drives HIGH only when VCC is greater than VSWITCH. When set to a ‘0’, the INT pin is active LOW and the drive mode is open drain. The INT pin must be pulled up to Vcc by a 10 k resistor while using the interrupt in active LOW mode. Pulse/Level (P/L). When set to a ‘1’ and an interrupt occurs, the INT pin is driven for approximately 200 ms. When P/L is set to a ‘0’, the INT pin is driven HIGH or LOW (determined by H/L) until the flags register is read. When an enabled interrupt source activates the INT pin, an external host reads the flags registers to determine the cause. All flags are cleared when the register is read. If the INT pin is programmed for level mode, then the condition clears and the INT pin returns to its inactive state. If the pin is programmed for pulse mode, then reading the flag also clears the flag and the pin. The pulse does not complete its specified duration if the flags register is read. If the INT pin is used as a host reset, then the flags register is not read during a reset. Page 10 of 34 [+] Feedback CY14B101KA CY14B101MA Flags Register The flags register has three flag bits: WDF, AF, and PF, which can be used to generate an interrupt. These flags are set by the watchdog timeout, alarm match, or power fail monitor respectively. The processor can either poll this register or enable interrupts to be informed when a flag is set. These flags are automatically reset when the register is read. The flags register is automatically loaded with the value 0x00 on power-up (except for the OSCF bit; see Stopping and Starting the Oscillator on page 9). Figure 4. RTC Recommended Component Configuration Recommended Values Y1 = 32.768 kHz (12.5 pF) C1 = 10 pF C2 = 67 pF Note: The recommended values for C1 and C2 include board trace capacitance. C1 Y1 C2 Xout Xin Figure 5. Interrupt Block Diagram WDF Watchdog Timer WIE P/L VCC PF Power Monitor PFE Pin Driver INT VINT H/L WDF - Watchdog Timer Flag WIE - Watchdog Interrupt Enable PF - Power Fail Flag PFE - Power Fail Enable AF - Alarm Flag AIE - Alarm Interrupt Enable P/L - Pulse Level H/L - High/Low VSS AF Clock Alarm AIE Document #: 001-42880 Rev. *I Page 11 of 34 [+] Feedback CY14B101KA CY14B101MA Table 3. RTC Register Map[11, 12, 13] BCD Format Data [12] Register CY14B101KA CY14B101MA D7 D6 D5 D4 D3 D1 D0 Function/Range 0x1FFFF 0x0FFFF 0x1FFFE 0x0FFFE 0 0 0x1FFFD 0x0FFFD 0 0 0x1FFFC 0x0FFFC 0 0 0x1FFFB 0x0FFFB 0 0 0x1FFFA 0x0FFFA 0 10s minutes Minutes Minutes: 00–59 0x1FFF9 0x0FFF9 0 10s seconds Seconds Seconds: 00–59 0x1FFF8 0x0FFF8 OSCEN (0) 0x1FFF7 0x0FFF7 WDS (0) WDW (0) 0x1FFF6 0x0FFF6 WIE (0) AIE (0) 0x1FFF5 0x0FFF5 M (1) 0 10s alarm date Alarm day Alarm, day of month: 01–31 0x1FFF4 0x0FFF4 M (1) 0 10s alarm hours Alarm hours Alarm, hours: 00–23 0x1FFF3 0x0FFF3 M (1) 10 alarm minutes Alarm minutes Alarm, minutes: 00–59 0x1FFF2 0x0FFF2 M (1) 10 alarm seconds Alarm, seconds Alarm, seconds: 00–59 0x1FFF1 0x0FFF1 0x1FFF0 0x0FFF0 10s years D2 0 10s months 10s day of month 0 0 Day of month: 01–31 Day of week Day of week: 01–07 Hours: 00–23 Calibration values [14] Calibration (00000) Cal sign (0) AF Day of month Hours Watchdog [14] WDT (000000) PFE (0) 0 H/L (1) 10s centuries WDF Years: 00–99 Months: 01–12 0 10s hours 0 Years Months PF P/L (0) 0 0 Centuries OSCF[15] 0 CAL (0) W (0) Interrupts [14] Centuries: 00–99 R (0) Flags [14] Notes 11. Upper byte D15–D8 (CY14B101MA) of RTC registers are reserved for future use. 12. The unused bits of RTC registers are reserved for future use and should be set to ‘0’. 13. ( ) designates values shipped from the factory. 14. This is a binary value, not a BCD value. 15. When user resets OSCF flag bit, the flags register will be updated after tRTCp time. Document #: 001-42880 Rev. *I Page 12 of 34 [+] Feedback CY14B101KA CY14B101MA Table 4. Register Map Detail Register CY14B101KA CY14B101MA 0x1FFFF 0x0FFFF Description Time Keeping - Years D7 D6 D5 D4 D3 D2 10s years D1 D0 Years Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99. 0x1FFFE 0x0FFFE Time Keeping - Months D7 D6 D5 D4 0 0 0 10s month D3 D2 D1 D0 Months Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1–12. 0x1FFFD 0x0FFFD Time Keeping - Date D7 D6 0 0 D5 D4 D3 10s day of month D2 D1 D0 Day of month Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3. The range for the register is 1–31. Leap years are automatically adjusted for. 0x1FFFC 0x0FFFC Time Keeping - Day D7 D6 D5 D4 D3 0 0 0 0 0 D2 D1 D0 Day of week Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, because the day is not integrated with the date. 0x1FFFB 0x0FFFB Time Keeping - Hours D7 D6 0 0 D5 D4 D3 D2 10s hours D1 D0 Hours Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0–23. 0x1FFFA 0x0FFFA Time Keeping - Minutes D7 D6 0 D5 D4 D3 D2 10s minutes D1 D0 Minutes Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5. The range for the register is 0–59. 0x1FFF9 0x0FFF9 Time Keeping - Seconds D7 0 D6 D5 10s seconds D4 D3 D2 D1 D0 Seconds Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper digit and operates from 0 to 5. The range for the register is 0–59. Document #: 001-42880 Rev. *I Page 13 of 34 [+] Feedback CY14B101KA CY14B101MA Table 4. Register Map Detail (continued) Register CY14B101KA CY14B101MA 0x1FFF8 0x0FFF8 Description Calibration/Control D7 D6 D5 OSCEN 0 Calibration sign D4 D3 D2 D1 D0 Calibration OSCEN Oscillator enable. When set to ‘1’, the oscillator is stopped. When set to ‘0’, the oscillator runs. Disabling the oscillator saves battery or capacitor power during storage. Calibration Sign Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base. Calibration 0x1FFF7 0x0FFF7 These five bits control the calibration of the clock. WatchDog Timer D7 D6 WDS WDW D5 D4 D3 D2 D1 D0 WDT WDS Watchdog strobe. Setting this bit to ‘1’ reloads and restarts the watchdog timer. Setting the bit to ‘0’ has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0. WDW Watchdog write enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value (D5–D0). This allows the user to set the watchdog strobe bit without disturbing the timeout value. Setting this bit to ‘0’ allows bits D5–D0 to be written to the watchdog register when the next write cycle is complete. This function is explained in more detail in Watchdog Timer on page 9. WDT Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a multiplier of the 32 Hz count (31.25 ms). The range of timeout value is 31.25 ms (a setting of 1) to 2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit was set to 0 on a previous cycle. 0x1FFF6 0x0FFF6 Interrupt Status/Control D7 D6 D5 D4 D3 D2 D1 D0 WIE AIE PFE 0 H/L P/L 0 0 WIE Watchdog interrupt enable. When set to ‘1’ and a watchdog timeout occurs, the watchdog timer drives the INT pin and the WDF flag. When set to ‘0’, the watchdog timeout affects only the WDF flag. AIE Alarm interrupt enable. When set to ‘1’, the alarm match drives the INT pin and the AF flag. When set to ‘0’, the alarm match only affects the AF flag. PFE Power fail enable. When set to ‘1’, the power fail monitor drives the INT pin and the PF flag. When set to ‘0’, the power fail monitor affects only the PF flag. 0 Reserved for future use H/L High/Low. When set to ‘1’, the INT pin is driven active HIGH. When set to ‘0’, the INT pin is open drain, active LOW. P/L Pulse/Level. When set to ‘1’, the INT pin is driven active (determined by H/L) by an interrupt source for approximately 200 ms. When set to ‘0’, the INT pin is driven to an active level (as set by H/L) until the flags register is read. 0x1FFF5 0x0FFF5 Alarm - Day D7 D6 M 0 D5 D4 10s alarm date D3 D2 D1 D0 Alarm date Contains the alarm value for the date of the month and the mask bit to select or deselect the date value. M Document #: 001-42880 Rev. *I Match. When this bit is set to ‘0’, the date value is used in the alarm match. Setting this bit to ‘1’ causes the match circuit to ignore the date value. Page 14 of 34 [+] Feedback CY14B101KA CY14B101MA Table 4. Register Map Detail (continued) Register CY14B101KA CY14B101MA 0x1FFF4 0x0FFF4 Description Alarm - Hours D7 D6 M 0 D5 D4 D3 10s alarm hours D2 D1 D0 Alarm hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value. M 0x1FFF3 Match. When this bit is set to ‘0’, the hours value is used in the alarm match. Setting this bit to ‘1’ causes the match circuit to ignore the hours value. 0x0FFF3 Alarm - Minutes D7 D6 M D5 D4 D3 10s alarm minutes D2 D1 D0 Alarm minutes Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value. M 0x1FFF2 Match. When this bit is set to ‘0’, the minutes value is used in the alarm match. Setting this bit to ‘1’ causes the match circuit to ignore the minutes value. 0x0FFF2 Alarm - Seconds D7 D6 M D5 D4 D3 10s alarm seconds D2 D1 D0 Alarm seconds Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value. M 0x1FFF1 Match. When this bit is set to ‘0’, the seconds value is used in the alarm match. Setting this bit to ‘1’ causes the match circuit to ignore the seconds value. 0x0FFF1 Time Keeping - Centuries D7 D6 D5 D4 D3 D2 10s centuries D1 D0 Centuries Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 9. The range for the register is 0–99 centuries. 0x1FFF0 0x0FFF0 Flags D7 D6 D5 D4 D3 D2 D1 D0 WDF AF PF OSCF 0 CAL W R WDF Watchdog timer flag. This read only bit is set to ‘1’ when the watchdog timer is allowed to reach 0 without being reset by the user. It is cleared to 0 when the flags register is read or on power-up AF Alarm flag. This read only bit is set to ‘1’ when the time and date match the values stored in the alarm registers with the match bits = 0. It is cleared when the flags register is read or on power-up. PF Power fail flag. This read only bit is set to ‘1’ when power falls below the power fail threshold VSWITCH. It is cleared to 0 when the flags register is read or on power-up. OSCF Oscillator fail flag. Set to ‘1’ on power-up if the oscillator is enabled and not running in the first 5 ms of operation. This indicates that RTC backup power failed and clock value is no longer valid. This bit survives the power cycle and is never cleared internally by the chip. The user must check for this condition and write '0' to clear this flag. When user resets OSCF flag bit, the bit will be updated after tRTCp time. CAL Calibration mode. When set to ‘1’, a 512 Hz square wave is output on the INT pin. When set to ‘0’, the INT pin resumes normal operation. This bit defaults to ‘0’ (disabled) on power-up. W Write enable: Setting the ‘W’ bit to ‘1’ freezes updates of the RTC registers. The user can then write to RTC registers, alarm registers, calibration register, interrupt register and flags register. Setting the ‘W’ bit to ‘0’ causes the contents of the RTC registers to be transferred to the time keeping counters if the time has changed. This transfer process takes tRTCp time to complete. This bit defaults to 0 on power-up. R Read enable: Setting ‘R’ bit to ‘1’, stops clock updates to user RTC registers so that clock updates are not seen during the reading process. Set ‘R’ bit to ‘0’ to resume clock updates to the holding register. Setting this bit does not require ‘W’ bit to be set to ‘1’. This bit defaults to 0 on power-up. Document #: 001-42880 Rev. *I Page 15 of 34 [+] Feedback CY14B101KA CY14B101MA Best Practices ■ Power-up boot firmware routines should rewrite the nvSRAM into the desired state (for example, AutoStore enabled). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently such as program bugs and incoming inspection routines. ■ The VCAP value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the maximum VCAP value because the nvSRAM internal algorithm calculates VCAP charge and discharge time based on this maximum VCAP value. Customers that want to use a larger VCAP value to make sure there is extra store charge and store time should discuss their VCAP size selection with Cypress to understand any impact on the VCAP voltage level at the end of a tRECALL period. ■ When base time is updated, these updates are transferred to the time keeping registers when ‘W’ bit is set to ‘0’. This transfer takes tRTCp time to complete. It is recommended to initiate software STORE or Hardware STORE after tRTCp time to save the base time into nonvolatile memory. nvSRAM products have been used effectively for over 27 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: ■ The nonvolatile cells in this nvSRAM product are delivered from Cypress with 0x00 written in all cells. Incoming inspection routines at customer or contract manufacturer’s sites sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End product’s firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. Document #: 001-42880 Rev. *I Page 16 of 34 [+] Feedback CY14B101KA CY14B101MA Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Maximum accumulated storage time Transient voltage (< 20 ns) on any pin to ground potential ................. –2.0 V to VCC + 2.0 V Package power dissipation capability (TA = 25 °C) ................................................. 1.0 W Surface mount Pb soldering temperature (3 seconds) ......................................... +260 C At 150 C ambient temperature ...................... 1000 h DC output current (1 output at a time, 1s duration) .... 15 mA At 85 C ambient temperature .................... 20 Years Static discharge voltage (per MIL-STD-883, Method 3015) ......................... > 2001 V Ambient temperature with power applied ................................... –55 C to +150 C Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V Voltage applied to outputs in High Z state .................................... –0.5 V to VCC + 0.5 V Input voltage ....................................... –0.5 V to VCC + 0.5 V Latch up current ............................................... ..... > 200 mA Operating Range Range Ambient Temperature VCC –40 C to +85 C 2.7 V to 3.6 V Industrial DC Electrical Characteristics Over the Operating Range (VCC = 2.7 V to 3.6 V) Parameter Description Test Conditions Min Typ [16] Max Unit 2.7 3.0 3.6 V VCC Power supply voltage ICC1 Average Vcc current tRC = 25 ns tRC = 45 ns Values obtained without output loads (IOUT = 0 mA) – – 70 52 mA mA ICC2 Average VCC current during STORE All inputs don’t care, VCC = Max. Average current for duration tSTORE – – 10 mA ICC3[16] Average VCC current at tRC= 200 ns, VCC(Typ), 25 °C All inputs cycling at CMOS levels. Values obtained without output loads (IOUT = 0 mA). – 35 – mA ICC4 Average VCAP current during AutoStore cycle All inputs don’t care. Average current for duration tSTORE – – 5 mA ISB VCC standby current CE > (VCC – 0.2 V). VIN < 0.2 V or > (VCC – 0.2 V). W bit set to ‘0’. Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. – – 5 mA IIX[17] Input leakage current (except HSB) VCC = Max, VSS < VIN < VCC –1 – +1 µA Input leakage current (for HSB) VCC = Max, VSS < VIN < VCC –100 – +1 µA IOZ Off state output leakage current VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or BHE/BLE > VIH or WE < VIL –1 – +1 µA VIH Input HIGH voltage 2.0 – VCC + 0.5 V VSS – 0.5 – 0.8 V 2.4 – – V VIL Input LOW voltage VOH Output HIGH voltage IOUT = –2 mA VOL Output LOW voltage IOUT = 4 mA – – 0.4 V VCAP[18] Storage capacitor Between VCAP pin and VSS, 5 V rated 61 68 180 µF Notes 16. Typical values are at 25 °C, VCC = VCC(Typ). Not 100% tested. 17. The HSB pin has IOUT = –2 µA for VOH of 2.4 V when both active HIGH and low drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested. 18. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options. Document #: 001-42880 Rev. *I Page 17 of 34 [+] Feedback CY14B101KA CY14B101MA Data Retention and Endurance Over the Operating Range Parameter Description DATAR Data retention NVC Nonvolatile STORE operations Min Unit 20 Years 1,000 K Max Unit Capacitance Parameter[19] Description Test Conditions Input capacitance (except BHE, BLE and HSB) CIN COUT TA = 25 C, f = 1 MHz, VCC = VCC(Typ) 7 pF Input capacitance (for BHE, BLE and HSB) 8 pF Output capacitance (except HSB) 7 pF Output capacitance (for HSB) 8 pF Thermal Resistance Parameter[19] Test Conditions 48-pin SSOP Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 37.47 41.74 36.4 C/W 24.71 11.90 10.13 C/W Description JA Thermal resistance (Junction to ambient) JC Thermal resistance (Junction to case) 44-pin 54-pin TSOP II TSOP II Unit AC Test Loads Figure 6. AC Test Loads 577 577 3.0 V 3.0 V R1 R1 OUTPUT OUTPUT 30 pF R2 789 5 pF R2 789 AC Test Conditions Input pulse levels ...................................................0 V to 3 V Input rise and fall times (10%–90%) ........................... < 3 ns Input and output timing reference levels ....................... 1.5 V Note 19. These parameters are guaranteed by design and are not tested. Document #: 001-42880 Rev. *I Page 18 of 34 [+] Feedback CY14B101KA CY14B101MA RTC Characteristics Over the Operating Range Parameter Description VRTCbat RTC battery pin voltage IBAK[21] RTC backup current VRTCcap[22] RTC capacitor pin voltage Min Typ [20] Max Units 1.8 3.0 3.6 V TA (Min) – – 0.35 µA 25 °C – 0.35 – µA TA (Max) – – 0.5 µA TA (Min) 1.6 – 3.6 V 25 °C 1.5 3.0 3.6 V TA (Max) 1.4 – 3.6 V tOCS RTC oscillator time to start – 1 2 sec tRTCp RTC processing time from end of ‘W’ bit set to ‘0’ – – 350 s RBKCHG RTC backup capacitor charge current-limiting resistor 350 – 850 Notes 20. These parameters are guaranteed by design and are not tested. 21. From either VRTCcap or VRTCbat. 22. If VRTCcap > 0.5 V or if no capacitor is connected to VRTCcap pin, the oscillator starts in tOCS time. If a backup capacitor is connected and VRTCcap < 0.5 V, the capacitor must be allowed to charge to 0.5 V for oscillator to start. Document #: 001-42880 Rev. *I Page 19 of 34 [+] Feedback CY14B101KA CY14B101MA AC Switching Characteristics Over the Operating Range Parameters [23] Cypress Alt Parameter Parameter SRAM Read Cycle tACS tACE tRC tRC [24] 25 ns Description 45 ns Unit Min Max Min Max Chip enable access time Read cycle time – 25 25 – – 45 45 – ns ns tAA [25] tAA Address access time – 25 – 45 ns tDOE tOE Output enable to data valid – 12 – 20 ns tOHA[25] tLZCE [26, 27] tHZCE [26, 27] tLZOE [26, 27] tHZOE [26, 27] tPU [26] tPD [26] tOH Output hold after address change 3 – 3 – ns tLZ Chip enable to output active 3 – 3 – ns tHZ Chip disable to output inactive – 10 – 15 ns tOLZ Output enable to output active 0 – 0 – ns tOHZ Output disable to output inactive – 10 – 15 ns tPA Chip enable to power active 0 – 0 – ns tPS Chip disable to power standby – 25 – 45 ns – tDBE – tLZBE[26] – tHZBE[26] SRAM Write Cycle tWC tWC tWP tPWE tCW tSCE tDW tSD tDH tHD tAW tAW tAS tSA tWR tHA [26, 27, 28] tWZ tHZWE Byte enable to data valid Byte enable to output active Byte disable to output inactive – 0 – 12 – 10 – 0 – 20 – 15 ns ns ns Write cycle time Write pulse width Chip enable to end of write Data setup to end of write Data hold after end of write Address setup to end of write Address setup to start of write Address hold after end of write Write enable to output disable 25 20 20 10 0 20 0 0 – – – – – – – – – 10 45 30 30 15 0 30 0 0 – – – – – – – – – 15 ns ns ns ns ns ns ns ns ns tOW Output active after end of write 3 – 3 – ns - Byte enable to end of write 20 – 30 – ns tLZWE [26, 27] tBW Switching Waveforms Figure 7. SRAM Read Cycle #1 (Address Controlled) [24, 25, 29] tRC Address Address Valid tAA Data Output Previous Data Valid Output Data Valid tOHA Notes 23. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH and load capacitance shown in Figure 6 on page 18. 24. WE must be HIGH during SRAM read cycles. 25. Device is continuously selected with CE, OE, and BHE/BLE LOW. 26. These parameters are guaranteed by design and are not tested. 27. Measured ±200 mV from steady state output voltage. 28. If WE is low when CE goes low, the outputs remain in the high impedance state. 29. HSB must remain HIGH during Read and Write cycles. Document #: 001-42880 Rev. *I Page 20 of 34 [+] Feedback CY14B101KA CY14B101MA Switching Waveforms (continued) Figure 8. SRAM Read Cycle #2 (CE and OE Controlled) [30, 31, 32] Address Address Valid tRC tHZCE tACE CE tAA tLZCE tHZOE tDOE OE tHZBE tLZOE tDBE BHE, BLE tLZBE Data Output High Impedance Output Data Valid tPU ICC tPD Active Standby Figure 9. SRAM Write Cycle #1 (WE Controlled) [30, 32, 33, 34] tWC Address Address Valid tSCE tHA CE tBW BHE, BLE tAW tPWE WE tSA tSD Data Input Input Data Valid tHZWE Data Output tHD Previous Data tLZWE High Impedance Note 30. BHE and BLE are applicable for × 16 configuration only. 31. WE must be HIGH during SRAM read cycles. 32. HSB must remain HIGH during read and write cycles. 33. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 34. CE or WE must be VIH during address transitions. Document #: 001-42880 Rev. *I Page 21 of 34 [+] Feedback CY14B101KA CY14B101MA Switching Waveforms (continued) Figure 10. SRAM Write Cycle #2 (CE Controlled) [35, 36, 37, 38] tWC Address Valid Address tSA tSCE tHA CE tBW BHE, BLE tPWE WE tHD tSD Input Data Valid Data Input High Impedance Data Output Figure 11. SRAM Write Cycle #3 (BHE and BLE Controlled) [36, 37, 38, 39, 40] (Not applicable for RTC register writes) tWC Address Address Valid tSCE CE tSA tHA tBW BHE, BLE tAW tPWE WE tSD Data Input tHD Input Data Valid High Impedance Data Output Note 35. BHE and BLE are applicable for × 16 configuration only. 36. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 37. HSB must remain HIGH during read and write cycles. 38. CE or WE must be VIH during address transitions. 39. While there are 19 address lines on the CY14B101KA (18 address lines on the CY14B101MA), only 13 address lines (A14–A2) are used to control software modes. The remaining address lines are don’t care. 40. Only CE and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register. Document #: 001-42880 Rev. *I Page 22 of 34 [+] Feedback CY14B101KA CY14B101MA AutoStore/Power-Up RECALL Over the Operating Range Parameter tHRECALL [41] CY14B101KA/CY14B101MA Min Max – 20 Description Power-Up RECALL duration Unit ms tSTORE [42] STORE cycle duration – 8 ms tDELAY [43] Time allowed to complete SRAM write cycle – 25 ns Low voltage trigger level – 2.65 V 150 – µs HSB output disable voltage – 1.9 V HSB to output active time HSB high active time – – 5 500 µs ns VSWITCH tVCCRISE [44] VHDIS[44] tLZHSB[44] tHHHD[44] VCC rise time Switching Waveforms Figure 12. AutoStore or Power-Up RECALL [45] VCC VSWITCH VHDIS t VCCRISE Note 42 tHHHD Note 42 tSTORE Note tHHHD 46 tSTORE 46 Note HSB OUT tDELAY tLZHSB AutoStore tLZHSB tDELAY POWERUP RECALL tHRECALL tHRECALL Read & Write Inhibited (RWI) POWER-UP RECALL Read & Write BROWN OUT AutoStore POWER-UP RECALL Read & Write POWER DOWN AutoStore Notes 41. tHRECALL starts from the time VCC rises above VSWITCH. 42. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place 43. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 44. These parameters are guaranteed by design and are not tested. 45. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 46. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor. Document #: 001-42880 Rev. *I Page 23 of 34 [+] Feedback CY14B101KA CY14B101MA Software Controlled STORE/RECALL Cycle Over the Operating Range Parameter [47, 48] tRC tSA tCW tHA tRECALL tSS [49, 50] 25 ns Description 45 ns Min 25 0 20 0 – – STORE/RECALL initiation cycle time Address setup time Clock pulse width Address hold time RECALL duration Soft sequence processing time Max – – – – 200 100 Min 45 0 30 0 – – Max – – – – 200 100 Unit ns ns ns ns µs µs Switching Waveforms Figure 13. CE & OE Controlled Software STORE/RECALL Cycle [48] tRC Address tRC Address #1 tSA Address #6 tCW tCW CE tHA tSA tHA tHA tHA OE tHHHD HSB (STORE only) tHZCE tLZCE t DELAY 51 Note tLZHSB High Impedance tSTORE/tRECALL DQ (DATA) RWI Figure 14. AutoStore Enable/Disable Cycle Address tSA CE tRC tRC Address #1 Address #6 tCW tCW tHA tSA tHA tHA tHA OE tLZCE tHZCE tSS 51 Note t DELAY DQ (DATA) Notes 47. The software sequence is clocked with CE controlled or OE controlled reads. 48. The six consecutive addresses must be read in the order listed in Table 1. WE must be HIGH during all six consecutive cycles. 49. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command. 50. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. 51. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time. Document #: 001-42880 Rev. *I Page 24 of 34 [+] Feedback CY14B101KA CY14B101MA Hardware STORE Cycle Over the Operating Range Parameter CY14B101KA/CY14B101MA Description Min Max Unit tDHSB HSB to output active time when write latch not set – 25 ns tPHSB Hardware STORE pulse width 15 – ns Switching Waveforms Figure 15. Hardware STORE Cycle [52] Write latch set tPHSB HSB (IN) tSTORE tHHHD tDELAY HSB (OUT) tLZHSB DQ (Data Out) RWI Write latch not set tPHSB HSB pin is driven high to VCC only by Internal 100 kOhm resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven low. HSB (IN) tDELAY HSB (OUT) tDHSB tDHSB RWI Figure 16. Soft Sequence Processing [53, 54] Soft Sequence Command Address Address #1 tSA Address #6 tCW tSS Soft Sequence Command Address #1 tSS Address #6 tCW CE VCC Notes 52. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. 53. This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command. 54. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. Document #: 001-42880 Rev. *I Page 25 of 34 [+] Feedback CY14B101KA CY14B101MA Truth Table For SRAM Operations HSB must remain HIGH for SRAM operations. Table 5. Truth Table for × 8 Configuration CE Inputs/Outputs[55] WE OE Mode Power H X X High Z Deselect/Power-down Standby L H L Data out (DQ0–DQ7) Read Active L H H High Z Output disabled Active L L X Data in (DQ0–DQ7) Write Active Table 6. Truth Table for × 16 Configuration BHE[56] BLE[56] Inputs/Outputs[55] CE WE OE Mode Power H X X X X High Z Deselect/Power-down Standby L X X H H High Z Output disabled Active L H L L L Data out (DQ0–DQ15) Read Active L H L H L Data out (DQ0–DQ7) DQ8–DQ15 in High Z Read Active L H L L H Data out (DQ8–DQ15) DQ0–DQ7 in High Z Read Active L H H L L High Z Output disabled Active L H H H L High Z Output disabled Active L H H L H High Z Output disabled Active L L X L L Data in (DQ0–DQ15) Write Active L L X H L Data in (DQ0–DQ7) DQ8–DQ15 in High Z Write Active L L X L H Data in (DQ8–DQ15) DQ0–DQ7 in High Z Write Active Notes 55. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration. 56. BHE and BLE are applicable for × 16 configuration only. Document #: 001-42880 Rev. *I Page 26 of 34 [+] Feedback CY14B101KA CY14B101MA Ordering Information Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) 25 45 Ordering Code Package Diagram Package Type CY14B101KA-ZS25XIT 51-85087 44-pin TSOP II CY14B101KA-ZS25XI 51-85087 44-pin TSOP II CY14B101KA-SP25XIT 51-85061 48-pin SSOP CY14B101KA-SP25XI 51-85061 48-pin SSOP CY14B101KA-ZS45XIT 51-85087 44-pin TSOP II CY14B101KA-ZS45XI 51-85087 44-pin TSOP II CY14B101KA-SP45XIT 51-85061 48-pin SSOP CY14B101KA-SP45XI 51-85061 48-pin SSOP Operating Range Industrial All the above parts are Pb-free. Ordering Code Definitions CY 14 B 101 K A - ZS 25 X I T Option: T - Tape and Reel Blank - Std. Pb-free Temperature: I - Industrial (–40 to 85 °C) Speed: 25 - 25 ns 45 - 45 ns Package: Die revision: Blank - No Rev A - First Rev ZS - 44-pin TSOP II SP - 48-pin SSOP Data Bus: K - × 8 + RTC M - × 16 + RTC Voltage: B - 3.0 V Density: 101 - 1 Mb 14 - nvSRAM Cypress Document #: 001-42880 Rev. *I Page 27 of 34 [+] Feedback CY14B101KA CY14B101MA Package Diagrams Figure 17. 44-pin TSOP II, 51-85087 51-85087 *C Figure 18. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm), 51-85160 51-85160 *A Document #: 001-42880 Rev. *I Page 28 of 34 [+] Feedback CY14B101KA CY14B101MA Package Diagrams (continued) Figure 19. 48-pin SSOP (300 Mils), 51-85061 51-85061 *D Document #: 001-42880 Rev. *I Page 29 of 34 [+] Feedback CY14B101KA CY14B101MA Document Conventions Acronyms Acronym Description Units of Measure BCD binary coded decimal BHE byte high enable °C degree Celsius BLE byte low enable F Farads CE CMOS chip enable Hz Hertz complementary metal oxide semiconductor kbit 1024 bits EIA electronic industries alliance kHz kilo Hertz HSB I/O hardware store busy k kilo ohms input/output MHz Mega Hertz nvSRAM non-volatile static random access memory A micro Amperes OE RoHS output enable F micro Farads restriction of hazardous substances s micro seconds RWI read and write inhibited mA milli Amperes RTC real time clock ms milli seconds SRAM static random access memory ns nano seconds SSOP shrink small outline package ohms TSOP thin small outline package % percent WE write enable pF pico Farads ppm parts per million V Volts W Watts Document #: 001-42880 Rev. *I Symbol Unit of Measure Page 30 of 34 [+] Feedback CY14B101KA CY14B101MA Document History Page Document Title: CY14B101KA/CY14B101MA, 1-Mbit (128 K × 8/64 K × 16) nvSRAM with Real Time Clock Document Number: 001-42880 Orig. of Rev. ECN No. Submission Description of Change Date Change ** 2050747 See ECN UNC / New Data Sheet PYRS *A 2607447 11/18/2008 GVCH / Removed 15 ns access speed, updated “Features”, added CY14B101MA AESA (x16) part, changed title to “CY14B101KA/CY14B101MA, 1-Mbit (128K x 8/64K x 16) nvSRAM with Real-Time-Clock”. Added 54-pin TSOP II package related information, updated Logic block diagram, added footnote 1 and 2. Pin definition: Updated WE, HSB and NC pin description. Page 4: Updated SRAM READ, SRAM WRITE, Autostore operation description, Page 4: Updated Software store and software recall description Updated Figure 2, Page 4: Updated Hardware store operation and Hardware RECALL (Power up) description Footnote 1 and 10 referenced for Mode selection Table Added footnote 10, updated footnote 8 and 9 Page 6: updated Data protection description Page 6: Updated starting and stopping the oscillator description Page 7: Updated Calibrating the clock description Page 8: Added Flags register Updated table 4, added footnote 12 and 13 Updated Register map detail Table 5 Maximum Ratings: Added Max. Accumulated storage time Changed Output short circuit current parameter name to DC output current Changed ICC2 from 6 mA to 10 mA Changed ICC3 from 15 mA to 35 mA Changed ICC4 from 6 mA to 5 mA Changed ISB from 3 mA to 5 mA Added IIX for HSB Updated ICC1, ICC3, ISB and IOZ Test conditions Changed VCAP voltage min value from 68uF to 61uF Added VCAP voltage max value to 180uF Updated footnote 14 and 15, added footnote 16 Added Data retention and Endurance Table Added thermal resistance value to 44/54 TSOP II packages Updated Input Rise and Fall time in AC test Conditions Changed VRTCcap min value from 1.2 to 1.5V for industrial Commercial temperature Changed VRTCcap min value from 2.7 to 3.6V for industrial Commercial temperature Updated RTC recommended component configuration values Updated tOCS value for minimum and room temperature from 10 and 5sec to 2 and 1sec resp. Referenced footnote 22 to tOHA parameter Updated All switching waveforms Updated footnote 22, added footnote 25 Added Figure 11 (SRAM WRITE CYCLE:BHE and BLE controlled) Changed tSTORE max value from 15ms to 8ms Updated tDELAY value Added VHDIS, tHHHD and tLZHSB parameters Updated footnote 29, added footnote 31 and 32 Software controlled STORE/RECALL Table: Changed tAS to tSA Changed tGHAX to tHA, changed tHA value from 1ns to 0ns Added Figure 14 Added tDHSB parameter, changed tHLHX to tPHSB Updated tSS from 70 us to 100 us, added truth table for SRAM operations Updated ordering information and part numbering nomenclature Document #: 001-42880 Rev. *I Page 31 of 34 [+] Feedback CY14B101KA CY14B101MA Document History Page (continued) Document Title: CY14B101KA/CY14B101MA, 1-Mbit (128 K × 8/64 K × 16) nvSRAM with Real Time Clock Document Number: 001-42880 Orig. of Rev. ECN No. Submission Description of Change Date Change *B 2654484 02/05/09 GVCH / Changed the data sheet from Advance information to Preliminary PYRS Changed X1, X2 pin names to Xout, Xin respectively Updated Real Time Clock operation description Added footnotes 11 and 12 Added default values to RTC Register Map” table 3 Updated flag register description in Register Map Detail” table 4 Changed C1, C2 values to 21pF, 21pF respectively Changed IBAK value from 350 nA to 450 nA at hot temperature Changed VRTCcap typical value from 2.4V to 3.0V Referenced Note 15 to parameters tLZCE, tHZCE, tLZOE, tHZOE, tLZBE, tLZWE, tHZWEand tHZBE Added footnote 24 Updated Figure 13 *C 2733909 07/09/09 GVCH / Page 3; Added note to AutoStore Operation description AESA Page 4; Updated Hardware STORE (HSB) Operation description Page 4; Updated Software STORE Operation description Added best practices Changed C1, C2 values to 10pF, 67pF respectively Changed IBAK and VRTCcap parameter values Added RBKCHG parameter Updated VHDIS parameter description Updated tDELAY parameter description Updated footnote 28 and added footnote 35 *D 2757375 08/28/09 GVCH Moved data sheet status from Preliminary to Final Removed commercial temperature related specs Removed 20ns access speed related specs Updated Thermal resistance values for all the packages Changed VRTCbat max value from 3.3V to 3.6V Changed RBKCHG min value from 450to 350 Updated footnote 18 *E 2767333 01/06/10 GVCH / Changed STORE cycles to QuantumTrap from 200K to 1 Million PYRS Added Data Retention and Endurance table Updated IBAK RTC backup current spec unit from nA to A Added Contents. *F 2899937 03/26/10 GVCH Added more clarity on HSB pin operation Table 1: Added more clarity on BHE/BLE pin opeartion Updated HSB pin operation in Switching Waveforms Updated footnote 30 Updated Ordering Information table. Updated package diagrams. Updated copyright section. *G 3134300 01/11/2011 GVCH Updated Setting the Clock description Added footnote 15 Updated ‘W’ bit desription in Register Map Detail table Updated best practices Updated input capacitance for BHE and BLE pin Updated input and output capacitance for HSB pin Added tRTCp parameter to RTC Characteristics table Figure 12: Typo error fixed Added Acronyms table and Document Conventions table *H 3150308 01/21/2011 GVCH No technical updates Document #: 001-42880 Rev. *I Page 32 of 34 [+] Feedback CY14B101KA CY14B101MA Document History Page (continued) Document Title: CY14B101KA/CY14B101MA, 1-Mbit (128 K × 8/64 K × 16) nvSRAM with Real Time Clock Document Number: 001-42880 Orig. of Rev. ECN No. Submission Description of Change Date Change *I 3313245 07/14/2011 GVCH Updated DC Electrical Characteristics (Added Note 18 and referred the same note in VCAP parameter). Updated AC Switching Characteristics (Added Note 23 and referred the same note in Parameters). Document #: 001-42880 Rev. *I Page 33 of 34 [+] Feedback CY14B101KA CY14B101MA Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2008-2011. 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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-42880 Rev. *I Revised July 22, 2011 Page 34 of 34 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback