CY14B108K CY14B108M 8-Mbit (1024 K × 8/512 K × 16) nvSRAM with Real Time Clock 8-Mbit (1024 K × 8/512 K × 16) nvSRAM with Real Time Clock Features ■ 25 ns and 45 ns access times ■ Internally organized as 1024 K × 8 (CY14B108K) or 512 K × 16 (CY14B108M) ■ Hands off automatic STORE on power-down with only a small capacitor ■ STORE to QuantumTrap nonvolatile elements is initiated by software, device pin, or AutoStore on power-down ■ RECALL to SRAM initiated by software or power-up ■ High reliability ■ Infinite Read, Write, and RECALL cycles ■ 1 million STORE cycles to QuantumTrap ■ 20 year data retention ■ Single 3 V +20%, –10% operation ■ Data integrity of Cypress nonvolatile static RAM (nvSRAM) combined with full-featured real time clock (RTC) ■ Watchdog timer ■ Clock alarm with programmable interrupts ■ Capacitor or battery backup for RTC ■ Industrial temperature ■ 44 and 54-pin thin small outline package (TSOP) Type II ■ Pb-free and restriction of hazardous substances (RoHS) compliant Functional Description The Cypress CY14B108K/CY14B108M combines a 8-Mbit nonvolatile static RAM (nvSRAM) with a full featured RTC in a monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM is read and written infinite number of times, while independent nonvolatile data resides in the nonvolatile elements. The RTC function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The alarm function is programmable for periodic minutes, hours, days, or months alarms. There is also a programmable watchdog timer for process control. For a complete list of related documentation, click here. Errata: AutoStore Disable feature does not work in the device. For more information, see Errata on page 33. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Cypress Semiconductor Corporation Document Number: 001-47378 Rev. *M • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 8, 2015 CY14B108K CY14B108M Logic Block Diagram [1, 2, 3] Quatrum Trap 2048 X 2048 X 2 A0 A1 A2 R O W A3 A4 A5 A6 A7 A8 A17 A18 D E C O D E R STORE VCC VCAP POWER CONTROL VRTCbat VRTCcap RECALL STATIC RAM ARRAY 2048 X 2048 X 2 STORE/RECALL CONTROL SOFTWARE DETECT HSB A14 - A2 A 19 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 RTC I N P U T B U F F E R S Xout Xin INT COLUMN I/O MUX A19- A 0 OE COLUMN DEC WE DQ12 DQ13 CE DQ14 DQ15 A9 A10 A11 A12 A13 A14 A15 A16 BLE BHE Notes 1. Address A0–A19 for × 8 configuration and Address A0–A18 for × 16 configuration. 2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration. 3. BHE and BLE are applicable for × 16 configuration only. Document Number: 001-47378 Rev. *M Page 2 of 36 CY14B108K CY14B108M Contents Pinouts .............................................................................. 4 Pin Definitions .................................................................. 5 Device Operation .............................................................. 6 SRAM Read ................................................................ 6 SRAM Write ................................................................. 6 AutoStore Operation .................................................... 6 Hardware STORE (HSB) Operation ............................ 6 Hardware RECALL (Power-Up) .................................. 7 Software STORE ......................................................... 7 Software RECALL ....................................................... 7 Preventing AutoStore .................................................. 9 Data Protection ............................................................ 9 Real Time Clock Operation ............................................ 10 nvTime Operation ...................................................... 10 Clock Operations ....................................................... 10 Reading the Clock ..................................................... 10 Setting the Clock ....................................................... 10 Backup Power ........................................................... 10 Stopping and Starting the Oscillator .......................... 10 Calibrating the Clock ................................................. 11 Alarm ......................................................................... 11 Watchdog Timer ........................................................ 11 Power Monitor ........................................................... 12 Interrupts ................................................................... 12 Flags Register ........................................................... 12 RTC External Components ....................................... 13 PCB Design Considerations for RTC ............................ 14 Layout requirements .................................................. 14 Maximum Ratings ........................................................... 19 Operating Range ............................................................. 19 DC Electrical Characteristics ........................................ 19 Data Retention and Endurance ..................................... 20 Capacitance .................................................................... 20 Document Number: 001-47378 Rev. *M Thermal Resistance ........................................................ 20 AC Test Loads ................................................................ 21 AC Test Conditions ........................................................ 21 RTC Characteristics ....................................................... 21 AC Switching Characteristics ....................................... 22 Switching Waveforms .................................................... 22 AutoStore/Power-Up RECALL ....................................... 25 Switching Waveforms .................................................... 25 Software Controlled STORE and RECALL Cycle ........ 26 Switching Waveforms .................................................... 26 Hardware STORE Cycle ................................................. 27 Switching Waveforms .................................................... 27 Truth Table For SRAM Operations ................................ 28 Ordering Information ...................................................... 29 Ordering Code Definitions ......................................... 29 Package Diagrams .......................................................... 30 Acronyms ........................................................................ 32 Document Conventions ................................................. 32 Units of Measure ....................................................... 32 Errata ............................................................................... 33 Part Numbers Affected .............................................. 33 8Mb (1024 K × 8, 512 K × 16) nvSRAM Qualification Status ........................................................... 33 8Mb (1024 K × 8, 512 K × 16) nvSRAM Errata Summary ............................................................... 33 Document History Page ................................................. 34 Sales, Solutions, and Legal Information ...................... 36 Worldwide Sales and Design Support ....................... 36 Products .................................................................... 36 PSoC® Solutions ...................................................... 36 Cypress Developer Community ................................. 36 Technical Support ..................................................... 36 Page 3 of 36 CY14B108K CY14B108M Pinouts Figure 1. Pin Diagram – 44-pIn and 54-pin TSOP II INT [4] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 VCC VSS DQ2 DQ3 WE A5 A6 A7 A8 A9 Xout Xin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 44 - TSOP II (x8) Top View (not to scale) 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 HSB NC A19 A18 A17 A16 A15 OE DQ7 DQ6 VSS VCC DQ5 DQ4 VCAP A14 A13 A12 A11 A10 VRTCcap VRTCbat INT [4] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 NC Xout Xin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 54 - TSOP II (x16) Top View (not to scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 HSB A18 A17 A16 A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC VRTCcap VRTCbat Note 4. Address expansion for 16-Mbit. NC pin not connected to die. Document Number: 001-47378 Rev. *M Page 4 of 36 CY14B108K CY14B108M Pin Definitions Pin Name A0–A19 A0–A18 DQ0–DQ7 DQ0–DQ15 NC WE CE OE I/O Type Input Input/Output No connect Input Input Input Input Input Output Input [5] Power supply VRTCcap VRTCbat[5] Power supply [5] Output INT BHE BLE Xout[5] Xin[5] VSS VCC HSB VCAP Ground Power supply Input/Output Power supply Description Address inputs. Used to select one of the 1,048,576 bytes of the nvSRAM for × 8 configuration. Address inputs. Used to select one of the 524,288 words of the nvSRAM for × 16 configuration. Bidirectional data I/O lines for × 8 configuration. Used as input or output lines depending on operation. Bidirectional data I/O lines for × 16 configuration. Used as input or output lines depending on operation. No connects. This pin is not connected to the die. Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific address location. Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tristate. Byte High Enable, Active LOW. Controls DQ15–DQ8. Byte Low Enable, Active LOW. Controls DQ7–DQ0. Crystal connection. Drives crystal on start up. Crystal connection. For 32.768 kHz crystal. Capacitor supplied backup RTC supply voltage. Left unconnected if VRTCbat is used. Battery supplied Backup RTC supply voltage. Left unconnected if VRTCcap is used. Interrupt output. Programmable to respond to the clock alarm, the watchdog timer, and the power monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain). Ground for the device. Must be connected to ground of the system. Power supply inputs to the device. 3.0 V +20%, –10%. Hardware STORE Busy (HSB) Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional). Input: Hardware STORE implemented by pulling this pin LOW externally. AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements. Note 5. Left unconnected if RTC feature is not used. Document Number: 001-47378 Rev. *M Page 5 of 36 CY14B108K CY14B108M The CY14B108K/CY14B108M nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations SRAM read and write operations are inhibited. The CY14B108K/CY14B108M supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 1 million STORE operations. See Truth Table For SRAM Operations on page 28 for a complete description of read and write modes. SRAM Read The CY14B108K/CY14B108M performs a read cycle when CE and OE are LOW, and WE and HSB are HIGH. The address specified on pins A0–19 or A0–18 determines which of the 1,048,576 data bytes or 524,288 words of 16 bits each are accessed. Byte enables (BHE, BLE) determine which bytes are enabled to the output, in the case of 16-bit words. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle 1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle 2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW. SRAM Write A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common I/O pins DO0–15 are written into the memory if it is valid for tSD time before the end of a WE controlled write or before the end of an CE controlled write. The Byte Enable inputs (BHE, BLE) determine which bytes are written, in the case of 16-bit words. Keep OE HIGH during the entire write cycle to avoid data bus contention on common I/O lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW. AutoStore Operation The CY14B108K/CY14B108M stores data to the nvSRAM using one of three storage operations. These three operations are: Hardware STORE, activated by the HSB; Software STORE, activated by an address sequence; AutoStore, on device power-down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B108K/CY14B108M. During a normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Note If the capacitor is not connected to VCAP pin, AutoStore must be disabled using the soft sequence specified in Preventing AutoStore on page 9. In case AutoStore is enabled without a capacitor on VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the Store. This corrupts the data stored in nvSRAM. Figure 2. AutoStore Mode CC 0.1 uF 10 kOhm Device Operation VCC WE VCAP VSS VCAP Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic STORE operation. Refer to DC Electrical Characteristics on page 19 for the size of the VCAP. The voltage on the VCAP pin is driven to VCC by a regulator on the chip. A pull-up should be placed on WE to hold it inactive during power-up. This pull-up is effective only if the WE signal is tristate during power-up. Many MPUs tristate their controls on power-up. This should be verified when using the pull-up. When the nvSRAM comes out of power-on-RECALL, the MPU must be active or the WE held inactive until the MPU comes out of reset. To reduce unnecessary nonvolatile STOREs, AutoStore, and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. Hardware STORE (HSB) Operation The CY14B108K/CY14B108M provides the HSB pin to control and acknowledge the STORE operations. The HSB pin is used to request a Hardware STORE cycle. When the HSB pin is driven LOW, the CY14B108K/CY14B108M conditionally initiates a STORE operation after tDELAY. An actual STORE cycle begins only if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver (internal 100 k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by internal 100 k pull-up resistor. SRAM write operations that are in progress when HSB is driven LOW by any means are given time (tDELAY) to complete before Document Number: 001-47378 Rev. *M Page 6 of 36 CY14B108K CY14B108M the STORE operation is initiated. However, any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. In case the write latch is not set, HSB is not driven LOW by the CY14B108K/CY14B108M. But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or other external source. During any STORE operation, regardless of how it is initiated, the CY14B108K/CY14B108M continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. Leave the HSB unconnected if it is not used. Hardware RECALL (Power-Up) During power-up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the VSWITCH on powerup, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, the HSB pin is driven LOW by the HSB driver and all reads and writes to nvSRAM are inhibited. Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14B108K/CY14B108M Software STORE cycle is initiated by executing sequential CE or OE controlled read cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of reads from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8FC0 Initiate STORE cycle The software sequence may be clocked with CE controlled reads or OE controlled reads, with WE kept HIGH for all the six READ sequences. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation. Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation. To initiate the RECALL cycle, perform the following sequence of CE or OE controlled read operations: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4C63 Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements. To initiate the Software STORE cycle, the following read sequence must be performed: Document Number: 001-47378 Rev. *M Page 7 of 36 CY14B108K CY14B108M Table 1. Mode Selection OE X BHE, BLE[6] X A15–A0[7] X Mode I/O Power Not selected Output High Z Standby H L L X Read SRAM Output data Active L X L X Write SRAM Input data Active L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Output data Output data Output data Output data Output data Output data Active[8] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Output data Output data Output data Output data Output data Output data Active[8] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output data Output data Output data Output data Output data Output High Z Active ICC2[8] L H L X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output data Output data Output data Output data Output data Output High Z Active[8] CE H WE X L L Errata: AutoStore Disable feature does not work in the device. For more information, see Errata on page 33. Notes 6. BHE and BLE are applicable for × 16 configuration only. 7. While there are 20 address lines on the CY14B108K (19 address lines on the CY14B108M), only the 13 address lines (A14–A2) are used to control software modes. The remaining address lines are don’t care. 8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. Notes 9. BHE and BLE are applicable for × 16 configuration only. 10. While there are 20 address lines on the CY14B108K (19 address lines on the CY14B108M), only the 13 address lines (A14–A2) are used to control software modes. Rest of the address lines are don’t care. 11. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. Document Number: 001-47378 Rev. *M Page 8 of 36 CY14B108K CY14B108M Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the Software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE or OE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable Note Errata: AutoStore Disable feature does not work in the device. For more information, see Errata on page 33. AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE or OE controlled read operations must be performed: Document Number: 001-47378 Rev. *M 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re-enabled, a manual STORE operation (hardware or software) must be issued to save the AutoStore state through subsequent power-down cycles. The part comes from the factory with AutoStore enabled and 0x00 written in all cells. Data Protection The CY14B108K/CY14B108M protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC is less than VSWITCH. If the CY14B108K/CY14B108M is in a write mode (both CE and WE are LOW) at power-up, after a RECALL or STORE, the write is inhibited until the SRAM is enabled after tLZHSB (HSB to output active). This protects against inadvertent writes during power-up or brown out conditions. Page 9 of 36 CY14B108K CY14B108M Real Time Clock Operation nvTime Operation The CY14B108K/CY14B108M offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. RTC registers use the last 16 address locations of the SRAM. Internal double buffering of the clock and timer information registers prevents accessing transitional internal clock data during a read or write operation. Double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data. Clock and alarm registers store data in BCD format. RTC functionality is described with respect to CY14B108K in the following sections. The same description applies to CY14B108M, except for the RTC register addresses. The RTC register addresses for CY14B108K range from 0xFFFF0 to 0xFFFFF, while those for CY14B108M range from 0x7FFF0 to 0x7FFFF. Refer to Table 3 on page 15 and Table 4 on page 16 for a detailed Register Map description. Clock Operations The clock registers maintain time up to 9,999 years in one-second increments. The time can be set to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and century transitions. There are eight registers dedicated to the clock functions, which are used to set time with a write cycle and to read time with a read cycle. These registers contain the time of day in BCD format. Bits defined as ‘0’ are currently not used and are reserved for future use by Cypress. Reading the Clock The double buffered RTC register structure reduces the chance of reading incorrect data from the clock. Internal updates to the CY14B108K time keeping registers are stopped when the read bit ‘R’ (in the Flags register at 0xFFFF0) is set to ‘1’ before reading clock data to prevent reading of data in transition. Stopping the register updates does not affect clock accuracy. When a read sequence of RTC device is initiated, the update of the user timekeeping registers stops and does not restart until a ‘0’ is written to the read bit ‘R’ (in the Flags register at 0xFFFF0). After the end of read sequence, all the RTC registers are simultaneously updated within 20 ms. Setting the Clock A write access to the RTC device stops updates to the time keeping registers and enables the time to be set when the write bit ‘W’ (in the Flags register at 0xFFFF0) is set to ‘1’. The correct day, date, and time is then written into the registers and must be in 24 hour BCD format. The time written is referred to as the “Base Time”. This value is stored in nonvolatile registers and used in the calculation of the current time. When the write bit ‘W’ is cleared by writing ‘0’ to it, the values of timekeeping registers are transferred to the actual clock counters after which the clock resumes normal operation. If the time written to the timekeeping registers is not in the correct BCD format, each invalid nibble of the RTC registers continue counting to 0xF before rolling over to 0x0 after which RTC resumes normal operation. Note After ‘W’ bit is set to ‘0’, values written into the timekeeping, alarm, calibration, and interrupt registers are transferred to the RTC time keeping counters in tRTCp time. These counter values Document Number: 001-47378 Rev. *M must be saved to nonvolatile memory either by initiating a Software/Hardware STORE or AutoStore operation. While working in AutoStore disabled mode, perform a STORE operation after tRTCp time while writing into the RTC registers for the modifications to be correctly recorded. Backup Power The RTC in the CY14B108K is intended for permanently powered operation. The VRTCcap or VRTCbat pin is connected depending on whether a capacitor or battery is chosen for the application. When the primary power, VCC, fails and drops below VSWITCH the device switches to the backup power supply. The clock oscillator uses very little current, which maximizes the backup time available from the backup source. Regardless of the clock operation with the primary source removed, the data stored in the nvSRAM is secure, having been stored in the nonvolatile elements when power was lost. During backup operation, the CY14B108K consumes a 0.35 µA (Typ) at room temperature. The user must choose capacitor or battery values according to the application. Note: If a battery is applied to VRTCbat pin prior to VCC, the chip will draw high IBAK current. This occurs even if the oscillator is disabled. In order to maximize battery life, VCC must be applied before a battery is applied to VRTCbat pin. Backup time values based on maximum current specifications are shown in the following Table 2. Nominal backup times are approximately two times longer. Table 2. RTC Backup Time Capacitor Value 0.1 F 0.47 F 1.0 F Backup Time 72 hours 14 days 30 days Using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up. If a battery is used, a 3 V lithium is recommended and the CY14B108K sources current only from the battery when the primary power is removed. However, the battery is not recharged at any time by the CY14B108K. The battery capacity must be chosen for total anticipated cumulative down time required over the life of the system. Stopping and Starting the Oscillator The OSCEN bit in the calibration register at 0xFFFF8 controls the enable and disable of the oscillator. This bit is nonvolatile and is shipped to customers in the “enabled” (set to ‘0’) state. To preserve the battery life when the system is in storage, OSCEN must be set to ‘1’. This turns off the oscillator circuit, extending the battery life. If the OSCEN bit goes from disabled to enabled, it takes approximately one second (two seconds maximum) for the oscillator to start. While system power is off, if the voltage on the backup supply (VRTCcap or VRTCbat) falls below their respective minimum level, the oscillator may fail.The CY14B108K has the ability to detect oscillator failure when system power is restored. This is recorded in the Oscillator Fail Flag (OSCF) of the Flags register at the address 0xFFFF0. When the device is powered on (VCC goes above VSWITCH) the OSCEN bit is checked for the ‘enabled’ status. If the OSCEN bit is enabled and the oscillator is not active Page 10 of 36 CY14B108K CY14B108M within the first 5 ms, the OSCF bit is set to ‘1’. The system must check for this condition and then write ‘0’ to clear the flag. Note that in addition to setting the OSCF flag bit, the time registers are reset to the ‘Base Time’, which is the value last written to the timekeeping registers. The control or calibration registers and the OSCEN bit are not affected by the ‘oscillator failed’ condition. The value of OSCF must be reset to ‘0’ when the time registers are written for the first time. This initializes the state of this bit which may have become set when the system was first powered on. To reset OSCF, set the write bit ‘W’ (in the Flags register at 0xFFFF0) to a ‘1’ to enable writes to the Flags register. Write a ‘0’ to the OSCF bit and then reset the write bit to ‘0’ to disable writes. Calibrating the Clock The RTC is driven by a quartz controlled crystal with a nominal frequency of 32.768 kHz. Clock accuracy depends on the quality of the crystal and calibration. The crystals available in market typically have an error of +20 ppm to +35 ppm. However, CY14B108K employs a calibration circuit that improves the accuracy to +1/–2 ppm at 25 °C. This implies an error of +2.5 seconds to –5 seconds per month. The calibration circuit adds or subtracts counts from the oscillator divider circuit to achieve this accuracy. The number of pulses that are suppressed (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in Calibration register at 0xFFFF8. The calibration bits occupy the five lower order bits in the Calibration register. These bits are set to represent any value between ‘0’ and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates positive calibration and a ‘0’ indicates negative calibration. Adding counts speeds the clock up and subtracting counts slows the clock down. If a binary ‘1’ is loaded into the register, it corresponds to an adjustment of 4.068 or –2.034 ppm offset in oscillator error, depending on the sign. Calibration occurs within a 64-minute cycle. The first 62 minutes in the cycle may, once every minute, have one second shortened by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is loaded into the register, only the first two minutes of the 64-minute cycle are modified. If a binary 6 is loaded, the first 12 are affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm of adjustment per calibration step in the Calibration register. To determine the required calibration, the CAL bit in the Flags register (0xFFFF0) must be set to ‘1’. This causes the INT pin to toggle at a nominal frequency of 512 Hz. Any deviation measured from the 512 Hz indicates the degree and direction of the required correction. For example, a reading of 512.01024 Hz indicates a +20 ppm error. Hence, a decimal value of –10 (001010b) must be loaded into the Calibration register to offset this error. Note Setting or changing the Calibration register does not affect the test output frequency. To set or clear CAL, set the write bit ‘W’ (in the Flags register at 0xFFFF0) to ‘1’ to enable writes to the Flags register. Write a value to CAL, and then reset the write bit to ‘0’ to disable writes. Document Number: 001-47378 Rev. *M Alarm The alarm function compares user programmed values of alarm time and date (stored in the registers 0xFFFF1-5) with the corresponding time of day and date values. When a match occurs, the alarm internal flag (AF) is set and an interrupt is generated on INT pin if Alarm Interrupt Enable (AIE) bit is set. There are four alarm match fields – date, hours, minutes, and seconds. Each of these fields has a match bit that is used to determine if the field is used in the alarm match logic. Setting the match bit to ‘0’ indicates that the corresponding field is used in the match process. Depending on the match bits, the alarm occurs as specifically as once a month or as frequently as once every minute. Selecting none of the match bits (all 1s) indicates that no match is required and therefore, alarm is disabled. Selecting all match bits (all 0s) causes an exact time and date match. There are two ways to detect an alarm event: by reading the AF flag or monitoring the INT pin. The AF flag in the Flags register at 0xFFFF0 indicates that a date or time match has occurred. The AF bit is set to ‘1’ when a match occurs. Reading the Flags register clears the alarm flag bit (and all others). A hardware interrupt pin may also be used to detect an alarm event. To set, clear or enable an alarm, set the ‘W’ bit (in Flags Register – 0xFFFF0) to ‘1’ to enable writes to Alarm Registers. After writing the alarm value, clear the ‘W’ bit back to ‘0’ for the changes to take effect. Note CY14B108K requires the alarm match bit for seconds (bit ‘D7’ in Alarm-Seconds register 0xFFFF2) to be set to ‘0’ for proper operation of Alarm Flag and Interrupt. Watchdog Timer The watchdog timer is a free running down counter that uses the 32 Hz clock (31.25 ms) derived from the crystal oscillator. The oscillator must be running for the watchdog to function. It begins counting down from the value loaded in the watchdog timer register. The timer consists of a loadable register and a free running counter. On power-up, the watchdog time out value in register 0xFFFF7 is loaded into the counter load register. Counting begins on power-up and restarts from the loadable value any time the watchdog strobe (WDS) bit is set to ‘1’. The counter is compared to the terminal value of ‘0’. If the counter reaches this value, it causes an internal flag and an optional interrupt output. You can prevent the time out interrupt by setting WDS bit to ‘1’ prior to the counter reaching ‘0’. This causes the counter to reload with the watchdog time out value and to be restarted. As long as the user sets the WDS bit prior to the counter reaching the terminal value, the interrupt and WDT flag never occur. New time out values are written by setting the watchdog write bit to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out value bits D5-D0 are enabled to modify the time out value. When WDW is ‘1’, writes to bits D5–D0 are ignored. The WDW function enables a user to set the WDS bit without concern that the watchdog timer value is modified. A logical diagram of the watchdog timer is shown in Figure 3. Note that setting the watchdog time out value to ‘0’ disables the watchdog function. The output of the watchdog timer is the flag bit WDF that is set if the watchdog is allowed to time out. If the watchdog interrupt enable (WIE) bit in the interrupt register is set, a hardware interrupt on INT pin is also generated on watchdog timeout. The Page 11 of 36 CY14B108K CY14B108M flag and the hardware interrupt are both cleared when user reads the flags registers. Figure 3. Watchdog Timer Block Diagram Clock Divider Oscillator 32,768 KHz 32 Hz Zero Compare WDF Load Register WDS Q D WDW Q write to Watchdog Register Interrupts are only generated while working on normal power and are not triggered when system is running in backup power mode. Note CY14B108K generates valid interrupts only after the Power-up RECALL sequence is completed. All events on INT pin must be ignored for tHRECALL duration after powerup. 1 Hz Counter mode is used as an interrupt to a host microcontroller. The control bits are summarized in the following section. Watchdog Register . Power Monitor The CY14B108K provides a power management scheme with power fail interrupt capability. It also controls the internal switch to backup power for the clock and protects the memory from low VCC access. The power monitor is based on an internal band gap reference circuit that compares the VCC voltage to VSWITCH threshold. As described in the section AutoStore Operation on page 6, when VSWITCH is reached as VCC decays from power loss, a data STORE operation is initiated from SRAM to the nonvolatile elements, securing the last SRAM data state. Power is also switched from VCC to the backup supply (battery or capacitor) to operate the RTC oscillator. Interrupt Register Watchdog Interrupt Enable (WIE). When set to ‘1’, the watchdog timer drives the INT pin and an internal flag when a watchdog time out occurs. When WIE is set to ‘0’, the watchdog timer only affects the WDF flag in flags register. Alarm Interrupt Enable (AIE). When set to ‘1’, the alarm match drives the INT pin and an internal flag. When AIE is set to ‘0’, the alarm match only affects the AF flags register. Power Fail Interrupt Enable (PFE). When set to ‘1’, the power fail monitor drives the pin and an internal flag. When PFE is set to ‘0’, the power fail monitor only affects the PF flag in flags register. High/Low (H/L). When set to a ‘1’, the INT pin is active HIGH and the driver mode is push pull. The INT pin drives HIGH only when VCC is greater than VSWITCH. When set to a ‘0’, the INT pin is active LOW and the drive mode is open drain. The INT pin must be pulled up to Vcc by a 10 k resistor while using the interrupt in active LOW mode. Pulse/Level (P/L). When set to a ‘1’ and an interrupt occurs, the INT pin is driven for approximately 200 ms. When P/L is set to a ‘0’, the INT pin is driven HIGH or LOW (determined by H/L) until the flags register is read. When operating from the backup source, read and write operations to nvSRAM are inhibited and the RTC functions are not available to the user. The RTC clock continues to operate in the background. The updated RTC time keeping registers data are available to the user after VCC is restored to the device (see AutoStore/Power-Up RECALL on page 25). When an enabled interrupt source activates the INT pin, an external host reads the flags registers to determine the cause. Remember that all flags are cleared when the register is read. If the INT pin is programmed for Level mode, then the condition clears and the INT pin returns to its inactive state. If the pin is programmed for pulse mode, then reading the flag also clears the flag and the pin. The pulse does not complete its specified duration if the flags register is read. If the INT pin is used as a host reset, the flags register is not read during a reset. Interrupts Flags Register The CY14B108K has flags register, interrupt register, and interrupt logic that can signal interrupt to the microcontroller. There are three potential sources for interrupt: watchdog timer, power monitor, and alarm timer. Each of these can be individually enabled to drive the INT pin by appropriate setting in the Interrupt register (0xFFFF6). In addition, each has an associated flag bit in the flags register (0xFFFF0) that the host processor uses to determine the cause of the interrupt. The INT pin driver has two bits that specify its behavior when an interrupt occurs. The flags register has three flag bits: WDF, AF, and PF, which can be used to generate an interrupt. These flags are set by the watchdog timeout, alarm match, or power fail monitor respectively. The processor can either poll this register or enable interrupts when a flag is set. These flags are automatically reset when the register is read. The flags register is automatically loaded with the value 0x00 on power-up (except for the OSCF bit. See Stopping and Starting the Oscillator on page 10). An interrupt is raised only if both a flag is raised by one of the three sources and the respective interrupt enable bit in interrupts register is enabled (set to ‘1’). After an interrupt source is active, two programmable bits, H/L and P/L, determine the behavior of the output pin driver on INT pin. These two bits are located in the interrupt register and can be used to drive level or pulse mode output from the INT pin. In pulse mode, the pulse width is internally fixed at approximately 200 ms. This mode is intended to reset a host microcontroller. In the level mode, the pin goes to its active polarity until the flags register is read by the user. This Document Number: 001-47378 Rev. *M Page 12 of 36 CY14B108K CY14B108M Figure 4. Interrupt Block Diagram WDF Watchdog Timer WIE P/L VCC PF Power Monitor Pin Driver PFE INT VINT H/L WDF - Watchdog Timer Flag WIE - Watchdog Interrupt Enable PF - Power Fail Flag PFE - Power Fail Enable AF - Alarm Flag AIE - Alarm Interrupt Enable P/L - Pulse Level H/L - High/Low VSS AF Clock Alarm AIE RTC External Components The RTC requires connecting an external 32.768 kHz crystal and C1, C2 load capacitance as shown in the Figure 5. The figure shows the recommnded RTC external component values. The load capacitances C1 and C2 are inclusive of parasitic of the printed circuit board (PCB). The PCB parasitic includes the capacitance due to land pattern of crystal pads/pins, Xin/Xout pads and copper traces connecting crystal and device pins. Figure 5. RTC Recommended Component Configuration [12] Recommended Values Y1 = 32.768 KHz (12.5 pF) C1 = 12 pF C2 = 69 pF Note: The recommended values for C1 and C2 include board trace capacitance. C1 Y1 C2 Xout Xin Note 12. For nonvolatile static random access memory (nvSRAM) real time clock (RTC) design guidelines and best practices, see application note AN61546. Document Number: 001-47378 Rev. *M Page 13 of 36 CY14B108K CY14B108M PCB Design Considerations for RTC RTC crystal oscillator is a low current circuit with high impedance nodes on their crystal pins. Due to lower timekeeping current of RTC, the crystal connections are very sensitive to noise on the board. Hence it is necessary to isolate the RTC circuit from other signals on the board. It is also critical to minimize the stray capacitance on the PCB. Stray capacitances add to the overall crystal load capacitance and therefore cause oscillation frequency errors. Proper bypassing and careful layout are required to achieve the optimum RTC performance. ■ Keep Xin and Xout trace width lesser than 8 mils. Wider trace width leads to larger trace capacitance. The larger these bond pads and traces are, the more likely it is that noise can couple from adjacent signals. ■ Shield the Xin and Xout signals by providing a guard ring around the crystal circuitry. This guard ring prevents noise coupling from neighboring signals. ■ Take care while routing any other high speed signal in the vicinity of RTC traces. The more the crystal is isolated from other signals on the board, the less likely it is that noise is coupled into the crystal. Maintain a minimum of 200 mil separation between the Xin, Xout traces and any other high speed signal on the board. ■ No signals should run underneath crystal components on the same PCB layer. ■ Create an isolated solid copper plane on adjacent PCB layer and underneath the crystal circuitry to prevent unwanted noise coupled from traces routed on the other signal layers of the PCB. The local plane should be separated by at least 40 mils from the neighboring plane on the same PCB layer. The solid plane should be in the vicinity of RTC components only and its perimeter should be kept equal to the guard ring perimeter. Figure 6 shows the recommended layout for RTC circuit. Layout requirements The board layout must adhere to (but not limited to) the following guidelines during routing RTC circuitry. Following these guidelines help you achieve optimum performance from the RTC design. ■ It is important to place the crystal as close as possible to the Xin and Xout pins. Keep the trace lengths between the crystal and RTC equal in length and as short as possible to reduce the probability of noise coupling by reducing the length of the antenna. Figure 6. Recommended Layout for RTC Top component layer: L1 Ground plane layer: L2 System ground C1 Isolated ground plane on layer 2 : L2 Guard ring - Top (Component) layer: L1 Y1 C2 Via: Via connects to isolated ground plane on L2 Document Number: 001-47378 Rev. *M Via: Via connects to system ground plane on L2 Page 14 of 36 CY14B108K CY14B108M Table 3. RTC Register Map [13] BCD Format Data [14] Register CY14B108K CY14B108M D7 D6 0xFFFFF 0x7FFFF 0xFFFFE 0x7FFFE 0 0 0xFFFFD 0x7FFFD 0 0 0xFFFFC 0x7FFFC 0 0 0xFFFFB 0x7FFFB 0 0 0xFFFFA 0x7FFFA 0 D5 D4 D3 D2 10s years 0 10s months 10s day of month 0 0 Function/Range Years: 00–99 Months Months: 01–12 Day of month Day of month: 01–31 Day of week 10s hours Day of week: 01–07 Hours Hours: 00–23 Minutes Minutes: 00–59 0xFFFF9 0x7FFF9 0 0xFFFF8 0x7FFF8 OSCEN (0) 0 0xFFFF7 0x7FFF7 WDS (0) WDW (0) 0xFFFF6 0x7FFF6 WIE (0) AIE (0) 0xFFFF5 0x7FFF5 M (1) 0 10s alarm date Alarm day Alarm, day of month: 01–31 0xFFFF4 0x7FFF4 M (1) 0 10s alarm hours Alarm hours Alarm, hours: 00–23 0xFFFF3 0x7FFF3 M (1) 10s alarm minutes Alarm minutes Alarm, minutes: 00–59 0xFFFF2 0x7FFF2 M (1) 10s alarm seconds Alarm, seconds Alarm, seconds: 00–59 0xFFFF1 0x7FFF1 0xFFFF0 0x7FFF0 10s seconds D0 Years 0 10s minutes D1 Seconds Cal sign (0) AF Calibration values [15] Watchdog [15] WDT (000000) PFE (0) 0 H/L (1) 10s centuries WDF Seconds: 00–59 Calibration (00000) PF P/L (0) 0 0 Centuries OSCF[16] 0 CAL (0) W (0) Interrupts [15] Centuries: 00–99 R (0) Flags [15] Notes 13. Upper Byte D15-D8 (CY14B108M) of RTC registers are reserved for future use. 14. ( ) designates values shipped from the factory. 15. This is a binary value, not a BCD value. 16. When the user resets OSCF flag bit, the flags register will be updated after tRTCp time. Document Number: 001-47378 Rev. *M Page 15 of 36 CY14B108K CY14B108M Table 4. Register Map Detail Register CY14B108K CY14B108M 0xFFFFF 0x7FFFF Description Time Keeping - Years D7 D6 D5 D4 D3 D2 10s years D1 D0 Years Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99. 0xFFFFE 0x7FFFE Time Keeping - Months D7 D6 D5 D4 0 0 0 10s month D3 D2 D1 D0 Months Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1–12. 0xFFFFD 0x7FFFD Time Keeping - Date D7 D6 0 0 D5 D4 D3 10s day of month D2 D1 D0 Day of month Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3. The range for the register is 1–31. Leap years are automatically adjusted for. 0xFFFFC 0x7FFFC Time Keeping - Day D7 D6 D5 D4 D3 0 0 0 0 0 D2 D1 D0 Day of week Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, because the day is not integrated with the date. 0xFFFFB 0x7FFFB Time Keeping - Hours D7 D6 0 0 D5 D4 D3 D2 10s hours D1 D0 Hours Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0–23. 0xFFFFA 0x7FFFA Time Keeping - Minutes D7 D6 0 D5 D4 D3 D2 10s minutes D1 D0 Minutes Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5. The range for the register is 0–59. 0xFFFF9 0x7FFF9 Time Keeping - Seconds D7 0 D6 D5 10s seconds D4 D3 D2 D1 D0 Seconds Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates from 0 to 9; upper nibble (three bits) contains the upper digit and operates from 0 to 5. The range for the register is 0 to 59. Document Number: 001-47378 Rev. *M Page 16 of 36 CY14B108K CY14B108M Table 4. Register Map Detail (continued) Register CY14B108K CY14B108M 0xFFFF8 0x7FFF8 OSCEN Calibration Sign Calibration 0xFFFF7 0x7FFF7 Description Calibration/Control D7 D6 D5 OSCEN 0 Calibration sign D4 D3 D2 D1 D0 Calibration Oscillator enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator saves battery or capacitor power during storage. Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base. These five bits control the calibration of the clock. WatchDog Timer D7 D6 WDS WDW D5 D4 D3 D2 D1 D0 WDT WDS Watchdog strobe. Setting this bit to ‘1’ reloads and restarts the watchdog timer. Setting the bit to ‘0’ has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0. WDW Watchdog write enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value (D5–D0). This allows the user to set the watchdog strobe bit without disturbing the timeout value. Setting this bit to 0 allows bits D5–D0 to be written to the watchdog register when the next write cycle is complete. This function is explained in more detail in Watchdog Timer on page 11. WDT Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a multiplier of the 32 Hz count (31.25 ms). The range of timeout value is 31.25 ms (a setting of 1) to 2 seconds (setting of 3 Fh). Setting the watchdog timer register to ‘0’ disables the timer. These bits can be written only if the WDW bit was set to 0 on a previous cycle. 0xFFFF6 0x7FFF6 Interrupt Status/Control D7 D6 D5 D4 D3 D2 D1 D0 WIE AIE PFE 0 H/L P/L 0 0 WIE Watchdog interrupt enable. When set to ‘1’ and a watchdog timeout occurs, the watchdog timer drives the INT pin and the WDF flag. When set to ‘0’, the watchdog timeout affects only the WDF flag. AIE Alarm interrupt enable. When set to ‘1’, the alarm match drives the INT pin and the AF flag. When set to ‘0’, the alarm match only affects the AF flag. PFE Power fail enable. When set to ‘1’, the power fail monitor drives the INT pin and the PF flag. When set to ‘0’, the power fail monitor affects only the PF flag. 0 Reserved for future use H/L High/Low. When set to ‘1’, the INT pin is driven active HIGH. When set to ‘0’, the INT pin is open drain, active LOW. P/L Pulse/Level. When set to ‘1’, the INT pin is driven active (determined by H/L) by an interrupt source for approximately 200 ms. When set to ‘0’, the INT pin is driven to an active level (as set by H/L) until the flags register is read. 0xFFFF5 0x7FFF5 Alarm - Day D7 D6 M 0 D5 D4 10s alarm date D3 D2 D1 D0 Alarm date Contains the alarm value for the date of the month and the mask bit to select or deselect the date value. M Match. When this bit is set to ‘0’, the date value is used in the alarm match. Setting this bit to ‘1’ causes the match circuit to ignore the date value. Document Number: 001-47378 Rev. *M Page 17 of 36 CY14B108K CY14B108M Table 4. Register Map Detail (continued) Register CY14B108K CY14B108M 0xFFFF4 0x7FFF4 Description Alarm - Hours D7 D6 M 0 D5 D4 D3 10s alarm hours D2 D1 D0 Alarm hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value. M 0xFFFF3 Match. When this bit is set to ‘0’, the hours value is used in the alarm match. Setting this bit to ‘1’ causes the match circuit to ignore the hours value. 0x7FFF3 Alarm - Minutes D7 D6 M D5 D4 D3 10s alarm minutes D2 D1 D0 Alarm minutes Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value. M 0xFFFF2 Match. When this bit is set to ‘0’, the minutes value is used in the alarm match. Setting this bit to ‘1’ causes the match circuit to ignore the minutes value. 0x7FFF2 Alarm - Seconds D7 D6 M D5 D4 D3 10s alarm seconds D2 D1 D0 Alarm seconds Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value. M 0xFFFF1 Match. When this bit is set to ‘0’, the seconds value is used in the alarm match. Setting this bit to ‘1’ causes the match circuit to ignore the seconds value. 0x7FFF1 Time Keeping - Centuries D7 D6 D5 D4 D3 D2 10s centuries D1 D0 Centuries Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 9. The range for the register is 0-99 centuries. 0xFFFF0 0x7FFF0 Flags D7 D6 D5 D4 D3 D2 D1 D0 WDF AF PF OSCF 0 CAL W R WDF Watchdog timer flag. This read only bit is set to ‘1’ when the watchdog timer is allowed to reach 0 without being reset by the user. It is cleared to ‘0’ when the flags register is read or on power-up AF Alarm flag. This read only bit is set to ‘1’ when the time and date match the values stored in the alarm registers with the match bits = 0. It is cleared when the flags register is read or on power-up. PF Power fail flag. This read only bit is set to ‘1’ when power falls below the power fail threshold VSWITCH. It is cleared to ‘0’ when the flags register is read or on power-up. OSCF Oscillator fail flag. Set to ‘1’ on power-up if the oscillator is enabled and not running in the first 5 ms of operation. This indicates that RTC backup power failed and clock value is no longer valid. This bit survives the power cycle and is never cleared internally by the chip. The user must check for this condition and write '0' to clear this flag. When user resets OSCF flag bit, the bit will be updated after tRTCp time. CAL Calibration mode. When set to ‘1’, a 512 Hz square wave is output on the INT pin. When set to ‘0’, the INT pin resumes normal operation. This bit defaults to 0 (disabled) on power-up. W Write enable: Setting the ‘W’ bit to ‘1’ freezes updates of the RTC registers. The user can then write to RTC registers, alarm registers, calibration register, interrupt register and flags register. Setting the ‘W’ bit to ‘0’ causes the contents of the RTC registers to be transferred to the time keeping counters if the time has changed. This transfer process takes tRTCp time to complete. This bit defaults to 0 on power-up. R Read enable: Setting ‘R’ bit to ’1’, stops clock updates to user RTC registers so that clock updates are not seen during the reading process. Set ‘R’ bit to ‘0’ to resume clock updates to the holding register. Setting this bit does not require ‘W’ bit to be set to ‘1’. This bit defaults to 0 on power-up. Document Number: 001-47378 Rev. *M Page 18 of 36 CY14B108K CY14B108M Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Transient voltage (< 20 ns) on any pin to ground potential ................. –2.0 V to VCC + 2.0 V Package power dissipation capability (TA = 25°C) .................................................. 1.0 W Maximum accumulated storage time Surface mount Pb soldering temperature (3 Seconds) ......................................... +260 C At 150 C ambient temperature ................................. 1000 h DC output current (1 output at a time, 1s duration) .... 15 mA At 85 C ambient temperature ................................ 20 Years Static discharge voltage (per MIL-STD-883, Method 3015) ......................... > 2001 V Maximum junction temperature .................................. 150 C Supply voltage on VCC relative to VSS ...........–0.5 V to 4.1 V Voltage applied to outputs in High Z state .................................... –0.5 V to VCC + 0.5 V Input voltage ....................................... –0.5 V to VCC + 0.5 V Latch up current .................................................... > 200 mA Operating Range Range Ambient Temperature VCC –40 C to +85 C 2.7 V to 3.6 V Industrial DC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Typ[17] Max Unit VCC Power supply 2.7 3.0 3.6 V ICC1 Average VCC current tRC = 25 ns tRC = 45 ns Values obtained without output loads (IOUT = 0 mA) – – 75 57 mA mA ICC2 Average VCC current during STORE All inputs don’t care, VCC = Max. Average current for duration tSTORE – – 20 mA ICC3 Average VCC current at tRC = 200 ns, VCC(Typ), 25 °C All inputs cycling at CMOS levels. Values obtained without output loads (IOUT = 0 mA). – 40 – mA ICC4 Average VCAP current during AutoStore cycle All inputs don’t care. Average current for duration tSTORE – – 10 mA ISB VCC standby current CE > (VCC – 0.2 V). VIN < 0.2 V or > (VCC – 0.2 V). W bit set to ‘0’. Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. – – 10 mA IIX[18] Input leakage current (except HSB) VCC = Max, VSS < VIN < VCC –2 – +2 A Input leakage current (for HSB) VCC = Max, VSS < VIN < VCC –200 – +2 A IOZ Off state output leakage current VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or BHE/BLE > VIH or WE < VIL –2 – +2 A VIH Input HIGH voltage 2.0 – VCC + 0.5 V VIL Input LOW voltage VSS – 0.5 – 0.8 V VOH Output HIGH voltage IOUT = –2 mA 2.4 – – V VOL Output LOW voltage IOUT = 4 mA – – 0.4 V Notes 17. Typical values are at 25 °C, VCC= VCC(Typ). Not 100% tested. 18. The HSB pin has IOUT = -2 uA for VOH of 2.4 V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested. Document Number: 001-47378 Rev. *M Page 19 of 36 CY14B108K CY14B108M DC Electrical Characteristics (continued) Over the Operating Range Parameter VCAP[19] VVCAP[20, 21] Description Storage capacitor Test Conditions Min Typ[17] Max Unit Between VCAP pin and VSS, 5 V rated 122 150 360 F – – VCC V Maximum voltage driven on VCAP VCC = Max pin by the device Data Retention and Endurance Over the Operating Range Parameter Description DATAR Data retention NVC Nonvolatile STORE operations Min Unit 20 Years 1,000 K Max Unit 14 pF 14 pF Capacitance Parameter[21] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC(Typ) Thermal Resistance Parameter[21] Description JA Thermal resistance (Junction to ambient) JC Thermal resistance (Junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 44-pin TSOP II 54-pin TSOP II Unit 45.3 44.22 C/W 5.2 8.26 C/W Notes 19. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options. 20. Maximum voltage on VCAP pin (VVCAP) is provided for guidance when choosing the VCAP capacitor. The voltage rating of the VCAP capacitor across the operating temperature range should be higher than the VVCAP voltage. 21. These parameters are guaranteed by design and are not tested. Document Number: 001-47378 Rev. *M Page 20 of 36 CY14B108K CY14B108M AC Test Loads Figure 7. AC Test Loads 577 577 3.0 V 3.0 V R1 R1 OUTPUT OUTPUT R2 789 30 pF R2 789 5 pF AC Test Conditions Input pulse levels ...................................................0 V to 3 V Input rise and fall times (10%–90%) ........................... < 3 ns Input and output timing reference levels ....................... 1.5 V RTC Characteristics Over the Operating Range Parameters Description Min Typ [22] Max Units VRTCbat RTC battery pin voltage 1.8 3.0 3.6 V IBAK[23] RTC backup current (Refer Figure 5 for the recommended external componets for RTC) TA (Min) – – 0.35 A 25 °C – 0.35 – A TA (Max) – – 0.5 A RTC capacitor pin voltage TA (Min) 1.6 – 3.6 V 25 °C 1.5 3.0 3.6 V TA (Max) 1.4 – 3.6 V – 1 2 sec VRTCcap [24] tOCS RTC oscillator time to start tRTCp RTC processing time from end of ‘W’ bit set to ‘0’ RBKCHG RTC backup capacitor charge current-limiting resistor – – 350 s 350 – 850 Notes 22. Typical values are at 25 °C, VCC = VCC(Typ). Not 100% tested. 23. From either VRTCcap or VRTCbat. 24. If VRTCcap > 0.5 V or if no capacitor is connected to VRTCcap pin, the oscillator starts in tOCS time. If a backup capacitor is connected and VRTCcap < 0.5 V, the capacitor must be allowed to charge to 0.5 V for oscillator to start. Document Number: 001-47378 Rev. *M Page 21 of 36 CY14B108K CY14B108M AC Switching Characteristics Over the Operating Range Parameters [25] Cypress Alt Parameter Parameter SRAM Read Cycle tACE tACS tRC tRC [26] tAA [27] tAA tOE tDOE [27] tOH tOHA tLZCE [28, 29] tLZ tHZ tHZCE [28, 29] tOLZ tLZOE [28, 29] tHZOE [28, 29] tOHZ tPA tPU [28] tPS tPD [28] tDBE [28] tLZBE tHZBE[28] SRAM Write Cycle tWC tWC tWP tPWE tSCE tCW tDW tSD tDH tHD tAW tAW tAS tSA tWR tHA tHZWE [28, 29, 30] tWZ tOW tLZWE [28, 29] tBW 25 ns Description 45 ns Unit Min Max Min Max Chip enable access time Read cycle time Address access time Output enable to data valid Output hold after address change Chip enable to output active Chip disable to output inactive Output enable to output active Output disable to output inactive Chip enable to power active Chip disable to power standby Byte enable to data valid Byte enable to output active Byte disable to output inactive – 25 – – 3 3 – 0 – 0 – – 0 – 25 – 25 12 – – 10 – 10 – 25 12 – 10 – 45 – – 3 3 – 0 – 0 – – 0 – 45 – 45 20 – – 15 – 15 – 45 20 – 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Write cycle time Write pulse width Chip enable to end of write Data setup to end of write Data hold after end of write Address setup to end of write Address setup to start of write Address hold after end of write Write enable to output disable Output active after end of write Byte enable to end of write 25 20 20 10 0 20 0 0 – 3 20 – – – – – – – – 10 – – 45 30 30 15 0 30 0 0 – 3 30 – – – – – – – – 15 – – ns ns ns ns ns ns ns ns ns ns ns Switching Waveforms Figure 8. SRAM Read Cycle 1 (Address Controlled) [26, 27, 31] tRC Address Address Valid tAA Data Output Previous Data Valid Output Data Valid tOHA Notes 25. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH and load capacitance shown in Figure 7 on page 21. 26. WE must be HIGH during SRAM read cycles. 27. Device is continuously selected with CE, OE and BHE / BLE LOW. 28. These parameters are only guaranteed by design and are not tested. 29. Measured ±200 mV from steady state output voltage. 30. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 31. HSB must remain HIGH during Read and Write cycles. Document Number: 001-47378 Rev. *M Page 22 of 36 CY14B108K CY14B108M Switching Waveforms (continued) Figure 9. SRAM Read Cycle 2 (CE and OE Controlled) [32, 33, 34] Address Address Valid tRC tHZCE tACE CE tAA tLZCE tHZOE tDOE OE tHZBE tLZOE tDBE BHE, BLE tLZBE Data Output High Impedance Output Data Valid tPU ICC tPD Active Standby Figure 10. SRAM Write Cycle 1 (WE Controlled) [32, 34, 35, 36] tWC Address Address Valid tSCE tHA CE tBW BHE, BLE tAW tPWE WE tSA tSD Data Input Input Data Valid tHZWE Data Output tHD Previous Data tLZWE High Impedance Notes 32. BHE and BLE are applicable for × 16 configuration only. 33. WE must be HIGH during SRAM read cycles. 34. HSB must remain HIGH during read and write cycles. 35. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 36. CE or WE must be VIH during address transitions. Document Number: 001-47378 Rev. *M Page 23 of 36 CY14B108K CY14B108M Switching Waveforms (continued) Figure 11. SRAM Write Cycle 2 (CE Controlled) [37, 38, 39, 40] tWC Address Valid Address tSA tSCE tHA CE tBW BHE, BLE tPWE WE tHD tSD Input Data Valid Data Input High Impedance Data Output Figure 12. SRAM Write Cycle 3 (BHE and BLE Controlled) [ 38, 39, 40, 41, 42] (Not applicable for RTC register writes) tWC Address Address Valid tSCE CE tSA tHA tBW BHE, BLE tAW tPWE WE tSD Data Input tHD Input Data Valid High Impedance Data Output Notes 37. BHE and BLE are applicable for × 16 configuration only. 38. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state. 39. HSB must remain HIGH during read and write cycles. 40. CE or WE must be VIH during address transitions. 41. While there are 19 address lines on the CY14B108K (18 address lines on the CY14B108M), only 13 address lines (A14–A2) are used to control software modes. The remaining address lines are don’t care. 42. Only CE and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register. Document Number: 001-47378 Rev. *M Page 24 of 36 CY14B108K CY14B108M AutoStore/Power-Up RECALL Over the Operating Range Parameter CY14B108K/CY14B108M Description Min Max Unit tHRECALL [43] Power-Up RECALL duration – 20 ms tSTORE [44] STORE cycle duration – 8 ms tDELAY [45] VSWITCH tVCCRISE [46] Time allowed to complete SRAM write cycle – 25 ns Low voltage trigger level – 2.65 V 150 – s – 1.9 V VCC rise time VHDIS[46] HSB output disable voltage tLZHSB[46] tHHHD[46] HSB to output active time – 5 s HSB high active time – 500 ns Switching Waveforms Figure 13. AutoStore or Power-Up RECALL [47] VCC VSWITCH VHDIS t VCCRISE tHHHD Note 44 44 tSTORE Note tHHHD 48 Note tSTORE Note 48 HSB OUT tDELAY tLZHSB AutoStore tLZHSB tDELAY POWERUP RECALL tHRECALL tHRECALL Read & Write Inhibited (RWI) POWER-UP RECALL Read & Write BROWN OUT AutoStore POWER-UP RECALL Read & Write POWER DOWN AutoStore Notes 43. tHRECALL starts from the time VCC rises above VSWITCH. 44. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. 45. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 46. These parameters are only guaranteed by design and are not tested. 47. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 48. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor. Document Number: 001-47378 Rev. *M Page 25 of 36 CY14B108K CY14B108M Software Controlled STORE and RECALL Cycle Over the Operating Range Parameter [49, 50] tRC tSA tCW tHA tRECALL tSS [51, 52] 25 ns Description Min 25 0 20 0 – – STORE/RECALL initiation cycle time Address setup time Clock pulse width Address hold time RECALL duration Soft sequence processing time 45 ns Max – – – – 200 100 Min 45 0 30 0 – – Max – – – – 200 100 Unit ns ns ns ns s s Switching Waveforms Figure 14. CE and OE Controlled Software STORE and RECALL Cycle [50] tRC Address tRC Address #1 tSA Address #6 tCW tCW CE tHA tSA tHA tHA tHA OE tHHHD HSB (STORE only) tHZCE tLZCE t DELAY 53 Note tLZHSB High Impedance tSTORE/tRECALL DQ (DATA) RWI Figure 15. AutoStore Enable and Disable Cycle[50] Address tRC tRC Address #1 Address #6 tSA CE tCW tCW tHA tSA tHA tHA tHA OE tLZCE tHZCE tSS 53 Note t DELAY DQ (DATA) RWI Notes 49. The software sequence is clocked with CE controlled or OE controlled reads. 50. The six consecutive addresses must be read in the order listed in Table 1. WE must be HIGH during all six consecutive cycles. 51. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command. 52. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. 53. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time. Document Number: 001-47378 Rev. *M Page 26 of 36 CY14B108K CY14B108M Hardware STORE Cycle Over the Operating Range Parameter CY14B108K/CY14B108M Description Min Max Unit tDHSB HSB to output active time when write latch not set – 25 ns tPHSB Hardware STORE pulse width 15 – ns Switching Waveforms Figure 16. Hardware STORE Cycle [54] Write latch set tPHSB HSB (IN) tSTORE tHHHD tDELAY HSB (OUT) tLZHSB DQ (Data Out) RWI Write latch not set tPHSB HSB pin is driven high to VCC only by Internal 100 kOhm resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven low. HSB (IN) HSB (OUT) tDELAY tDHSB tDHSB RWI Figure 17. Soft Sequence Processing [55, 56] Soft Sequence Command Address Address #1 tSA Address #6 tCW tSS Soft Sequence Command Address #1 tSS Address #6 tCW CE VCC Notes 54. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. 55. This is the amount of time it takes to take action on a soft sequence command. VCC power must remain HIGH to effectively register command. 56. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. Document Number: 001-47378 Rev. *M Page 27 of 36 CY14B108K CY14B108M Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations. Table 5. Truth Table for × 8 Configuration CE Inputs and Outputs[57] WE OE Mode Power H X X High Z Deselect/Power-down Standby L H L Data out (DQ0–DQ7); Read Active L H H High Z Output disabled Active L L X Data in (DQ0–DQ7); Write Active Table 6. Truth Table for × 16 Configuration BHE[58] BLE[58] Inputs and Outputs[57] CE WE OE Mode Power H X X X X High Z Deselect/Power-down Standby L X X H H High Z Output disabled Active L H L L L Data out (DQ0–DQ15) Read Active L H L H L Data out (DQ0–DQ7); DQ8–DQ15 in High Z Read Active L H L L H Data out (DQ8–DQ15); DQ0–DQ7 in High Z Read Active L H H L L High Z Output disabled Active L H H H L High Z Output disabled Active L H H L H High Z Output disabled Active L L X L L Data in (DQ0–DQ15) Write Active L L X H L Data in (DQ0–DQ7); DQ8–DQ15 in High Z Write Active L L X L H Data in (DQ8–DQ15); DQ0–DQ7 in High Z Write Active Notes 57. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration. 58. BHE and BLE are applicable for × 16 configuration only. Document Number: 001-47378 Rev. *M Page 28 of 36 CY14B108K CY14B108M Ordering Information Speed (ns) 25 45 Ordering Code CY14B108K-ZS25XIT Package Diagram 51-85087 Package Type 44-pin TSOPII CY14B108K-ZS25XI 51-85087 44-pin TSOPII CY14B108M-ZSP25XIT 51-85160 54-pin TSOPII CY14B108M-ZSP25XI 51-85160 54-pin TSOPII CY14B108K-ZS45XIT 51-85087 44-pin TSOPII CY14B108K-ZS45XI 51-85087 44-pin TSOPII CY14B108M-ZSP45XIT 51-85160 54-pin TSOPII CY14B108M-ZSP45XI 51-85160 54-pin TSOPII Operating Range Industrial All the above parts are Pb-free. Ordering Code Definitions CY 14 B 108 K - ZSP 25 X I T Option: T - Tape & Reel Pb-free Package: ZSP - 44 TSOP II ZSP - 54 TSOP II Temperature: I - Industrial (–40 to 85 °C) Speed: 25 - 25 ns 45 - 45 ns Data Bus: K - × 8 + RTC M - × 16 + RTC Density: 108 - 8 Mb Voltage: B - 3.0V 14 - NVSRAM Cypress Document Number: 001-47378 Rev. *M Page 29 of 36 CY14B108K CY14B108M Package Diagrams Figure 18. 44-pin TSOP II Package Outline, 51-85087 51-85087 *E Document Number: 001-47378 Rev. *M Page 30 of 36 CY14B108K CY14B108M Package Diagrams (continued) Figure 19. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Package Outline, 51-85160 51-85160 *E Document Number: 001-47378 Rev. *M Page 31 of 36 CY14B108K CY14B108M Acronyms Acronym Document Conventions Description Units of Measure AIE alarm interrupt enable BCD binary coded decimal °C degree Celsius BHE byte high enable F farad BLE byte low enable Hz hertz CE CMOS chip enable kHz kilohertz complementary metal oxide semiconductor k kilohm EIA electronic industries alliance MHz megahertz HSB I/O hardware store busy A microampere input/output F microfarad nvSRAM non-volatile static random access memory s microsecond OE output enable mA milliampere PCB PFE Printed circuit board ms millisecond power fail interrupt enable ns nanosecond RoHS restriction of hazardous substances ohm RTC real time clock % percent RWI read and write inhibited pF picofarad SRAM static random access memory ppm parts per million TSOP thin small outline package s second WE write enable V volt WIE watchdog interrupt enable W watt Document Number: 001-47378 Rev. *M Symbol Unit of Measure Page 32 of 36 CY14B108K CY14B108M Errata This section describes the errata for the 8 Mb (2048 K × 8 and 1024 K × 16) nvSRAM product families. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. You can also send your related queries directly to [email protected]. Part Numbers Affected Part Number Device Characteristics CY14B108K 1024 K × 8, Asynchronous Interface nvSRAM with Real Time Clock in 44 TSOP-II package option CY14B108M 512 K × 16, Asynchronous Interface nvSRAM with Real Time Clock in 54 TSOP-II package option 8Mb (1024 K × 8, 512 K × 16) nvSRAM Qualification Status Production parts. 8Mb (1024 K × 8, 512 K × 16) nvSRAM Errata Summary The following table defines the errata applicability to available CY14B108K, CY14B108M devices. Items Part Number Silicon Revision Fix Status 1. AutoStore Disable feature does not work correctly CY14B108K CY14B108M Rev 0 None. This issue is applicable to all 8Mb nvSRAM parts in production 1. AutoStore Disable feature does not work correctly ■ Problem Definition The AutoStore Disable soft sequence disables the AutoStore feature in nvSRAMs. The AutoStore Disable feature is used in applications where data written in the SRAM is not required to be saved automatically on power loss. The 8Mb nvSRAM executes the nonvolatile Store automatically in half the memory (4Mb) even after the AutoStore feature is disabled. The reason is as follows: The 8Mb nvSRAM uses two dice stack of 4Mb with HSB pin of each die are tied together. Each nvSRAM die in the stacked-die monitors the VCC power independently. When the device VCC fails, the die which detects the VCC dropping below VSWITCH first, internally triggers the power down interrupt and drives its HSB output low. Since the HSB is a bidirectional pin, the low HSB output driven by one die is detected as HSB input by the other die. Therefore, low on the HSB input of other die internally triggers hardware Store and executes unintended nonvolatile Store even though AutoStore was disabled by AutoStore Disable soft sequence. ■ Parameters Affected None. ■ Trigger Condition(S) Device VCC power down with nvSRAM AutoStore disable. ■ Scope of Impact It can corrupt the data in half of the memory by overwriting the existing data in its nonvolatile memory with unintended data. ■ Workaround None. AutoStore disable feature should not be used in 8Mb nvSRAMs. ■ Fix Status This issue is applicable to all 8Mb nvSRAM parts in production and will continue serving with errata. There is no plan to fix this issue in the existing parts in production. Document Number: 001-47378 Rev. *M Page 33 of 36 CY14B108K CY14B108M Document History Page Document Title: CY14B108K/CY14B108M, 8-Mbit (1024 K × 8/512 K × 16) nvSRAM with Real Time Clock Document Number: 001-47378 Rev. ECN Orig. of Change Submission Date ** 2681767 GVCH/ PYRS 04/01/09 *A 2712462 GVCH/PY RS 05/29/2009 Moved data sheet status from Preliminary to Final Updated AutoStore operation Updated C1, C2 values to 12pF, 69pF from 21pF, 21pF respectively Updated ISB test condition Updated footnote 10 Updated IBAK and VRTCcap parameter values Added RBKCHG parameter to RTC characteristics table Added footnote 14 Referenced footnote 12 to VCCRISE, tHHHD and tLZHSB parameters Updated VHDIS parameter description *B 2746310 GVCH 07/29/2009 Page 4: Updated Hardware STORE (HSB) operation description page 4: Updated Software STORE description Updated tDELAY parameter description Updated footnote 24 and added footnote 31 Referenced footnote 31 to Figure 11 and Figure 12 *C 2759948 GVCH 09/04/2009 Removed commercial temperature related specs Removed 20 ns access speed related specs Changed VRTCbat max value from 3.3V to 3.6V Changed RBKCHG min value from 450to 350 Updated footnote 14 *D 2828257 GVCH 12/15/2009 Changed STORE cycles to QuantumTrap from 200K to 1 Million Updated IBAK RTC backup current spec unit from nA to A Added Contents on page 2 *E 2923475 GVCH / AESA 04/27/2010 Table 1: Added more clarity on HSB pin operation Hardware STORE (HSB) Operation: Added more clarity on HSB pin operation Table 1: Added more clarity on BHE/BLE pin operation Updated HSB pin operation in Figure 13 Updated footnote 48 Updated Package Diagrams and Sales, Solutions, and Legal Information. *F 3143765 GVCH 01/17/2011 Updated Setting the Clock description Added footnote 12 Updated W bit description in Register Map Detail table Updated Maximum Ratings Updated thermal resistance values for all packages Added tRTCp parameter to RTC Characteristics table Added Acronyms table and Document Conventions table *G 3311413 GVCH 07/13/2011 Updated DC Electrical Characteristics (Added Note 18 and referred the same note in VCAP parameter). Updated AC Switching Characteristics (Added Note 25 and referred the same note in Parameters). *H 3580269 GVCH 04/12/2012 Updated Pin Definitions (Added Note 5 and referred the same note in VRTCcap, VRTCbat, Xout, Xin, INT pins). Added Note 12 and referred the same note in Figure 5. Updated Package Diagrams. Document Number: 001-47378 Rev. *M Description of Change New Data Sheet Page 34 of 36 CY14B108K CY14B108M Document History Page (continued) Document Title: CY14B108K/CY14B108M, 8-Mbit (1024 K × 8/512 K × 16) nvSRAM with Real Time Clock Document Number: 001-47378 Rev. ECN Orig. of Change Submission Date Description of Change *I 3658005 GVCH 08/10/2012 Updated Real Time Clock Operation (description). Updated Maximum Ratings (Changed “Ambient temperature with power applied” to “Maximum junction temperature”). Updated DC Electrical Characteristics (Added VVCAP parameter and its details, added Note 20 and referred the same note in VVCAP parameter, also referred Note 21 in VVCAP parameter). Updated Package Diagrams (spec 51-85160 (Changed revision from *C to *D)). *J 4047965 GVCH 07/03/2013 Updated Pin Definitions: Updated HSB pin description (Added more clarity). Updated Device Operation: Updated AutoStore Operation (Removed sentence “The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress.”). Updated Real Time Clock Operation: Updated Backup Power (Added Note). Added RTC External Components. Moved Figure 5 from Flags Register section to RTC External Components section. Added PCB Design Considerations for RTC. Updated Package Diagrams: spec 51-85087 – Changed revision from *D to *E. Updated to new template. *K 4500772 ZSK 09/12/2014 Updated Package Diagrams: spec 51-85160 – Changed revision from *D to *E. Added Errata. *L 4563189 ZSK 11/06/2014 Added related documentation hyperlink in page 1 *M 4714292 GVCH 04/08/2015 No technical updates. Completing Sunset Review. Document Number: 001-47378 Rev. *M Page 35 of 36 CY14B108K CY14B108M Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/psoc psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-47378 Rev. *M Revised April 8, 2015 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 36 of 36