CYPRESS CY23S09OC-1

05
CY23S09
CY23S05
Low-Cost 3.3V Spread Aware™ Zero Delay Buffer
Features
• 10-MHz to 100-/133-MHz operating range, compatible
with CPU and PCI bus frequencies
• Zero input-output propagation delay
up to 100-/133-MHz frequencies, and have higher drive than
the -1 devices. All parts have on-chip PLLs that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
The CY23S09 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in the Select Input
Decoding table on page 2. If all output clocks are not required,
Bank B can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
• Multiple low-skew outputs
— Output-output skew less than 250 ps
— Device-device skew less than 700 ps
— One input drives five outputs (CY23S05)
• Test Mode to bypass PLL (CY23S09 only, see Select
Input Decoding table on page 2)
The CY23S09 and CY23S05 PLLs enter a power-down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0 µA of current draw (for commercial temperature devices) and 25.0 µA (for industrial temperature
devices). The CY23S09 PLL shuts down in one additional
case, as shown in the table below.
• Available in space-saving 16-pin, 150-mil SOIC, 4.4 mm
TSSOP, and 150-mil SSOP ( CY23S09) or 8-pin, 150-mil
SOIC package (CY23S05)
Multiple CY23S09 and CY23S05 devices can accept the same
input clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
• 3.3V operation, advanced 0.65µ CMOS technology
All outputs have less than 200 ps of cycle-to-cycle jitter. The
input to output propagation delay on both devices is
guaranteed to be less than 350 ps, and the output to output
skew is guaranteed to be less than 250 ps.
— One input drives nine outputs, grouped as 4 + 4 + 1
(CY23S09)
• Less than 200 ps cycle-to-cycle jitter is compatible with
Pentium-based systems
• Spread Aware™
Functional Description
The CY23S09 is a low-cost 3.3V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC
package. The CY23S05 is an eight-pin version of the
CY23S09. It accepts one reference input, and drives out five
low-skew clocks. The -1H versions of each device operate at
The CY23S05/CY23S09 is available in two different configurations, as shown in the ordering information on page 6. The
CY23S05-1/CY23S09-1 is the base part. The CY23S05-1H/
CY23S09-1H is the high-drive version of the -1, and its rise
and fall times are much faster than -1.
Block Diagram
Pin Configuration
PLL
SOIC/TSSOP/SSOP
Top View
CLKOUT
MUX
REF
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
S2
Select Input
Decoding
CLKB2
CLKB3
S1
CY23S09
REF
REF
CLKA1
1
16
CLKOUT
2
15
CLKA2
VDD
3
14
4
13
CLKA4
CLKA3
VDD
GND
CLKB1
CLKB2
S2
5
12
6
11
7
10
8
9
CY23S09
CLKB4
PLL
GND
CLKB4
CLKB3
S1
SOIC
Top View
CLKOUT
CLK1
REF
CLK2
CLK1
GND
CLK2
CLK3
1
8
2
7
3
6
4
5
CLKOUT
CLK4
VDD
CLK3
CLK4
CY23S05
Cypress Semiconductor Corporation
Document #: 38-07296 Rev. *B
CY23S05
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 22, 2002
CY23S05
CY23S09
Select Input Decoding for CY23S09
S2
S1
CLOCK A1–A4
CLOCK B1–B4
CLKOUT[1]
Output Source
PLL Shut-down
0
0
Three-state
Three-state
Driven
PLL
N
0
1
Driven
Three-state
Driven
PLL
N
1
0
Driven
Driven
Driven
Reference
Y
1
1
Driven
Driven
Driven
PLL
N
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs,
including CLKOUT, must be equally loaded. Even if CLKOUT
is not used, it must have a capacitive load equal to that on
other outputs, for obtaining zero input-output delay. If input to
output delay adjustments are required, use the above graph to
calculate loading differences between the CLKOUT pin and
other outputs.
For zero output-output skew, be sure to load all outputs
equally. For further information, refer to the application note
“CY23S05 and CY23S09 as PCI and SDRAM Buffers.”
Spread Aware
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we
designed this product so as not to filter off the Spread
Spectrum feature of the Reference input, assuming it exists.
When a zero delay buffer is not designed to pass the SS
feature through, the result is a significant amount of tracking
skew which may cause problems in systems requiring
synchronization.
For more details on Spread Spectrum timing technology,
please see the Cypress application note entitled, “EMI
Suppression Techniques with Spread Spectrum Frequency
Timing Generator (SSFTG) ICs.”
Note:
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document #: 38-07296 Rev. *B
Page 2 of 9
CY23S05
CY23S09
Pin Description for CY23S09
Pin
Signal
Description
1
REF[2]
Input reference frequency, 5V-tolerant input
2
CLKA1[3]
Buffered clock output, bank A
3
CLKA2[3]
Buffered clock output, bank A
4
VDD
3.3V supply
5
GND
Ground
6
CLKB1[3]
Buffered clock output, bank B
7
CLKB2[3]
Buffered clock output, bank B
8
S2
[4]
Select input, bit 2
9
S1[4]
Select input, bit 1
10
CLKB3[3]
Buffered clock output, bank B
11
CLKB4
[3]
Buffered clock output, bank B
12
GND
Ground
13
VDD
3.3V supply
14
CLKA3[3]
Buffered clock output, bank A
15
CLKA4[3]
Buffered clock output, bank A
16
CLKOUT[3]
Buffered output, internal feedback on this pin
Pin Description for CY23S05
Pin
Signal
Description
1
REF[2]
Input reference frequency, 5V-tolerant input
2
CLK2[3]
Buffered clock output
3
CLK1
[3]
Buffered clock output
4
GND
Ground
5
CLK3[3]
Buffered clock output
6
VDD
3.3V supply
7
CLK4[3]
Buffered clock output
8
CLKOUT[3]
Buffered clock output, internal feedback on this pin
Notes:
2. Weak pull-down.
3. Weak pull-down on all outputs.
4. Weak pull-up on these inputs.
Document #: 38-07296 Rev. *B
Page 3 of 9
CY23S05
CY23S09
Storage Temperature ................................. –65°C to +150°C
Maximum Ratings
Max. Soldering Temperature (10 sec.) ....................... 260°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Junction Temperature................................................. 150°C
DC Input Voltage (Except REF) ............–0.5V to VDD + 0.5V
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ........................... > 2,000V
DC Input Voltage REF ............................................. −0.5V to 7V
Operating Conditions for CY23S05SC-XX and CY23S09SC-XX Commercial Temperature Devices [5]
Parameter
Description
Min.
Max.
VDD
Supply Voltage
Unit
3.0
3.6
V
0
70
°C
Load Capacitance, below 100 MHz
30
pF
CL
Load Capacitance, from 100 MHz to 133 MHz
10
pF
CIN
Input Capacitance
7
pF
TA
Operating Temperature (Ambient Temperature)
CL
Electrical Characteristics for CY23S05SC-XX and CY23S09SC-XX Commercial Temperature Devices
Parameter
Description
Test Conditions
Min.
[6]
Input LOW Voltage
VIL
[6]
Max.
Unit
0.8
V
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0V
2.0
50.0
µA
IIH
Input HIGH Current
VIN = VDD
100.0
µA
0.4
V
VOL
Output LOW Voltage[7]
IOL = 8 mA (–1)
IOH = 12 mA (–1H)
VOH
Output HIGH Voltage[7]
IOH = –8 mA (–1)
IOL = –12 mA (–1H)
IDD (PD mode)
IDD
Power-down Supply Current
Supply Current
V
2.4
V
REF = 0 MHz
12.0
µA
Unloaded outputs at 66.67 MHz,
SEL inputs at VDD
32.0
mA
Switching Characteristics for CY23S05SC-1 and CY23S09SC-1 Commercial Temperature Devices[8]
Parameter
t1
Description
Test Conditions
Min.
30-pF load
10-pF load
10
10
Duty Cycle[7] = t2 ÷ t1
Measured at 1.4V, Fout = 66.67 MHz
40.0
[7]
Output Frequency
t3
Rise Time
t4
Fall Time[7]
[7]
Typ.
Max.
Unit
100
133.33
MHz
MHz
60.0
%
Measured between 0.8V and 2.0V
2.50
ns
Measured between 0.8V and 2.0V
2.50
ns
All outputs equally loaded
250
ps
50.0
t5
Output-to-Output Skew
t6
Delay, REF Rising Edge to
CLKOUT Rising Edge[7]
Measured at VDD/2
0
±350
ps
t7
Device-to-Device Skew[7]
Measured at VDD/2 on the CLKOUT
pins of devices
0
700
ps
tJ
Cycle-to-Cycle Jitter[7]
Measured at 66.67 MHz, loaded outputs
200
ps
Stable power supply, valid clock
presented on REF pin
1.0
ms
tLOCK
PLL Lock Time
[7]
Notes:
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6. REF input has a threshold voltage of VDD/2.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. All parameters specified with loaded outputs.
Document #: 38-07296 Rev. *B
Page 4 of 9
CY23S05
CY23S09
Switching Characteristics for CY23S05SI-1H and CY23S09SI-1H Industrial Temperature Devices[8]
Parameter
t1
t3
t4
Description
Output Frequency
Test Conditions
Min.
30-pF load
10-pF load
10
10
Typ.
Max.
Unit
100
133.33
MHz
MHz
Duty Cycle[7] = t2 ÷ t1
Measured at 1.4V, Fout = 66.67 MHz
40.0
50.0
60.0
%
Duty Cycle[7] = t2 ÷ t1
Measured at 1.4V, Fout <50.0 MHz
45.0
50.0
55.0
%
[7]
Measured between 0.8V and 2.0V
1.50
ns
Measured between 0.8V and 2.0V
1.50
ns
All outputs equally loaded
250
ps
Rise Time
Fall Time
[7]
[7]
t5
Output-to-Output Skew
t6
Delay, REF Rising Edge to
CLKOUT Rising Edge[7]
Measured at VDD/2
0
±350
ps
t7
Device-to-Device Skew[7]
Measured at VDD/2 on the CLKOUT
pins of devices
0
700
ps
t8
Output Slew Rate[7]
Measured between 0.8V and 2.0V using
Test Circuit #2
tJ
Cycle-to-Cycle Jitter[7]
Measured at 66.67 MHz, loaded outputs
200
ps
Stable power supply, valid clock
presented on REF pin
1.0
ms
tLOCK
PLL Lock Time[7]
1
V/ns
Switching Waveforms
Duty Cycle Timing
t1
t2
1.4V
1.4V
1.4V
2309–4
All Outputs Rise/Fall Time
OUTPUT
2.0V
0.8V
2.0V
0.8V
t3
3.3V
0V
t4
2309–5
Output-Output Skew
OUTPUT
1.4V
1.4V
OUTPUT
2309–6
t5
Document #: 38-07296 Rev. *B
Page 5 of 9
CY23S05
CY23S09
Switching Waveforms (continued)
Input-Output Propagation Delay
INPUT
VDD/2
VDD/2
OUTPUT
2309–7
t6
Device-Device Skew
VDD/2
CLKOUT, Device 1
VDD/2
CLKOUT, Device 2
2309–8
t7
Test Circuits
Test Circuit # 2
Test Circuit # 1
VDD
VDD
CLK out
0.1 µF
0.1 µF
OUTPUTS
0.1 µF
GND
1 kΩ
VDD
VDD
GND
OUTPUTS
10 pF
CLOAD
0.1 µF
1 kΩ
GND
GND
For parameter t8 (output slew rate) on –1H devices
Ordering Information
Ordering Code
CY23S05SC-1
Package Name
Package Type
Operating Range
S8
8-pin 150-mil SOIC
Commercial
CY23S05SC-1H
S8
8-pin 150-mil SOIC
Commercial
CY23S09SC-1
S16
16-pin 150-mil SOIC
Commercial
CY23S09SC-1H
S16
16-pin 150-mil SOIC
Commercial
CY23S09ZC-1
Z16
16-pin 4.4mm TSSOP
Commercial
CY23S09ZC-1H
Z16
16-pin 4.4mm TSSOP
Commercial
CY23S09OC-1
O16
16-pin 150-mil SSOP
Commercial
CY23S09OC-1H
O16
16-pin 150-mil SSOP
Commercial
Document #: 38-07296 Rev. *B
Page 6 of 9
CY23S05
CY23S09
Package Diagram
8-lead (150-Mil) SOIC S8
51-85066-A
16-lead (150-Mil) Molded SOIC S16
51-85068-A
Document #: 38-07296 Rev. *B
Page 7 of 9
CY23S09
CY23S05
16-lead Thin Shrunk Small Outline Package (4.40-MM Body) Z16
51-85091
16-lead (150-mil) QSOP Q1
51-85053-B
Pentium is a registered trademark of Intel Corporation. Spread Aware is a trademark of Cypress Semiconductor Corporation. All
product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07296 Rev. *B
Page 8 of 9
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY23S05
CY23S09
Document Title: CY23S09/CY23S05 Low-Cost 3.3V Spread Aware™ Zero Delay Buffer
Document Number: 38-07296
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
111147
11/14/01
DSG
Change from spec number 38-01094 to 38-07296
*A
111773
02/20/02
CTK
Add 150-mil SSOP option
*B
122885
12/22/02
RBI
Added power up requirements to Operating Conditions
Document #: 38-07296 Rev. *B
Page 9 of 9