CY62167DV20 MoBL2™ 16-Mb (1024K x 16) Static RAM Features toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW or both BHE and BLE are HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE LOW). • Very high speed: 55 ns and 70 ns • Wide voltage range: 1.65V to 2.2V • Ultra-low active power — Typical active current: 1.5 mA @ f = 1 MHz — Typical active current: 18 mA @ f = fMAX • Ultra-low standby power • Easy memory expansion with CE1, CE2, and OE features • Automatic power-down when deselected • CMOS for optimum speed/power • Packages offered in a 48-ball FBGA Writing to the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then das pins (A0 through A 19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the ad Functional Description [1] DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1024K x 16 RAM ARRAY 2048 x 512 x 16 ROW DECODER Logic Block Diagram Reading from the device is accomplished by taking Chip Enable 1 (CE 1) LOW and Chip Enable 2 (CE 2) HIGH and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (<>O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. SENSE AMPS The CY62167DV20 is a high-performance CMOS static RAM organized as 1024K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not I/O 0–I/O7 I/O 8–I/O15 COLUMN DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19 BHE WE CE2 CE1 OE BLE Power-down Circuit CE2 CE1 BHE BLE Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress SemiconductorCorporation Document #: 38-05327 Rev. *B • 3901 North First Street • SanJose, CA 95134 • 408-943-2600 Revised January 2, 2004 CY62167DV20 MoBL2™ Pin Configuration[2, 3.] 1 2 3 4 5 6 BLE OE A0 A1 A2 CE 2 A I/O8 BHE A3 A4 CE 1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VS S I/O11 A17 A7 I/O3 Vcc D VCC I/O12 DNU A16 I/O4 Vss E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H Notes: 2. DNU pins are to be connected to V SS or left open. 3. NC pins are not connected on the die. Document #: 38-05327 Rev. *B Page 2 of 10 CY62167DV20 MoBL2™ DC Input Voltage [4, 5.] ......................−0.2V to V CCMAX + 0.2V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage ......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature .................................–65°C to +150°C Latch-up Current.....................................................> 200 mA Ambient Temperature with Power Applied.............................................–55°C to +125°C Operating Range Supply Voltage to Ground Potential ......................................... −0.2V to V CCMAX + 0.2V DC Voltage Applied to Outputs in High-Z State [4, 5.] ......................... −0.2V to V CCMAX + 0.2V Range Ambient Temperature (TA) VCC[6] Industrial −40 oC to +85oC 1.65V to 2.2V Product Portfolio Power Dissipation Operating, Icc (mA) VCC Range(V) Product Min. Typ. Max. Speed (ns) CY62167DV20L 1.65 1.8 2.2 55 CY62167DV20LL 1.65 1.8 2.2 f = 1 MHz Typ. [7] Max. 1.5 5 1.5 5 f = fMAX Typ.[7] Max. 70 55 70 Standby, ISB2 (µA) Typ.[7] Max. 18 35 2.5 40 15 30 2.5 40 18 35 2.5 30 15 30 2.5 30 DC Electrical Characteristics (over the operating range) CY62167DV20-55 Parameter Description Test Conditions Min. Typ.[7] Max. VOH Output HIGH Voltage IOH = −0.1 mA VCC = 1.65V VOL Output LOW Voltage IOL = 0.1 mA VCC = 1.65V VIH Input HIGH Voltage 1.4 VCC + 0.2 VIL Input LOW Voltage –0.2 IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current ICC VCC Operating Supply f = fMAX = 1/t RC Current f = 1 MHz ISB1 ISB2 GND < VO < VCC, Output Disabled Vcc = 2.2V, IOUT = 0mA, CMOS level 1.4 CY62167DV20-70 Typ.[7] Min. Max. 1.4 Unit V 0.2 0.2 V 1.4 VCC + 0.2 V 0.4 –0.2 0.4 V –1 +1 –1 +1 µA –1 +1 –1 +1 µA mA 18 35 15 30 1.5 5 1.5 5 Automatic CE CE1 > VCC − 0.2V, CE2 < L Power-down Current − 0.2V, V IN > VCC − 0.2V, V IN LL CMOS Inputs < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE) 2.5 40 2.5 40 2.5 30 2.5 30 Automatic CE CE1 > VCC − 0.2V, CE2 < L Power-down Current − 0.2V, VIN > VCC − 0.2V or LL CMOS Inputs VIN < 0.2V, f = 0, V CC=2.2V 2.5 40 2.5 40 2.5 30 2.5 30 µA µA Capacitance [8] Parameter Description CIN Input Capacitance COUT Output Capacitance 4. 5. 6. 7. 8. Test Conditions TA = 25°C, f = 1 MHz VCC = VCC(typ) Max. Unit 8 pF 10 pF V IL(min.) = −2.0V for pulse durations less than 20 ns. V IH(max) = VCC + 0.75V for pulse durations less than 20 ns. Full device AC operation assumes a 100 µs ramp time from 0 to V cc (min) and 100 µs wait time after Vcc stabilization. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V CC = V CC(typ.), T A = 25°C. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05327 Rev. *B Page 3 of 10 CY62167DV20 MoBL2™ Thermal Resistance Parameter Description θJA Thermal Resistance (Junction to Ambient)[8] θJC Thermal Resistance (Junction to Case)[8] Test Conditions BGA Unit Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 55 C/W 16 C/W AC Test Loads and Waveforms R1 ALL INPUT PULSES VCC VCC Typ OUTPUT 10% 90% 10% 90% GND R2 CL = 30 pF Rise Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: Fall Time: 1 V/ns THÉVENIN EQUIVALENT OUTPUT RTH V Parameters 1.8 V UNIT R1 1350 0 Ω R2 1080 0 Ω R TH 6000 Ω V TH 0.80 V Data Retention Characteristics Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR [8] Chip Deselect to Data Retention Time tR[9] Operation Recovery Time Min. 1.0 VCC=1.0V, CE1 > VCC − 0.2V, CE2 < L 0.2V, V IN > VCC − 0.2V or VIN < 0.2V LL Typ. Max. Unit 2.2 V 15 µA 10 0 ns tRC ns Data Retention Waveform [10] DATA RETENTION MODE VCC VCC(min.) tCDR VDR > 1.0V VCC(min.) tR CE1 or BHE .BLE or CE2 Notes: 9. Full device operation requires linear VCC ramp from V DR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. 10. BHE . BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05327 Rev. *B Page 4 of 10 CY62167DV20 MoBL2™ Switching Characteristics (over the operating range)[11] Parameter Description CY62167DV20-55 CY62167DV20-70 Min. Min. Max. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid 55 70 tOHA Data Hold from Address Change tACE CE 1 LOW or CE2 HIGH to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns tLZOE OE LOW to Low Z[12] 55 10 10 5 [12, 13] tHZOE OE HIGH to High Z tLZCE CE 1 LOW or CE2 HIGH to Low Z[12] ns ns 5 ns 20 10 Z[12, 13] ns 70 25 10 ns tHZCE CE 1 HIGH or CE2 LOW to High tPU CE 1 LOW or CE2 HIGH to Power-up tPD CE 1 HIGH or CE2 LOW to Power-down 55 70 ns tDBE BLE/BHE LOW to Data Valid 55 70 ns tLZBE[10] BLE/BHE LOW to Low tHZBE BLE/BHE HIGH to High-Z[12, 13] Write Z[12] 20 ns 0 25 0 10 ns ns 5 ns 20 25 ns Cycle [14] tWC Write Cycle Time 55 70 ns tSCE CE 1 LOW or CE2 HIGH to Write End 40 60 ns tAW Address Set-up to Write End 40 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 40 45 ns tBW BLE/BHE LOW to Write End 45 60 ns tSD Data Set-up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns Z[12, 13] tHZWE WE LOW to High tLZWE WE HIGH to Low Z[12] 20 10 25 10 ns ns Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[15, 16] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 11. Test conditions assume signal transition time of 2 ns or less, timing reference levels of V CC(typ.)/2 , input pulse levels of 0 to V CC(typ.), and output loading of the specified I O L. 12. At any given temperature and voltage condition, tHZCE is less than tLZCE, t HZBE is less than t LZBE, tHZOE is less than tLZOE, and tHZWE is less than t LZWE for any given device. 13. tHZOE, t HZCE, t HZBE , and tHZWE transitions are measured when the outputs enter a high-impedance state. 14. The internal Write time of the memory is defined by the overlap of WE, CE 1 = V IL, BHE and/or BLE = V IL . 15. Device is continuously selected. OE, CE1 = V IL, CE2 = V IH 16. WE is HIGH for Read cycle. Document #: 38-05327 Rev. *B Page 5 of 10 CY62167DV20 MoBL2™ Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[16, 17] ADDRESS t RC CE 1 t PD t HZCE CE2 t ACE BHE / BLE t DBE t HZBE t LZBE OE t HZOE t DOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID t LZCE tPU VCC SUPPLY CURRENT ICC 50% 50% ISB Write Cycle No. 1 (WE Controlled)[14, 18, 19, 20] t WC ADDRESS t SCE CE1 CE2 t AW t HA t SA t PWE WE t BW BHE/BLE OE t SD DATA I/O t HD DATAIN VALID DON'T CARE t HZOE Notes: 17. Address valid prior to or coincident with CE 1, BHE, BLE transition LOW and CE 2 transition HIGH. 18. Data I/O is high-impedance if OE = V IH . 19. If CE 1 goes HIGH or CE 2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 20. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05327 Rev. *B Page 6 of 10 CY62167DV20 MoBL2™ Switching Waveforms (continued) Write Cycle No. 2 ( CE1 or CE2 Controlled)[14, 18, 19, 20] t WC ADDRESS t SCE CE1 CE2 t SA t AW t HA t PWE WE t BW BHE/BLE OE tS D DATA I/O t HD DATA IN VALID DON'T CARE t HZOE Write Cycle No. 3 (WE Controlled, OE LOW) [19, 20] tWC ADDRESS tSCE CE1 CE2 tA W tSA tHA tPWE WE tS D DATA I/O DATAIN VALID DON'T CARE tHZWE Document #: 38-05327 Rev. *B tHD tLZWE Page 7 of 10 CY62167DV20 MoBL2™ Switching Waveforms (continued) Write Cycle No. 4(BHE/BLE Controlled, OE LOW)[19] t WC ADDRESS CE 1 CE 2 t SCE t AW t HA t BW BHE/ BLE t SA t PWE WE t SD DATA I/O t HD DATAIN VALID DON'T CARE Truth Table CE1 CE2 WE OE BHE BLE H X X X X X X L X X X X X X X L H H L H L Mode Power High Z Deselect/Power-down Standby (I SB ) X High Z Deselect/Power-down Standby (I SB ) H H High Z Deselect/Power-down Standby (I SB ) L L L Data Out (I/O0– I/O15) Read Active (I CC) H L H L Data Out (I/O0– I/O7); High Z (I/O8– I/O15) Read Active (I CC) H H L L H High Z (I/O0– I/O7); Data Out (I/O8– I/O15) Read Active (I CC) L H H H L H High Z Output Disabled Active (I CC) L H H H H L High Z Output Disabled Active (I CC) L H H H L L High Z Output Disabled Active (I CC) L H L X L L Data In (I/O0– I/O15) Write Active (I CC) L H L X H L Data In High Z (I/O0– I/O7); (I/O8– I/O15) Write Active (I CC) L H L X L H High Z Data In (I/O0– I/O7); (I/O8– I/O15) Write Active (I CC) Document #: 38-05327 Rev. *B Input / Outputs Page 8 of 10 CY62167DV20 MoBL2™ Ordering Information Speed (ns) 55 70 Package Name Package Type Operating Range CY62167DV20L-55BVI BV48B 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) Industrial CY62167DV20LL-55BVI BV48B 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) CY62167DV20L-70BVI BV48B 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) CY62167DV20LL-70BVI BV48B 48-ball Fine Pitch BGA (8.0 x 9.5 x 1.0 mm) Ordering Code Industrial Package Diagrams 48-lead VFBGA (8 x 9.5 x 1 mm) BV48B 51-85178-** MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05327 Rev. *B Page 9 of 10 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62167DV20 MoBL2™ Document History Page Document Title: CY62167DV20 MoBL2™ 16-Mb (1024K x 16) Static RAM Document Number: 38-05327 REV. ECN NO. Issue Date Orig. of Change ** 118407 09/30/02 GUG New Data Sheet A 123691 02/11/03 DPM Changed Advance Information to Preliminary Added package diagram B 131496 11/25/03 XRJ/LDZ Document #: 38-05327 Rev. *B Description of Change Changed from Preliminary to Final Added MoBL2 to title Added package name BV48B Page 10 of 10