CY62157CV18 MoBL2™ 512K x 16 Static RAM Features The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). • High Speed — 55 ns and 70 ns availability • Low voltage range: — CY62157CV18: 1.65V–1.95V • Ultra-low active power — Typical Active Current: 0.5 mA @ f = 1 MHz • • • • Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). — Typical Active Current: 4 mA @ f = fmax (70 ns speed) Low standby power Easy memory expansion with CE1, CE2 and OE features Automatic power-down when deselected CMOS for optimum speed/power Reading from the device is accomplished by taking Chip Enable (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this datasheet for a complete description of read and write modes. Functional Description The CY62157CV18 is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The CY62157CV18 is available in a 48-ball FBGA package. Logic Block Diagram 512K x 16 RAM Array 2048 X 4096 SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A11 A12 A13 A14 A15 A16 A17 A18 BHE WE CE2 CE1 OE BLE Power -Down Circuit BHE BLE CE2 CE1 MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation Document #: 38-05012 Rev. *C • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised October 31, 2001 CY62157CV18 MoBL2™ Pin Configuration[1, 2] FBGA Top View 4 3 1 2 BLE OE A0 I/O8 BHE I/O9 5 6 A1 A2 CE2 A A3 A4 CE1 I/O0 B I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vccq D VCC I/O12 DNU A16 I/O4 Vssq E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G A18 A8 A9 A10 A11 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.2V to +2.4V NC H DC Voltage Applied to Outputs in High Z State[3 .............................................]–0.2V to VCC + 0.2V DC Input Voltage[3] ................................ −0.2V to VCC + 0.2V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .....................................................>200 mA Operating Range Device CY62157CV18 Range Ambient Temperature VCC Industrial –40°C to +85°C 1.65V to 1.95V Product Portfolio Power Dissipation (Industrial) Operating (ICC) VCC Range f = 1 MHz f = fmax Standby (ISB2) Product Min. Typ.[4] Max. Speed Typ.[4] Max. Typ.[4] Max. Typ.[4] Max. CY62157CV18 1.65V 1.8V 1.95V 55 ns 0.5 mA 3 mA 5 mA 15 mA 1.5 µA 20 µA 70 ns 0.5 mA 3 mA 4 mA 12 mA Notes: 1. NC pins are not connected to the die. 2. E3 (DNU) can be left as NC or VSS to ensure proper application. 3. VIL(min.) = –2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. Document #: 38-05012 Rev. *C Page 2 of 11 CY62157CV18 MoBL2™ Electrical Characteristics Over the Operating Range CY62157CV18-55 Parameter Description Test Conditions Min. Typ. VOH Output HIGH Voltage IOH = –0.1 mA VCC = 1.65V VOL Output LOW Voltage IOL = 0.1 mA VCC = 1.65V VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Leakage Current GND < VI < VCC IOZ Output Leakage Current GND < VO < VCC, Output Disabled VCC Operating Supply Current f = fMAX = 1/tRC ICC f = 1 MHz ISB1 ISB2 Automatic CE CE1 > VCC – 0.2V or CE2 < 0.2V, Power-Down Current— VIN > VCC – 0.2V or VIN < 0.2V, f = 0, VCC = 1.95V CMOS Inputs CY62157CV18-70 Min. Typ.[4] Max. 1.4 Max. Unit 1.4 V 0.2 V 1.4 VCC +0.2V 0.2 1.4 VCC +0.2V V –0.2 0.4 –0.2 0.4 V –1 +1 –1 +1 µA –1 +1 –1 +1 µA VCC = 1.95V IOUT = 0 mA CMOS levels Automatic CE CE1 > VCC − 0.2V, CE2< 0.2V Power-Down Current— VIN > VCC – 0.2V, VIN < 0.2V) f = fMAX (Address and Data Only), CMOS Inputs f = 0 (OE, WE, BHE, and BLE) [4] 5 15 4 12 mA 0.5 3 0.5 3 mA 1.5 20 1.5 20 µA Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 6 pF 8 pF TA = 25°C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance Description Thermal Resistance (Junction to Ambient)[5] Test Conditions Symbol BGA Unit Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board ΘJA 55 °C/W ΘJC 16 °C/W Thermal Resistance (Junction to Case)[5] Note: 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05012 Rev. *C Page 3 of 11 CY62157CV18 MoBL2™ AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES OUTPUT VCC Typ R2 30 pF 90% 10% GND Rise Time = 1 V/ns 90% 10% Fall Time = 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters 1.8V Unit R1 13500 R2 10800 RTH 6000 Ohms Ohms Ohms VTH 0.80 Volts Data Retention Characteristics (Over the Operating Range) Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR[5] Chip Deselect to Data Retention Time tR[6] Operation Recovery Time Conditions Min. Typ.[4] 1.0 VCC= 1.0V CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V 1 Max. Unit 1.95 V 10 µA 0 ns tRC ns Data Retention Waveform[7] DATA RETENTION MODE VCC VCC, min. tCDR VDR > 1.0 V VCC, min. tR CE1 or BHE,BLE or CE2 Notes: 6. Full Device operation requires linear VCC ramp from VDR to VCC(min.) > 100 us or stable at VCC(min.) > 100 µs. 7. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05012 Rev. *C Page 4 of 11 CY62157CV18 MoBL2™ Switching Characteristics Over the Operating Range[8] 55 ns Parameter Description Min. 70 ns Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid 55 tOHA Data Hold from Address Change tACE CE1 LOW and CE2 HIGH to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z[9] 10 tLZCE 10 25 5 OE HIGH to High Z CE1 LOW and CE2 HIGH to Low Z 10 [9, 10] 70 ns 35 ns ns 25 10 ns ns tHZCE CE1 HIGH and CE2 LOW to High Z tPU CE1 LOW and CE2 HIGH to Power-Up tPD CE1 HIGH and CE2 LOW to Power-Down 55 70 ns tDBE BLE / BHE LOW to Data Valid 55 70 ns [9] tLZBE BLE / BHE LOW to Low Z tHZBE BLE / BHE HIGH to HIGH Z[9, 10] 20 ns ns 5 20 [9] ns 70 55 [9, 10] tHZOE 70 55 0 25 0 5 ns 5 20 ns ns 25 ns [11] WRITE CYCLE tWC Write Cycle Time 55 70 ns tSCE CE1 LOW and CE2 HIGH to Write End 45 60 ns tAW Address Set-Up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 45 50 ns tBW BLE / BHE LOW to Write End 45 60 ns tSD Data Set-Up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns [9, 10] tHZWE WE LOW to High Z tLZWE WE HIGH to Low Z[9] 20 5 25 10 ns ns Notes: 8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30-pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device 10. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 11. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL, CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05012 Rev. *C Page 5 of 11 CY62157CV18 MoBL2™ Switching Waveforms Read Cycle No. 1 (Address Transition controlled)[12, 13] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID Read Cycle No. 2 (OE controlled)[13, 14] ADDRESS tRC CE1 tPD tHZCE CE2 tACE BHE/BLE tDBE tHZBE tLZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT ICC tPU 50% 50% ISB Notes: 12. Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05012 Rev. *C Page 6 of 11 CY62157CV18 MoBL2™ Switching Waveforms (continued) Write Cycle No. 1(WE Controlled) [11, 15, 16] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID NOTE 17 tHZOE Write Cycle No. 2 (CE1 or CE2 Controlled) [11, 15, 16] tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID NOTE 17 tHZOE Notes: 15. Data I/O is high impedance if OE = VIH. 16. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied. Document #: 38-05012 Rev. *C Page 7 of 11 CY62157CV18 MoBL2™ Switching Waveforms (continued) [16] Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW tHA tSA tPWE WE tSD DATAI/O NOTE 17 tHD DATAIN VALID tLZWE tHZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [16] tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA I/O NOTE 17 Document #: 38-05012 Rev. *C tHD DATAIN VALID Page 8 of 11 CY62157CV18 MoBL2™ Typical DC and AC Characteristics (Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C) Standby Current vs. Supply Voltage Operating Current vs. Supply Voltage 3.0 6.0 (f = fmax, 55 ns) ICC (mA) (f = fmax, 70 ns) 4.0 2.5 ISB (µA) MoBL2 5.0 MoBL2 2.0 1.5 3.0 1.0 2.0 0.5 1.0 (f = 1 MHz) 0.0 1.65 1.80 SUPPLY VOLTAGE (V) 0 1.65 1.95 1.80 1.95 SUPPLY VOLTAGE (V) Access Time vs. Supply Voltage 40 MoBL2 35 TAA (ns) 30 25 20 15 10 1.65 1.95 1.80 SUPPLY VOLTAGE (V) Truth Table CE1 CE2 WE OE BHE BLE H X X X X X X L X X X Inputs/Outputs Mode Power High Z Deselect/Power-Down Standby (ISB) X High Z Deselect/Power-Down Standby (ISB) X X X X H H High Z Deselect/Power-Down Standby (ISB) L H H L L L Data Out (I/O0–I/O15) Read Active (ICC) L H H L H L Data Out (I/O0–I/O7); High Z (I/O8–I/O15) Read Active (ICC) L H H L L H High Z (I/O0–I/O7); Data Out (I/O8–I/O15) Read Active (ICC) L H H H L H High Z Output Disabled Active (ICC) L H H H H L High Z Output Disabled Active (ICC) L H H H L L High Z Output Disabled Active (ICC) L H L X L L Data In (I/O0–I/O15) Write Active (ICC) L H L X H L Data In High Z (I/O0–I/O7); (I/O8–I/O15) Write Active (ICC) L H L X L H High Z Data In (I/O0–I/O7); (I/O8–I/O15) Write Active (ICC) Document #: 38-05012 Rev. *C Page 9 of 11 CY62157CV18 MoBL2™ Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 55 CY62157CV18LL-55BAI BA48F 48-Ball Fine Pitch BGA Industrial 70 CY62157CV18LL-70BAI Package Diagram 48-Ball (6 mm x 10 mm x 1.2 mm) Fine Pitch BGA BA48F 51-85128-*A Document #: 38-05012 Rev. *C Page 10 of 11 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62157CV18 MoBL2™ Document Title:CY62157CV18 MoBL2™ 512K x 16 Static RAM Document Number: 38-05012 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106158 04/06/01 MGN New Data Sheet, replaces CY62157BV18. *A 107242 07/31/01 MGN Changing from Preliminary to Final. *B 109231 08/31/01 MGN Add comment on front page about Active Current at different frequencies. *C 110574 11/02/01 MGN Improved tDOE from 35 ns to 25 ns (@55 ns). Added Typical DC & AC Characteristics. Format standardization Document #: 38-05012 Rev. *C Page 11 of 11