CY7C6435x CY7C64345, CY7C6431x PRELIMINARY enCoRe™ V Full-Speed USB Controller Features ❐ Configurable inputs on all GPIO Low dropout voltage regulator for Port1 pins. Programmable to output 3.0, 2.5, or 1.8V at the IO pins. ❐ Selectable, regulated digital IO on Port 1 • Configurable Input Threshold for Port 1 • 3.0V, 20 mA Total Port 1 Source Current • Hot-Swappable ❐ 5 mA Strong drive mode on Ports 0 and 1 ❐ ■ Powerful Harvard Architecture Processor ❐ M8C Processor speeds running up to 24 MHz ❐ Low power at high processing speeds ❐ Interrupt controller ❐ 3.0V to 5.5V Operating voltage ❐ Temperature range: 0°C to 70°C ■ Flexible On-Chip Memory ❐ Up to 32K Flash program storage 50,000 Erase/write cycles ❐ Up to 2048 bytes SRAM data storage ❐ Flexible protection modes ❐ In-System Serial Programming (ISSP) ■ Complete Development Tools ❐ Free development tool (PSoC Designer™) ❐ Full-featured, in-circuit emulator and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128K Trace memory ■ Precision, Programmable Clocking ❐ Crystal-less oscillator with support for an external crystal or resonator ❐ Internal ±5.0% 6/12/24 MHz main oscillator ❐ Internal low-speed oscillator at 32 kHz for watchdog and sleep. The frequency range is 19-50 kHz with a 32 kHz typical value. ❐ 0.25% Accuracy for USB with no external components ■ Programmable Pin Configurations ❐ 25 mA Sink current on all GPIO ❐ Pull up, high Z, open drain, CMOS drive modes on all GPIO enCoRe V Block Diagram Port 4 Port 3 ■ Full-Speed USB (12 Mbps) ❐ Eight unidirectional endpoints ❐ One bidirectional control endpoint ❐ USB 2.0 compliant ❐ Dedicated 512 bytes buffer ❐ No external crystal required ■ Additional System Resources ❐ Configurable communication speeds 2 ❐ I C™ slave • Selectable to 50 kHz, 100 kHz, or 400 kHz • Implementation requires no clock stretching • Implementation during sleep modes with less than 100 μA • Hardware address detection ❐ SPI master and SPI slave • Configurable between 46.9 kHz - 3 MHz ❐ Three 16-bit timers ❐ 10-bit ADC to use for monitoring battery voltage or other signals ❐ Watchdog and sleep timers ❐ Integrated supervisory circuit Port 2 Port 1 Port 0 Prog. LDO enCoRe V CORE System Bus SRAM 2048 Bytes SROM Flash 32K CPU Core (M8C) Interrupt Controller Sleep and Watchdog 6/12/24 MHz Internal Main Oscillator 3 16-Bit Timers I2C Slave/SPI Master-Slave POR and LVD System Resets Full Speed USB SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 001-12394 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 17, 2007 [+] Feedback PRELIMINARY CY7C6435x CY7C64345, CY7C6431x ■ Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (power on reset) circuit eliminates the need for a system supervisor. ■ The 5V maximum input, 1.8/2.5/3V-selectable output, low-dropout regulator (LDO) provides regulation for IOs. A register controlled bypass mode allows the user to disable the LDO. The architecture for this device family, as illustrated (enCoRe V), is comprised of three main areas: the CPU core, the system resources, and the full-speed USB system. Depending on the enCoRe V package, up to 36 general purpose IO (GPIO) are also included. ■ Standard Cypress PSoC IDE tools are available for debugging the enCoRe V family of parts. This product is an enhanced version of Cypress’ successful full-speed USB peripheral controllers. Enhancements include faster CPU at lower voltage operation, lower current consumption, twice the RAM and Flash, hot-swapable IOs, I2C hardware address recognition, new very low current sleep mode, and new package options. The quickest path to understanding the enCoRe V silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the enCoRe V integrated circuit and presents specific pin, register, and electrical specifications. Functional Overview The enCoRe V family of devices are designed to replace multiple traditional full-speed USB microcontroller system components with one, low cost single-chip programmable component. Communication peripherals (I2C/SPI), a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts. The enCoRe V Core The enCoRe V Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four-MIPS, 8-bit Harvard architecture microprocessor. System resources provide additional capability, such as a configurable I2C slave/SPI master-slave communication interface and various system resets supported by the M8C. Additional System Resources System resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. Brief statements describing the merits of each system resource are presented below. ■ Full-speed USB (12 Mbps) with nine configurable endpoints and 512 bytes of dedicated USB RAM. No external components are required except two series resistors. It is specified for commercial temperature USB operation. For reliable USB operation, ensure the supply voltage is between 4.35V and 5.25V, or around 3.3V. ■ 10-bit on-chip ADC shared between system performance manager (used to calculate parameters based on temperature for flash write operations) and the user. ■ The I2C slave/SPI master-slave module provides 50/100/400 kHz communication over two wires. SPI communication over 3 or 4 wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). ■ In the case of I2C slave mode, the hardware address recognition feature reduces the already low power consumption by eliminating the need for CPU intervention until a packet addressed to the target device has been received. Document Number: 001-12394 Rev. *D Getting Started For up-to-date ordering, packaging, and electrical specification information, reference the latest enCoRe V device data sheets on the web at http://www.cypress.com. Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click USB (Universal Serial Bus) to view a current list of available items. Technical Training Free PSoC and USB technical training is available for beginners and is taught by a marketing or application engineer over the phone. PSoC training classes cover designing, debugging, advanced analog, as well as application-specific classes covering topics such as PSoC, USB and the LIN bus. Go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select Technical Training for more details. Consultants Certified Cypress USB Consultants offer everything from technical assistance to completed USB designs. To contact or become a Cypress PSoC/USB Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants. Technical Support Cypress application engineers take pride in fast and accurate response. You can reach them with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm. Application Notes Many application notes are available to assist you in every aspect of your design effort. To view the USB application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. By default, application notes are sorted by date . Page 2 of 26 [+] Feedback PRELIMINARY CY7C6435x CY7C64345, CY7C6431x Development Tools using the enCoRe V device blocks. Examples of user modules are timers, 10-bit ADC, SPI/I2C etc. PSoC Designer is a Microsoft Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.) The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration allows for changing configurations at run time. PSoC Designer helps the customer to select an operating configuration for the USB, write application code that uses the USB, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. Figure 1. PSoC Designer Subsystems PSoC Designer sets up power-on initialization tables for selected enCoRe V block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of enCoRe V block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It is also possible to change the selected components and regenerate the framework. Application Editor In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler allows the merging of assembly code seamlessly with C code. The link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports the enCoRe V family of devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the enCoRe V family devices. The embedded, optimizing C compiler provides all the features of C tailored to the enCoRe V architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read the program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System PSoC Designer Software Subsystems Device Editor The device editor subsystem allows the user to select different onboard analog and digital components called user modules Document Number: 001-12394 Rev. *D The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Page 3 of 26 [+] Feedback PRELIMINARY Hardware Tools CY7C6435x CY7C64345, CY7C6431x Figure 2. User Module and Source Code Development Flows In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with most Cypress USB and all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the enCoRe V device in the target board and performs full-speed (24 MHz) operation. Designing with User Modules To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a feature where the resources of the part are selected as user modules. For example, the timers, I2C, SPI resources are available as user modules. User modules make selecting and implementing peripheral devices simple and easy. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides high-level functions to control and respond to hardware events at run time. The API also provides optional interrupt service routines that you can adapt as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick and place the user modules you need for your project. The tool automatically builds signal chains by connecting user modules to the default IO pins or as required. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions. Device Editor User Module Selection Source Code Generator Generate Application Application Editor Project Manager Source Code Editor Build Manager Build All Debugger Interface to ICE Storage Inspector Event & Breakpoint Manager The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive “grep-style” patterns. A single mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full-speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Document Number: 001-12394 Rev. *D Page 4 of 26 [+] Feedback CY7C6435x CY7C64345, CY7C6431x PRELIMINARY Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Acronym Description Acronym Description POR power on reset PPOR precision power on reset PSoC® Programmable System-on-Chip™ SLIMO slow IMO SRAM static random access memory API application programming interface CPU central processing unit Units of Measure GPIO general purpose IO GUI graphical user interface ICE in-circuit emulator A units of measure table is located in the Electrical Specifications section. Table 5 on page 15 lists all the abbreviations used to measure the enCoRe V devices. ILO internal low speed oscillator Numeric Naming IMO internal main oscillator IO input/output LSb least-significant bit LVD low voltage detect MSb most-significant bit Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal. Document Number: 001-12394 Rev. *D Page 5 of 26 [+] Feedback CY7C6435x CY7C64345, CY7C6431x PRELIMINARY Pin Configuration The enCoRe V USB device is available in a variety of packages which are listed and illustrated in the subsequent tables. 16-Pin Part Pinout P2[5] P0[1] P0[3] P0[7] 15 14 13 7 8 D– P0[4] XRES P1[4] P1[0] Vdd 6 D+ 12 QFN 11 (Top View) 10 9 5 P1[5] P1[1] 1 2 3 4 Vss P2[3] P1[7] 16 Figure 3. CY7C64315/CY7C64316 16-Pin enCoRe V Device Table 1. 16-Pin Part Pinout (QFN) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type Digital IO IOHR IOHR IOHR Power USB line USB line Power IOHR IOHR Input IOH IOH IOH IOH IO Name P2[3] P1[7] P1[5] P1[1](1) Vss D+ D– Vdd P1[0](1) P1[4] XRES P0[4] P0[7] P0[3] P0[1] P2[5] Description Digital IO, Crystal Input (Xin) Digital IO, SPI SS, I2C SCL Digital IO, SPI MISO, I2C SDA Digital IO, ISSP CLK, 12C SCL, SPI MOSI Ground connection USB PHY USB PHY Supply Digital IO, ISSP DATA, I2C SDA, SPI CLK Digital IO, optional external clock input (EXTCLK) Active high external reset with internal pull down Digital IO Digital IO Digital IO Digital IO Digital IO, Crystal Output (Xout) LEDGEND I = Input, O = Outpit, OH = 5 mA High Output Drive, R = Regulated Output. Note 1. These are the in-system serial programming (ISSP) pins, that are not High Z at power on reset (POR). Document Number: 001-12394 Rev. *D Page 6 of 26 [+] Feedback CY7C6435x CY7C64345, CY7C6431x PRELIMINARY 32-Pin Part Pinout P0[5] P0[7] Vdd P0[6] P0[4] P0[2] 30 29 28 27 26 25 P0[3] Vss 32 31 Figure 4. CY7C64345 32-Pin enCoRe V USB Device P0[1] 1 24 P0[0] P2[5] P2[3] 2 23 P2[6] 18 P3[0] 17 XRES D+ 16 P3[2] 15 19 7 8 P1[6] 6 P1[4] P1[5] P1[3] P1[1] P1[2] P2[0] 13 14 20 P1[0] ( Top View) 12 5 Vdd P2[4] P2[2] 11 22 21 D– QFN 9 10 3 4 Vss P2[1] P1[7] Table 2. 32-Pin Part Pinout (QFN) Pin No. Type Name Description 1 IOH P0[1] Digital IO 2 IO P2[5] Digital IO, Crystal Output (Xout) 3 IO P2[3] Digital IO, Crystal Input (Xin) 4 IO P2[1] Digital IO 5 IOHR P1[7] Digital IO, I2C SCL, SPI SS 6 IOHR P1[5] Digital IO, I2C SDA, SPI MISO 7 IOHR P1[3] Digital IO, SPI CLK 8 IOHR P1[1](2) Digital IO, ISSP CLK, I2C SCL, SPI MOSI 9 Power Vss Ground 10 IO D+ USB PHY 11 IO D– USB PHY 12 Power Vdd Supply voltage 13 IOHR P1[0](2) Digital IO, ISSP DATA, I2C SDA, SPI CLK 14 IOHR P1[2] Digital IO 15 IOHR P1[4] Digital IO, optional external clock input (EXTCLK) 16 IOHR P1[6] Digital IO 17 Reset XRES Active high external reset with internal pull down 18 IO P3[0] Digital IO 19 IO P3[2] Digital IO 20 IO P2[0] Digital IO 21 IO P2[2] Digital IO Note 2. These are the in-system serial programming (ISSP) pins, that are not High Z at power on reset (POR). Document Number: 001-12394 Rev. *D Page 7 of 26 [+] Feedback CY7C6435x CY7C64345, CY7C6431x PRELIMINARY Table 2. 32-Pin Part Pinout (QFN) (continued) Pin No. Type Name Description 22 IO P2[4] Digital IO 23 IO P2[6] Digital IO 24 IOH P0[0] Digital IO 25 IOH P0[2] Digital IO 26 IOH P0[4] Digital IO 27 IOH P0[6] Digital IO 28 Power Vdd Supply voltage 29 IOH P0[7] Digital IO 30 IOH P0[5] Digital IO 31 IOH P0[3] Digital IO 32 Power Vss Ground CP Power Vss Ensure the center pad is connected to ground LEDGEND I = Input, O = Outpit, OH = 5 mA High Output Drive, R = Regulated Output. Document Number: 001-12394 Rev. *D Page 8 of 26 [+] Feedback CY7C6435x CY7C64345, CY7C6431x PRELIMINARY 48-Pin Part Pinout P0[0] 38 37 39 Vdd P0[6] P0[4] P0[2] P0[7] NC NC 42 41 40 43 P0[5] 45 44 46 47 1 2 7 8 9 10 P3[1] P1[7] 11 12 5 6 QFN 30 29 28 27 18 19 20 21 22 23 24 Vss D+ DVdd P1[0] 26 25 P2[6] P2[4] P2[2] P2[0] P4[2] P4[0] P3[6] P3[4] P3[2] P3[0] XRES P1[6] P1[4] 17 P1[1] P1[2] 16 15 P1[3] (Top View) 13 14 P1[5] 36 35 34 33 32 31 3 4 P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] NC NC NC P2[7] P2[5] 48 P0[1] Vss P0[3] Figure 5. CY7C64355/CY7C64356 48-Pin enCoRe V USB Device Table 3. 48-Pin Part Pinout (QFN) Pin No. Type 1 NC NC No connection 2 IO P2[7] Digital IO 3 IO P2[5] Digital IO, Crystal Out (Xout) 4 IO P2[3] Digital IO, Crystal In (Xin) 5 IO P2[1] Digital IO 6 IO P4[3] Digital IO 7 IO P4[1] Digital IO 8 IO P3[7] Digital IO 9 IO P3[5] Digital IO 10 IO P3[3] Digital IO 11 IO P3[1] Digital IO 12 IOHR P1[7] Digital IO, I2C SCL, SPI SS 13 IOHR P1[5] Digital IO, I2C SDA, SPI MISO 14 NC NC No connection 15 NC NC No connection 16 IOHR P1[3] Digital IO, SPI CLK 17 IOHR P1[1](3) Digital IO, ISSP CLK, I2C SCL, SPI MOSI 18 Power Vss Supply ground 19 IO D+ USB 20 IO D– USB 21 Power Vdd Supply voltage IOHR P1[0](3) Digital IO, ISSP DATA, I2C SDA, SPI CLK 22 Pin Name Description Note 3. These are the in-system serial programming (ISSP) pins, that are not High Z at power on reset (POR). Document Number: 001-12394 Rev. *D Page 9 of 26 [+] Feedback PRELIMINARY CY7C6435x CY7C64345, CY7C6431x Table 3. 48-Pin Part Pinout (QFN) (continued) Pin No. Type Pin Name Description 23 IOHR P1[2] Digital IO, 24 IOHR P1[4] Digital IO, optional external clock input (EXTCLK) 25 IOHR P1[6] Digital IO 26 XRES Ext Reset Active high external reset with internal pull down 27 IO P3[0] Digital IO 28 IO P3[2] Digital IO 29 IO P3[4] Digital IO 30 IO P3[6] Digital IO 31 IO P4[0] Digital IO 32 IO P4[2] Digital IO 33 IO P2[0] Digital IO 34 IO P2[2] Digital IO 35 IO P2[4] Digital IO 36 IO P2[6] Digital IO 37 IOH P0[0] Digital IO 38 IOH P0[2] Digital IO 39 IOH P0[4] Digital IO 40 IOH P0[6] Digital IO 41 Power Vdd Supply voltage 42 NC NC No connection 43 NC NC No connection 44 IOH P0[7] Digital IO 45 IOH P0[5] Digital IO 46 IOH P0[3] Digital IO 47 Power Vss Supply ground 48 IOH P0[1] Digital IO LEDGEND I = Input, O = Outpit, OH = 5 mA High Output Drive, R = Regulated Output. Document Number: 001-12394 Rev. *D Page 10 of 26 [+] Feedback CY7C6435x CY7C64345, CY7C6431x PRELIMINARY Register Reference The section discusses the registers of the enCoRe V device. It lists all the registers in mapping tables, in address order. Register Conventions The register conventions specific to this section and the Register Reference chapter are listed in the following table. Table 4. Register Conventions Convention Description R Read register or bits W Write register or bits O Only a read/write register or bits L Logical register or bits C Clearable register or bits # Access is bit specific Register Mapping Tables The enCoRe V device has a total register address space of 512 bytes. The register space is also referred to as IO space and is broken into two parts: Bank 0 (user space) and Bank 1 (configuration space). The XIO bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XIO bit is set, the user is said to be in the “extended” address space or the “configuration” registers. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT1DR PRT1IE PRT2DR PRT2IE PRT3DR PRT3IE PRT4DR PRT4IE Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 Access RW RW RW RW RW RW RW RW Name EP1_CNT0 EP1_CNT1 EP2_CNT0 EP2_CNT1 EP3_CNT0 EP3_CNT1 EP4_CNT0 EP4_CNT1 EP5_CNT0 EP5_CNT1 EP6_CNT0 EP6_CNT1 EP7_CNT0 EP7_CNT1 EP8_CNT0 EP8_CNT1 RW RW PMA0_DR PMA1_DR PMA2_DR PMA3_DR PMA4_DR PMA5_DR PMA6_DR PMA7_DR 22 Gray fields are reserved; do not access these fields. Document Number: 001-12394 Rev. *D Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 Access # RW # RW # RW # RW # RW # RW # RW # RW RW RW RW RW RW RW RW RW 62 # Access is bit specific. Name Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 Access Name I2C_XCFG I2C_XSTAT I2C_ADDR I2C_BP I2C_CP CPU_BP CPU_CP I2C_BUF CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK2 INT_MSK1 INT_MSK0 INT_SW_E N INT_VC Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 Access RW R RW R R RW R RW RW RW RW RW RW RW # RW RW RW RW RW RW RW RW RW RC Page 11 of 26 [+] Feedback CY7C6435x CY7C64345, CY7C6431x PRELIMINARY Addr Name (0,Hex) Access 23 24 PMA8_DR 25 PMA9_DR 26 PMA10_DR 27 PMA11_DR 28 PMA12_DR SPI_TXR 29 W PMA13_DR SPI_RXR 2A R PMA14_DR SPI_CR 2B # PMA15_DR 2C TMP_DR0 2D TMP_DR1 2E TMP_DR2 2F TMP_DR3 30 USB_SOF0 31 R USB_SOF1 32 R USB_CR0 33 RW USBIO_CR0 34 # USBIO_CR1 35 # EP0_CR 36 # EP0_CNT0 37 # EP0_DR0 38 RW EP0_DR1 39 RW EP0_DR2 3A RW EP0_DR3 3B RW EP0_DR4 3C RW EP0_DR5 3D RW EP0_DR6 3E RW EP0_DR7 3F RW Gray fields are reserved; do not access these fields. Name Document Number: 001-12394 Rev. *D Addr Access Name (0,Hex) 63 64 RW 65 RW 66 RW 67 RW 68 RW 69 RW 6A RW 6B RW 6C RW 6D RW 6E RW 6F RW 70 PT0_CFG 71 PT0_DATA1 72 PT0_DATA0 73 PT1_CFG 74 PT1_DATA1 75 PT1_DATA0 76 PT2_CFG 77 PT2_DATA1 78 PT2_DATA0 79 7A 7B 7C 7D 7E 7F # Access is bit specific. Addr (0,Hex) A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Access Name RES_WDT INT_MSK3 RW RW RW RW RW RW RW RW RW CPU_F CPU_SCR1 CPU_SCR0 Addr (0,Hex) E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access W RW RL # # Page 12 of 26 [+] Feedback CY7C6435x CY7C64345, CY7C6431x PRELIMINARY Register Map Bank 1 Table: Configuration Space Addr Access Name (1,Hex) PRT0DM0 00 RW PMA4_RA PRT0DM1 01 RW PMA5_RA 02 PMA6_RA 03 PMA7_RA PRT1DM0 04 RW PMA8_WA PRT1DM1 05 RW PMA9_WA 06 PMA10_WA 07 PMA11_WA PRT2DM0 08 RW PMA12_WA PRT2DM1 09 RW PMA13_WA 0A PMA14_WA 0B PMA15_WA PRT3DM0 0C RW PMA8_RA PRT3DM1 0D RW PMA9_RA 0E PMA10_RA 0F PMA11_RA PRT4DM0 10 RW PMA12_RA PRT4DM1 11 RW PMA13_RA 12 PMA14_RA 13 PMA15_RA 14 EP1_CR0 15 EP2_CR0 16 EP3_CR0 17 EP4_CR0 18 EP5_CR0 19 EP6_CRO 1A EP7_CR0 1B EP8_CR0 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 SPI_CFG 29 RW 2A 2B 2C TMP_DR0 2D TMP_DR1 2E TMP_DR2 2F TMP_DR3 USB_CR1 30 # 31 32 USBIO_CR2 33 RW PMA0_WA 34 RW PMA1_WA 35 RW PMA2_WA 36 RW PMA3_WA 37 RW PMA4_WA 38 RW PMA5_WA 39 RW Gray fields are reserved; do not access these fields. Name Document Number: 001-12394 Rev. *D Addr Access Name (1,Hex) 40 RW 41 RW 42 RW 43 RW 44 RW 45 RW 46 RW 47 RW 48 RW 49 RW 4A RW 4B RW 4C RW 4D RW 4E RW 4F RW 50 RW 51 RW 52 RW 53 RW 54 # 55 # 56 # 57 # 58 # 59 # 5A # 5B # 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C RW 6D RW 6E RW 6F RW 70 71 72 73 74 75 76 77 78 79 # Access is bit specific. Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 Access Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB IO_CFG DC OUT_P1 DD DE DF OSC_CR0 E0 ECO_CFG E1 OSC_CR2 E2 VLT_CR E3 VLT_CMP E4 E5 E6 E7 IMO_TR E8 ILO_TR E9 EA SLP_CFG EB SLP_CFG2 EC SLP_CFG3 ED EE EF F0 F1 F2 F3 F4 F5 F6 CPU_F F7 F8 F9 Name Access RW RW RW # RW RW R W W RW RW RW RL Page 13 of 26 [+] Feedback CY7C6435x CY7C64345, CY7C6431x PRELIMINARY Addr Name (1,Hex) Access PMA6_WA 3A RW PMA7_WA 3B RW PMA0_RA 3C RW PMA1_RA 3D RW PMA2_RA 3E RW PMA3_RA 3F RW Gray fields are reserved; do not access these fields. Name Document Number: 001-12394 Rev. *D Addr Access Name (1,Hex) 7A 7B 7C 7D 7E 7F # Access is bit specific. Addr (1,Hex) BA BB BC BD BE BF Access Name Addr (1,Hex) FA FB FC FD FE FF Access Page 14 of 26 [+] Feedback PRELIMINARY CY7C6435x CY7C64345, CY7C6431x Electrical Specifications This chapter presents the DC and AC electrical specifications of the enCoRe V USB devices. For the most up to date electrical specifications, verify that you have the most recent data sheet available by visiting the company web site at http://www.cypress.com Figure 6. Voltage versus CPU Frequency 5.5V lid ng Va rati n pe gio Re Vdd Voltage O 3.0V 750 kHz 3 MHz 24 MHz CPU Frequency Figure 7. IMO Frequency Trim Options 5.5V Vdd Voltage SLIMO Mode = 01 SLIMO Mode = 00 SLIMO Mode = 10 3.0V 750 kHz 3 MHz 6 MHz 12 MHz 24 MHz The following table lists the units of measure that are used in this chapter. Table 5. Units of Measure Symbol o C dB fF Hz KB Kbit kHz kΩ MHz MΩ μA μF μH μs μV μVrms μW mA ms mV nA ns nV W pA pF pp ppm ps sps s V Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts IMO Frequency Document Number: 001-12394 Rev. *D Page 15 of 26 [+] Feedback PRELIMINARY CY7C6435x CY7C64345, CY7C6431x Electrical Characteristics Absolute Maximum Ratings Storage Temperature (TSTG) (4) ............................................. ..............................................................-55oC to 125oC (Typical +25oC) Supply Voltage Relative to Vss (Vdd) .................................... ......................................................................................... -0.5V to +6.0V DC Input Voltage (VIO)........................................................... .........................................................................Vss - 0.5V to Vdd + 0.5V DC Voltage Applied to Tri-state (VIOZ) ................................... .........................................................................Vss - 0.5V to Vdd + 0.5V Maximum Current into any Port Pin (IMIO)............................. ..................................................................................... -25mA to +50mA Electro Static Discharge Voltage (ESD) (5) ............................ ......................................................................................................2000V Latch-up Current (LU) (6) ....................................................... .................................................................................................... 200mA Operating Conditions Ambient Temperature (TA) ..................................................... .............................................................................................0oC to 70oC Operational Die Temperature (TJ)(7) ...................................... .............................................................................................0oC to 85oC DC Electrical Characteristics DC Chip-Level Specifications Table 6 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 6. DC Chip-Level Specifications Parameter Description Conditions Min Typ Max Units 3.0 – 5.5 V Vdd Supply Voltage See table titled DC POR and LVD Specifications on page 18. IDD24 Supply Current, IMO = 24 MHz Conditions are Vdd = 3.0V, TA = 25oC, CPU = 24 MHz, No USB/I2C/SPI. – – 2.15 mA IDD12 Supply Current, IMO = 12 MHz Conditions are Vdd = 3.0V, TA = 25oC, CPU = 12 MHz, No USB/I2C/SPI. – – 1.45 mA IDD6 Supply Current, IMO = 6 MHz Conditions are Vdd = 3.0V, TA = 25oC, CPU = 6 MHz, No USB/I2C/SPI. – – 1.1 mA ISB0 Deep Sleep Current Vdd = 3.0V, TA = 25oC, IO regulator turned off. – 0.1 – μA ISB1 Standby Current with POR, LVD and Sleep Timer Vdd = 3.0V, TA = 25oC, IO regulator turned off. – – 1.5 μA Notes 4. Higher storage temperatures reduce data retention time. Recommended Storage Temperature is +25°C ± 25°C. Extended duration storage temperatures above 85oC degrade reliability. 5. Human Body Model ESD. 6. Per JESD78 standard. 7. The temperature rise from ambient to junction is package specific. See “Package Diagram” on page 22 for Thermal Impedances. The user must limit the power consumption to comply with this requirement. Document Number: 001-12394 Rev. *D Page 16 of 26 [+] Feedback PRELIMINARY CY7C6435x CY7C64345, CY7C6431x Table 7. DC Characteristics – USB Interface Symbol Min Typ Max Units USB D+ pull up resistance With idle bus 0.900 TBD 1.575 kΩ Rusba USB D+ pull up resistance While receiving traffic 1.425 TBD 3.090 kΩ Vohusb Static Output High 2.8 TBD 3.6 V TBD 0.3 V 0.2 TBD Rusbi Description Volusb Static Output Low Vdi Differential Input Sensitivity Vcm Differential Input Common Mode Range Vse Single Ended Receiver Threshold Cin Transceiver Capacitance Iio Hi-Z State Data Line Leakage Rps2 PS/2 Pull-up resistance Rext External USB Series Resistor Conditions On D+ or D- line In series with each USB pin V TBD TBD TBD V 0.8 TBD 2.0 V TBD 50 pF TBD TBD TBD uA 3 TBD 7 kΩ 23 TBD 25 Ω DC General Purpose IO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 5.5V and 0°C ≤ TA ≤ 70°C. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 8. 3.0V and 5.5V DC GPIO Specifications Symbol RPU VOH1 VOL Description Pull up resistor High Output Voltage Port 0, 2, or 3 Pins High Output Voltage Port 0, 2, or 3 Pins High Output Voltage Port 1 Pins with LDO Regulator Disabled High Output Voltage Port 1 Pins with LDO Regulator Disabled High Output Voltage Port 1 Pins with LDO Regulator Enabled High Output Voltage Port 1 Pins with LDO Regulator Enabled Low Output Voltage VIL VIH VH IIL CIN Input Low Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load on Pins as Input COUT Capacitive Load on Pins as Output VOH2 VOH3 VOH4 VOH5 VOH6 Document Number: 001-12394 Rev. *D Conditions Min 4 OH < 10 µA, Vdd > 3.0V, maximum of Vdd - 0.2 10 mA source current in all IOs. OH = 1mA Vdd > 3.0, maximum of 20 Vdd - 0.9 mA source current in all IOs. OH < 10 µA, Vdd > 3.0V, maximum of Vdd - 0.2 10 mA source current in all IOs. OH = 5mA, Vdd > 3.0V, maximum of 20 Vdd - 0.9 mA source current in all IOs. OH < 10µA, Vdd > 3.1V, maximum of 4 2.85 IOs all sourcing 5 mA. OH = 5 mA, Vdd > 3.1V, maximum of 2.2 20 mA source current in all IOs. – OL = 20mA, Vdd > 3.3V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]). Vdd = 3.3 to 5.5. – Vdd = 3.3 to 5.5. 2.0 50 – Package and pin dependent. 0.5 Temp = 25oC. Package and pin dependent. 0.5 Temp = 25oC. Typ 5.6 – Max 8 – Units kΩ V – – V – – V – – V 3.0 3.15 V – – V – 0.75 V – – 60 1 1.7 0.8 200 25 5 V V mV nA pF 1.7 5 pF Page 17 of 26 [+] Feedback CY7C6435x CY7C64345, CY7C6431x PRELIMINARY DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 9. DC POR and LVD Specifications Symbol Description VPPOR Vdd Value for PPOR Trip PORLEV[1:0] = 10b, HPOR = 1 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b M[2:0] = 010b(8) VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min Typ Max Units – 2.82 2.95 V – – 2.85 2.95 3.06 – – 4.62 – – 2.92 3.02 3.13 – – 4.73 – – 2.99 3.09 3.20 – – 4.83 – – V V V – – V DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 10.DC Programming Specifications Symbol VddIWRITE IDDP VILP VIHP IILP Description Supply Voltage for Flash Write Operations Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify(9) IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify(10) VOLV Output Low Voltage During Programming or Verify VOHV Output High Voltage During Programming or Verify FlashENPB Flash Write Endurance(11) FlashDR Flash Data Retention(12) Min 3.0 – – VIH – Typ – 5 – – – Max – 25 VIL – 0.2 Units V mA V V mA – – 1.5 mA – Vdd - 1.0 50,000 10 – – – 20 Vss + 0.75 Vdd – – V V Cycles Years Notes 8. Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply. 9. Driving internal pull down resistor. 10. Driving internal pull down resistor. 11. Erase/write cycles per block. 12. Following maximum Flash write cycles. Document Number: 001-12394 Rev. *D Page 18 of 26 [+] Feedback PRELIMINARY CY7C6435x CY7C64345, CY7C6431x AC Electrical Characteristics AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 11.AC Chip-Level Specifications Symbol FMAX FCPU F32K1 FIMO24 FIMO12 FIMO6 DCIMO TRAMP Description Maximum Operating Frequency(13) Maximum Processing Frequency(14) Internal Low Speed Oscillator Frequency Internal Main Oscillator Stability for 24 MHz ± 5%(15) Internal Main Oscillator Stability for 12 MHz(16) Internal Main Oscillator Stability for 6 MHz(17) Duty Cycle of IMO Supply Ramp Time Min 24 24 30.4 22.8 11.4 5.7 40 0 Typ – – 32 24 12 6.0 50 – Max – – 33.6 25.2 12.6 6.3 60 – Units MHz MHz kHz MHz MHz MHz % μs Min Typ Max Units Table 12.AC Characteristics – USB Data Timings Symbol Description Conditions Tdrate Full-speed data rate Average bit rate 12–0.25% 12 12 + 0.25 MHz Tdjr1 Receiver data jitter tolerance To next transition -8 TBD 8 ns Tdjr2 Receiver data jitter tolerance To pair transition -5 TBD 5 ns Tudj1 Driver differential jitter To next transition -3.5 TBD 3.5 ns Tudj2 Driver differential jitter To pair transition -4.0 TBD 4.0 ns Tfdeop Source jitter for differntial transition To SE0 transition -2 TBD 5 ns 175 Tfeopt Source SE0 interval of EOP 160 TBD Tfeopr Receiver SE0 interval of EOP 82 TBD Tfst Width of SE0 interval during differential transition ns ns TBD 14 ns Min Typ Max Units Table 13.AC Characteristics – USB Driver Symbol Description Conditions Tr Transition rise time 50 pF 4 TBD 20 ns Tf Transition fall time 50 pF 4 TBD 20 ns TR Rise/fall time matching 90.00 TBD 111.11 % Vcrs Output signal crossover voltage 1.3 TBD 2.0 V Notes 13. Vdd = 3.0V and TJ = 85oC, digital clocking functions. 14. Vdd = 3.0V and TJ = 85oC, CPU speed. 15. Trimmed for 3.3V operation using factory trim values. 16. Trimmed for 3.3V operation using factory trim values. 17. Trimmed for 3.3V operation using factory trim values. Document Number: 001-12394 Rev. *D Page 19 of 26 [+] Feedback PRELIMINARY CY7C6435x CY7C64345, CY7C6431x AC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 14.AC GPIO Specifications Symbol Description FGPIO GPIO Operating Frequency TRise023 Rise Time, Strong Mode Ports 0, 2, 3 TRise1 Rise Time, Strong Mode Port 1 TFall Fall Time, Strong Mode All Ports Conditions Normal Strong Mode, Port 1 Vdd = 3.3 to 5.5V, 10% - 90% Min 0 15 Typ – – Max 12 80 Units MHz ns Vdd = 3.3 to 5.5V, 10% - 90% 7 – 50 ns Vdd = 3.3 to 5.5V, 10% - 90% 7 – 50 ns Figure 8. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TFall TRise023 TRise1 AC External Clock Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 15.AC External Clock Specifications Symbol Description Min Typ Max Units FOSCEXT Frequency 0.750 – 25.2 MHz – High Period 20.6 – 5300 ns – Low Period 20.6 – – ns – Power Up IMO to Switch 150 – – μs Document Number: 001-12394 Rev. *D Page 20 of 26 [+] Feedback CY7C6435x CY7C64345, CY7C6431x PRELIMINARY AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 16.AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TDSCLK2 Description Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Min 1 1 40 40 0 – – – – – Typ – – – – – – – – – – Max 20 20 – – 8 18 25 45 50 70 Units ns ns ns ns MHz ms ms ns ns ns AC SPI Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 17.AC SPI Specifications Symbol Description Min Typ Max Units – – 8.2 MHz Maximum Input Clock Frequency Selection, Slave – – 4.1 MHz Width of SS_ Negated Between Transmissions 50 – – ns FSPIM Maximum Input Clock Frequency Selection, Master(18) FSPIS TSS AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 18.AC Characteristics of the I2C SDA and SCL Pins Symbol Description SCL Clock Frequency FSCLI2C THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. TLOWI2C LOW Period of the SCL Clock THIGHI2C HIGH Period of the SCL Clock TSUSTAI2C Set-up Time for a Repeated START Condition THDDATI2C Data Hold Time TSUDATI2C Data Set-up Time TSUSTOI2C Set-up Time for STOP Condition Bus Free Time Between a STOP and START Condition TBUFI2C Pulse Width of spikes are suppressed by the input filter. TSPI2C Standard Mode Min Max 0 100 4.0 – 4.7 4.0 4.7 0 250 4.0 4.7 – – – – – – – – – Fast Mode Min Max 0 400 0.6 – 1.3 0.6 0.6 0 100(19) 0.6 1.3 0 – – – – – – – 50 Units kHz μs μs μs μs μs ns μs μs ns Notes 18. Output clock frequency is half of input clock rate. 19. A Fast mode I2C-bus device can be used in a standard mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-12394 Rev. *D Page 21 of 26 [+] Feedback CY7C6435x CY7C64345, CY7C6431x PRELIMINARY Figure 9. Definition for Timing for Fast/Standard Mode on the I2C Bus SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S Package Diagram This chapter illustrates the packaging specifications for the enCoRe V USB device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the enCoRe V emulation tools and their dimensions, refer to the development kit. Packaging Dimensions Figure 10. 16-Lead (3x3 x 0.6 mm) QFN Document Number: 001-12394 Rev. *D Page 22 of 26 [+] Feedback PRELIMINARY CY7C6435x CY7C64345, CY7C6431x Figure 11. 32-Lead (5x5 x 0.6 mm) QFN 001-06335 ** Document Number: 001-12394 Rev. *D Page 23 of 26 [+] Feedback CY7C6435x CY7C64345, CY7C6431x PRELIMINARY Figure 12. 48-Lead (7x7 mm) QFN SOLDERABLE EXPOSED PAD NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.13g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE PART # DESCRIPTION LF48A LY48A STANDARD LEAD FREE UNLESS OTHERWISE SPECIFIED ALL DIMENSIONS ARE IN INCHES [MILLIMETERS] STANDARD TOLERANCES ON: ANGLES DECIMALS .XX -+ -+ .XXX -+ .XXXX + - DESIGNED BY DRAWN CHK BY DATE JSO DATE 02/02/07 CYPRESS 51-85152 *B DATE 001-12919 *A COMPANY CONFIDENTIAL TITLE APPROVED BY DATE APPROVED BY DATE MATERIAL SIZE 48LD QFN 7 X 7mm PACKAGE OUTLINE (SUBCON PUNCH TYPE PKG with 5.1 X 5.1 EPAD) PART NO. SEE NOTES DWG NO R 001-12919 . Document Number: 001-12394 Rev. *D Page 24 of 26 [+] Feedback CY7C6435x CY7C64345, CY7C6431x PRELIMINARY Thermal Impedances Table 19.Thermal Impedances per Package Package 16 QFN 32 QFN** 48 QFN** Typical θJA * 46 oC/W 14.5 oC/W 28 oC/W * TJ = TA + Power x θJA ** To achieve the thermal impedance specified for the ** package, solder the center thermal pad to the PCB ground plane. Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 20.Solder Reflow Peak Temperature Package Minimum Peak Temperature* Maximum Peak Temperature 16 QFN 240oC 260oC 32 QFN 240oC 260oC 48 QFN 240oC 260oC *Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Ordering Information Ordering Code Package Information Flash SRAM No. of GPIOs CY7C64315-16LKXC 16-lead QFN (3x3x0.6mm) 16K 1K 11 Mid-tier FS USB dongle, RC-host module CY7C64316-16LKXC 16-lead QFN (3x3x0.6mm) 32K 2K 11 Hi-end FS USB dongle, RC-host module CY7C64345-32LKXC 32-lead QFN (5x5x0.6mm) 16K 1K 25 Full-speed USB mouse CY7C64355-48LFXC 48-lead QFN (7x7x1.0mm) 16K 1K 36 Full-speed USB keyboard CY7C64356-48LFXC 48-lead QFN (7x7x1.0mm) 32K 2K 36 Hi-End FS USB keyboard Document Number: 001-12394 Rev. *D Target Applications Page 25 of 26 [+] Feedback PRELIMINARY CY7C6435x CY7C64345, CY7C6431x Document History Page Document Title: CY7C6431X, CY7C64345, CY7C6435X ENCORE TM V FULL-SPEED USB CONTROLLER Document Number: 001-12394 REV. ECN. Orig. of Change ** 626256 TYJ *A 735718 TYJ/ARI Filled in TBDs, added new block diagram, and corrected some values. Part numbers updated as per new specifications. *B 1120404 ARI Corrected the block diagram and Figure 3, which is the 16-pin enCoRe V device. Corrected the description to pin 29 on Table 2, the Typ/Max values for ISB0 on the DC chip-level specifications, the current value for the latch-up current in the Electrical Characteristics section, and corrected the 16 QFN package information in the Thermal Impedance table. Corrected some of the bulleted items on the first page. Added DC Characteristics–USB Interface table. Added AC Characteristics–USB Data Timings table. Added AC Characteristics–USB Driver table. Corrected Flash Write Endurance minimum value in the DC Programming Specifications table. Corrected the Flash Erase Time max value and the Flash Block Write Time max value in the AC Programming Specifications table. Implemented new latest template. Include paramters: Vcrs, Rpu (USB, active), Rpu (USB suspend), Tfdeop, Tfeopr2, Tfeopt, Tfst. Added register map tables. Corrected a value in the DC Chip-Level Specifications table. *C 1241024 TYJ/ARI *D 1639963 AESA Description of Change New data sheet. Corrected Idd values in Table 6 - DC Chip-Level Specifications. Post to www.cypress.com © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-12394 Rev. *D Revised October 17, 2007 Page 26 of 26 PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback