PSoC® Mixed-Signal Array Final Data Sheet CY8C20234 CY8C20334 and CY8C20434 Features ■ Low Power CapSense Block ❐ Configurable Capacitive Sensing Elements ❐ Supports Combination of CapSense Buttons, Sliders, Touchpads and Proximity Sensors ■ Powerful Harvard Architecture Processor ❐ ❐ ❐ ❐ M8C Processor Speeds Running up to 12 MHz Low Power at High Speed 2.4V to 5.25V Operating Voltage Industrial Temperature Range: -40°C to +85°C ■ Flexible On-Chip Memory ❐ 8K Flash Program Storage 50,000 Erase/Write Cycles ❐ 512 Bytes SRAM Data Storage ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ Interrupt Controller ❐ In-System Serial Programming (ISSP) ■ Complete Development Tools ❐ Free Development Tool (PSoC Designer™) ❐ Full-Featured, In-Circuit Emulator and Programmer ❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128K Trace Memory ■ Precision, Programmable Clocking ❐ Internal ±5.0% 6/12 MHz Main Oscillator ❐ Internal Low Speed Oscillator at 32 kHz for Watchdog and Sleep ■ Programmable Pin Configurations ❐ Pull Up, High Z, Open Drain, CMOS Drive Modes on All GPIO ❐ Up to 28 Analog Inputs on GPIO ❐ Configurable Inputs on All GPIO ❐ Selectable, Regulated Digital IO on Port 1 -- 3.0V, 20 mA Total Port 1 Source Current -- 5 mA Strong Drive Mode on Port 1 ■ Versatile Analog Mux ❐ ❐ ❐ ❐ Common Internal Analog Bus Simultaneous Connection of IO Combinations Comparator Noise Immunity Low-Dropout Voltage Regulator for the Analog Array ■ Additional System Resources ❐ Configurable Communication Speeds -- I2C: Selectable to 50 kHz, 100 kHz or 400 kHz -- SPI : Configurable between 46.9 kHz and 3 MHz ❐ ❐ ❐ ❐ ❐ I2C™ Slave SPI Master and SPI Slave Watchdog and Sleep Timers Internal Voltage Reference Integrated Supervisory Circuit PSoC® Functional Overview The PSoC family consists of many Mixed-Signal Array with OnChip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, as well as programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts. The PSoC architecture for this device family, as illustrated on the left, is comprised of three main areas: the Core, the System Resources, and the CapSense Analog System. A common, versatile bus allows connection between IO and the analog system. Each CY8C20x34 PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 28 general purpose IO (GPIO) are also included. The GPIO provide access to the MCU and analog mux. September 18, 2006 © Cypress Semiconductor Corp. 2005-2006 — Document No. 001-05356 Rev. *B 1 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet PSoC® Overview The PSoC Core The Analog Multiplexer System The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 12 MHz. The M8C is a two-MIPS, 8-bit Harvard architecture microprocessor. The Analog Mux Bus can connect to every GPIO pin. Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator. System Resources provide additional capability, such as a configurable I2C slave/SPI master-slave communication interface and various system resets supported by the M8C. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: ■ Complex capacitive sensing interfaces, such as sliders and touchpads. The Analog System is composed of the CapSense PSoC block and an internal 1.8V analog reference, which together support capacitive sensing of up to 28 inputs. ■ Chip-wide mux that allows analog input from any IO pin. ■ Crosspoint connection between any IO pin combinations. The CapSense Analog System Additional System Resources The Analog System contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins can be completed quickly and easily across multiple ports. System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. Brief statements describing the merits of each system resource are presented below. ■ The I2C slave/SPI master-slave module provides 50/100/400 kHz communication over two wires. SPI communication over 3 or 4 wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). ■ Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. ■ An internal 1.8V reference provides an absolute reference for capacitive sensing. ■ The 5V maximum input, 3V fixed output, low-dropout regulator (LDO) provides regulation for IOs. A register-controlled bypass mode allows the user to disable the LDO. Analog Global Bus IDAC Vr Reference Buffer Cinternal Comparator Mux Mux Refs Cap Sense Counters CSCLK IMO CapSense Clock Select Relaxation Oscillator (RO) Analog System Block Diagram September 18, 2006 Document No. 001-05356 Rev. *B 2 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet PSoC® Overview Getting Started Development Tools The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoC Mixed-Signal Array Technical Reference Manual, which can be found on http://www.cypress.com/psoc. PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-onChip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.) Development Kits PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. Technical Training Free PSoC technical training is available for beginners and is taught by a marketing or application engineer over the phone. PSoC training classes cover designing, debugging, advanced analog, as well as application-specific classes covering topics such as PSoC and the LIN bus. Go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select Technical Training for more details. Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants. Context Sensitive Help Graphical Designer Interface PSoC Designer Results Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items. Commands For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at http://www.cypress.com. PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. Importable Design Database Device Database PSoC Configuration Sheet PSoC Designer Core Engine Application Database Manufacturing Information File Project Database User Modules Library Technical Support PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm. Emulation Pod In-Circuit Emulator Device Programmer PSoC Designer Subsystems Application Notes A long list of application notes will assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are sorted by date by default. September 18, 2006 Document No. 001-05356 Rev. *B 3 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet PSoC® Overview PSoC Designer Software Subsystems Device Editor Debugger The device editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read the program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration allows for changing configurations at run time. PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It’s also possible to change the selected components and regenerate the framework. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Hardware Tools In-Circuit Emulator Application Editor In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. C Language Compiler. A C language compiler is available that supports the PSoC family of devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. September 18, 2006 Document No. 001-05356 Rev. *B 4 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet PSoC® Overview Designing with User Modules The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements. Device Editor User Module Selection The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions. September 18, 2006 Source Code Generator Generate Application Application Editor Project Manager To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called “User Modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run time. The API also provides optional interrupt service routines that you can adapt as needed. Placement and Parameter -ization Source Code Editor Build Manager Build All Debugger Interface to ICE Storage Inspector Event & Breakpoint Manager User Module and Source Code Development Flows The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive “grep-style” patterns. A single mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Document No. 001-05356 Rev. *B 5 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet PSoC® Overview Document Conventions Table of Contents Acronyms Used For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed-Signal Array Technical Reference Manual on http://www.cypress.com. This document is organized into the following chapters and sections. The following table lists the acronyms that are used in this document. Acronym Description AC alternating current API application programming interface CPU central processing unit DC direct current GPIO general purpose IO GUI graphical user interface ICE in-circuit emulator ILO internal low speed oscillator IMO internal main oscillator IO input/output LSb least-significant bit LVD low voltage detect MSb most-significant bit POR power on reset PPOR precision power on reset PSoC® Programmable System-on-Chip™ SLIMO slow IMO SRAM static random access memory 1. Units of Measure Pinouts ..............................................................................7 1.1.1 16-Pin Part Pinout ...............................................7 1.1.2 24-Pin Part Pinout ...............................................8 1.1.3 32-Pin Part Pinout ...............................................9 1.1.4 48-Pin OCD Part Pinout .....................................10 2. Electrical Specifications .........................................................11 2.1 Absolute Maximum Ratings .............................................12 2.2 Operating Temperature ...................................................12 2.3 DC Electrical Characteristics ...........................................12 2.3.1 DC Chip-Level Specifications .............................12 2.3.2 DC General Purpose IO Specifications ..............13 2.3.3 DC Analog Mux Bus Specifications ....................14 2.3.4 DC POR and LVD Specifications .......................14 2.3.5 DC Programming Specifications ........................15 2.4 AC Electrical Characteristics ...........................................16 2.4.1 AC Chip-Level Specifications .............................16 2.4.2 AC General Purpose IO Specifications ..............17 2.4.3 AC Comparator Amplifier Specifications ............18 2.4.4 AC Analog Mux Bus Specifications ....................18 2.4.5 AC External Clock Specifications .......................19 2.4.6 AC Programming Specifications .........................20 2.4.7 AC SPI Specifications ........................................21 2.4.8 AC I2C Specifications .........................................22 3. Packaging Information ...........................................................23 3.1 Packaging Dimensions ....................................................23 3.2 Thermal Impedances ......................................................27 3.3 Solder Reflow Peak Temperature ...................................27 4. Development Tool Selection ..................................................28 4.1 Software ..........................................................................28 4.1.1 PSoC Designer ...................................................28 4.1.2 PSoC Express ....................................................28 4.1.3 PSoC Programmer .............................................28 4.1.4 CY3202-C iMAGEcraft C Compiler ....................28 4.2 Development Kits ............................................................28 4.2.1 CY3215-DK Basic Development Kit ...................28 4.2.2 CY3210-ExpressDK Development Kit ................29 4.3 Evaluation Tools ..............................................................29 4.3.1 CY3210-MiniProg1 .............................................29 4.3.2 CY3210-PSoCEval1 ...........................................29 4.3.3 CY3214-PSoCEvalUSB .....................................29 4.4 Device Programmers .......................................................29 4.4.1 CY3216 Modular Programmer ...........................29 4.4.2 CY3207ISSP In-System Programmer ...............29 4.5 Accessories (Emulation and Programming) ....................30 4.6 3rd-Party Tools ................................................................30 4.7 Build a PSoC Emulator into Your Board ..........................30 5. Ordering Information ..............................................................31 5.1 Ordering Code Definitions ...............................................31 6. Sales and Service Information ...............................................32 6.1 Revision History ..............................................................32 6.2 Copyrights and Code Protection .....................................32 A units of measure table is located in the Electrical Specifications section. Table 2-1 on page 11 lists all the abbreviations used to measure the PSoC devices. Numeric Naming Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal. September 18, 2006 Pin Information ..........................................................................7 1.1 Document No. 001-05356 Rev. *B 6 [+] Feedback 1. Pin Information This chapter describes, lists, and illustrates the CY8C20234, CY8C20334 and CY8C20434 PSoC device pins and pinout configurations. 1.1 Pinouts The CY8C20x34 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, and XRES are not capable of Digital IO. 1.1.1 16-Pin Part Pinout Table 1-1. 16-Pin Part Pinout (QFN**) IO I P2[5] 2 IO I P2[1] 3 IOH I P1[7] I2C SCL, SPI SS. 4 IOH I P1[5] I2C SDA, SPI MISO. 5 IOH I P1[3] SPI CLK. AI, P2[5] 6 IOH I P1[1] CLK*, I2C SCL, SPI MOSI. AI, P2[1] 1 2 AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] 3 4 Power I P1[0] DATA*, I2C SDA. 9 IOH I P1[2] 10 IOH I P1[4] Optional external clock input (EXTCLK). XRES Active high external reset with internal pull down. 11 12 Input IO 13 I Power P0[4] Vdd 14 IO I P0[7] 15 IO I P0[3] 16 IO I P0[1] CP Power Vss Supply voltage. Integrating input. Center pad must be connected to ground. 16 15 P0[1], AI Ground connection. IOH 5 6 Vss 8 12 QFN (Top View) 11 10 CP AI, SPI CLK, P1[3] 7 Description 14 13 1 Name 9 7 8 Analog P0[3], AI P0[7], AI Vdd CY8C20234 16-Pin PSoC Device Digital P0[4], AI XRES P1[4], AI, EXTCLK P1[2], AI CLK, I2C SCL, SPI MOSI P1[1] Vss AI, DATA, I2C SDA, P1[0] Type Pin No. LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive. * These are the ISSP pins, which are not High Z at POR (Power On Reset). ** The center pad (CP) on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. September 18, 2006 Document No. 001-05356 Rev. *B 7 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 1.1.2 1. Pin Information 24-Pin Part Pinout Table 1-2. 24-Pin Part Pinout (QFN**) Digital Analog 1 IO I P2[5] 2 IO I P2[3] 3 IO I P2[1] 4 IOH I P1[7] I2C SCL, SPI SS. 5 IOH I P1[5] I2C SDA, SPI MISO. 6 IOH I P1[3] SPI CLK. 7 IOH I P1[1] CLK*, I2C SCL, SPI MOSI. NC No connection. Vss Ground connection. DATA*, I2C SDA. 8 9 Power 10 IOH I P1[0] 11 IOH I P1[2] 12 IOH I P1[4] 13 IOH I P1[6] 14 Input XRES IO I P2[0] IO I P0[0] 17 IO I P0[2] 18 IO I P0[4] 19 IO I P0[6] Analog bypass. Vdd Supply voltage. 21 IO I P0[7] 22 IO I P0[5] 23 IO I P0[3] 24 IO I P0[1] CP Power Vss 24 23 22 21 20 19 Active high external reset with internal pull down. 16 Power AI,P2[5] AI,P2[3] AI,P2[1] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] AI, SPI CLK, P1[3] Optional external clock input (EXTCLK). 15 20 CY8C20334 24-Pin PSoC Device Description P0[1],AI P0[3],AI P0[5],AI P0[7],AI Vdd P0[6],AI Name 1 2 3 4 5 6 18 17 QFN 16 (Top View ) 15 14 13 AI, CLK*, I2C SCL SPIMOSI,P1[1] 7 8 NC 9 Vss AI, DATA*, I2C SDA, P1[0] 10 AI,P1[2] 11 AI,EXTCLK,P1[4] 12 Type Pin No. P0[4],AI P0[2],AI P0[0],AI P2[0],AI XRES P1[6],AI Integrating input. Center pad must be connected to ground. LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details. ** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. September 18, 2006 Document No. 001-05356 Rev. *B 8 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 1.1.3 1. Pin Information 32-Pin Part Pinout Table 1-3. 32-Pin Part Pinout (QFN**) Digital Analog 1 IO I P0[1] 2 IO I P2[7] 3 IO I P2[5] 4 IO I P2[3] 5 IO I P2[1] 6 IO I P3[3] 7 IO I P3[1] 8 IOH I P1[7] I2C SCL, SPI SS. 9 IOH I P1[5] I2C SDA, SPI MISO. 10 IOH I P1[3] SPI CLK. 11 IOH I P1[1] CLK*, I2C SCL, SPI MOSI. Vss Ground connection. DATA*, I2C SDA. Power 13 IOH I P1[0] 14 IOH I P1[2] 15 IOH I P1[4] 16 IOH I P1[6] 17 Input XRES IO I P3[0] IO I P3[2] 20 IO I P2[0] 21 IO I P2[2] 22 IO I P2[4] 23 IO I P2[6] 24 IO I P0[0] 25 IO I P0[2] 26 IO I P0[4] 27 IO I P0[6] Analog bypass. Vdd Supply voltage. 29 IO I P0[7] 30 IO I P0[5] 31 IO I P0[3] AI, I2C SCL Active high external reset with internal pull down. 19 Power 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 AI,P0[1] AI,P2[7] AI,P2[5] AI,P2[3] AI,P2[1] AI,P3[3] AI,P3[1] SPISS,P1[7] Optional external clock input (EXTCLK). 18 28 CY8C20434 32-Pin PSoC Device Vss P0[3],AI P0[5],AI P0[7],AI Vdd P0[6],AI P0[4],AI P0[2],AI Description QFN (Top View ) 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 12 Name P0[0],AI P2[6],AI P2[4],AI P2[2],AI P2[0],AI P3[2],AI P3[0],AI XRES AI, I2C SDA, SPI MISO, P1[5] AI, SPI CLK, P1[3] AI, CLK*, I2C SCL, SPI MOSI, P1[1] Vss AI, DATA*, I2C SDA, P1[0] AI,P1[2] AI,EXTCLK,P1[4] AI,P1[6] Type Pin No. Integrating input. 32 Power Vss Ground connection. CP Power Vss Center pad must be connected to ground. LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details. ** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. September 18, 2006 Document No. 001-05356 Rev. *B 9 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 1.1.4 1. Pin Information 48-Pin OCD Part Pinout The 48-pin QFN part table and drawing below is for the CY8C20000 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production Table 1-4. 48-Pin OCD Part Pinout (QFN**) Digital Analog CY8C20000 OCD PSoC Device 2 IO I P0[1] 3 IO I P2[7] 4 IO I P2[5] 5 IO I P2[3] 6 IO I P2[1] 7 IO I P3[3] 8 IO I P3[1] 9 IOH I P1[7] I2C SCL, SPI SS. 10 IOH I No connection. 14 NC No connection. 15 IOH I P1[3] SPI CLK. 16 IOH I P1[1] CLK*, I2C SCL, SPI MOSI. 17 Power 18 19 Vss Ground connection. CCLK OCD CPU clock output. OCD high speed clock output. IOH I P1[0] DATA*, I2C SDA. 21 IOH I P1[2] 22 NC No connection. 23 NC No connection. 24 NC No connection. Optional external clock input (EXTCLK). 25 IOH I P1[4] 26 IOH I P1[6] 27 Input XRES 28 IO I P3[0] 29 IO I P3[2] 30 IO I P2[0] 31 IO I P2[2] 32 IO I P2[4] Pin No. Power Name NC NC P2[0], AI P3[2], AI P3[0], AI XRES P1[6], AI P1[4], EXT CLK, AI Description IO I P2[6] 41 Vdd Supply voltage. IO I P0[0] 42 OCDO OCD even data IO. 35 IO I P0[2] 43 OCDE OCD odd data output. 36 IO I P0[4] 44 IO I P0[7] 37 NC No connection. 45 IO I P0[5] 38 NC No connection. 46 IO I P0[3] 39 NC No connection. 47 P0[6] Analog bypass. 48 I P0[2], AI P0[0], AI P2[6], AI P2[4], AI P2[2], AI Active high external reset with internal pull down. 34 IO P0[4], AI Not for Production 33 40 39 38 37 OCDO Vdd P0[6],AI NC 42 41 40 P0[5],AI P0[7],AI OCDE NC Vss P0[3],AI HCLK 20 22 23 24 NC (Top V ie w ) 20 21 No connection. 13 36 35 34 33 32 31 30 29 28 27 26 25 Vss CCLK HCLK AI,DATA*,I2CSDA,P1[0] AI,P1[2] NC NC NC NC OCD QFN 7 8 9 10 11 12 15 16 17 18 19 No connection. 12 3 4 5 6 AI,SPICLK,P1[3] AI,CLK*, I2CSCL, SPIMOSI,P1[1] I2C SDA, SPI MISO. NC 1 2 13 14 P1[5] 11 NC AI, P0[1] AI, P2[7] AI, P2[5] AI, P2[3] AI, P2[1] AI, P3[3] AI, P3[1] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI M ISO, P1[5] NC NC 48 47 46 45 44 43 No connection. NC NC NC Description Analog 1 Name Digital Pin No. CP Power Power Integrating input. Vss Ground connection. NC No connection. Vss Center pad must be connected to ground. LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive. * ISSP pin which is not HighZ at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details. ** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. September 18, 2006 Document No. 001-05356 Rev. *B 10 [+] Feedback 2. Electrical Specifications This chapter presents the DC and AC electrical specifications of the CY8C20234, CY8C20334 and CY8C20434 PSoC devices. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http:// www.cypress.com/psoc. Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC as specified, except where noted. Refer to Table 2-10 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. 5.25 5.25 SLIMO SLIMO SLIMO Mode=1 Mode=1 Mode=0 4.75 Vdd Voltage Vdd Voltage lid g Va ratin n pe io O Reg 4.75 3.00 3.60 SLIMO SLIMO Mode=1 Mode=0 3.00 SLIMO Mode=1 2.70 2.40 SLIMO Mode=0 2.40 750 kHz 3 MHz 750 kHz 12 MHz 3 MHz 6 MHz 12 MHz IMOFrequency CPU Frequency Figure 2-1a. Voltage versus CPU Frequency Figure 2-1b. IMO Frequency Trim Options The following table lists the units of measure that are used in this chapter. Table 2-1: Units of Measure Symbol Unit of Measure Symbol Unit of Measure oC degree Celsius µW microwatts dB decibels mA milli-ampere fF femto farad ms milli-second Hz hertz mV milli-volts KB 1024 bytes nA nanoampere Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts kΩ kilohm Ω ohm MHz megahertz pA picoampere MΩ megaohm pF picofarad µA microampere pp peak-to-peak µF microfarad ppm µH microhenry ps picosecond µs microsecond sps samples per second µV microvolts σ sigma: one standard deviation microvolts root-mean-square V volts µVrms September 18, 2006 parts per million Document No. 001-05356 Rev. *B 11 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 2.1 2. Electrical Specifications Absolute Maximum Ratings Table 2-2. Absolute Maximum Ratings Symbol Description Min Typ Max Units TSTG Storage Temperature -55 25 +100 oC TA Ambient Temperature with Power Applied -40 – +85 oC Vdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 V VIO DC Input Voltage Vss - 0.5 – Vdd + 0.5 V VIOZ DC Voltage Applied to Tri-state Vss - 0.5 – Vdd + 0.5 V IMIO Maximum Current into any Port Pin -25 – +50 mA ESD Electro Static Discharge Voltage 2000 – – V LU Latch-up Current – – 200 mA 2.2 Notes Higher storage temperatures will reduce data retention time. Recommended storage temperature is +25oC ± 25oC. Extended duration storage temperatures above 65oC will degrade reliability. Human Body Model ESD. Operating Temperature Table 2-3. Operating Temperature Symbol Description Min Typ Max Units TA Ambient Temperature -40 – +85 oC TJ Junction Temperature -40 – +100 oC 2.3 2.3.1 Notes The temperature rise from ambient to junction is package specific. See “Thermal Impedances” on page 27. The user must limit the power consumption to comply with this requirement. DC Electrical Characteristics DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 2-4. DC Chip-Level Specifications Symbol Description Min Typ Max Units Notes Vdd Supply Voltage 2.40 – 5.25 V See table titled “DC POR and LVD Specifications” on page 14. IDD12 Supply Current, IMO = 12 MHz – 1.5 2.5 mA Conditions are Vdd = 3.0V, TA = 25oC, CPU = 12 MHz. IDD6 Supply Current, IMO = 6 MHz – 1 1.5 mA Conditions are Vdd = 3.0V, TA = 25oC, CPU = 6 MHz. ISB27 Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Mid temperature range. – 2.6 4. µA Vdd = 2.55V, 0oC ≤ TA ≤ 40oC. ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. – 2.8 5 µA Vdd = 3.3V, -40oC ≤ TA ≤ 85oC. September 18, 2006 Document No. 001-05356 Rev. *B 12 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 2.3.2 2. Electrical Specifications DC General Purpose IO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only. Table 2-5. 5V and 3.3V DC GPIO Specifications Symbol Description Min Typ Max Units Notes RPU Pull-up Resistor 4 5.6 8 kΩ VOH1 High Output Voltage Port 0, 2, or 3 Pins Vdd - 0.2 – – V IOH < 10 µA, Vdd > 3.0V, maximum of 10 mA source current in all IOs. VOH2 High Output Voltage Port 0, 2, or 3 Pins Vdd - 0.9 – – V IOH = 1 mA, Vdd > 3.0V, maximum of 20 mA source current in all IOs. VOH3 High Output Voltage Port 1 Pins with LDO Regulator Disabled Vdd - 0.2 – – V IOH < 10 µA, Vdd > 3.0V, maximum of 10 mA source current in all IOs. VOH4 High Output Voltage Port 1 Pins with LDO Regulator Disabled Vdd - 0.9 – – V IOH = 5 mA, Vdd > 3.0V, maximum of 20 mA source current in all IOs. VOH5 High Output Voltage Port 1 Pins with LDO Regulator Enabled 2.75 3.0 3.2 V IOH < 10 µA, Vdd > 3.1V, maximum of 4 IOs all sourcing 5 mA. VOH6 High Output Voltage Port 1 Pins with LDO Regulator Enabled 2.2 – – V IOH = 5 mA, Vdd > 3.1V, maximum of 20 mA source current in all IOs. VOL Low Output Voltage – – 0.75 V IOL = 20 mA, Vdd > 3V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]). 0.8 V Vdd = 3.0 to 5.25. V Vdd = 3.0 to 5.25. VIL Input Low Voltage – – VIH Input High Voltage 2.0 – VH Input Hysteresis Voltage – 140 – mV IIL Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 µA. CIN Capacitive Load on Pins as Input 0.5 1.7 5 pF Package and pin dependent. Temp = 25oC. COUT Capacitive Load on Pins as Output 0.5 1.7 5 pF Package and pin dependent. Temp = 25oC. Table 2-6. 2.7V DC GPIO Specifications Symbol Description Min Typ Max Units Notes RPU Pull-up Resistor 4 5.6 8 kΩ VOH1 High Output Voltage Port 0, 2, or 3 Pins Vdd - 0.2 – – V IOH < 10 µA, maximum of 10 mA source current in all IOs. VOH2 High Output Voltage Port 0, 2, or 3 Pins Vdd - 0.5 – – V IOH = 0.2 mA, maximum of 10 mA source current in all IOs. VOH3 High Output Voltage Port 1 Pins with LDO Regulator Disabled Vdd - 0.2 – – V IOH < 10 µA, maximum of 10 mA source current in all IOs. VOH4 High Output Voltage Port 1 Pins with LDO Regulator Disabled Vdd - 0.5 – – V IOH = 2 mA, maximum of 10 mA source current in all IOs. VOL Low Output Voltage – – 0.75 V IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]). 0.8 V Vdd = 2.4 to 3.0V. V Vdd = 2.4 to 3.0V. VIL Input Low Voltage – – VIH Input High Voltage 2.0 – VH Input Hysteresis Voltage – 60 – mV IIL Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 µA. CIN Capacitive Load on Pins as Input 0.5 1.7 5 pF Package and pin dependent. Temp = 25oC. COUT Capacitive Load on Pins as Output 0.5 1.7 5 pF Package and pin dependent. Temp = 25oC. September 18, 2006 Document No. 001-05356 Rev. *B 13 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 2.3.3 2. Electrical Specifications DC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 2-7. DC Analog Mux Bus Specifications Symbol RSW 2.3.4 Description Min Switch Resistance to Common Analog Bus – Typ – Max 400 800 Units Ω Ω Notes Vdd ≥ 2.7V 2.4V ≤ Vdd ≤ 2.7V DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 2-8. DC POR and LVD Specifications Symbol Description Min Typ Max Units Vdd Value for PPOR Trip VPPOR0 PORLEV[1:0] = 00b VPPOR1 PORLEV[1:0] = 01b VPPOR2 PORLEV[1:0] = 10b – 2.36 2.40 V 2.60 2.65 V 2.82 2.95 V Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog. Vdd Value for LVD Trip VLVD0 VM[2:0] = 000b 2.39 2.45 2.51a V VLVD1 VM[2:0] = 001b 2.54 2.71 2.78b V VLVD2 VM[2:0] = 010b 2.75 2.92 2.99c V VLVD3 VM[2:0] = 011b 2.85 3.02 3.09 V VLVD4 VM[2:0] = 100b 2.96 3.13 3.20 V VLVD5 VM[2:0] = 101b – – – V VLVD6 VM[2:0] = 110b – – – V VLVD7 VM[2:0] = 111b 4.52 4.73 4.83 V a. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply. b. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply. c. Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply. September 18, 2006 Document No. 001-05356 Rev. *B 14 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 2.3.5 2. Electrical Specifications DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 2-9. DC Programming Specifications Symbol Description Min Typ Max Units Notes VddIWRITE Supply Voltage for Flash Write Operations 2.70 – – V IDDP Supply Current During Programming or Verify – 5 25 mA VILP Input Low Voltage During Programming or Verify – – 0.8 V VIHP Input High Voltage During Programming or Verify 2.2 – – V IILP Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify – – 0.2 mA Driving internal pull-down resistor. IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify – – 1.5 mA Driving internal pull-down resistor. VOLV Output Low Voltage During Programming or Verify – – Vss + 0.75 V VOHV Output High Voltage During Programming or Verify Vdd - 1.0 – Vdd V FlashENPB Flash Endurance (per block) 50,000 – – – Erase/write cycles per block. FlashENT Flash Endurance (total)a 1,800,000 – – – Erase/write cycles. FlashDR Flash Data Retention 10 – – Years a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). September 18, 2006 Document No. 001-05356 Rev. *B 15 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 2.4 2.4.1 2. Electrical Specifications AC Electrical Characteristics AC Chip-Level Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 2-10. 5V and 3.3V AC Chip-Level Specifications Symbol Description Min Typ Max Units Notes FCPU1 CPU Frequency (3.3V Nominal) 0.75 – 12.6 MHz 12 MHz only for SLIMO Mode = 0. F32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHz FIMO12 Internal Main Oscillator Stability for 12 MHz (Commercial Temperature)a 11.4 12 12.6 MHz Trimmed for 3.3V operation using factory trim values. See Figure 2-1b, SLIMO Mode = 0. FIMO6 Internal Main Oscillator Stability for 6 MHz (Commercial Temperature) 5.70 6.0 6.30 MHz Trimmed for 3.3V operation using factory trim values. See Figure 2-1b, SLIMO Mode = 1. DCIMO Duty Cycle of IMO 40 50 60 % TRAMP Supply Ramp Time 0 – – µs a. 0 to 70 °C ambient, Vdd = 3.3 V. Table 2-11. 2.7V AC Chip-Level Specifications Symbol Description Min Typ Max Units Notes FCPU1 CPU Frequency (2.7V Nominal) 0.75 – 3.25 MHz F32K1 Internal Low Speed Oscillator Frequency 8 32 96 kHz FIMO12 Internal Main Oscillator Stability for 12 MHz (Commercial Temperature)a 11.0 12 12.9 MHz Trimmed for 2.7V operation using factory trim values. See Figure 2-1b, SLIMO Mode = 0. FIMO6 Internal Main Oscillator Stability for 6 MHz (Commercial Temperature) 5.60 6.0 6.40 MHz Trimmed for 2.7V operation using factory trim values. See Figure 2-1b, SLIMO Mode = 1. DCIMO Duty Cycle of IMO 40 50 60 % TRAMP Supply Ramp Time 0 – – µs a. 0 to 70 °C ambient, Vdd = 3.3 V. September 18, 2006 Document No. 001-05356 Rev. *B 16 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 2.4.2 2. Electrical Specifications AC General Purpose IO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 2-12. 5V and 3.3V AC GPIO Specifications Symbol Description Min Typ Max Units Notes FGPIO GPIO Operating Frequency 0 – 6 MHz Normal Strong Mode, Port 1. TRise023 Rise Time, Strong Mode, Cload = 50 pF Ports 0, 2, 3 15 – 80 ns Vdd = 3.0 to 3.6V and 4.75V to 5.25V, 10% 90% TRise1 Rise Time, Strong Mode, Cload = 50 pF Port 1 10 – 50 ns Vdd = 3.0 to 3.6V, 10% - 90% TFall Fall Time, Strong Mode, Cload = 50 pF All Ports 10 – 50 ns Vdd = 3.0 to 3.6V and 4.75V to 5.25V, 10% 90% Table 2-13. 2.7V AC GPIO Specifications Symbol Description Min Typ Max Units Notes FGPIO GPIO Operating Frequency 0 – 1.5 MHz Normal Strong Mode, Port 1. TRise023 Rise Time, Strong Mode, Cload = 50 pF Ports 0, 2, 3 15 – 100 ns Vdd = 2.4 to 3.0V, 10% - 90% TRise1 Rise Time, Strong Mode, Cload = 50 pF Port 1 10 – 70 ns Vdd = 2.4 to 3.0V, 10% - 90% TFall Fall Time, Strong Mode, Cload = 50 pF All Ports 10 – 70 ns Vdd = 2.4 to 3.0V, 10% - 90% 90% GPIO Pin Output Voltage 10% TRise023 TRise1 TFall Figure 2-2. GPIO Timing Diagram September 18, 2006 Document No. 001-05356 Rev. *B 17 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 2.4.3 2. Electrical Specifications AC Comparator Amplifier Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 2-14. AC Operational Amplifier Specifications Symbol TCOMP 2.4.4 Description Min Typ Comparator Response Time, 50 mV Overdrive Max 100 200 Units ns ns Notes Vdd ≥ 3.0V. 2.4V < Vcc < 3.0V. AC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 2-15. AC Analog Mux Bus Specifications Symbol FSW Description Switch Rate September 18, 2006 Min – Typ – Max 3.17 Document No. 001-05356 Rev. *B Units Notes MHz 18 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 2.4.5 2. Electrical Specifications AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 2-16. 5V AC External Clock Specifications Symbol Description FOSCEXT Frequency Min Typ Max Units 0.750 – 12.6 MHz – High Period 38 – 5300 ns – Low Period 38 – – ns – Power Up IMO to Switch 150 – – µs Notes Table 2-17. 3.3V AC External Clock Specifications Symbol Description FOSCEXT Frequency with CPU Clock divide by 1 – – – Min Typ Max Units 0.750 – 12.6 MHz High Period with CPU Clock divide by 1 41.7 – 5300 ns Low Period with CPU Clock divide by 1 41.7 – – ns Power Up IMO to Switch 150 – – µs Notes Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. Table 2-18. 2.7V AC External Clock Specifications Symbol Description Min Typ Max Units Notes FOSCEXT Frequency with CPU Clock divide by 1 0.750 – 3.080 MHz Maximum CPU frequency is 3 MHz at 2.7V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. FOSCEXT Frequency with CPU Clock divide by 2 or greater 0.15 – 6.35 MHz If the frequency of the external clock is greater than 3 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. – High Period with CPU Clock divide by 1 160 – 5300 ns – Low Period with CPU Clock divide by 1 160 – – ns – Power Up IMO to Switch 150 – – µs September 18, 2006 Document No. 001-05356 Rev. *B 19 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 2.4.6 2. Electrical Specifications AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 2-19. AC Programming Specifications Symbol Description Min Typ Max Units Notes TRSCLK Rise Time of SCLK 1 – 20 ns TFSCLK Fall Time of SCLK 1 – 20 ns TSSCLK Data Set up Time to Falling Edge of SCLK 40 – – ns THSCLK Data Hold Time from Falling Edge of SCLK 40 – – ns FSCLK Frequency of SCLK 0 – 8 MHz TERASEB Flash Erase Time (Block) – 15 – ms TWRITE Flash Block Write Time – 30 – ms TDSCLK Data Out Delay from Falling Edge of SCLK – – 45 ns 3.6 < Vdd TDSCLK3 Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6 TDSCLK2 Data Out Delay from Falling Edge of SCLK – – 70 ns 2.4 ≤ Vdd ≤ 3.0 September 18, 2006 Document No. 001-05356 Rev. *B 20 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 2.4.7 2. Electrical Specifications AC SPI Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 2-20. 5V and 3.3V AC SPI Specifications Symbol Description Min Typ Max Units FSPIM Maximum Input Clock Frequency Selection, Master – – 6.3 MHz FSPIS Maximum Input Clock Frequency Selection, Slave – – 2.05 MHz TSS Width of SS_ Negated Between Transmissions 50 – – ns Notes Output clock frequency is half of input clock rate. Table 2-21. 2.7V AC SPI Specifications Symbol Description Min Typ Max Units FSPIM Maximum Input Clock Frequency Selection, Master – – 3.15 MHz FSPIS Maximum Input Clock Frequency Selection, Slave – – 1.025 MHz TSS Width of SS_ Negated Between Transmissions 50 – – ns September 18, 2006 Document No. 001-05356 Rev. *B Notes Output clock frequency is half of input clock rate. 21 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 2.4.8 2. Electrical Specifications AC I2C Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 2-22. AC Characteristics of the I2C SDA and SCL Pins for Vdd ≥ 3.0V Standard Mode Symbol Description Min Fast Mode Max Min Max Units FSCLI2C SCL Clock Frequency 0 100 0 400 kHz THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. 4.0 – 0.6 – µs TLOWI2C LOW Period of the SCL Clock 4.7 – 1.3 – µs THIGHI2C HIGH Period of the SCL Clock 4.0 – 0.6 – µs TSUSTAI2C Set-up Time for a Repeated START Condition 4.7 – 0.6 – µs THDDATI2C Data Hold Time 0 – 0 – µs TSUDATI2C Data Set-up Time 250 – 100a – ns TSUSTOI2C Set-up Time for STOP Condition 4.0 – 0.6 – µs TBUFI2C Bus Free Time Between a STOP and START Condition 4.7 – 1.3 – µs TSPI2C Pulse Width of spikes are suppressed by the input filter. – 0 50 ns – Notes a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Table 2-23. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) Standard Mode Symbol Description Min Fast Mode Max Min Max Units FSCLI2C SCL Clock Frequency 0 100 – – kHz THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. 4.0 – – – µs TLOWI2C LOW Period of the SCL Clock 4.7 – – – µs THIGHI2C HIGH Period of the SCL Clock 4.0 – – – µs TSUSTAI2C Set-up Time for a Repeated START Condition 4.7 – – – µs THDDATI2C Data Hold Time 0 – – – µs TSUDATI2C Data Set-up Time 250 – – – ns TSUSTOI2C Set-up Time for STOP Condition 4.0 – – – µs TBUFI2C Bus Free Time Between a STOP and START Condition 4.7 – – – µs TSPI2C Pulse Width of spikes are suppressed by the input filter. – – – ns – SDA TLOWI2C TSUDATI2C THDSTAI2C Notes TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S Figure 2-3. Definition for Timing for Fast/Standard Mode on the I2C Bus September 18, 2006 Document No. 001-05356 Rev. *B 22 [+] Feedback 3. Packaging Information This chapter illustrates the packaging specifications for the CY8C20x34 PSoC device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. 3.1 Packaging Dimensions 001-09116 ** Figure 3-1. 16-Lead (3x3 mm x 0.6 MAX) QFN -- Preliminary September 18, 2006 Document No. 001-05356 Rev. *B 23 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 3. Packaging Information 001-09049 ** Figure 3-2. 24-Lead (4x4 x 0.6 mm) QFN -- Preliminary September 18, 2006 Document No. 001-05356 Rev. *B 24 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 3. Packaging Information 001-06392 ** Figure 3-3. 32-Lead (5x5 mm 0.60 MAX) QFN September 18, 2006 Document No. 001-05356 Rev. *B 25 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 3. Packaging Information 51-85152 *B Figure 3-4. 48-Lead (7x7 mm) QFN Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. September 18, 2006 Document No. 001-05356 Rev. *B 26 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 3.2 3. Packaging Information Thermal Impedances Table 3-1. Thermal Impedances per Package Package Typical θJA * 16 QFN** 46 oC/W 24 QFN** 40 oC/W 32 QFN** 27 oC/W 48 QFN** 28 oC/W * TJ = TA + Power x θJA ** To achieve the thermal impedance specified for the ** package, the center thermal pad should be soldered to the PCB ground plane. 3.3 Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 3-2. Solder Reflow Peak Temperature Package Minimum Peak Temperature* Maximum Peak Temperature 16 QFN 240 C 260oC 24 QFN 240oC 260oC 32 QFN 240oC 260oC 48 QFN 240oC 260oC o *Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. September 18, 2006 Document No. 001-05356 Rev. *B 27 [+] Feedback 4. Development Tool Selection This chapter presents the development tools available for all current PSoC device families including the CY8C20x34 family. 4.1 4.1.1 Software 4.2 All development kits can be purchased from the Cypress Online Store. PSoC Designer™ At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http:// www.cypress.com under DESIGN RESOURCES >> Software and Drivers. 4.1.2 Development Kits PSoC Express™ As the newest addition to the PSoC development software suite, PSoC Express is the first visual embedded system design tool that allows a user to create an entire PSoC project and generate a schematic, BOM, and data sheet without writing a single line of code. Users work directly with application objects such as LEDs, switches, sensors, and fans. PSoC Express is available free of charge at http://www.cypress.com/psocexpress. 4.2.1 CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes: ■ PSoC Designer Software CD ■ ICE-Cube In-Circuit Emulator ■ ICE Flex-Pod for CY8C29x66 Family ■ Cat-5 Adapter ■ Mini-Eval Programming Board ■ 110 ~ 240V Power Supply, Euro-Plug Adapter ■ iMAGEcraft C Compiler (Registration Required) ■ ISSP Cable 4.1.3 PSoC Programmer ■ USB 2.0 Cable and Blue Cat-5 Cable Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube InCircuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocprogrammer. 4.1.4 ■ 2 CY8C29466-24PXI 28-PDIP Chip Samples CY3202-C iMAGEcraft C Compiler CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It can be purchased from the Cypress Online Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items.. September 18, 2006 Document No. 001-05356 Rev. *B 28 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 4.2.2 CY3210-ExpressDK PSoC Express Development Kit The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (may be used with ICE-Cube In-Circuit Emulator). It provides access to I2C buses, voltage reference, switches, upgradeable modules and more. The kit includes: ■ PSoC Express Software CD 4. Development Tool Selection 4.3.3 CY3214-PSoCEvalUSB The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes: ■ PSoCEvalUSB Board ■ Express Development Board ■ LCD Module ■ 4 Fan Modules ■ MIniProg Programming Unit ■ 2 Proto Modules ■ Mini USB Cable ■ MiniProg In-System Serial Programmer ■ PSoC Designer and Example Projects CD ■ MiniEval PCB Evaluation Board ■ Getting Started Guide ■ Jumper Wire Kit ■ Wire Pack ■ USB 2.0 Cable ■ Serial Cable (DB9) 4.4 ■ 110 ~ 240V Power Supply, Euro-Plug Adapter ■ 2 CY8C24423A-24PXI 28-PDIP Chip Samples Device Programmers All device programmers can be purchased from the Cypress Online Store. ■ 2 CY8C27443-24PXI 28-PDIP Chip Samples ■ 2 CY8C29466-24PXI 28-PDIP Chip Samples 4.4.1 4.3 Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store. 4.3.1 The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: ■ Modular Programmer Base CY3210-MiniProg1 ■ 3 Programming Module Cards The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: ■ MiniProg Programming Unit ■ MiniEval Socket Programming and Evaluation Board ■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample ■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample ■ MiniProg Programming Unit ■ PSoC Designer Software CD ■ Getting Started Guide ■ USB 2.0 Cable 4.4.2 CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: ■ PSoC Designer Software CD ■ Getting Started Guide ■ USB 2.0 Cable 4.3.2 CY3216 Modular Programmer CY3210-PSoCEval1 ■ CY3207 Programmer Unit The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ PSoC ISSP Software CD ■ 110 ~ 240V Power Supply, Euro-Plug Adapter ■ USB 2.0 Cable ■ Evaluation Board with LCD Module ■ MiniProg Programming Unit ■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) ■ PSoC Designer Software CD ■ Getting Started Guide ■ USB 2.0 Cable September 18, 2006 Document No. 001-05356 Rev. *B 29 [+] Feedback CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 4.5 4. Development Tool Selection Accessories (Emulation and Programming) Table 4-1. Emulation and Programming Accessories Part # Pin Package Flex-Pod Kita Foot Kitb Prototyping Module Adapterc CY8C20334 -12LFXI 24 QFN CY325020334QFN CY325024QFN-FK CY32100X34 AS-24-2801ML-6 CY8C20434 -12LKXI 32 QFN CY325020434QFN CY325032QFN-FK CY32100X34 AS-32-2803ML-6 a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. b. Foot kit includes surface mount feet that can be soldered to the target PCB. c. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. 4.6 3rd-Party Tools Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards. 4.7 Build a PSoC Emulator into Your Board For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note “Debugging - Build a PSoC Emulator into Your Board - AN2323” at http://www.cypress.com/ design/AN2323. September 18, 2006 Document No. 001-05356 Rev. *B 30 [+] Feedback 5. Ordering Information The following table lists the CY8C20234, CY8C20334 and CY8C20434 PSoC device’s key package features and ordering codes. CapSense Blocks Digital IO Pins Analog Outputs XRES Pin 512 0 1 13 13a 0 Yes 16 Pin (3x3 mm 0.60 MAX) QFN (Tape and Reel) CY8C20234-12LKXIT 8K 512 0 1 13 13a 0 Yes 24 Pin (4x4 mm 0.60 MAX) QFN CY8C20334-12LKXI 8K 512 0 1 20 20a 0 Yes 24 Pin (4x4 mm 0.60 MAX) QFN (Tape and Reel) CY8C20334-12LKXIT 8K 512 0 1 20 20a 0 Yes 32 Pin (5x5 mm 0.60 MAX) QFN CY8C20434-12LKXI 8K 512 0 1 28 28a 0 Yes 32 Pin (5x5 mm 0.60 MAX) QFN (Tape and Reel) CY8C20434-12LKXIT 8K 512 0 1 28 28a 0 Yes 48 Pin OCD QFN CY8C20000-12LFXI 8K 512 0 1 28 28a 0 Yes Analog Digital Blocks 8K Inputs a SRAM (Bytes) CY8C20234-12LKXI Ordering Code 16 Pin (3x3 mm 0.60 MAX) QFN Package Flash (Bytes) Table 5-1. PSoC Device Key Features and Ordering Information a. Dual-function Digital IO Pins also connect to the common analog mux. 5.1 Ordering Code Definitions CY 8 C 20 xxx-12xx Package Type: PX = PDIP Pb-Free SX = SOIC Pb-Free PVX = SSOP Pb-Free LFX = QFN Pb-Free LKX = QFN Pb-Free AX = TQFP Pb-Free Thermal Rating: C = Commercial I = Industrial E = Extended Speed: 12 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress September 18, 2006 Document No. 001-05356 Rev. *B 31 [+] Feedback 6. Sales and Service Information To obtain information about Cypress Semiconductor or PSoC sales and technical support, reference the following information. Cypress Semiconductor 198 Champion Court San Jose, CA 95134 408.943.2600 Web Links: 6.1 Company Information – http://www.cypress.com Sales – http://www.cypress.com/aboutus/sales_locations.cfm Technical Support – http://www.cypress.com/support/login.cfm Revision History Document Title: CY8C20234, CY8C20334, CY8C20434 PSoC® Mixed-Signal Array Final Data Sheet Document Number: 001-05356 Revision ECN # Issue Date Origin of Change Description of Change ** 404571 See ECN HMT New silicon and document (Revision **). *A 418513 See ECN HMT Update Electrical Specs., including Storage Temperature and Maximum Input Clock Frequency. Update Features and Analog System Overview. Modify 32-pin QFN E-PAD dimensions. Add new 32-pin QFN. Add High Output Drive indicator to all P1[x] pinouts. Update trademarks. *B 490071 See ECN HMT Make data sheet “Final.” Add new Dev. Tool section. Add OCD pinout and package diagram. Add 16-pin QFN. Update 24- and 32-pin QFN package diagrams to 0.60 MAX thickness. Change from commercial to industrial temperature range. Update Storage Temperature specification and notes. Update thermal resistance data. Add dev. tool kit part numbers. Finetune features and electrical specs. Distribution: External/Public 6.2 Posting: None Copyrights and Code Protection Copyrights © Cypress Semiconductor Corp. 2005-2006. All rights reserved. PSoC Designer™, Programmable System-on-Chip™, and PSoC Express are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress Semiconductor. Flash Code Protection Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices. Cypress Semiconductor products meet the specifications contained in their particular data sheets. Cypress Semiconductor believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Semiconductor are committed to continuously improving the code protection features of our products. September 18, 2006 © Cypress Semiconductor Corp. 2005-2006 — Document No. 001-05356 Rev. *B 32 [+] Feedback