CYPRESS CY7C1460AV33-167

CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined
SRAM with NoBL™ Architecture
Features
Functional Description
• Pin-compatible and functionally equivalent to ZBT™
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are 3.3V,
1 Mbit x 36 / 2 Mbit x 18 / 512K x72 Synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They
are designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1460AV33/
CY7C1462AV33/CY7C1464AV33 are equipped with the
advanced (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent Write/Read transitions.The
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33
are
pin
compatible and functionally equivalent to ZBT devices.
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate the
need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 3.3V power supply
• 3.3V/2.5V I/O power supply
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock input
is qualified by the Clock Enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 3.2 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Clock Enable (CEN) pin to suspend operation
Write operations are controlled by the Byte Write Selects
(BWa–BWh for CY7C1464AV33, BWa–BWd for CY7C1460AV33
and BWa–BWb for CY7C1462AV33) and a Write Enable (WE)
input. All writes are conducted with on-chip synchronous
self-timed write circuitry.
• Synchronous self-timed writes
• CY7C1460AV33 and CY7C1462AV33 are available in
lead-free 100-pin TQFP and 165-Ball fBGA packages;
CY7C1464AV33 available in 209-Ball fBGA package
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Logic Block Diagram-CY7C1460AV33 (1 Mbit x 36)
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWa
BWb
BWc
BWd
WRITE
DRIVERS
MEMORY
ARRAY
A
M
P
S
WE
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
ZZ
E
O
U
T
P
U
T
D
A
T
A
S
T
E
E
R
I
N
G
INPUT
REGISTER 0
B
U
F
F
E
R
S
DQs
DQPa
DQPb
DQPc
DQPd
E
E
READ LOGIC
SLEEP
CONTROL
Cypress Semiconductor Corporation
Document #: 38-05353 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 19, 2004
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Logic Block Diagram-CY7C1462AV33 (2 Mbit x 18)
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWa
WRITE
DRIVERS
MEMORY
ARRAY
BWb
S
E
N
S
E
A
M
P
S
WE
O
U
T
P
U
T
O
U
T
P
U
T
D
A
T
A
R
E
G
I
S
T
E
R
S
B
U
F
F
E
R
S
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
DQs
DQPa
DQPb
E
INPUT
REGISTER 0 E
READ LOGIC
Sleep
Control
Logic Block Diagram-CY7C1464AV33 (512K x 72)
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
E
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQPa
DQPb
DQPc
DQPd
DQPe
DQPf
DQPg
DQPh
WE
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
INPUT
REGISTER 0 E
READ LOGIC
Sleep
Control
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby
Current
CY7C1460AV33-250
CY7C1462AV33-250
CY7C1464AV33-250
CY7C1460AV33-200
CY7C1462AV33-200
CY7C1464AV33-200
CY7C1460AV33-167
CY7C1462AV33-167
CY7C1464AV33-167
Unit
2.6
475
100
3.2
425
100
3.4
375
100
ns
mA
mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05353 Rev. *A
Page 2 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CY7C1462AV33
(2 Mbit × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
NC/72M
VSS
VDD
DDQ
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
NC
VDD
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
VSS
VSS
VDDQ VDDQ
NC
DQa
DQa
NC
DQPa
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC/144M
A
A
A
A
A
A
A
A
NC/72M
VSS
VDD
NC/144M
NC/288M
MODE
A
A
A
A
A1
A0
Document #: 38-05353 Rev. *A
NC
DQPb
NC
DQb
NC
DQb
VDDQ VDDQ
VSS
VSS
NC
DQb
DQb
NC
DQb
DQb
DQb
DQb
VSS
VSS
VDDQ
V
NC/288M
CY7C1460AV33
(1 Mbit × 36)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
100-pin TQFP Packages
Page 3 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Pin Configurations (continued)
1
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
R
3
A
CE1
NC
A
CE2
DQPc
DQc
NC
DQc
VDDQ
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
165-Ball fBGA Pinout
CY7C1460AV33 (1 Mbit × 36)
4
5
6
7
BWc
BWb
8
9
10
ADV/LD
A
A
NC
CLK
CEN
WE
OE
A
A
NC/144M
VSS
VSS
VSS
VDD
VDDQ
DQPb
DQb
CE3
11
BWa
VSS
VDDQ
BWd
VSS
VDD
VSS
VSS
VSS
VDDQ
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
DQb
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQb
DQc
NC
DQd
DQb
NC
DQa
DQb
ZZ
DQa
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQPd
DQd
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
DQa
DQPa
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
NC
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
11
CY7C1462AV33 (2 Mbit × 18)
1
2
3
4
5
6
7
8
9
10
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
CE1
BWb
NC
NC
CE3
CEN
ADV/LD
A
A
R
NC
A
CE2
NC
NC
NC
DQb
VDDQ
NC
DQb
NC
NC
NC
DQb
DQb
DQb
DQb
A
NC/144M
BWa
CLK
VDDQ
VDDQ
VSS
VSS
VSS
OE
VSS
VDD
A
VSS
WE
VSS
VSS
A
VSS
VDD
VDDQ
NC
NC
DQPa
DQa
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
VDDQ
VDDQ
NC
VDDQ
VDD
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
NC
NC
DQa
DQa
DQa
ZZ
NC
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
DQPb
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
NC
NC
NC
NC/72M
A
A
TDI
A1
TDO
A
A
A
NC
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
DQb
NC
NC
Document #: 38-05353 Rev. *A
Page 4 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Pin Configurations (continued)
209-Ball PBGA
CY7C1464AV33 (512K x 72)
1
2
A
DQg
DQg
B
DQg
DQg
C
DQg
D
3
4
5
6
7
8
9
10
11
ADV/LD
A
CE3
A
DQb
DQb
CE2
A
BWSc
BWSg
NC
WE
A
BWSb
BWSf
DQb
DQb
DQg
BWSh
BWSd
NC
CE1
NC
BWSe
BWSa
DQb
DQb
DQg
DQg
VSS
NC
NC
OE
NC
NC
VSS
DQb
DQb
E
DQPg
DQPc
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPf
DQPb
F
DQc
DQc
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQf
G
DQc
DQc
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQf
DQf
H
DQc
DQc
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQf
DQf
J
DQc
DQc
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQf
DQf
K
NC
NC
CLK
NC
VSS
CEN
VSS
NC
NC
NC
NC
L
DQh
DQh
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
M
DQh
DQh
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQa
DQa
N
DQh
DQh
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQa
DQa
P
DQh
DQh
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQa
DQa
R
DQPd
DQPh
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
T
DQd
DQd
VSS
NC
NC
MODE
NC
NC
VSS
DQe
DQe
U
DQd
DQd
NC
A
A
A
A
NC
DQe
DQe
V
DQd
DQd
A
A
A
A1
A
A
A
DQe
DQe
W
DQd
DQd
TMS
TDI
A
A0
A
TCK
DQe
DQe
A
NC/72M
TDO
DQPa
DQf
DQPe
Pin Definitions
I/O Type
Pin Description
A0
A1
A
Pin Name
InputSynchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,
BWc controls DQc and DQPc, BWd controls DQd and DQPd, BWe controls DQe and DQPe, BWf
controls DQf and DQPf, BWg controls DQg and DQPg, BWh controls DQh and DQPh.
WE
InputSynchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
ADV/LD
InputSynchronous
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
Document #: 38-05353 Rev. *A
Page 5 of 27
PRELIMINARY
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE1
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
OE
InputAsynchronous
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state
and when the device has been deselected.
CEN
InputSynchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
DQa
DQb
DQc
DQd
DQe
DQf
DQg
DQh
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by AX during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging
from a deselected state, and when the device is deselected, regardless of the state of OE.
DQPa
DQPb
DQPc
DQPd
DQPe
DQPf
DQPg
DQPh
I/OSynchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During
write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by
BWc, and DQPd is controlled by BWd, DQPe is controlled by BWe, DQPf is controlled by BWf,
DQPg is controlled by BWg, DQPh is controlled by BWh.
MODE
Input Strap Pin
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
TDO
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Synchronous
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
TCK
JTAG-Clock
VDD
Power Supply
VDDQ
Clock input to the JTAG circuitry.
Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
VSS
NC
NC/72M
Ground
N/A
N/A
NC/144M
N/A
Not connected to the die. Can be tied to any voltage level.
N/A
Not connected to the die. Can be tied to any voltage level.
NC/288M
ZZ
InputAsynchronous
Document #: 38-05353 Rev. *A
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
Not connected to the die. Can be tied to any voltage level.
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin can be connected to Vss or left
floating.
Page 6 of 27
PRELIMINARY
Introduction
Functional Overview
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 are
synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(tCO) is 2.6 ns (250-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BW[x] can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.6 ns
(250-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will tri-state following the
next clock rise.
Burst Read Accesses
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 have
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four Reads without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load a new address into the SRAM, as described in
the Single Read Access section above. The sequence of the
burst counter is determined by the MODE input signal. A LOW
input on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and
Document #: 38-05353 Rev. *A
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment
the internal burst counter regardless of the state of chip
enables inputs or WE. WE is latched at the beginning of a burst
cycle. Therefore, the type of access (Read or Write) is
maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address inputs
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
for
CY7C1464AV33,
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b
for CY7C1462AV33). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the
Address Register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
for
CY7C1464AV33,
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 & DQa,b/DQPa,b for
CY7C1462AV33) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into
the device and the write is complete.
The data written during the Write operation is controlled by BW
(BWa,b,c,d,e,f,g,h
for
CY7C1464AV33,
BWa,b,c,d
for
CY7C1460AV33 and BWa,b for CY7C1462AV33) signals. The
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 provides
byte write capability that is described in the Write Cycle
Description table. Asserting the Write Enable input (WE) with
the selected Byte Write Select (BW) input will selectively write
to only the desired bytes. Bytes not selected during a byte
write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations. Byte write capability has been included in
order to greatly simplify Read/Modify/Write sequences, which
can be reduced to simple byte write operations.
Because
the
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33
are
common I/O devices, data should not be driven into the device
while the outputs are active. The Output Enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
for
CY7C1464AV33,
(DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV33 and DQa,b/DQPa,b
for CY7C1462AV33) inputs. Doing so will tri-state the output
drivers. As a safety precaution, DQ and DQP (DQa,b,c,d,e,f,g,h/
DQPa,b,c,d,e,f,g,h for CY7C1464AV33, DQa,b,c,d/ DQPa,b,c,d for
CY7C1460AV33 and DQa,b/DQPa,b for CY7C1462AV33) are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 has
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD is
Page 7 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
driven HIGH on the subsequent clock rise, the chip enables
(CE1, CE2, and CE3) and WE inputs are ignored and the burst
counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h for
CY7C1464AV33 , BWa,b,c,d for CY7C1460AV33 and BWa,b for
CY7C1462AV33) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
A1,A0
A1,A0
A1,A0
Sleep Mode
00
01
10
11
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Sleep mode standby current
Min.
ZZ > VDD − 0.2V
tZZS
Device operation to ZZ
ZZ > VDD − 0.2V
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ active to sleep current
This parameter is sampled
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
Max
Unit
100
mA
2tCYC
ns
2tCYC
ns
2tCYC
0
ns
ns
Truth Table[1, 2, 3, 4, 5, 6, 7]
Operation
Address
Used
CE
ZZ
ADV/LD
WE
BWx
OE
CEN
CLK
DQ
Deselect Cycle
None
H
L
L
X
X
X
L
L-H
Tri-State
Continue
Deselect Cycle
None
X
L
H
X
X
X
L
L-H
Tri-State
Read Cycle
(Begin Burst)
External
L
L
L
H
X
L
L
L-H
Data Out (Q)
Read Cycle
(Continue Burst)
Next
X
L
H
X
X
L
L
L-H
Data Out (Q)
NOP/Dummy Read
(Begin Burst)
External
L
L
L
H
X
H
L
L-H
Tri-State
Dummy Read
(Continue Burst)
Next
X
L
H
X
X
H
L
L-H
Tri-State
Write Cycle
(Begin Burst)
External
L
L
L
L
L
X
L
L-H
Data In (D)
Write Cycle
(Continue Burst)
Next
X
L
H
X
L
X
L
L-H
Data In (D)
NOP/WRITE ABORT None
(Begin Burst)
L
L
L
L
H
X
L
L-H
Tri-State
WRITE ABORT
(Continue Burst)
X
L
H
X
H
X
L
L-H
Tri-State
Next
Document #: 38-05353 Rev. *A
Page 8 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Truth Table[1, 2, 3, 4, 5, 6, 7]
Operation
Address
Used
CE
ZZ
ADV/LD
WE
BWx
IGNORE CLOCK
EDGE
(Stall)
Current
X
L
X
X
X
X
OE
H
CEN
L-H
CLK
SLEEP MODE
None
X
H
X
X
X
X
X
X
DQ
-
Tri-State
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWX. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Tri-state when OE is
inactive or when the device is deselected, and DQs=data when OE is active.
Document #: 38-05353 Rev. *A
Page 9 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Partial Write Cycle Description[1, 2, 3, 8]
Function (CY7C1460AV33)
WE
BWd
BWc
BWb
BWa
Read
H
X
X
X
X
Write – No bytes written
L
H
H
H
H
Write Byte a – (DQa and DQPa)
L
H
H
H
L
Write Byte b – (DQb and DQPb)
L
H
H
L
H
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)
L
H
L
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
LL
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)
L
L
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
L
H
L
H
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Function (CY7C1462AV33)[2,8]
WE
BWb
BWa
Read
H
x
x
Write – No Bytes Written
L
H
H
Write Byte a – (DQa and DQPa)
L
H
L
Write Byte b – (DQb and DQPb)
L
L
H
Write Both Bytes
L
L
L
Function (CY7C1464AV33)[2,8]
WE
BWx
Read
H
x
Write – No Bytes Written
L
H
Write Byte X − (DQx and DQPx)
L
L
Write All Bytes
L
All BW = L
Note:
8. Table only lists a partial listing of the byte write combinations. Any combinaion of BW[a:d] is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05353 Rev. *A
Page 10 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Data-In (TDI)
The CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 incorporates a serial boundary scan test access port (TAP). This
part is fully compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic level.
The
CY7C1460AV33/CY7C1462AV33/CY7C1464AV33
contains a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
1
0
Bypass Register
TEST-LOGIC
RESET
2 1 0
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
1
CAPTURE-DR
0
Selection
Circuitry
TDO
Identification Register
CAPTURE-IR
x . . . . . 2 1 0
SHIFT-IR
1
Instruction Register
31 30 29 . . . 2 1 0
0
SHIFT-DR
Boundary Scan Register
0
1
EXIT1-DR
1
EXIT1-IR
0
1
TCK
0
PAUSE-DR
0
PAUSE-IR
1
0
TMS
TAP CONTROLLER
1
EXIT2-DR
0
EXIT2-IR
1
Performing a TAP Reset
1
UPDATE-DR
1
TDI
Selection
Circuitry
0
0
0
1
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test MODE SELECT (TMS)
Instruction Register
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Test Access Port (TAP)
Test Clock (TCK)
Document #: 38-05353 Rev. *A
Page 11 of 27
PRELIMINARY
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The length of the Boundary
Scan Register for the SRAM in different packages is listed in
the Scan Register Sizes table.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
Document #: 38-05353 Rev. *A
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE / PRELOAD is a 1149.1 mandatory instruction.
When the SAMPLE / PRELOAD instructions are loaded into
the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins
is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE / PRELOAD instruction. If
this is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required - that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #89
( for 165-FBGA package) or bit #138 ( for 209 BGA package).
Page 12 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
Reserved
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR,” the value
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
Test Clock
(TCK)
3
t TH
t TMSS
t TMSH
t TDIS
t TDIH
t
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter
Description
Min.
Max.
Unit
Clock
tTCYC
TCK Clock Cycle Time
50
ns
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH time
25
20
MHz
ns
tTL
TCK Clock LOW time
25
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
5
ns
0
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
5
ns
tTDIS
TDI Set-up to TCK Clock Rise
5
ns
Capture Set-up to TCK Rise
5
ns
tTMSH
TMS hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
Capture Hold after Clock Rise
5
ns
tCS
Hold Times
tCH
Notes:
9.tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
10.Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1ns.
Document #: 38-05353 Rev. *A
Page 13 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ................................................ VSS to 3.3V
Input pulse levels ........................................ VSS to 2.5V
Input rise and fall times ..................... ..............................1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels ...........................................1.5V
Input timing reference levels................... ......................1.25V
Output reference levels...................................................1.5V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage...............................1.5V
Test load termination supply voltage .................... ........1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; Vdd =3.135V to 3.6V unless otherwise noted)[11]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = -4.0 mA,VDDQ = 3.3V
2.4
V
IOH = -1.0 mA,VDDQ = 2.5V
2.0
V
VOH2
Output HIGH Voltage
IOH = -100 µA
VDDQ = 3.3V
2.9
V
VDDQ = 2.5V
2.1
VOL1
Output LOW Voltage
IOL = 8.0 mA
VDDQ = 3.3V
0.4
V
IOL = 1.0 mA
VDDQ = 2.5V
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
VDDQ = 3.3V
0.2
V
VIH
Input HIGH Voltage
VDDQ = 3.3V
VIL
Input LOW Voltage
VDDQ = 2.5V
IX
Input Load Current
VDDQ = 2.5V
V
0.2
V
2.0
VDD + 0.3
V
VDDQ = 2.5V
1.7
VDD + 0.3
V
VDDQ = 3.3V
-0.3
0.8
V
-0.3
0.7
V
-5
5
µA
GND < VIN < VDDQ
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Device Depth (28:24)[12]
CY7C1460AV33 CY7C1462AV33 CY7C1464AV33
(1 Mbit ×36)
(2 Mbit ×18)
(512K ×72)
000
000
000
Description
Describes the version number.
01011
01011
01011
Architecture/Memory Type(23:18)
001000
001000
001000
Defines memory type and architecture
Bus Width/Density(17:12)
100111
010111
110111
Defines width and density
00000110100
00000110100
00000110100
1
1
1
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Reserved for Internal Use
Allows unique identification of
SRAM vendor.
Indicates the presence of an ID
register.
Notes:
11. All voltages referenced to VSS (GND).
12. Bit #24 is “1” in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
Document #: 38-05353 Rev. *A
Page 14 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Scan Register Sizes
Register Name
Instruction
Bit Size (×36)
Bit Size (×18)
Bit Size (×72)
3
3
3
Bypass
1
1
1
ID
32
32
32
Boundary Scan Order-165FBGA
89
89
-
Boundary Scan Order- 209BGA
-
-
138
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05353 Rev. *A
Page 15 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
165-Ball fBGA Boundary Scan Order [13]
CY7C1460AV33 (1 Mbit x 36)
CY7C1460AV33 (1 Mbit x 36)
Bit#
Ball ID
Bit#
Ball ID
Bit#
Ball ID
1
N6
42
A7
83
P2
2
N7
43
B7
84
R4
3
N10
44
B6
85
P4
4
P11
45
A6
86
N5
5
P8
46
B5
87
P6
6
R8
47
A5
88
R6
7
R9
48
A4
89
Internal
8
P9
49
B4
9
P10
50
B3
10
R10
51
A3
1
CY7C1462AV33 (2 Mbit x 18)
11
R11
52
A2
2
N7
12
H11
53
B2
3
10N
N6
13
N11
54
C2
4
P11
14
M11
55
B1
5
P8
15
L11
56
A1
6
R8
16
K11
57
C1
7
R9
17
J11
58
D1
8
P9
18
M10
59
E1
9
P10
19
L10
60
F1
10
R10
20
K10
61
G1
11
R11
21
J10
62
D2
12
H11
22
H9
63
E2
13
N11
23
H10
64
F2
14
M11
24
G11
65
G2
15
L11
25
F11
66
H1
16
K11
26
E11
67
H3
17
J11
27
D11
68
J1
18
M10
28
G10
69
K1
19
L10
29
F10
70
L1
20
K10
30
E10
71
M1
21
J10
31
D10
72
J2
22
H9
32
C11
73
K2
23
H10
33
A11
74
L2
24
G11
34
B11
75
M2
25
F11
35
A10
76
N1
26
E11
36
B10
77
N2
27
D11
37
A9
78
P1
28
G10
38
B9
79
R1
29
F10
39
C10
80
R2
30
E10
40
A8
81
P3
31
D10
41
B8
82
R3
32
C11
Note:
13. Bit# 89 is preset HIGH.
Document #: 38-05353 Rev. *A
Page 16 of 27
PRELIMINARY
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
165-Ball fBGA Boundary Scan Order [13]
CY7C1462AV33 (2 Mbit x 18)
Bit#
Ball ID
Bit#
Ball ID
33
A11
61
G1
34
B11
62
D2
35
A10
63
E2
36
B10
64
F2
37
A9
65
G2
38
B9
66
H1
39
C10
67
H3
40
A8
68
J1
41
B8
69
K1
42
A7
70
L1
43
B7
71
M1
44
B6
72
J2
45
A6
73
K2
46
B5
74
L2
47
A5
75
M2
48
A4
76
N1
49
B4
77
N2
50
B3
78
P1
51
A3
79
R1
52
A2
80
R2
53
B2
81
P3
54
C2
82
R3
55
B1
83
P2
56
A1
84
R4
57
C1
85
P4
58
D1
86
N5
59
E1
87
P6
60
F1
88
R6
89
Internal
Document #: 38-05353 Rev. *A
Page 17 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
209-Ball BGA Boundary Scan Order [13, 14]
CY7C1464AV33 (512K x 72)
Bit#
CY7C1464AV33 (512K x 72)
Bit#
Ball ID
Ball ID
1
W6
35
J6
2
V6
36
F6
3
U6
37
K8
4
W7
38
K9
Bit#
Ball ID
Bit#
Ball ID
69
D6
104
K1
70
G6
105
N6
71
H6
106
K3
72
C6
107
K4
5
V7
39
K10
73
B6
108
K6
6
U7
40
J11
74
A6
109
K2
7
T7
41
J10
75
A5
110
L2
8
V8
42
H11
76
B5
111
L1
9
U8
43
H10
77
C5
112
M2
10
T8
44
G11
78
D5
113
M1
11
V9
45
G10
79
D4
114
N2
12
U9
46
F11
80
C4
115
N1
13
P6
47
F10
81
A4
116
P2
14
W11
48
E10
82
B4
117
P1
15
W10
49
E11
83
C3
118
R2
16
V11
50
D11
84
B3
119
R1
17
V10
51
D10
85
A3
120
T2
18
U11
52
C11
86
A2
121
T1
19
U10
53
C10
87
A1
122
U2
20
T11
54
B11
88
B2
123
U1
21
T10
55
B10
89
B1
124
V2
22
R11
56
A11
90
C2
125
V1
23
R10
57
A10
91
C1
126
W2
24
P11
58
C9
92
D2
127
W1
25
P10
59
B9
93
D1
128
T6
26
N11
60
A9
94
E1
129
U3
27
N10
61
D8
95
E2
130
V3
28
M11
62
C8
96
F2
131
T4
29
M10
63
B8
97
F1
132
T5
30
L11
64
A8
98
G1
133
U4
31
L10
65
D7
99
G2
134
V4
32
K11
66
C7
100
H2
135
W5
33
M6
67
B7
101
H1
136
V5
34
L6
68
A7
102
J2
137
U5
103
J1
138
Internal
Note:
14. Bit# 138 is preset HIGH.
Document #: 38-05353 Rev. *A
Page 18 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Range
DC to Outputs in Tri-State ................... –0.5V to VDDQ + 0.5V
Commercial
Ambient
Temperature
DC Input Voltage....................................–0.5V to VDD + 0.5V
VDD
VDDQ
0°C to +70°C 3.3V–5%/+10% 2.5V –5% to
VDD
Electrical Characteristics Over the Operating Range[15, 16]
Parameter
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage[15]
VIL
Input LOW Voltage[15]
IX
Input Load Current except ZZ and MODE
Test Conditions
Min.
3.135
3.6
V
3.135
VDD
V
VDDQ = 2.5V
2.375
2.625
V
VDD = Min., IOH = −4.0 mA, VDDQ = 3.3V
2.4
VDD = Min., IOH= −1.0 mA, VDDQ = 2.5V
2.0
VDD = Max., IOL= 8.0 mA, VDDQ = 3.3V
V
0.4
V
0.4
V
VDD + 0.3V
V
VDDQ = 2.5V
1.7
VDD + 0.3V
V
VDDQ = 3.3V
–0.3
0.8
V
VDDQ = 2.5V
–0.3
0.7
V
–5
5
µA
GND ≤ VI ≤ VDDQ
µA
–5
Input = VDD
30
Input = VSS
µA
µA
–30
5
µA
5
µA
4.0-ns cycle, 250 MHz
475
mA
5.0-ns cycle, 200 MHz
425
mA
6.0-ns cycle, 167 MHz
375
mA
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
VIN ≥ VIH or VIN ≤ VIL, f = fMAX = 5.0-ns cycle, 200 MHz
1/tCYC
6.0-ns cycle, 167 MHz
225
mA
225
mA
225
mA
Input = VDD
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Automatic CE
Power-down
Current—TTL Inputs
V
2.0
VDDQ = 3.3V
Input Current of MODE Input = VSS
ISB1
Unit
VDDQ = 3.3V
VDD = Max., IOL= 1.0 mA, VDDQ = 2.5V
Input Current of ZZ
Max.
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
–5
ISB2
Automatic CE
Max. VDD, Device Deselected, All speed grades
Power-down
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
Current—CMOS Inputs f = 0
100
mA
ISB3
Automatic CE
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
Power-down
VIN ≤ 0.3V or VIN > VDDQ − 0.3V, 5.0-ns cycle, 200 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
6.0-ns cycle, 167 MHz
200
mA
200
mA
200
mA
Automatic CE
Power-down
Current—TTL Inputs
110
mA
ISB4
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
All speed grades
Shaded areas contain advance information.
Notes:
15. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2).
16. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05353 Rev. *A
Page 19 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Capacitance[17]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
100 TQFP
TA = 25°C, f = 1 MHz,
VDD = 2.5V VDDQ = 2.5V
165 FBGA
209 FBGA
Unit
6.5
5
5
pF
3
5
5
pF
5.5
7
7
pF
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
GND
5 pF
INCLUDING
JIG AND
SCOPE
VT = 1.5V
(a)
2.5V I/O Test Load
VT = 1.25V
(a)
≤ 1 ns
≤ 1 ns
(b)
(c)
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
Z0 = 50Ω
Thermal
R = 351Ω
R = 1667Ω
2.5V
OUTPUT
90%
10%
90%
10%
5 pF
INCLUDING
JIG AND
SCOPE
90%
10%
90%
10%
GND
R =1538Ω
≤ 1ns
≤ 1ns
(b)
(c)
Resistance[17]
Parameters
Description
QJA
Thermal Resistance
(Junction to Ambient)
QJC
Thermal Resistance
(Junction to Case)
Test Conditions
100 TQFP
165 FBGA
209 FBGA
Unit
Test conditions follow standard
test methods and procedures
for measuring thermal
impedence, per EIA / JESD51.
25.21
20.8
25.31
°C/W
2.28
3.2
4.48
°C/W
Switching Characteristics Over the Operating Range [22, 23]
250
Parameter
tPower[18]
200
Max.
Min.
167
Max.
Min.
Max.
Unit
Description
Min.
VCC (typical) to the first access read or write
1
1
1
ms
4.0
5.0
6.0
ns
Clock
tCYC
Clock Cycle Time
FMAX
Maximum Operating Frequency
tCH
Clock HIGH
1.5
2.0
2.4
ns
tCL
Clock LOW
1.5
2.0
2.4
ns
250
200
167
MHz
Output Times
tCO
Data Output Valid After CLK Rise
2.6
3.2
3.4
ns
tEOV
OE LOW to Output Valid
2.6
3.0
3.4
ns
tDOH
Data Output Hold After CLK Rise
tCHZ
Clock to High-Z[19, 20, 21]
3.4
ns
1.0
1.5
2.6
1.5
3.0
ns
Shaded areas contain advance information.
Notes:
17. Tested initially and after any design or process changes that may affect these parameters.
18. This part has a voltage regulator internally; tpower is the time power needs to be supplied above Vdd minimum initially, before a Read or Write operation can be
initiated.
19. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
20. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
22. Timing reference is 1.5V when VDDQ=3.3V and is 1.25V when VDDQ=2.5V.
23. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05353 Rev. *A
Page 20 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[22, 23]
250
Parameter
Description
Min.
[19, 20, 21]
Clock to Low-Z
tCLZ
167
Max.
Min.
1.3
Max.
Unit
3.4
ns
1.5
2.6
OE HIGH to Output High-Z
OE LOW to Output Low-Z[19, 20, 21]
tEOLZ
Min.
1.0
[19, 20, 21]
tEOHZ
200
Max.
3.0
ns
0
0
0
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
1.2
1.4
1.5
ns
tDS
Data Input Set-up Before CLK Rise
1.2
1.4
1.5
ns
tCENS
CEN Set-up Before CLK Rise
WE, BWx Set-up Before CLK Rise
1.2
1.4
1.5
ns
1.2
1.4
1.5
ns
ADV/LD Set-up Before CLK Rise
Chip Select Set-up
1.2
1.4
1.5
ns
1.2
1.4
1.5
ns
tAH
Address Hold After CLK Rise
0.3
0.4
0.5
ns
tDH
tWES
tALS
tCES
Hold Times
Data Input Hold After CLK Rise
0.3
0.4
0.5
ns
tCENH
CEN Hold After CLK Rise
0.3
0.4
0.5
ns
tWEH
WE, BWx Hold After CLK Rise
0.3
0.4
0.5
ns
ADV/LD Hold after CLK Rise
Chip Select Hold After CLK Rise
0.3
0.4
0.5
ns
0.3
0.4
0.5
ns
tALH
tCEH
Switching Waveforms
Read/Write/Timing[24,25,26]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCH
tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BWx
A1
ADDRESS
A2
tCO
tAS
tDS
tAH
Data
tDH
D(A1)
tCLZ
D(A2)
D(A2+1)
tDOH
Q(A3)
tOEV
Q(A4)
tCHZ
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
tOEHZ
tDOH
tOELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes:
24. For this waveform ZZ is tied low.
25. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH,CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
26. Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional.
Document #: 38-05353 Rev. *A
Page 21 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Switching Waveforms (continued)
NOP,STALL and DESELECT Cycles[24,25,27]
1
2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
A1
ADDRESS
A2
A5
tCHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
ZZ
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
ModeTiming[28,29]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
27. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
29. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05353 Rev. *A
Page 22 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Ordering Information
Speed
(MHz)
250
200
167
Ordering Code
Package
Name
Package Type
CY7C1460AV33-250AXC
CY7C1462AV33-250AXC
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
CY7C1460AV33-250BZC
CY7C1462AV33-250BZC
BB165C
165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1464AV33-250BGC
BB209A
209-ball Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1460AV33-250BZXC
CY7C1462AV33-250BZXC
BB165C
Lead-Free 165-ball Fine Pitch Ball Grid Array (15 x
17 x 1.4 mm)
CY7C1464AV33-250BGXC
BB209A
Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76
mm)
CY7C1460AV33-200AXC
CY7C1462AV33-200AXC
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
CY7C1460AV33-200BZC
CY7C1462AV33-200BZC
BB165C
165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1464AV33-200BGC
BB209A
209-ball Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1460AV33-200BZXC
CY7C1462AV33-200BZXC
BB165C
Lead-Free 165-ball Fine Pitch Ball Grid Array (15 x
17 x 1.4 mm)
CY7C1464AV33-200BGXC
BB209A
Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76
mm)
CY7C1460AV33-167AXC
CY7C1462AV33-167AXC
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
CY7C1460AV33-167BZC
CY7C1462AV33-167BZC
BB165C
165-ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
CY7C1464AV33-167BGC
BB209A
209-ball Ball Grid Array (14 × 22 × 1.76 mm)
CY7C1460AV33-167BZXC
CY7C1462AV33-167BZXC
BB165C
Lead-Free 165-ball Fine Pitch Ball Grid Array (15 x
17 x 1.4 mm)
CY7C1464AV33-167BGXC
BB209A
Lead-Free 209-ball Ball Grid Array (14 × 22 × 1.76
mm)
Operating
Range
Commercial
Shaded areas contain advance information.
Document #: 38-05353 Rev. *A
Page 23 of 27
PRELIMINARY
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05353 Rev. *A
Page 24 of 27
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
PRELIMINARY
Package Diagrams (continued)
165-Ball FBGA (15 x 17 x 1.40 mm) BB165C
PIN 1 CORNER
BOTTOM VIEW
TOP VIEW
Ø0.05 M C
PIN 1 CORNER
Ø0.25 M C A B
Ø0.45±0.05(165X)
1
2
3
4
5
6
7
8
9
10
11
11
10
9
8
7
6
5
4
3
2
1
A
B
B
C
C
1.00
A
D
D
F
F
G
G
H
J
14.00
E
17.00±0.10
E
H
J
K
L
L
7.00
K
M
M
N
N
P
P
R
R
A
1.00
5.00
0.35
0.15 C
+0.05
-0.10
0.53±0.05
0.25 C
10.00
B
15.00±0.10
0.15(4X)
SEATING PLANE
1.40 MAX.
0.36
C
51-85165-*A
Document #: 38-05353 Rev. *A
Page 25 of 27
PRELIMINARY
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Package Diagrams (continued)
209-Ball FBGA (14 x 22 x 1.76 mm) BB209A
51-85167-**
ZBT is a registered trademark of Integrated Device Technology. No Bus Latency and NoBL are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders.
Document #: 38-05353 Rev. *A
Page 26 of 27
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Document History Page
Document Title: CY7C1460AV33/CY7C1462AV33/CY7C1464AV33 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM
with NoBL™ Architecture
Document Number: 38-05353
REV.
ECN No.
Issue Date
Orig. of
Change
**
254911
See ECN
SYT
New Datasheet
Part number changed from previous revision. New and old part number differ
by the letter “A”
*A
303533
See ECN
SYT
Changed H9 pin from VSSQ to VSS on the Pin Configuration table for 209
FBGA on Page # 5
Changed the test condition from VDD = Min to VDD = Max for VOL in the
Electrical Characteristics table.
Replaced ΘJA and ΘJC from TBD to respective Thermal Values for All
Packages on the Thermal Resistance Table
Changed IDD from 450, 400 & 350 mA to 475, 425 & 375 mA for 250, 200
and 167 Mhz respectively
Changed ISB1 from 190, 180 and 170 mA to 225 mA for 250, 200 and 167
Mhz respectively.
Changed ISB2 from 80 mA to 100 mA for all frequencies
Changed ISB3 from 180, 170 & 160 mA to 200 mA for 250, 200 and 167 Mhz
respectively.
Changed ISB4 from 100 mA to 110 mA for all frequencies
Changed CIN ,CCLK and CI/O to 6.5, 3 and 5.5 pF from 5, 5 and 7 pF for TQFP
Package.
Changed tCO from 3.0 to 3.2 ns and tDOH from 1.3 ns to 1.5 ns for 200 Mhz
Speed Bin
Added lead-free information for 100-Pin TQFP and 165 FBGA and 209 BGA
packages
Document #: 38-05353 Rev. *A
Description of Change
Page 27 of 27