PRELIMINARY CYV15G0102EQ Multi-Rate Video Cable Equalizer Features Functional Description • Multi-Rate Adaptive Equalization • SMPTE 292M, SMPTE 344M, and SMPTE 259M Compliant • Supports DVB-ASI at 270 Mbps • Cable Length Indicator for HD-SDI and SD-SDI data rates • Maximum Cable Length Adjustment for HD-SDI and SD-SDI data rates The CYV15G0102EQ is a multi-rate adaptive equalizer designed to equalize and restore signals received over 75Ω coaxial cable. The equalizer is designed to meet SMPTE 292M, SMPTE 344M, and SMPTE 259M data rates. The CYV15G0102EQ is optimized to equalize up to 400m of Belden 1694A coaxial cable at 270 Mbps and up to 200m of Belden 1694A coaxial cable at 1.485 Gbps. The CYV15G0102EQ connects seamlessly to the HOTLink II family of transceiver devices. • Low Power 160 mW @ 3.3V The CYV15G0102EQ has DC restoration for compensation of the DC content of the SMPTE pathological patterns. A cable length indicator (CLI) provides an indication of the cable length being equalized at HD-SDI and SD-SDI data rates. The Maximum cable length adjust (MCLADJ) sets the approximate maximum cable length to be equalized at SD and HD data rates. The CYV15G0102EQ’s differential serial outputs (SDO, SDO) mute, when the approximate cable length set by MCLADJ is reached. CD/MUTE is a bidirectional pin that provides an indication of the signal being present at the equalizer inputs. It also controls muting the outputs of the equalizer at HD and SD data rates. • Single 3.3V supply Power consumption is typically 160 mW at 3.3V. • Carrier detect and Mute functionality for HD-SDI and SD-SDI data rates • Equalizer Bypass Mode • Seamless connection with HOTLink II™ Family • Equalizes up to 400m of Belden 1694A coaxial cable at 270 Mbps • Equalizes up to 200m of Belden 1694A coaxial cable at 1.485 Gbps • 16-pin SOIC • 0.18-µm CMOS technology • Pb-free and RoHS compliant • Pin-compatible to existing equalizer devices Equalizer System Connection Diagram HOTLink II Serializer Cypress Semiconductor Corporation Document #: 001-04205 Rev. *A CYV15G0102EQ Multi-Rate Cable Equalizer Serial Links Cable Driver Copper Cable Connections • 198 Champion Court • HOTLink II Deserializer San Jose, CA 95134-1709 • 408-943-2600 Revised August 30, 2005 PRELIMINARY CYV15G0102EQ Equalizer Block Diagram CYV15G0102EQ Multi-Rate Video Cable Equalizer Block Diagram CYV15G0102EQ Multi-Rate Video Cable Equalizer Block Diagram CLI MCLADJ Cable Length Analog Indicator and Mute Threshold Block Carrier Detect and Mute Control Block CD / MUTE DC Restore BYPASS SDI, SDI Equalizer Differential Output SDO, SDO Pin Configuration (Top View) 16-PIN SOIC Top View CLI 16 CD/MUTE VCC 2 15 VCC GND 3 14 GND SDI 4 13 SDO CYV15G0102EQ SDI 5 12 SDO GND 6 11 GND AGC+ 7 10 MCLADJ AGC- 8 9 BYPASS Document #: 001-04205 Rev. *A Page 2 of 10 PRELIMINARY CYV15G0102EQ Pin Descriptions CYV15G0102EQ Single Channel Cable Equalizer Name I/O Characteristics Signal Description Control Signals CLI Analog Output Cable Length Indicator: CLI provides an analog voltage proportional to the cable length being equalized. CLI works at both SD-SDI and HD-SDI data rates. CD/MUTE LVTTL I/O Carrier Detect/Mute Indicator: Output: When the incoming data stream is present, the CD/MUTE outputs a voltage less than 0.8V. When the incoming data stream is not present, the CD/MUTE outputs a voltage greater than 3V. Input: When the CD/MUTE pin is tied to ground, the equalizer’s differential serial outputs are not muted and the MCLADJ setting is overwritten. When the CD/MUTE pin is tied to VCC, the equalizer’s differential serial outputs are muted and the MCLADJ setting is overwritten. MCLADJ Analog Input Maximum Cable Length Adjust: The maximum cable length to be equalized is set by the voltage applied to the MCLADJ input. When the maximum cable length set by MCLADJ is reached, the differential output is muted. MCLADJ works at both SD and HD data rates. BYPASS LVTTL Input Equalizer Bypass: When BYPASS is tied to VCC, the signal presented at the equalizer’s differential serial inputs (SDI, SDI) is routed to the equalizer’s differential serial outputs (SDO, SDO) without performing equalization. When BYPASS is tied to GND, the incoming video data stream is equalized and presented at the equalizer‘s serial differential outputs (SDO, SDO). In equalizer bypass mode, CD/MUTE is not functional. AGC± Analog Automatic Gain Control: A capacitor of 1 µF should be placed between the AGC± pins. SDO, SDO Differential Output Differential Serial Outputs: The equalized serial video data stream is presented at the SDO/SDO differential serial CML output. SDI, SDI Differential Input Differential Serial Inputs: SDI/SDI can accept either a single ended or differential serial video data stream over 75Ω coaxial cable. VCC Power +3.3V Power. GND Gnd Connect to Ground. Power Equalizer Operation by RP178. The CYV15G0102EQ multi-rate Cable Equalizer is auto-adaptive from 143 Mbps to 1.485 Gbps. The CYV15G0102EQ is a high-speed adaptive cable equalizer designed to equalize standard definition (SD) and high definition (HD) serial digital interface (SDI) video data streams. CYV15G0102EQ equalizer is optimized to equalize up to 400m of Belden 1694A cable at 270 Mbps and up to 200m of Belden 1694A cable at 1.485 Gbps. The CYV15G0102EQ equalizer contains one power supply and typically consumes 160 mW power at 3.3V. The multi-rate equalizer is designed to meet the SMPTE 259M, SMPTE 292M, SMPTE 344M and DVB-ASI video standards. The equalizer meets all pathological requirements for SMPTE 292M as defined by RP198. and for SMPTE 259M as defined The CYV15G0102EQ equalizer has variable gain, multiple equalization stages, that reverse the effects of the cable. This equalization is achieved by separate regulation of the lower and higher frequency components in the signal to give a clean eye. The CYV15G0102EQ has DC restoration for compensating the DC content of the SMPTE pathological patterns. Document #: 001-04205 Rev. *A SDI, SDI CYV15G0102EQ accepts single-ended or differential serial video data streams over 75Ω coaxial cable. It is recommended to AC-couple the SDI, SDI inputs as they are internally biased to 1.2V. Page 3 of 10 PRELIMINARY SDO, SDO The CYV15G0102EQ has differential serial output interface drivers that use current mode logic [CML] drivers to provide source matching for the transmission line. These outputs can be either AC coupled or DC coupled to HOTLink II SerDes device. CLI Cable Length Indicator (CLI) is an analog output that gives an output voltage proportional to the cable length being equalized. CLI gives an approximation of the length of cable at the differential serial inputs (SDI, SDI). CLI works at high definition (HD) data rates as well as standard definition (SD) data rates. The graph in Figure 2 illustrates the CLI output voltage at various Belden 1694A cable lengths. With an increase in cable length, CLI output voltage decreases. CYV15G0102EQ equalizer’s input, or it controls the muting of the equalizer’s output. The (CD/MUTE) operates for both HD and SD data rates. If CD/MUTE is used as an output, and the incoming data stream is not present, the voltage at the CD/MUTE output will be greater than 3.0V. If CD/MUTE is used as an output, and the incoming data stream is present, then the voltage at the CD/MUTE output will be less than 0.8V. If CD/MUTE is used as an input, and tied to ground, the equalizer serial outputs are not muted and the MCLADJ setting is overwritten. If the CD/MUTE is used as an input and is tied to VCC, then the equalizer serial outputs are muted and the MCLADJ setting is overwritten. When an invalid signal or a signal transmitted with a launch amplitude of less than 500 mV at HD data-rates is received, the equalizer’s serial outputs are muted and the MCLADJ setting is overwritten. MCLADJ BYPASS Maximum Cable Length Adjust (MCLADJ) sets the approximate maximum amount of cable to be equalized. When the maximum cable length set by MCLADJ is reached, the outputs are muted. MCLADJ works at SD as well HD data rates. The CYV15G0102EQ has a bypass mode that allows the user to bypass the equalizer’s equalization and DC restoration functions. When the Bypass mode is tied to VCC, the signal presented at the equalizer’s differential serial inputs (SDI, SDI) is routed to the equalizer’s differential serial outputs (SDO, SDO) without performing equalization. If the MCLADJ voltage is greater than the CLI output voltage, the equalizer serial differential outputs (SDO, SDO) are muted. If the MCLADJ voltage is less than CLI voltage, then the equalizer’s differential serial outputs (SDO, SDO) are not muted and the incoming data stream is equalized. The graph in Figure 1 illustrates the voltage needed at MCLADJ input, to equalize various Belden 1694A cable lengths for SD and HD data rates. The MCLADJ pin can be left unconnected in applications that do not require muting of the outputs. CD/MUTE When BYPASS is tied to GND, the incoming video data stream is equalized and presented at the equalizer‘s differential serial outputs (SDO, SDO). In equalizer bypass mode, CD/MUTE is not functional. AGC A capacitor of 1 µF should be placed between the AGC± pins of the CYV15G0102EQ equalizer. Carrier Detect/MUTE (CD/MUTE) is a bidirectional pin that provides an indication of the signal being present at the Document #: 001-04205 Rev. *A Page 4 of 10 PRELIMINARY CYV15G0102EQ Maximum Ratings Power-up Requirements Above which the useful life may be impaired. User guidelines only, not tested The CYV15G0102EQ contains one power-supply. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Storage Temperature .................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential ............... –0.5V to +3.8V Range Ambient Temperature VCC DC Voltage Applied to Outputs in High-Z State .......................................–0.5V to VCC + 0.5V Commercial 0°C to +40°C +3.3V ±5% DC Input Voltage......................................–0.5V to VCC+0.5V Electro Static Discharge (ESD) HBM .......................> 2000 V (per JEDEC EIA/JESD-A114A) Latch-Up Current ....................................................> 200 mA DC Electrical Characteristics Parameter Description Voltage[1] VCC Supply PD Power Consumption[2] IS Supply Current[1] VCMOUT VCMIN – – Test Conditions Min. Typ. Max. – – Unit 3.135 3.3 3.465 V 125 160 190 mW – 38 48 58 mA Load = 50Ω – VCC – ∆VSDO/2 – V Voltage[1] – 1 1.24 1.4 V Input Common Mode Voltage[1] [Bypass = Low] – 0 1.24 2.9 V CLI DC Voltage (0m)[1] – 2.5 2.65 2.9 V – 1.6 1.9 2.3 V Output Common Mode Input Common Mode [Bypass = High] CLI DC Voltage (no signal)[1] – Floating MCLADJ DC – MCLADJ Range[1] VCD/MUTE(OH) CD/MUTE Output Voltage[1] Voltage[1] Voltage[1] VCD/MUTE(OL) – 1.2 1.3 1.4 V – 0.55 0.72 1.02 V Carrier Not Present 3.0 – – V Carrier Present – – 0.8 V VCD/MUTE CD/MUTE Input Voltage Required to Force Outputs to Mute[1] Min. to Mute 2.2 – – V VCD/MUTE CD/MUTE Input Voltage Required to Force Active[1] Max. to Activate – – 1.2 V Notes: 1. Production test. 2. Calculated results from production test. Document #: 001-04205 Rev. *A Page 5 of 10 PRELIMINARY CYV15G0102EQ AC Electrical Characteristics Parameter Description Test Conditions Min. [1] Typ. Max. Unit – Serial Input Data Rate – 143 – 1485 Mbps VSDI Input Voltage Swing Single ended, at the transmitter, HD data rate 500 800[1] 1200 mV VSDI Input Voltage Swing Single ended, at the transmitter, SD data rate 620 800[1] 1200 mV ∆VSDO Output Voltage Swing[1] Differentialp-p,50Ω load 650 800 900 mV – Maximum Equalized Cable Length[1] 270 Mbps, Belden 1694A, 800 mV transmit amplitude, equalizer pathological pattern, 0.2 UI equalizer output jitter – 400 – m 1.485 Gbps, Belden 1694A, 800 mV transmit amplitude, equalizer pathological pattern, 0.3 UI equalizer output jitter – 200 – m 20% - 80% – Output Rise/Fall Time[3, 4] – Mismatch in Rise/Fall time[3, 4] distortion[3, 4] – Duty cycle – Overshoot[3, 4] Loss[3] 80 120 220 ps – – – 30 ps – – – 30 ps – – – 10 % – – Input Return 15 – – dB – Input Resistance[3, 4] Single ended – 2.5 – kΩ – Input Capacitance[3, 4] Single ended – 1 – pF – Output Resistance[3, 4] Single ended – 50 – Ω Notes: 3. Not tested. Based on characterization. 4. Not tested. Guaranteed by design simulations. Document #: 001-04205 Rev. *A Page 6 of 10 PRELIMINARY CYV15G0102EQ Typical Performance Graphs (Unless Otherwise mentioned, VCC = 3.3V, TA = 25°C) 2.7 2.6 2.5 VOLTAGE (V) 2.4 2.3 2.2 2.1 2 1.9 1.8 1.7 0 50 100 150 200 250 300 350 400 CABLE LENGTH (m) Figure 1. MCLADJ Input Voltage Vs. Belden 1694A Cable Length at SD-SDI and HD-SDI Data Rates 2.7 2.6 2.5 VOLTAGE (V) 2.4 2.3 2.2 2.1 2 1.9 1.8 1.7 0 50 100 150 200 250 300 350 400 CABLE LENGTH (m) Figure 2. CLI Output Voltage Vs. Belden 1694A Cable Length at SD-SDI and HD-SDI Data Rates Document #: 001-04205 Rev. *A Page 7 of 10 PRELIMINARY CYV15G0102EQ Typical Application Circuit CL I +3.3V CD/ MUTE +3.3V LFI RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 RXOP RXST2 RXST1 RXST0 RXCLK+ RXCLK− RXCLKC+ RXLE SDASEL LPEN INSEL IN1+ IN1− C12 0. 01 µF C10 0.01 µF 16 CD/ MUTE CLI 15 VCC VCC 14 VEE VEE 13 SDO SDI 12 SDO SDI 11 VEE VEE 10 MCLADJAGC+ 9 BYPASSAGC− Z0 2 Z0 R18 Z0 FRAMCHAR RFEN RFMODE DECMODE RXCKSEL RXMODE RXRATE 1 2 3 4 5 6 7 8 CYV15G0102EQ 1 µF R16 C15 BNC JACK 75Ω 75 Ω 1 µF L2 C16 6.4 n H + 1 µF 37.4 Ω R15 R14 75Ω C11 CYV15G0101DXB MCL ADJ Figure 3. Interfacing CYV15G0102EQ to the HOTLink II SerDes Ordering Information Ordering Code Package Name CYV15G0102EQ-SXC SZ16.15 Document #: 001-04205 Rev. *A Package Type Pb-Free16-lead 150-mil SOIC Operating Range 0 to 40°C Page 8 of 10 PRELIMINARY CYV15G0102EQ Package Dimensions 16-Lead (150-Mil) SOIC S16.15 0).)$ $)-%.3)/.3).).#(%3;--=-). -!8 2%&%2%.#%*%$%#-3 0!#+!'%7%)'(4GMS ;= ;= ;= ;= 0!24 334!.$!2$0+' 3:,%!$&2%%0+' ;= ;= ;= ;= 3%!4).'0,!.% 8² ;= ;= ;= ;= "3# ;= ;= ²^² ;= ;= ;= ;= ;= ;= 51-85068-*B HOTLink II is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-04205 Rev. *A Page 9 of 10 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY CYV15G0102EQ Document History Page Document Title: CYV15G0102EQ Multi-Rate Cable Equalizer Document Number: 001-04205 REV. ECN NO. ISSUE DATE ORIG. OF CHANGE ** 389196 SEE ECN BCD New Preliminary Data Sheet *A 394763 SEE ECN BCD Updated Preliminary Data Sheet for release to the internet Document #: 001-04205 Rev. *A DESCRIPTION OF CHANGE Page 10 of 10