CYPRESS CY14V104LA

CY14V104LA
CY14V104NA
4-Mbit (512 K × 8 / 256 K × 16) nvSRAM
4-Mbit (512 K × 8 / 256 K × 16) nvSRAM
Features
Functional Description
■
25 ns and 45 ns access times
■
Internally organized as 512 K × 8 (CY14V104LA) or 256 K × 16
(CY14V104NA)
■
Hands off automatic STORE on power-down with only a small
capacitor
■
STORE to QuantumTrap non-volatile elements initiated by
software, device pin, or AutoStore on power-down
■
RECALL to SRAM initiated by software or power-up
■
Infinite read, write, and recall cycles
■
1-million STORE cycles to QuantumTrap
■
20 year data retention
■
Core VCC = 3.0 V to 3.6 V; IO VCCQ = 1.65 V to 1.95 V
■
Industrial temperature
■
48-ball fine-pitch ball grid array (FBGA) package
■
Pb-free and restriction of hazardous substances (RoHS)
compliance
The Cypress CY14V104LA/CY14V104NA is a fast static RAM,
with a non-volatile element in each memory cell. The memory is
organized as 512 K bytes of 8 bits each or 256 K words of 16 bits
each. The embedded non-volatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
non-volatile memory. The SRAM provides infinite read and write
cycles, while independent non-volatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
non-volatile elements (the STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM (the RECALL operation) from the non-volatile
memory. Both the STORE and RECALL operations are also
available under software control.
Logic Block Diagram [1, 2, 3]
VCC VCCQ VCAP
Quatrum Trap
2048 X 2048
A0
A1
A2
A3
A4
A5
A6
A7
A8
A17
A18
R
O
W
POWER
CONTROL
STORE
RECALL
D
E
C
O
D
E
R
STORE/RECALL
CONTROL
STATIC RAM
ARRAY
2048 X 2048
SOFTWARE
DETECT
HSB
A14 - A2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
I
N
P
U
T
B
U
F
F
E
R
S
COLUMN I/O
OE
COLUMN DEC
WE
DQ12
DQ13
CE
DQ14
BLE
A9 A10 A11 A12 A13 A14 A15 A16
DQ15
BHE
Notes
1. Address A0–A18 for × 8 configuration and Address A0–A17 for × 16 configuration.
2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-53954 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 6, 2011
[+] Feedback
CY14V104LA
CY14V104NA
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Read ....................................................................... 4
SRAM Write ....................................................................... 4
AutoStore Operation ........................................................ 4
Hardware STORE Operation ............................................ 4
Hardware RECALL (Power-Up) ....................................... 5
Software STORE ............................................................... 5
Software RECALL ............................................................. 5
Preventing AutoStore ....................................................... 6
Data Protection ................................................................. 6
Noise Considerations ....................................................... 6
Best Practices ................................................................... 7
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
DC Electrical Characteristics .......................................... 8
Data Retention and Endurance ....................................... 9
Capacitance ...................................................................... 9
Thermal Resistance .......................................................... 9
AC Test Loads ................................................................ 10
AC Test Conditions ........................................................ 10
Document #: 001-53954 Rev. *F
AC Switching Characteristics ....................................... 11
SRAM Read Cycle .................................................... 11
SRAM Write Cycle ..................................................... 11
Switching Waveforms .................................................... 11
AutoStore/Power-Up RECALL ....................................... 14
Switching Waveforms .................................................... 14
Software Controlled STORE/RECALL Cycle ................ 15
Switching Waveforms .................................................... 15
Hardware STORE Cycle ................................................. 16
Switching Waveforms .................................................... 16
Truth Table For SRAM Operations ................................ 17
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC Solutions ......................................................... 22
Page 2 of 22
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CY14V104LA
CY14V104NA
Pinouts
Figure 1. Pin Diagram – 48-ball FBGA
(× 8)
Top View
(not to scale)
(× 16)
Top View
(not to scale)
1
2
3
4
5
6
A
BLE
OE
A0
A1
A2
VCC
A
NC
B
DQ8
BHE
A3
A4
CE
DQ0
B
DQ4
C
DQ9 DQ10
A5
A6
DQ1
DQ2
C
A7
DQ5 VCCQ
D
VSS
A17
A7
DQ3 VCCQ
VCAP
A16
DQ6
VSS
E
VCCQ DQ12
VCAP
A16
DQ4
VSS
E
NC
A14
A15
NC
DQ7
F
DQ14 DQ13
A14
A15
DQ5
DQ6
F
NC
HSB
A12
A13
WE
NC
G
DQ15 HSB
A12
A13
WE
DQ7
G
A18
A8
A9
A10
A11
H
NC
A9
A10
A11
NC
H
2
3
4
5
6
NC
OE
A0
A1
A2
VCC
NC
NC
A3
A4
CE
DQ0
NC
A5
A6
NC
VSS
DQ1
A17
1
VCCQ DQ2
DQ3
NC
[4]
[4]
DQ11
A8
D
Pin Definitions
Pin Name
A0–A18
I/O Type
Input
A0–A17
Description
Address Inputs Used to Select One of the 524,288 bytes of the nvSRAM for × 8 Configuration.
Address Inputs Used to Select One of the 262,144 words of the nvSRAM for × 16 Configuration.
DQ0–DQ7 Input/output
DQ0–DQ15
Bidirectional Data I/O Lines for × 8 Configuration. Used as input or output lines depending on operation.
Bidirectional Data I/O Lines for × 16 Configuration. Used as input or output lines depending on operation.
WE
Input
Write Enable Input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
CE
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles.
I/O pins are tri-stated on deasserting OE HIGH.
BHE
Input
Byte High Enable, Active LOW. Controls DQ15–DQ8.
BLE
VSS
Input
Byte Low Enable, Active LOW. Controls DQ7–DQ0.
Ground
Ground for the Device. Must be connected to the ground of the system.
VCC
Power supply Power Supply Inputs to the Core of the Device.
VCCQ
Power supply Power Supply Inputs for the Inputs and Outputs of the Device.
HSB
Input/output
VCAP
Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
non-volatile elements.
NC
No Connect
Hardware Store Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a non-volatile STORE operation. After each Hardware
and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high
current and then a weak internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection
optional).
No Connect. This pin is not connected to the die.
Note
4. Address expansion for 8-Mbit. NC pin not connected to die.
Document #: 001-53954 Rev. *F
Page 3 of 22
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CY14V104LA
CY14V104NA
The CY14V104LA/CY14V104NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
a SRAM memory cell and a non-volatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the non-volatile cell (the STORE
operation), or from the non-volatile cell to the SRAM (the
RECALL operation). Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations, SRAM read and write operations are inhibited. The
CY14V104LA/CY14V104NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the non-volatile cells and up to 1 million STORE
operations. See Truth Table For SRAM Operations on page 17
for a complete description of read and write modes.
SRAM Read
The CY14V104LA/CY14V104NA performs a read cycle when
CE and OE are LOW and WE and HSB are HIGH. The address
specified on pins A0–18 or A0–17 determines which of the 524,288
data bytes or 262,144 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
an address transition, the outputs are valid after a delay of tAA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at tACE or at tDOE, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
tAA access time without the need for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
on VCAP pin, the device attempts an AutoStore operation without
sufficient charge to complete the Store. This may corrupt the data
stored in nvSRAM.
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to DC Electrical
Characteristics on page 8 for the size of VCAP. The voltage on
the VCAP pin is driven to VCC by a regulator on the chip. A pull-up
should be placed on WE to hold it inactive during power-up. This
pull-up is effective only if the WE signal is tristate during
power-up. Many MPUs tristate their controls on power-up. This
should be verified when using the pull-up. When the nvSRAM
comes out of power-on-recall, the MPU must be active or the WE
held inactive until the MPU comes out of reset.
To reduce unnecessary non-volatile stores, AutoStore and
hardware store operations are ignored unless at least one write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
Figure 2. AutoStore Mode
VCCQ
VCC
0.1 uF
0.1 uF
10 kOhm
Device Operation
VCCQ
VCC
WE
VCAP
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins DQ0–15
are written into the memory if the data is valid tSD before the end
of a WE controlled write or before the end of an CE controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. It is recommended that
OE be kept HIGH during the entire write cycle to avoid data bus
contention on common I/O lines. If OE is left LOW, internal
circuitry turns off the output buffers tHZWE after WE goes LOW.
AutoStore Operation
The CY14V104LA/CY14V104NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
Store activated by HSB; Software Store activated by an address
sequence; AutoStore on device power-down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14V104LA/CY14V104NA.
During a normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a single STORE operation.
If the voltage on the VCC pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from VCC. A STORE
operation is initiated with power provided by the VCAP capacitor.
Note If a capacitor is not connected to VCAP pin, AutoStore
must be disabled using the soft sequence specified in Preventing
AutoStore on page 6. If AutoStore is enabled without a capacitor
Document #: 001-53954 Rev. *F
VCAP
VSS
Hardware STORE Operation
The CY14V104LA/CY14V104NA provides the HSB pin to control
and acknowledge the STORE operations. Use the HSB pin to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14V104LA/CY14V104NA conditionally initiates a
STORE operation after tDELAY. An actual STORE cycle only
begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver (internal 100 k weak pull-up resistor) that is
internally driven LOW to indicate a busy condition when the
STORE (initiated by any means) is in progress.
Note After each Hardware and Software STORE operation
HSB is driven HIGH for a short time (tHHHD) with standard output
high current and then remains HIGH by internal 100 k pull-up
resistor.
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14V104LA/CY14V104NA. But any SRAM read
and write cycles are inhibited until HSB is returned HIGH by MPU
or other external source.
Page 4 of 22
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CY14V104LA
CY14V104NA
During any STORE operation, regardless of how it is initiated,
the CY14V104LA/CY14V104NA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion
of
the
STORE
operation,
the
CY14V104LA/CY14V104NA remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
Hardware RECALL (Power-Up)
During power-up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven LOW by the HSB driver.
Software STORE
Data is transferred from SRAM to the non-volatile memory by a
software address sequence. The CY14V104LA/CY14V104NA
software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
non-volatile data is first performed, followed by a program of the
non-volatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following read
sequence must be performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from non-volatile memory to the SRAM by a
software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the non-volatile information is transferred into
the SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the non-volatile elements.
Table 1. Mode Selection
CE
WE
OE
BHE, BLE[5]
A15–A0[6]
Mode
I/O
Power
H
X
X
X
X
Not Selected
Output High Z
Standby
L
H
L
L
X
Read SRAM
Output Data
Active
L
L
X
L
X
Write SRAM
Input Data
Active
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[7]
Notes
5. BHE and BLE are applicable for × 16 configuration only.
6. While there are 19 address lines on the CY14V104LA (18 address lines on the CY14V104NA), only the 13 address lines (A14–A2) are used to control software
modes. Rest of the address lines are don’t care.
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
Document #: 001-53954 Rev. *F
Page 5 of 22
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CY14V104LA
CY14V104NA
Table 1. Mode Selection (continued)
CE
WE
OE
BHE, BLE[5]
A15–A0[6]
Mode
I/O
Power
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[8]
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Non-volatile
Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active ICC2[8]
L
H
L
X
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Non-volatile
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active[8]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) must be issued to save
the AutoStore state through subsequent power-down cycles.
The part comes from the factory with AutoStore enabled.
Data Protection
The CY14V104LA/CY14V104NA protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected
when
VCC
<
VSWITCH.
If
the
CY14V104LA/CY14V104NA is in a write mode (both CE and WE
are LOW) at power-up, after a RECALL or STORE, the write is
inhibited until the SRAM is enabled after tLZHSB (HSB to output
active). When VCCQ < VIODIS, I/Os are disabled (no STORE
takes place). This protects against inadvertent writes during
brown out conditions on VCCQ supply.
Noise Considerations
Refer to Cypress application note, AN1064.
Note
8. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a non-volatile cycle.
Document #: 001-53954 Rev. *F
Page 6 of 22
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CY14V104LA
CY14V104NA
Best Practices
nvSRAM products have been used effectively for over 26 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The non-volatile cells in this nvSRAM product are delivered
from Cypress with 0x00 written in all cells. Incoming inspection
routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
Document #: 001-53954 Rev. *F
■
Power-up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, autostore enabled). While
the nvSRAM is shipped in a preset state, best practice is to
again rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently such as
program bugs and incoming inspection routines.
■
The VCAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum VCAP value because
the nvSRAM internal algorithm calculates VCAP charge and
discharge time based on this max VCAP value. Customers that
want to use a larger VCAP value to make sure there is extra store
charge and store time should discuss their VCAP size selection
with Cypress to understand any impact on the VCAP voltage level
at the end of a tRECALL period.
Page 7 of 22
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CY14V104LA
CY14V104NA
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Transient voltage (< 20 ns) on
any pin to ground potential ............... –2.0 V to VCCQ + 2.0 V
Storage temperature ................................–65 C to +150 C
Package power dissipation
capability (TA = 25 °C) ..................................................1.0 W
Maximum accumulated storage time
At 150 C ambient temperature ....................... 1000 h
At 85 C ambient temperature ......................20 Years
Ambient temperature with
power applied ...........................................–55 C to +150 C
Supply voltage on VCC relative to VSS .......... –0.5 V to 4.1 V
Supply voltage on VCCQ relative to VSS ...... –0.5 V to 2.45 V
Voltage applied to outputs
in High Z state .................................. –0.5 V to VCCQ + 0.5 V
Input voltage ..................................... –0.5 V to VCCQ + 0.5 V
Surface mount Pb soldering
temperature (3 seconds) ..........................................+260 C
DC output current (1 output at a time, 1s duration) .....15 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) ......................... > 2001 V
Latch up current .................................................... > 140 mA
Operating Range
Range Ambient Temperature
Industrial
–40 C to +85 C
VCC
VCCQ
3.0 V – 3.6 V 1.65 V – 1.95 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
VCC
Test Conditions
Min
Typ [9]
Max
Unit
3.0
3.3
3.6
V
1.65
1.8
1.95
V
–
–
70
mA
–
–
52
mA
–
–
15
mA
Power supply voltage
–
ICC1
Average VCC current
ICCQ1
Average VCCQ current
tRC = 25 ns
tRC = 45 ns
Values obtained without output loads
(IOUT = 0 mA)
–
–
10
mA
ICC2
Average VCC current during
STORE
All inputs don’t care, VCC = Max
Average current for duration tSTORE
–
–
10
mA
ICC3
Average VCC current at
tRC= 200 ns, VCC(Typ), 25 °C
–
35
–
mA
ICCQ3
Average VCCQ current at
tRC= 200 ns, VCCQ(Typ), 25 °C
All inputs cycling at CMOS levels.
Values obtained without output loads
(IOUT = 0 mA).
–
5
–
mA
ICC4
Average VCAP current during
AutoStore cycle
All inputs don’t care. Average current
for duration tSTORE
–
–
8
mA
ISB
VCC standby current
CE > (VCC – 0.2 V).
VIN < 0.2 V or > (VCC – 0.2 V).
Standby current level after
non-volatile cycle is complete. Inputs
are static. f = 0 MHz.
–
–
8
mA
IIX[10]
Input leakage current
(except HSB)
VCCQ = Max, VSS < VIN < VCCQ
–1
–
+1
A
Input leakage current (for HSB)
VCCQ = Max, VSS < VIN < VCCQ
VCCQ
–100
–
+1
A
IOZ
Off-state output leakage current VCCQ = Max, VSS < VOUT < VCCQ,
CE or OE > VIH or BHE/BLE > VIH or
WE < VIL
–1
–
+1
A
VCAP[11]
Storage capacitor
61
68
180
F
Between VCAP pin and VSS, 5 V rated
Notes
9. Typical values are at 25 °C, VCC = VCC(Typ) and VCCQ = VCCQ(Typ). Not 100% tested.
10. The HSB pin has IOUT = -4 µA for VOH of 1.07 V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
11. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor
on VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore
it is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options.
Document #: 001-53954 Rev. *F
Page 8 of 22
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CY14V104LA
CY14V104NA
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
Description
Test Conditions
VIH
Input HIGH voltage
–
VIL
Input LOW voltage
–
VOH
Output HIGH voltage
IOUT = –1 mA
VOL
Output LOW voltage
IOUT = 2 mA
Min
Typ [9]
Max
Unit
0.7 × VCCQ
–
VCCQ + 0.3
V
– 0.3
–
0.3 × VCCQ
V
VCCQ – 0.45
–
–
V
–
0.45
V
Data Retention and Endurance
Over the Operating Range
Parameter
Description
DATAR
Data retention
NVC
Non-volatile STORE operation
Min
Unit
20
Years
1,000
K
Max
Unit
7
pF
Input capacitance (for BLE, BHE
and HSB)
8
pF
Output capacitance (except HSB)
7
pF
Output capacitance (for HSB)
8
pF
Capacitance
Parameter[12]
CIN
COUT
Description
Input capacitance (except BLE,
BHE and HSB)
Test Conditions
TA = 25 C, f = 1 MHz, VCC = VCC (Typ), VCCQ = VCCQ (Typ)
Thermal Resistance
In the following table, the thermal resistance parameters are listed.
Parameter[12]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance
with EIA/JESD51.
48-ball FBGA
Unit
46.09
C/W
7.84
C/W
Note
12. These parameters are guaranteed by design but not tested.
Document #: 001-53954 Rev. *F
Page 9 of 22
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CY14V104LA
CY14V104NA
AC Test Loads
Figure 3. AC Test Loads
450 
1.8 V
450 
1.8 V
R1
for tri-state specs
R1
Output
Output
30 pF
R2
450 
5 pF
R2
450 
AC Test Conditions
Input pulse levels ................................................0 V to 1.8 V
Input rise and fall times (10%–90%) ......................... <1.8 ns
Input and output timing reference levels ....................... 0.9 V
Document #: 001-53954 Rev. *F
Page 10 of 22
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CY14V104LA
CY14V104NA
AC Switching Characteristics
Over the Operating Range
Parameters [13]
Cypress
Alt Parameter
Parameter
25 ns
Description
45 ns
Unit
Min
Max
Min
Max
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
Byte enable to data valid
Byte enable to output active
Byte disable to output inactive
–
25
–
–
3
3
–
0
–
0
–
–
0
–
25
–
25
12
–
–
10
–
10
–
25
12
–
10
–
45
–
–
3
3
–
0
–
0
–
–
0
–
45
–
45
20
–
–
15
–
15
–
45
20
–
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
Byte enable to end of write
25
20
20
10
0
20
0
0
–
3
20
–
–
–
–
–
–
–
–
10
–
–
45
30
30
15
0
30
0
0
–
3
30
–
–
–
–
–
–
–
–
15
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SRAM Read Cycle
tACE
tRC[14]
tAA[15]
tDOE
tOHA[15]
tLZCE[16, 17]
tHZCE[16, 17]
tLZOE[16, 17]
tHZOE[16, 17]
tPU[16]
tPD[16]
tDBE
tLZBE[16]
tHZBE[16]
tACS
tRC
tAA
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
–
–
–
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tHD
tAW
tSA
tHA
tHZWE[16, 17, 18]
tLZWE[16, 17]
tBW
tWC
tWP
tCW
tDW
tDH
tAW
tAS
tWR
tWZ
tOW
–
Switching Waveforms
Figure 4. SRAM Read Cycle #1 (Address Controlled) [14, 15, 19]
tRC
Address
Address Valid
tAA
Data Output
Previous Data Valid
Output Data Valid
tOHA
Notes
13. Test conditions assume signal transition time of 1.8 ns or less, timing reference levels of VCCQ/2, input pulse levels of 0 to VCC Q(typ), and output loading of the specified
IOL/IOH and load capacitance shown in Figure 3 on page 10.
14. WE must be HIGH during SRAM read cycles.
15. Device is continuously selected with CE, OE and BHE / BLE LOW.
16. These parameters are guaranteed by design but not tested.
17. Measured ±200 mV from steady state output voltage.
18. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
19. HSB must remain HIGH during read and write cycles.
Document #: 001-53954 Rev. *F
Page 11 of 22
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CY14V104LA
CY14V104NA
Switching Waveforms (continued)
Figure 5. SRAM Read Cycle #2 (CE and OE Controlled) [20, 21, 22]
Address
Address Valid
tRC
tHZCE
tACE
CE
tAA
tLZCE
tHZOE
tDOE
OE
tHZBE
tLZOE
tDBE
BHE, BLE
tLZBE
Data Output
High Impedance
Output Data Valid
tPU
ICC
tPD
Active
Standby
Figure 6. SRAM Write Cycle #1 (WE Controlled) [22, 23, 24, 25]
tWC
Address
Address Valid
tSCE
tHA
CE
tBW
BHE, BLE
tAW
tPWE
WE
tSA
tSD
Data Input
Input Data Valid
tHZWE
Data Output
tHD
Previous Data
tLZWE
High Impedance
Notes
20. Typical values are at 25 °C, VCC = VCC(Typ) and VCCQ = VCCQ(Typ). Not 100% tested.
21. WE must be HIGH during SRAM read cycles.
22. HSB must remain HIGH during read and write cycles.
23. BHE and BLE are applicable for x16 configuration only.
24. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
25. CE or WE must be >VIH during address transitions.
Document #: 001-53954 Rev. *F
Page 12 of 22
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CY14V104LA
CY14V104NA
Switching Waveforms (continued)
Figure 7. SRAM Write Cycle #2 (CE Controlled) [26, 27, 28, 29]
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tBW
BHE, BLE
tPWE
WE
tHD
tSD
Input Data Valid
Data Input
High Impedance
Data Output
Figure 8. SRAM Write Cycle #3 (BHE and BLE Controlled) [26, 27, 28, 29]
tWC
Address
Address Valid
tSCE
CE
tSA
tHA
tBW
BHE, BLE
tAW
tPWE
WE
tSD
Data Input
tHD
Input Data Valid
High Impedance
Data Output
Notes
26. HSB must remain HIGH during read and write cycles.
27. BHE and BLE are applicable for × 16 configuration only.
28. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
29. CE or WE must be >VIH during address transitions.
Document #: 001-53954 Rev. *F
Page 13 of 22
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CY14V104LA
CY14V104NA
AutoStore/Power-Up RECALL
Over the Operating Range
Parameter
Description
tHRECALL [30]
tSTORE [31]
tDELAY [32]
VSWITCH
VIODIS[33]
tVCCRISE[36]
VHDIS[36]
tLZHSB[36]
tHHHD[36]
Power-Up RECALL duration
STORE cycle duration
Time allowed to complete SRAM write cycle
Low voltage trigger level for VCC
I/O disable voltage on VCCQ
VCC rise time
HSB output disable voltage on VCC
HSB to output active time
HSB high active time
CY14V104LA/CY14V104NA
Min
Max
–
20
–
8
–
25
–
2.90
–
1.50
150
–
–
1.9
–
5
–
500
Unit
ms
ms
ns
V
V
s
V
s
ns
Switching Waveforms
Figure 9. AutoStore or Power-Up RECALL [34]
VCC
VSWITCH
VHDIS
VCCQ
VIODIS
32
t VCCRISE
Note
tHHHD
HSB OUT
VCCQ
Note 32
tSTORE
t HHHD
tSTORE
Note
35
35
Note
tDELAY
tLZHSB
AutoStore
t LZHSB
tDELAY
POWERUP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write
VCC
BROWN
OUT
AutoStore
Read POWER
POWER-UP Read
&
DOWN
&
RECALL
Write V
Write AutoStore
CCQ
BROWN
OUT
I/O Disable
Notes
30. tHRECALL starts from the time VCC rises above VSWITCH.
31. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware Store takes place.
32. On a Hardware Store and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
33. HSB will not be defined below VIODIS voltage.
34. Read and write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
35. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
36. These parameters are guaranteed by design but not tested.
Document #: 001-53954 Rev. *F
Page 14 of 22
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CY14V104LA
CY14V104NA
Software Controlled STORE/RECALL Cycle
Over the Operating Range
Parameters [37, 38]
tRC
tSA
tCW
tHA
tRECALL
25 ns
Description
Min
25
0
20
0
–
STORE/RECALL initiation cycle time
Address setup time
Clock pulse width
Address hold time
RECALL duration
45 ns
Max
–
–
–
–
200
Min
45
0
30
0
–
Max
–
–
–
–
200
Unit
ns
ns
ns
ns
s
Switching Waveforms
Figure 10. CE and OE Controlled Software STORE/RECALL Cycle [38]
tRC
Address
tRC
Address #1
tSA
Address #6
tCW
tCW
CE
tHA
tSA
tHA
tHA
tHA
OE
tHHHD
HSB (STORE only)
tHZCE
tLZCE
t DELAY
39
Note
tLZHSB
High Impedance
tSTORE/tRECALL
DQ (DATA)
RWI
Figure 11. AutoStore Enable/Disable Cycle
Address
tSA
CE
tRC
tRC
Address #1
Address #6
tCW
tCW
tHA
tSA
tHA
tHA
tHA
OE
tLZCE
tHZCE
tSS
39
Note
t DELAY
DQ (DATA)
Notes
37. The software sequence is clocked with CE controlled or OE controlled reads.
38. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles.
39. DQ output data at the sixth read may be invalid since the output is disabled at tDELAY time.
Document #: 001-53954 Rev. *F
Page 15 of 22
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CY14V104LA
CY14V104NA
Hardware STORE Cycle
Over the Operating Range
Parameters
CY14V104LA/CY14V104NA
Description
Min
Max
Unit
tDHSB
HSB to output active time when write latch not set
–
25
ns
tPHSB
Hardware STORE pulse width
15
–
ns
Soft sequence processing time
–
100
s
tSS
[40, 41]
Switching Waveforms
Figure 12. Hardware STORE Cycle [42]
Write latch set
tPHSB
HSB (IN)
tSTORE
tHHHD
tDELAY
HSB (OUT)
tLZHSB
DQ (Data Out)
RWI
Write latch not set
tPHSB
HSB pin is driven HIGH to VCC only by Internal
100 kOhm resistor,
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
HSB (IN)
tDELAY
HSB (OUT)
tDHSB
tDHSB
RWI
Figure 13. Soft Sequence Processing [40, 41]
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
tSS
Soft Sequence
Command
Address #1
tSS
Address #6
tCW
CE
VCC
Notes
40. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
41. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
42. If an SRAM write has not taken place since the last non-volatile cycle, no AutoStore or Hardware Store takes place.
Document #: 001-53954 Rev. *F
Page 16 of 22
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CY14V104LA
CY14V104NA
Truth Table For SRAM Operations
HSB should remain HIGH for SRAM Operations.
Table 2. Truth Table for × 8 Configuration
Inputs/Outputs[43]
CE
WE
OE
Mode
Power
H
X
X
High Z
Deselect/Power-down
Standby
L
H
L
Data out (DQ0–DQ7)
Read
Active
L
H
H
High Z
Output disabled
Active
L
L
X
Data in (DQ0–DQ7)
Write
Active
Table 3. Truth Table for × 16 Configuration
CE
WE
OE
BHE[44]
BLE[44]
H
X
X
X
X
L
X
X
H
L
H
L
L
L
H
L
L
H
L
L
H
L
H
L
Inputs/Outputs[43]
Mode
Power
High Z
Deselect/Power-down
Standby
H
High Z
Output disabled
Active
L
Data out (DQ0–DQ15)
Read
Active
H
L
Data out (DQ0–DQ7);
DQ8–DQ15 in High Z
Read
Active
L
H
Data out (DQ8–DQ15);
DQ0–DQ7 in High Z
Read
Active
H
L
L
High Z
Output disabled
Active
H
H
L
High Z
Output disabled
Active
H
H
L
H
High Z
Output disabled
Active
L
L
X
L
L
Data in (DQ0–DQ15)
Write
Active
L
L
X
H
L
Data in (DQ0–DQ7);
DQ8–DQ15 in High Z
Write
Active
L
L
X
L
H
Data in (DQ8–DQ15);
DQ0–DQ7 in High Z
Write
Active
Notes
43. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
44. BHE and BLE are applicable for × 16 configuration only.
Document #: 001-53954 Rev. *F
Page 17 of 22
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CY14V104LA
CY14V104NA
Ordering Information
Speed
(ns)
25
Package
Diagram
Ordering Code
CY14V104LA-BA25XIT
Package Type
Operating Range
51-85128 48-ball FBGA
Industrial
CY14V104LA-BA25XI
CY14V104NA-BA25XIT
CY14V104NA-BA25XI
45
CY14V104LA-BA45XIT
CY14V104LA-BA45XI
CY14V104NA-BA45XIT
CY14V104NA-BA45XI
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 14 V 104 L A - BA 25 X I T
Option:
T - Tape and Reel
Blank - Std.
X - Pb-free
Temperature:
I - Industrial (–40 to 85 °C)
Package:
BA - 48-ball FBGA
Die Revision:
Blank - No Rev
A - 1st Rev
Speed:
25 - 25 ns
45 - 45 ns
Data Bus:
L-×8
N - × 16
Voltage:
V - 3.3 V VCC, 1.8 V VCCQ
Density:
104 - 4 Mb
14 - NVSRAM
Cypress
Document #: 001-53954 Rev. *F
Page 18 of 22
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CY14V104LA
CY14V104NA
Package Diagrams
Figure 14. 48-ball FBGA (6 × 10 × 1.2 mm) BA48B, 51-85128
51-85128 *F
Document #: 001-53954 Rev. *F
Page 19 of 22
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CY14V104LA
CY14V104NA
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
byte high enable
BLE
byte low enable
°C
degree Celsius
CE
CMOS
chip enable
k
kilo ohms
complementary metal oxide semiconductor
MHz
Mega Hertz
EIA
electronic industries alliance
A
micro Amperes
FBGA
fine-pitch ball grid array
mA
milli Amperes
HSB
I/O
hardware store busy
F
micro Farads
input/output
s
micro seconds
nvSRAM
non-volatile static random access memory
ms
milli seconds
OE
RoHS
output enable
ns
nano seconds
restriction of hazardous substances

ohms
SRAM
static random access memory
%
percent
WE
write enable
pF
pico Farads
V
Volts
W
Watts
Document #: 001-53954 Rev. *F
Symbol
Unit of Measure
Page 20 of 22
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CY14V104LA
CY14V104NA
Document History Page
Document Title: CY14V104LA/CY14V104NA, 4-Mbit (512 K × 8 / 256 K × 16) nvSRAM
Document Number: 001-53954
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
2729117
GVCH /
AESA
07/02/2009
New Data Sheet
*A
2826127
GVCH /
AESA
12/11/2009
Removed commercial temperature related specs
Changed part number from CY14A104L/CY14A104N to
CY14V104LA/CY14V104NA
Removed 20 ns Access speed specs
Removed 44/54 TSOP II package related information
Updated STORE cycles to QuantumTrap from 200K to 1 million
Figure 3: Updated Autostore Mode
Page 4: Updated Hardware STORE (HSB) Operation description
Page 5: Updated Software STORE Operation description
Maximum Ratings: Supply Voltage on VCCQ Relative to GND from –0.5V to
2.5V to –0.5V to 2.45V
Added ICCQ1 and ICCQ3 for VCCQ operation
Updated ICC4 test condition
Updated footnote 8
Updated VIH/VIL as 70%/30% of VCCQ
Updated VOH test condition.
Updated Input Rise and Fall Times (10% - 90%) from 3ns to 1.8 ns
Updated footnote 19, 22 and added footnote 20, 25
Updated VIODIS parameter value from 1.6V to 1.5V
Updated Figure 10, 11 and 12
*B
2858300
GVCH
01/19/2010
Changed latch up current from 200 mA to 140 mA.
Changed status from Advance to Preliminary.
Added Contents.
*C
2951754
GVCH /
AESA
06/14/2010
Pin Definitions: Added more clarity on HSB pin operation
Hardware STORE Operation: Added more clarity on HSB pin operation
Table 1: Added more clarity on status of BHE/BLE pin operation
Updated HSB pin operation in Figure 9
Updated footnote 22
*D
3115647
GVCH
12/20/2010
Change datasheet status from “Preliminary” to “Final”
48 FBGA package: 16 Mb address expansion is not supported
Changed ISB and ICC4 value from 5 mA to 8 mA
Changed ICCQ1 value from 25 mA to 15 mA for 25 ns access speed and
15 mA to 10 mA for 45 ns access speed.
Added Acronyms and Units of Measure table
*E
3150253
GVCH
01/21/11
*F
3303659
GVCH
07/06/2011
Document #: 001-53954 Rev. *F
Description of Change
Updated input capacitance for BHE and BLE pin
Updated DC Electrical Characteristics (Added Note 11 and referred the same
note in VCAP parameter).
Updated AC Switching Characteristics (Added Note 13 and referred the same
note in Parameters).
Updated Thermal Resistance (Values of JA for 48-ball FBGA package).
Updated Package Diagrams.
Page 21 of 22
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CY14V104NA
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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© Cypress Semiconductor Corporation, 2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-53954 Rev. *F
Revised July 6, 2011
Page 22 of 22
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