CYPRESS CY14B256L

PRELIMINARY
CY14B256L
256-Kbit (32K x 8) nvSRAM
Features
Functional Description
• 25 ns, 35 ns, and 45 ns access times
• “Hands-off” automatic STORE on power down with only a
small capacitor
• STORE to QuantumTrap™ nonvolatile elements is initiated
by software, device pin, or AutoStore™ on power down
• RECALL to SRAM initiated by software or power up
• Infinite READ, WRITE, and RECALL cycles
• 10 mA typical ICC at 200 ns cycle time
• 200,000 STORE cycles to QuantumTrap
• 20-year data retention @ 55°C
• Single 3V operation with tolerance of +15%, –10%
• Commercial and industrial temperature
• SOIC and SSOP packages
• RoHS compliance
The Cypress CY14B256L is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
infinite read and write cycles while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down.
On power up, data is restored to the SRAM (the RECALL
operation) from the nonvolatile memory. The STORE and
RECALL operations are also available under software control.
Logic Block Diagram
VCC
QuantumTrap
512 X 512
A5
DQ 3
DQ 4
DQ 5
DQ 6
RECALL
STORE/
RECALL
CONTROL
HSB
A13 - A 0
COLUMN IO
INPUT BUFFERS
DQ 2
STATIC RAM
ARRAY
512 X 512
SOFTWARE
DETECT
DQ 0
DQ 1
POWER
CONTROL
STORE
ROW DECODER
A6
A7
A8
A9
A 11
A 12
A 13
A 14
VCAP
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A 10
DQ 7
OE
CE
WE
Cypress Semiconductor Corporation
Document #: 001-06422 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 27, 2007
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PRELIMINARY
CY14B256L
Pin Configurations
V CAP
1
48
V CC
NC
A 14
2
47
NC
3
46
HSB
4
45
5
44
WE
A 13
A 12
A7
A6
6
43
A5
7
42
A9
NC
8
41
NC
A4
9
NC
10
NC
11
NC
V SS
12
NC
14
NC
DQ0
48-SSOP
Top View
40
A 11
39
NC
38
NC
37
NC
36
V SS
35
NC
15
34
NC
16
33
DQ 6
A3
17
32
A2
18
31
OE
A 10
13
(Not To Scale)
A1
19
30
A0
CE
20
29
DQ7
DQ5
DQ1
21
28
DQ2
22
27
DQ4
NC
23
26
DQ3
NC
24
25
V CC
V CAP
Document #: 001-06422 Rev. *E
A8
1
32
V CC
A 14
2
31
HSB
A 12
3
30
WE
A7
4
29
A 13
A6
5
28
A8
A5
6
27
A9
A4
7
26
A 11
A3
8
25
OE
NC
9
A2
10
A1
11
A0
DQ0
DQ1
32 - Lead SOIC
Top View
(Not To Scale)
24
NC
23
A 10
22
CE
12
21
DQ7
13
20
DQ6
14
19
DQ5
DQ2
15
18
DQ4
V SS
16
17
DQ3
Page 2 of 17
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PRELIMINARY
CY14B256L
Pin Definitions
Pin Name
IO Type
A0 – A14
Input
Description
Address inputs used to select one of the 32,768 bytes of the nvSRAM.
DQ0 – DQ7 Input Output Bidirectional data IO lines. Used as input or output lines depending on operation.
NC
No Connect No Connects. This pin is not connected to the die.
WE
Input
Write Enable Input, active LOW. When selected LOW, enables data on the IO pins to be written
to the address location latched by the falling edge of CE.
CE
Input
Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input
Output Enable, active LOW. The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the IO pins to tri-state.
VSS
Ground
VCC
HSB
VCAP
Ground for the device. Must be connected to ground of the system.
Power Supply Power supply inputs to the device.
Input Output Hardware Store Busy. When low this output indicates a Hardware Store is in progress. When pulled
low external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor
keeps this pin high if not connected. (connection optional)
Power Supply AutoStore capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
Device Operation
The CY14B256L nvSRAM is made up of two functional
components paired in the same physical cell. These are a
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM can be transferred to the nonvolatile cell
(the STORE operation), or from the nonvolatile cell to SRAM
(the RECALL operation). This unique architecture allows all
cells to be stored and recalled in parallel. During the STORE
and RECALL operations SRAM READ and WRITE operations
are inhibited. The CY14B256L supports infinite reads and
writes just like a typical SRAM. In addition, it provides infinite
RECALL operations from the nonvolatile cells and up to
200,000 STORE operations.
SRAM READ
The CY14B256L performs a READ cycle whenever CE and
OE are low while WE and HSB are high. The address specified
on pins A0-14 determines which of the 32,768 data bytes will
be accessed. When the READ is initiated by an address
transition, the outputs will be valid after a delay of tAA (READ
cycle 1). If the READ is initiated by CE or OE, the outputs will
be valid at tACE or at tDOE, whichever is later (READ cycle 2).
The data outputs repeatedly responds to address changes
within the tAA access time without the need for transitions on
any control input pins, and remains valid until another address
change or until CE or OE is brought high, or WE or HSB is
brought low.
SRAM WRITE
A WRITE cycle is performed whenever CE and WE are low
and HSB is high. The address inputs must be stable before
entering the WRITE cycle and must remain stable until either
CE or WE goes high at the end of the cycle. The data on the
Document #: 001-06422 Rev. *E
common IO pins IO0–7 will be written into the memory tSD
before the end of a WE controlled WRITE or before the end of
an CE controlled WRITE. Keep the OE HIGH during the entire
WRITE cycle to avoid data bus contention on common IO
lines.
If OE is left low, internal circuitry turns off the output buffers
tHZWE after WE goes low.
AutoStore Operation
The CY14B256L stores data to nvSRAM using one of three
storage operations. These three operations are Hardware
Store, activated by HSB, Software Store, activated by an
address sequence, and AutoStore, on device power down.
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14B256L.
During normal operation, the device draws current from VCC
to charge a capacitor connected to the VCAP pin. This stored
charge will be used by the chip to perform a single STORE
operation. If the voltage on the VCC pin drops below VSWITCH,
the part automatically disconnects the VCAP pin from VCC. A
STORE operation will be initiated with power provided by the
VCAP capacitor.
Figure 1 on page 4 shows the proper connection of the storage
capacitor (VCAP) for automatic store operation. Refer to the DC
Electrical Characteristics on page 7 for the size of VCAP. The
voltage on the VCAP pin is driven to 5V by a charge pump
internal to the chip. A pull up must be placed on WE to hold it
inactive during power up.
To reduce unnecessary nonvolatile stores, AutoStore, and
Hardware Store operations will be ignored unless at least one
WRITE operation has taken place since the most recent
STORE or RECALL cycle. Software initiated STORE cycles
are performed regardless of whether a WRITE operation has
taken place. The HSB signal can be monitored by the system
to detect an AutoStore cycle is in progress.
Page 3 of 17
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PRELIMINARY
Figure 1. AutoStore Mode
V CC
0.1UF
10k Ohm
V CC
V CAP
V CAP
WE
CY14B256L
CE-controlled READ cycles from six specific address locations
in exact order. During the STORE cycle an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. Once a STORE cycle is
initiated, further input and output are disabled until the cycle is
completed.
Because a sequence of READs from specific addresses is
used for STORE initiation, it is important that no other READ
or WRITE accesses intervene in the sequence, or the
sequence will be aborted and no STORE or RECALL takes
place.
To initiate the software STORE cycle, the following READ
sequence must be performed:
1. Read address 0x0E38, valid READ
2. Read address 0x31C7, valid READ
3. Read address 0x03E0, valid READ
4. Read address 0x3C1F, valid READ
5. Read address 0x303F, valid READ
6. Read address 0x0FC0, initiate STORE cycle
Hardware STORE (HSB) Operation
The CY14B256L provides the HSB pin for controlling and
acknowledging the STORE operations. Use the HSB pin to
request a hardware STORE cycle. When the HSB pin is driven
low, the CY14B256L conditionally initiates a STORE operation
after tDELAY. An actual STORE cycle only begins if a WRITE to
the SRAM took place since the last STORE or RECALL cycle.
The HSB pin also acts as an open drain driver that is internally
driven low to indicate a busy condition while the STORE
(initiated by any means) is in progress.
SRAM READ and WRITE operations that are in progress
when HSB is driven low by any means are given time to
complete before the STORE operation is initiated. After HSB
goes low, the CY14B256L continues SRAM operations for
tDELAY. During tDELAY, multiple SRAM READ operations may
take place. If a WRITE is in progress when HSB is pulled low
it will be allowed a time, tDELAY, to complete. However, any
SRAM WRITE cycles requested after HSB goes low will be
inhibited until HSB returns high.
During any STORE operation, regardless of how it was
initiated, the CY14B256L continues to drive the HSB pin low,
releasing it only when the STORE is complete. Upon
completion of the STORE operation the CY14B256L remains
disabled until the HSB pin returns high.
If HSB is not used, it must be left unconnected.
Hardware RECALL (Power Up)
During power up, or after any low power condition
(VCC < VSWITCH), an internal RECALL request will be latched.
When VCC once again exceeds the sense voltage of VSWITCH,
a RECALL cycle will automatically be initiated and takes
tHRECALL to complete.
Software STORE
Data can be transferred from the SRAM to the nonvolatile
memory by a software address sequence. The CY14B256L
software STORE cycle is initiated by executing sequential
Document #: 001-06422 Rev. *E
The software sequence may be clocked with CE-controlled
READs or OE-controlled READs. Once the sixth address in
the sequence has been entered, the STORE cycle
commences, and the chip will be disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence.
It is not necessary that OE be low for the sequence to be valid.
After the tSTORE cycle time has been fulfilled, the SRAM will
again be activated for READ and WRITE operation.
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a
manner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of CE-controlled
READ operations must be performed:
1. Read address 0x0E38, valid READ
2. Read address 0x31C7, valid READ
3. Read address 0x03E0, valid READ
4. Read address 0x3C1F, valid READ
5. Read address 0x303F, valid READ
6. Read address 0x0C63, initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is
transferred into the SRAM cells. After the tRECALL cycle time
the SRAM will once again be ready for READ and WRITE
operations. The RECALL operation does not alter the data in
the nonvolatile elements.
Data Protection
The CY14B256L protects data from corruption during low
voltage conditions by inhibiting all externally initiated STORE
and WRITE operations. The low voltage condition is detected
when VCC < VSWITCH. If the CY14B256L is in a WRITE mode
(both CE and WE low) at power up, after a RECALL, or after
a STORE, the WRITE will be inhibited until a negative
transition on CE or WE is detected. This protects against
inadvertent writes during power up or brownout conditions.
Page 4 of 17
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PRELIMINARY
CY14B256L
Table 1. Mode Selection
CE
WE
OE
A13 – A0
Mode
IO
Power
H
X
X
X
Not Selected
Output High-Z
Standby
L
H
L
X
Read SRAM
Output Data
Active
L
L
X
X
Write SRAM
Input Data
Active
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x03F8
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[1, 2, 3]
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x07F0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active[1, 2, 3]
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Output Data
Output Data
Output Data
Output Data
Output Data
Output High-Z
Active ICC2[1, 2, 3]
L
H
L
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High-Z
Active[1, 2, 3]
Notes
1. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
2. While there are 15 address lines on the CY14B256L, only the lower 14 lines are used to control software modes.
3. IO state depends on the state of OE. The IO table shown assumes OE low.
Document #: 001-06422 Rev. *E
Page 5 of 17
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PRELIMINARY
CY14B256L
Preventing AutoStore
Low Average Active Power
Disable the AutoStore function by initiating an AutoStore
Disable Sequence. A sequence of READ operations is
performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable Sequence, the
following sequence of CE-controlled READ operations must
be performed:
1. Read address 0x0E38 valid READ
2. Read address 0x31C7 valid READ
3. Read address 0x03E0 valid READ
4. Read address 0x3C1F valid READ
5. Read address 0x303F valid READ
6. Read address 0x03F8 AutoStore Disable
CMOS technology provides the CY14B256L the benefit of
drawing less current when it is cycled at times longer than
50 ns. Figure 2 shows the relationship between ICC and
READ/WRITE cycle time. Worst-case current consumption is
shown for commercial temperature range, VCC = 3.45V, and
chip enable at maximum frequency. Only standby current is
drawn when the chip is disabled. The overall average current
drawn by the CY14B256L depends on the following items:
• The duty cycle of chip enable.
• The overall cycle rate for accesses.
• The ratio of READs to WRITEs.
• The operating temperature.
• The VCC level.
• IO loading.
Re-enable the AutoStore by initiating an AutoStore Enable
sequence. A sequence of READ operations is performed in a
manner similar to the software RECALL initiation. To initiate
the AutoStore Enable sequence, the following sequence of
CE-controlled READ operations must be performed:
1. Read address 0x0E38 valid READ
2. Read address 0x31C7 valid READ
3. Read address 0x03E0 valid READ
4. Read address 0x3C1F valid READ
5. Read address 0x303F valid READ
6. Read address 0x07F0 AutoStore Enable
Figure 2. Current vs. Cycle Time
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power down
cycles. The part comes from the factory with AutoStore
enabled.
Noise Considerations
The CY14B256L is a high speed memory and so must have a
high frequency bypass capacitor of approximately 0.1 µF
connected between VCC and VSS, using leads and traces that
are as short as possible. As with all high speed CMOS ICs,
careful routing of power, ground, and signals reduces circuit
noise.
Document #: 001-06422 Rev. *E
Page 6 of 17
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PRELIMINARY
Maximum Ratings
Exceeding maximum ratings may impair the useful life of
device. For user guidelines, not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC Relative to GND.......... –0.5V to 4.1V
Voltage Applied to Outputs
in High-Z State .......................................–0.5V to VCC + 0.5V
Input Voltage .......................................... –0.5V to Vcc + 0.5V
Transient Voltage (< 20 ns) on
Any Pin to Ground Potential...................–2.0V to VCC + 2.0V
CY14B256L
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Surface Mount Pb Soldering
Temperature (3 seconds) .......................................... +260°C
Output Short Circuit Current [4] .................................... 15 mA
Static Discharge Voltage.......................................... > 2001V
(in accordance with MIL-STD-883, method 3015)
Latch Up Current ................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
VCC
0°C to +70°C
2.7V to 3.45V
–40°C to +85°C
2.7V to 3.45V
DC Electrical Characteristics
(over the operating range) VCC = 2.7V to 3.45V [5, 6]
Parameter
ICC1
Description
Test Conditions
Average VCC Current tRC = 25 ns
tRC = 35 ns
tRC = 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads.
IOUT = 0 mA
Min
Commercial
Max
Unit
65
55
50
mA
mA
mA
mA
55
(tRC = 45 ns) mA
mA
Industrial
ICC2
Average VCC Current All inputs do not care, VCC = Max
during STORE
Average current for duration tSTORE
3
mA
ICC3
Average VCC Current WE > (VCC – 0.2). All other inputs cycling.
at tAVAV = 200 ns, 3V, Dependent on output loading and cycle rate.
Values obtained without output loads.
25°C typical
10
mA
ICC4
Average VCAP Current All inputs do not care, VCC = Max
during AutoStore Cycle Average current for duration tSTORE
3
mA
ISB
VCC Standby Current CE > (VCC – 0.2). All others VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
3
mA
IIX
Input Leakage Current VCC = Max, VSS < VIN < VCC
–1
+1
µA
IOZ
Off State Output
Leakage Current
–1
+1
µA
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
VIL
Input LOW Voltage
VSS – 0.5
0.8
V
VOH
Output HIGH Voltage IOUT = – 2 mA
VOL
Output LOW Voltage
IOUT = 4 mA
VCAP
Storage Capacitor
Between VCAP pin and Vss, 5V rated
VCC = Max, VSS < VIN < VCC, CE or OE > VIH
2.4
17
V
0.4
V
120
µF
Notes
4. Outputs shorted for no more than one second. No more than one output shorted at a time.
5. Typical conditions for the active current shown on the front page of the data sheet are average values at 25°C (room temperature), and VCC = 3V. Not 100% tested.
6. The HSB pin has IOUT = –10 µA for VOH of 2.4 V, this parameter is characterized but not tested.
Document #: 001-06422 Rev. *E
Page 7 of 17
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PRELIMINARY
CY14B256L
Capacitance[7]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max
Unit
TA = 25°C, f = 1 MHz, VCC = 0 to 3.0 V
7
pF
7
pF
Thermal Resistance [7]
Parameter
ΘJA
Description
Test Conditions
Thermal Resistance Test conditions follow standard
(junction to ambient) test methods and procedures for
measuring thermal impedance, in
Thermal Resistance accordance with EIA/JESD51.
(junction to case)
ΘJC
32-SOIC
48-SSOP
Unit
TBD
TBD
°C/W
TBD
TBD
°C/W
AC Test Loads
R1 577Ω
R1 577Ω
3.0V
3.0V
FOR TRI-STATE
SPECS
OUTPUT
OUTPUT
30 pF
R2
789Ω
5 pF
R2
789Ω
AC Test Conditions
Input Pulse Levels .................................................. 0 V to 3 V
Input Rise and Fall Times (10% - 90%)........................ <5 ns
Input and Output Timing Reference Levels................... 1.5 V
Note
7. These parameters are guaranteed but not tested.
Document #: 001-06422 Rev. *E
Page 8 of 17
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PRELIMINARY
CY14B256L
AC Switching Characteristics
Parameter
Cypress
Parameter
Alt.
Parameter
25 ns part
Description
Min
Max
35 ns part
45 ns part
Min
Min
Max
Max
Unit
SRAM READ Cycle
tACS
Chip Enable Access Time
tRC
[8]
tRC
Read Cycle Time
tAA
[9]
tAA
Address Access Time
25
35
45
ns
tOE
Output Enable to Data Valid
12
15
20
ns
tACE
tDOE
tOHA [9]
25
25
35
35
45
45
ns
ns
tOH
Output Hold After Address Change
3
3
3
ns
tLZCE
[10]
tLZ
Chip Enable to Output Active
3
3
3
ns
tHZCE
[10]
tHZ
Chip Disable to Output Inactive
tLZOE
[10]
tOLZ
Output Enable to Output Active
tHZOE [10]
tOHZ
Output Disable to Output Inactive
tPU
[7]
tPA
Chip Enable to Power Active
tPD
[7]
tPS
Chip Disable to Power Standby
10
0
13
0
10
0
15
0
13
0
25
ns
15
0
35
ns
ns
ns
45
ns
SRAM WRITE Cycle
tWC
tWC
Write Cycle Time
25
35
45
ns
tPWE
tWP
Write Pulse Width
20
25
30
ns
tSCE
tCW
Chip Enable To End of Write
20
25
30
ns
tSD
tDW
Data Setup to End of Write
10
12
15
ns
tHD
tDH
Data Hold After End of Write
0
0
0
ns
tAW
tAW
Address Setup to End of Write
20
25
30
ns
tSA
tAS
Address Setup to Start of Write
0
0
0
ns
tHA
tWR
Address Hold After End of Write
0
0
0
ns
tWZ
Write Enable to Output Disable
tOW
Output Active after End of Write
tHZWE [10, 11]
tLZWE
[10]
10
3
13
3
15
3
ns
ns
Notes
8. WE must be HIGH during SRAM READ Cycles.
9. Device is continuously selected with CE and OE both Low.
10. Measured ± 200 mV from steady state output voltage.
Document #: 001-06422 Rev. *E
Page 9 of 17
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PRELIMINARY
CY14B256L
AutoStore/Power Up RECALL
Parameter
tHRECALL [12]
CY14B256L
Description
Min
Unit
Max
20
ms
STORE Cycle Duration
12.5
ms
VSWITCH
Low Voltage Trigger Level
2.65
V
tVCCRISE
VCC Rise Time
tSTORE
[13, 14]
Power Up RECALL Duration
µs
150
Software Controlled STORE/RECALL Cycle [15, 16]
Parameter
Description
25 ns part
35 ns part
45 ns part
Min
Min
Min
Max
Max
Max
Unit
tRC
STORE/RECALL Initiation Cycle Time
25
35
45
ns
tAS
Address Setup Time
0
0
0
ns
tCW
Clock Pulse Width
20
25
30
ns
tGHAX
Address Hold Time
1
1
1
ns
tRECALL
RECALL Duration
50
50
50
µs
tSS[17, 18]
Soft Sequence Processing Time
70
70
70
µs
Hardware STORE Cycle
Parameter
Description
CY14B256L
Min
Max
70
tDELAY [19]
Time allowed to complete SRAM Cycle
1
tHLHX
Hardware STORE Pulse Width
15
Unit
µs
ns
Notes
11. If WE is low when CE goes low, the outputs remain in the high impedance state.
12. tHRECALL starts from the time VCC rises above VSWITCH.
13. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE takes place.
14. Industrial grade devices require 15 ms max.
15. The software sequence is clocked with CE-controlled or OE-controlled READs.
16. The six consecutive addresses must be read in the order listed in the Table 1,Mode Selection, on page 5. WE must be HIGH during all six consecutive cycles.
17. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register the command.
18. Commands like STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
19. READ and WRITE cycles in progress before HSB are given this amount of time to complete.
Document #: 001-06422 Rev. *E
Page 10 of 17
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PRELIMINARY
CY14B256L
Switching Waveforms
SRAM Read Cycle 1 (address controlled) [8, 9, 20]
tRC
ADDRESS
t AA
t OHA
DQ (DATA OUT)
DATA VALID
SRAM Read Cycle 2 (CE controlled) [8, 20]
tRC
ADDRESS
tLZCE
CE
tACE
tPD
tHZCE
OE
tLZOE
DQ (DATA OUT)
t PU
ICC
tHZOE
tDOE
DATA VALID
ACTIVE
STANDBY
Note
20. HSB must remain HIGH during READ and WRITE cycles.
Document #: 001-06422 Rev. *E
Page 11 of 17
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PRELIMINARY
CY14B256L
Switching Waveforms (continued)
SRAM Write Cycle 1 (WE controlled) [20, 21]
tWC
ADDRESS
tHA
tSCE
CE
tAW
tSA
tPWE
WE
tSD
tHD
DATA VALID
DATA IN
tHZWE
DATA OUT
tLZWE
HIGH IMPEDANCE
PREVIOUS DATA
SRAM Write Cycle 2 (CE controlled)
tWC
ADDRESS
CE
WE
tHA
tSCE
tSA
tAW
tPWE
tSD
DATA IN
DATA OUT
tHD
DATA VALID
HIGH IMPEDANCE
Note
21. CE or WE must be > VIH during address transitions.
Document #: 001-06422 Rev. *E
Page 12 of 17
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PRELIMINARY
CY14B256L
Switching Waveforms (continued)
Figure 3. AutoStore/Power Up RECALL
No STORE occurs
without atleast one
SRAM write
STORE occurs only
if a SRAM write
has happened
VCC
VSWITCH
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
tHRECALL
Read & Write Inhibited
Figure 4. CE-Controlled Software STORE/RECALL Cycle [16]
tRC
a
a
a a
tSCE
ADDRESS # 6
ttGHAX
GLAX
OE
DQ (DATA)
DATA VALID
Document #: 001-06422 Rev. *E
a
a
t STORE / t RECALL
DATA VALID
a
a
a
a
tSA
CE
a
a
a a
ADDRESS # 1
ADDRESS
tRC
HIGH IMPEDANCE
Page 13 of 17
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PRELIMINARY
CY14B256L
Switching Waveforms (continued)
Figure 5. OE-Controlled Software STORE/RECALL Cycle [16]
tRC
ADDRESS # 1
ADDRESS
CE
tSA
ADDRESS # 6
tSCE
OE
t STORE / t RECALL
DQ (DATA)
a
a
ttGHAX
GLAX
DATA VALID
a
a
a
a
a
a
a
a
a
a
a a
tRC
HIGH IMPEDANCE
DATA VALID
Figure 6. Hardware STORE Cycle
a
a
tHLHX
HSB (IN)
tSTORE
HIGH IMPEDANCE
a
a
tHLBL
HSB (OUT)
HIGH IMPEDANCE
a
a
t DELAY
DATA VALID
DQ (DATA OUT)
DATA VALID
Figure 7. Soft Sequence Processing [17, 18]
ADDRESS # 1
ADDRESS # 6
34
t SS
Soft Sequence Command
ADDRESS # 1
a
a
ADDRESS
a
a
Soft Sequence Command
34
t SS
ADDRESS # 6
VCC
Document #: 001-06422 Rev. *E
Page 14 of 17
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PRELIMINARY
CY14B256L
Part Numbering Nomenclature
CY 14 B 256 L - SZ 25 X C T
Option:
T - Tape & Reel
Blank - Std.
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (– 40 to 85°C)
Pb-Free
Package:
SZ - 32 SOIC
SP - 48 SSOP
Data Bus:
L - x8
Speed:
25 - 25 ns
35 - 35 ns
45 - 45 ns
Density:
256 - 256 Kb
Voltage:
B - 3.0V
NVSRAM
14 - AutoStore + Software Store + Hardware Store
Cypress
Ordering Information
All of the above mentioned parts are of “Pb-free” type. Shaded areas contain advance information. Contact your local Cypress
sales representative for availability of these parts.
Speed
(ns)
25
35
45
45
Ordering Code
Package
Diagram
CY14B256L-SZ25XCT
51-85127
32-pin SOIC
CY14B256L-SP25XCT
51-85061
48-pin SSOP
CY14B256L-SZ35XCT
51-85127
32-pin SOIC
CY14B256L-SP35XCT
51-85061
48-pin SSOP
CY14B256L-SZ45XCT
51-85127
32-pin SOIC
Package Type
CY14B256L-SP45XCT
51-85061
48-pin SSOP
CY14B256L-SZ45XIT
51-85127
32-pin SOIC
CY14B256L-SP45XIT
51-85061
48-pin SSOP
CY14B256L-SZ45XI
51-85127
32-pin SOIC
CY14B256L-SP45XI
51-85061
48-pin SSOP
Document #: 001-06422 Rev. *E
Operating
Range
Commercial
Commercial
Commercial
Industrial
Page 15 of 17
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PRELIMINARY
CY14B256L
Package Diagrams
Figure 8. 32-pin (300-Mil) SOIC, 51-85127
PIN 1 ID
16
1
REFERENCE JEDEC MO-119
0.405[10.287]
0.419[10.642]
17
MIN.
MAX.
DIMENSIONS IN INCHES[MM]
0.292[7.416]
0.299[7.594]
PART #
S32.3 STANDARD PKG.
SZ32.3 LEAD FREE PKG.
32
SEATING PLANE
0.810[20.574]
0.822[20.878]
0.090[2.286]
0.100[2.540]
0.004[0.101]
0.050[1.270]
TYP.
0.026[0.660]
0.032[0.812]
0.014[0.355]
0.020[0.508]
0.004[0.101]
0.0100[0.254]
0.021[0.533]
0.041[1.041]
0.006[0.152]
0.012[0.304]
51-85127-*A
Figure 9. 48-pin Shrunk Small Outline Package, 51-85061
51-85061-*C
AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in
this document are the trademarks of their respective holders.
Document #: 001-06422 Rev. *E
Page 16 of 17
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
CY14B256L
Document History Page
Document Title: CY14B256L, 256-Kbit (32K x 8) nvSRAM
Document Number: 001-06422
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
425138
See ECN
TUP
New Data Sheet
*A
437321
See ECN
TUP
Show Data Sheet on External Web
*B
471966
See ECN
TUP
Changed VIH(min) from 2.2V to 2.0V
Changed tRECALL from 60 µs to 50 µs
Changed Endurance from 1Million Cycles to 500K Cycles
Changed Data Retention from 100 Years to 20 Years
Added Soft Sequence Processing Time Waveform
Updated Part Numbering Nomenclature and Ordering Information
*C
503277
See ECN
PCI
Changed from “Advance” to “Preliminary”
Changed the term “Unlimited” to “Infinite”
Changed endurance from 500K cycles to 200K cycles
Device operation: Tolerance limit changed from + 20% to + 15% in the
“Features Section” and “Operating Range Table”
Removed Icc1 values from the DC table for 25 ns and 35 ns industrial grade
Changed VSWITCH(min) from 2.55V to 2.45V
Added temperature spec. to data retention - 20 years at 55°C
Changed the max value of Vcap storage capacitor from 120 µF to 57 µF
Updated “Part Nomenclature Table” and “Ordering Information Table”
*D
597004
See ECN
TUP
Removed VSWITCH(min) spec from the AutoStore/Power Up RECALL table
Changed tGLAX spec from 20 ns to 1 ns
Added tDELAY(max) spec of 70 µs in the Hardware STORE Cycle table
Removed tHLBL specification
Changed tSS specification form 70 µs (min) to 70 µs (max)
Changed VCAP(max) from 57 µF to 120 µF
*E
696097
See ECN
VKN
Added footnote 6 related to HSB
Changed tGLAX to tGHAX
Document #: 001-06422 Rev. *E
Description of Change
Page 17 of 17
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