16V8 PALCE16V8 Flash Erasable, Reprogrammable CMOS PAL® Device Features • Up to 16 input terms and 8 outputs • 7.5 ns com’l version 5 ns tCO 5 ns tS 7.5 ns tPD 125-MHz state machine • 10 ns military/industrial versions 7 ns tCO 10 ns tS 10 ns tPD 62-MHz state machine • High reliability — Proven Flash technology • Active pull-up on data input pins • Low power version (16V8L) — 55 mA max. commercial (10, 15, 25 ns) — 65 mA max. industrial (10, 15, 25 ns) — 65 mA military (15 and 25 ns) • Standard version has low power — 90 mA max. commercial (10, 15, 25 ns) — 115 mA max. commercial (7 ns) — 130 mA max. military/industrial (10, 15, 25 ns) • CMOS Flash technology for electrical erasability and reprogrammability • PCI compliant • User-programmable macrocell — Output polarity control — 100% programming and functional testing Functional Description The Cypress PALCE16V8 is a CMOS Flash Electrical Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-product (AND-OR) logic structure and the programmable macrocell. — Individually selectable for registered or combinatorial operation Logic Block Diagram (PDIP/CDIP) GND I8 I7 I6 I5 I4 I3 I2 I1 CLK/I0 10 9 8 7 6 5 4 3 2 1 8 8 8 Macrocell Macrocell Macrocell 17 PROGRAMMABLE AND ARRAY (64 x 32) 8 8 8 8 Macrocell Macrocell Macrocell Macrocell 11 12 13 14 15 16 OE/I9 I/O0 I/O1 I/O2 I/O3 I/O4 Pin Configurations • 19 20 I/O7 VCC 16V8–1 VCC I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 OE/I9 I2 I1 CLK/I 0 VCC I/O7 20 19 18 17 16 15 14 13 12 11 18 I/O6 I3 I4 I5 I6 I7 16V8–2 3901 North First Street • 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10111213 I8 GND OE/I9 I/O0 I/O1 1 2 3 4 5 6 7 8 9 10 Macrocell PLCC/LCC Top View DIP Top View CLK/I0 I1 I2 I3 I4 I5 I6 I7 I8 GND Cypress Semiconductor Corporation Document #: 38-03025 Rev. ** I/O5 8 San Jose • I/O6 I/O5 I/O4 I/O3 I/O2 16V8–3 CA 95134 • 408-943-2600 Revised September 3, 1998 PALCE16V8 Selection Guide tPD ns Generic Part Number Com’l/Ind tS ns Mil Com’l/Ind tCO ns Mil Com’l/Ind ICC mA Mil Com’l Mil/Ind PALCE16V8-5 5 3 4 115 PALCE16V8-7 7.5 7 5 115 PALCE16V8-10 10 10 10 10 7 10 90 130 PALCE16V8-15 15 15 12 12 10 10 90 130 PALCE16V8-25 25 25 15 20 12 12 90 130 PALCE16V8L-15 15 15 12 12 10 12 55 65 PALCE16V8L-25 25 25 15 20 12 20 55 65 Shaded area contains preliminary information. Functional Description (continued) Power-Up Reset The PALCE16V8 is executed in a 20-pin 300-mil molded DIP, a 300-mil cerdip, a 20-lead square ceramic leadless chip carrier, and a 20-lead square plastic leaded chip carrier. All registers in the PALCE16V8 power-up to a logic LOW for predictable system initialization. For each register, the associated output pin will be HIGH due to active-LOW outputs. The device provides up to 16 inputs and 8 outputs. The PALCE16V8 can be electrically erased and reprogrammed. The programmable macrocell enables the device to function as a superset to the familiar 20-pin PLDs such as 16L8, 16R8, 16R6, and 16R4. Electronic Signature The PALCE16V8 features 8 product terms per output and 32 input terms into the AND array. The first product term in a macrocell can be used either as an internal output enable control or as a data product term. Security Bit There are a total of 18 architecture bits in the PALCE16V8 macrocell; two are global bits that apply to all macrocells and 16 that apply locally, two bits per macrocell. The architecture bits determine whether the macrocell functions as a register or combinatorial with inverting or noninverting output. The output enable control can come from an external pin or internally from a product term. The output can also be permanently enabled, functioning as a dedicated output or permanently disabled, functioning as a dedicated input. Feedback paths are selectable from either the input/output pin associated with the macrocell, the input/output pin associated with an adjacent pin, or from the macrocell register itself. An electronic signature word is provided in the PALCE16V8 that consists of 64 bits of programmable memory that can contain user-defined data. A security bit is provided that defeats the readback of the internal programmed pattern when the bit is programmed. Low Power The Cypress PALCE16V8 provides low-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability. Product Term Disable Product Term Disable (PTD) fuses are included for each product term. The PTD fuses allow each product term to be individually disabled. Configuration Table CG0 CG1 CL0x 0 1 0 Registered Output Registered Med PALs 0 1 1 Combinatorial I/O Registered Med PALs 1 0 0 Combinatorial Output Small PALs 1 0 1 Input Small PALs 1 1 1 Combinatorial I/O 16L8 only Document #: 38-03025 Rev. ** Cell Configuration Devices Emulated Page 2 of 13 PALCE16V8 Macrocell OE 1 1 VCC 0 X To Adjacent Macrocell 1 1 1 0 0 0 0 1 1 0 CG1 CL0x 1 1 0 X D Q I/Ox 1 0 VCC CLK Q 1 0 1 1 0 X CL1x CG1 for pin 13 to 18 CG0 for pin 12 and 19 CL0x From Adjacent Pin 16V8–4 Document #: 38-03025 Rev. ** Page 3 of 13 PALCE16V8 Maximum Ratings Output Current into Outputs (LOW)............................. 24 mA DC Programming Voltage............................................. 12.5V (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current..................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 24 to Pin 12) ........................................... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V Range Ambient Temperature VCC Commercial 0°C to +75°C 5V ±5% Military[1] –55°C to +125°C 5V ±10% Industrial –40°C to +85°C 5V ±10% DC Input Voltage............................................ –0.5V to +7.0V Electrical Characteristics Over the Operating Range[2] Parameter Description Test Conditions Min. VOH Output HIGH Voltage VCC = Min., VIN = VIH or VIL IOH = –3.2 mA Com’l IOH = –2 mA Mil/Ind VOL Output LOW Voltage VCC = Min., VIN = VIH or VIL IOL = 24 mA Com’l IOL = 12 mA Mil/Ind V 0.5 Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs[3] 2.0 VIL[4] Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs[3] –0.5 IIH Input or I/O HIGH Leakage Current 3.5V < VIN < VCC IIL[5] Input or I/O LOW Leakage Current 0V < VIN < VIN (Max.) ISC Output Short Circuit Current VCC = Max., VOUT = 0.5V[6, 7] ICC Operating Power Supply Current 5, 7 ns Unit 2.4 VIH VCC = Max., VIL = 0V, VIH = 3V, Output Open, f = 15 MHz (counter) Max. –30 Com’l 10, 15, 25 ns 15L, 25L ns V V 0.8 V 10 µA –100 µA –150 mA 115 mA 90 mA 55 mA 10, 15, 25 ns Mil/Ind 130 mA 15L, 25L ns Mil. 65 mA 15L, 25L ns Ind. 65 mA Capacitance[7] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Typ. Unit VIN = 2.0V @ f = 1 MHz 5 pF VOUT = 2.0V @ f = 1 MHz 5 pF Endurance Characteristics[7] Parameter N Description Minimum Reprogramming Cycles Test Conditions Min. Normal Programming Conditions 100 Max. Unit Cycles Notes: 1. TA is the “instant on” case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 4. VIL (Min.) is equal to –3.0V for pulse durations less than 20 ns. 5. The leakage current is due to the internal pull-up resistor on all pins. 6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 7. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-03025 Rev. ** Page 4 of 13 PALCE16V8 AC Test Loads and Waveforms ALL INPUT PULSES 3.0V 90% 90% 10% GND 10% < 2 ns < 2 ns 16V8–5 5V S1 R1 OUTPUT TEST POINT R2 CL 16V8–6 Commercial Specification S1 tPD, tCO Closed tPZX, tEA Z · H: Open Z · L: Closed tPXZ, tER H · Z: Open L · Z: Closed Document #: 38-03025 Rev. ** Military CL R1 R2 R1 R2 Measured Output Value 50 pF 200Ω 390Ω 390Ω 750Ω 1.5V 1.5V 5 pF H · Z: VOH – 0.5V L · Z: VOL + 0.5V Page 5 of 13 PALCE16V8 Commercial and Industrial Switching Characteristics[2] 16V8-5 Parameter Description 16V8-7 16V8-10 16V8-15 16V8-25 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tPD Input to Output Propagation Delay[8, 9] 1 5 3 7.5 3 10 3 15 3 25 ns tPZX OE to Output Enable 1 6 6 10 15 20 ns tPXZ OE to Output Disable 1 5 6 10 15 20 ns tEA Input to Output Enable Delay[7] 1 6 9 10 15 25 ns tER Input to Output Disable Delay[7, 10] 1 5 9 10 15 25 ns tCO Clock to Output Delay[8,9] 1 4 12 ns tS Input or Feedback Set-Up Time 3 tH Input Hold Time 0 0 0 tP External Clock Period (tCO + tS) 7 10 14.5 tWH Clock Width HIGH[7] 3 4 6 tWL Clock Width LOW [7] 3 4 fMAX1 External Maximum Frequency (1/(tCO + tS))[7, 11] 143 fMAX2 Data Path Maximum Frequency (1/(tWH + tWL))[7, 12] fMAX3 Internal Feedback Maximum Frequency (1/(tCF + tS))[7, 13] tCF Register Clock to Feedback Input[7, 14] tPR Power-Up Reset Time[7] 2 5 5 2 7 10 ns 0 0 ns 22 27 ns 8 12 ns 6 8 12 ns 100 69 45.5 37 MHz 166 125 83 62.5 41.6 MHz 166 125 74 50 40 MHz 1 3 1 12 2 15 3 7.5 2 6 1 8 1 10 1 ns µs Shaded area contains preliminary information. Notes: 8. Min. times are tested initially and after any design or process changes that may affect these parameters. 9. This specification is guaranteed for all device outputs changing state in a given access cycle. 10. This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max. 11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate. 12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode. 13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate. 14. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note 7 above) minus tS. Document #: 38-03025 Rev. ** Page 6 of 13 PALCE16V8 Military Switching Characteristics[7] 16V8-10 Parameter Description 16V8-15 16V8-25 Min. Max. Min. Max. Min. Max. Unit 3 10 3 15 3 25 ns tPD Input to Output Propagation Delay[8, 9] tPZX OE to Output Enable 10 15 20 ns tPXZ OE to Output Disable 10 15 20 ns 10 15 25 ns 10 15 25 ns 12 ns [7] tEA Input to Output Enable Delay tER Input to Output Disable Delay[7, 10] [8, 9] tCO Clock to Output Delay tS Input or Feedback Set-Up Time 2 tH Input Hold Time .5 tP External Clock Period (tCO + tS) 17 tWH Clock Width HIGH [7] 6 tWL Clock Width LOW[7] 6 fMAX1 External Maximum Frequency (1/(tCO + tS)[7, 11] fMAX2 Data Path Maximum Frequency (1/(tWH + tWL))[7, 12] fMAX3 Internal Feedback Maximum Frequency (1/(tCF + tS))[7, 13] tCF Register Clock to Feedback Input[7, 14] tPR Power-Up Reset Time[7] 7 2 10 10 2 12 15 ns .5 .5 ns 22 27 ns 8 12 ns 8 12 ns 58 45.5 37 MHz 83 62.5 41.6 MHz 62.5 50 40 MHz 6 8 1 10 1 1 ns µs Switching Waveform INPUTS, I/O, REGISTERED FEEDBACK tS t WH tH t WL CP t CO tP tPXZ, tER [10] tEA, tPZX [10] REGISTERED OUTPUTS tPXZ, tER [10] t PD [10] tEA, tPZX COMBINATORIAL OUTPUTS 16V8–7 Power-Up Reset Waveform POWER SUPPLY VOLTAGE 10% VCC 90% t PR REGISTERED ACTIVE LOW OUTPUTS tS CLOCK tPR MAX = 1 µs Document #: 38-03025 Rev. ** t WL 16V8–8 Page 7 of 13 PALCE16V8 Functional Logic Diagram for PALCE16V8 PIN NUMBERS INPUT LINE NUMBERS PRODUCT LINE FIRST CELL NUMBERS 1 0 00 64 128 192 3 4 7 8 11 12 15 16 PIN NUMBERS VCC 20 19 20 23 24 27 28 31 32 96 160 224 MC7 CL1=2048 CL0=2120 PTD=2128 -2135 19 MC6 CL1=2049 CL0=2121 PTD=2136 -2143 18 MC5 CL1=2050 CL0=2122 PTD=2144 -2151 17 MC4 CL1=2051 CL0=2123 PTD=2152 -2159 16 MC3 CL1=2052 CL0=2124 PTD=2160 -2167 15 MC2 CL1=2053 CL0=2125 PTD=2168 -2175 14 MC1 CL1=2054 CL0=2126 PTD=2176 -2183 13 MC0 CL1=2055 CL0=2127 PTD=2184 -2191 12 2 256 320 384 448 288 352 416 480 3 512 576 640 704 544 608 672 736 4 768 832 896 960 800 864 928 992 5 1024 1088 1152 1216 1056 1120 1184 1248 6 1280 1344 1408 1312 1376 14721440 1504 7 1536 1600 1664 1568 1632 17281696 1760 8 1792 1856 1920 1824 1888 19841952 2016 9 10 0 3 4 7 8 11 12 USER 2056 2064 15 16 19 20 23 24 27 28 11 31 ELECTRONIC SIGNATURE ROW 2072 2080 2088 2096 2104 2112 2119 GLOBAL ARCH BITS BYTE 0 BYTE 1 MSB LSB Document #: 38-03025 Rev. ** BYTE2 BYTE3 BYTE4 BYTE5 BYTE 6 BYTE 7 MSB CG0=2192 CG1=2193 16V8–9 LSB Page 8 of 13 PALCE16V8 Ordering Information ICC (mA) Package Name tPD (ns) tS (ns) tCO (ns) 115 5 3 4 PALCE16V8-5JC J61 20-Lead Plastic Leaded Chip Carrier Commercial 115 7.5 5 5 PALCE16V8-7JC J61 20-Lead Plastic Leaded Chip Carrier Commercial PALCE16V8-7PC P5 20-Lead (300-Mil) Molded DIP 90 10 7.5 7 PALCE16V8-10JC J61 20-Lead Plastic Leaded Chip Carrier PALCE16V8-10PC P5 20-Lead (300-Mil) Molded DIP 130 10 7.5 7 PALCE16V8-10JI J61 20-Lead Plastic Leaded Chip Carrier PALCE16V8-10PI P5 20-Lead (300-Mil) Molded DIP 130 10 10 7 PALCE16V8-10DMB D6 20-Lead (300-Mil) CerDIP PALCE16V8-10LMB L61 20-Pin Square Leadless Chip Carrier 90 15 12 10 PALCE16V8-15JC J61 20-Lead Plastic Leaded Chip Carrier PALCE16V8-15PC P5 20-Lead (300-Mil) Molded DIP 130 15 12 10 PALCE16V8-15PI P5 20-Lead(300Mil) Molded DIP Industrial PALCE16V8-15DMB D6 20-Lead (300-Mil) CerDIP Military PALCE16V8-15LMB L61 20-Pin Square Leadless Chip Carrier PALCE16V8-25JC J61 20-Lead Plastic Leaded Chip Carrier PALCE16V8-25PC P5 20-Lead (300-Mil) Molded DIP PALCE16V8-25JI J61 20-Lead Plastic Leaded Chip Carrier Industrial PALCE16V8-25DMB D6 20-Lead (300-Mil) CerDIP Military PALCE16V8-25LMB L61 20-Pin Square Leadless Chip Carrier PALCE16V8L-10JC J61 20-Lead Plastic Leaded Chip Carrier PALCE16V8L-10PC P5 20-Lead (300-Mil) Molded DIP PALCE16V8L-10JI J61 20-Lead Plastic Leaded Chip Carrier PALCE16V8L-10PI P5 20-Lead (300-Mil) Molded DIP PALCE16V8L-15JC J61 20-Lead Plastic Leaded Chip Carrier PALCE16V8L-15PC P5 20-Lead (300-Mil) Molded DIP PALCE16V8L-15DMB D6 20-Lead (300-Mil) CerDIP PALCE16V8L-15LMB L61 20-Pin Square Leadless Chip Carrier PALCE16V8L-25JC J61 20-Lead Plastic Leaded Chip Carrier PALCE16V8L-25PC P5 20-Lead (300-Mil) Molded DIP PALCE16V8L-25DMB D6 20-Lead (300-Mil) CerDIP PALCE16V8L-25LMB L61 20-Pin Square Leadless Chip Carrier 90 130 25 25 15 15 12 12 55 10 7.5 7 65 10 10 7 55 15 12 10 65 15 12 10 55 25 15 12 65 25 15 12 Ordering Code Package Type Operating Range Industrial Military Commercial Commercial Commercial Industrial Commercial Military Commercial Military Shaded area contains preliminary information. Document #: 38-03025 Rev. ** Page 9 of 13 PALCE16V8 MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups Switching Characteristics Parameter Subgroups tPD 9, 10, 11 VOH 1, 2, 3 tCO 9, 10, 11 VOL 1, 2, 3 tS 9, 10, 11 VIH 1, 2, 3 tH 9, 10, 11 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC 1, 2, 3 Package Diagrams 20-Lead (300-Mil) CerDIP D6 MIL-STD-1835 D-8 Config. A 51-80029 Document #: 38-03025 Rev. ** Page 10 of 13 PALCE16V8 Package Diagrams (continued) 20-Lead Plastic Leaded Chip Carrier J61 51-85000-A 20-Square Leadless Chip Carrier L61 51-80049 Document #: 38-03025 Rev. ** Page 11 of 13 PALCE16V8 Package Diagrams (continued) 20-Lead (300-Mil) Molded DIP P5 51-85011-A Document #: 38-03025 Rev. ** Page 12 of 13 © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PALCE16V8 Document Title: PALCE16V8 Flash Erasable, Reprogrammable CMOS PAL® Device Document Number: 38-03025 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106370 07/11/01 SZV Change from Spec Number: 38-00364 to 38-03025 Document #: 38-03025 Rev. ** Page 13 of 13