fax id: 6010 1P AL CE 20 V8 PALCE20V8 Flash Erasable, Reprogrammable CMOS PAL Device Features • QSOP package available — 10, 15, and 25 ns com’l version • Active pull-up on data input pins • Low power version (20V8L) — 55 mA max. commercial (15, 25 ns) — 15, and 25 ns military/industrial versions • High reliability — Proven Flash technology — 65 mA max. military/industrial (15, 25 ns) • Standard version has low power — 90 mA max. commercial (15, 25 ns) — 100% programming and functional testing Functional Description The Cypress PALCE20V8 is a CMOS Flash Erasable second-generation programmable array logic device. It is implemented with the familiar sum-of-product (AND-OR) logic structure and the programmable macrocell. — 115 mA max. commercial (10 ns) — 130 mA max. military/industrial (15, 25 ns) • CMOS Flash technology for electrical erasability and reprogrammability • User-programmable macrocell — Output polarity control The PALCE20V8 is executed in a 24-pin 300-mil molded DIP, a 300-mil cerdip, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and a 24-lead quarter size outline. The device provides up to 20 inputs and 8 outputs. The PALCE20V8 can be electrically erased and reprogrammed. The programmable macrocell enables the device to function as a superset to the familiar 24-pin PLDs such as 20L8, 20R8, 20R6, 20R4. — Individually selectable for registered or combinatorial operation Logic Block Diagram (PDIP/CDIP/QSOP) GND I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 CLK/I0 12 11 10 9 8 7 6 5 4 3 2 1 PROGRAMMABLE AND ARRAY (64 x 40) MUX 8 8 8 8 Macrocell Macrocell Macrocell Macrocell 8 Macrocell 8 8 Macrocell Macrocell 8 Macrocell MUX 13 OE/I11 14 15 16 17 18 19 20 21 22 23 24 I12 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I13 VCC 20V8–1 PAL is a registered trademark of Advanced Micro Devices, Inc. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 June 1994 – Revised March 26, 1997 PALCE20V8 Pin Configuration PLCC/LCC Top View DIP/QSOP Top View CLK/I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I13 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 4 3 2 1 2827 26 I3 I4 I5 NC I6 I7 I8 I/O0 I12 OE/I11 20V8–2 5 6 7 8 9 10 11 121314 1516 1718 I/O6 I/O5 I/O4 NC I/O3 I/O2 I/O1 25 24 23 22 21 20 19 20V8–3 Selection Guide tPD ns Generic Part Number Com’l/Ind tS ns Mil Com’l/Ind tCO ns Mil Com’l/Ind ICC mA Mil Com’l Mil/Ind PALCE20V8−5 5 3 4 115 PALCE20V8−7 7.5 7 5 115 PALCE20V8−10 10 10 10 10 7 10 115 130 PALCE20V8−15 15 15 12 12 10 12 90 130 PALCE20V8−25 25 25 15 20 12 20 90 130 PALCE20V8L−15 15 15 12 12 10 12 55 65 PALCE20V8L−25 25 25 15 20 12 20 55 65 Shaded area contains preliminary information. Electronic Signature Functional Description (continued) An electronic signature word is provided in the PALCE20V8 that consists of 64 bits of programmable memory that can contain user-defined data. The PALCE20V8 features 8 product terms per output and 40 input terms into the AND array. The first product term in a macrocell can be used either as an internal output enable control or as a data product term. Security Bit There are a total of 18 architecture bits in the PALCE20V8 macrocell; two are global bits that apply to all macrocells and 16 that apply locally, two bits per macrocell. The architecture bits determine whether the macrocell functions as a register or combinatorial with inverting or noninverting output. The output enable control can come from an external pin or internally from a product term. The output can also be permanently enabled, functioning as a dedicated output or permanently disabled, functioning as a dedicated input. Feedback paths are selectable from either the input/output pin associated with the macrocell, the input/output pin associated with an adjacent pin, or from the macrocell register itself. A security bit is provided that defeats the readback of the internal programmed pattern when the bit is programmed. Low Power The Cypress PALCE20V8 provides low-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability. Product Term Disable Product Term Disable (PTD) fuses are included for each product term. The PTD fuses allow each product term to be individually disabled. Power-Up Reset Input and I/O Pin Pull-Ups All registers in the PALCE20V8 power-up to a logic LOW for predictable system initialization. For each register, the associated output pin will be HIGH due to active-LOW outputs. The PALCE20V8 input and I/O pins have built-in active pull-ups that will float unused inputs and I/Os to an active HIGH state (logical 1). All unused inputs and three-stated I/O pins should be connected to another active input, VCC, or Ground to improve noise immunity and reduce ICC. 2 PALCE20V8 Configuration Table CG0 CG1 CL0x Cell Configuration Devices Emulated 0 1 0 Registered Output Registered Med PALs 0 1 1 Combinatorial I/O Registered Med PALs 1 0 0 Combinatorial Output Small PALs 1 0 1 Input Small PALs 1 1 1 Combinatorial I/O 20L8 only Macrocell OE 1 1 VCC To Adjacent Macrocell 1 1 1 0 0 0 0 1 0 X 1 0 CG1 CL0x 1 1 0 X D Q I/Ox 1 0 VCC CLK Q 1 0 1 1 0 X CL1x CG1 for pin 16 to 21 (DIP) CG0 for pin 15 and 22 (DIP) Maximum Ratings CL0x From Adjacent Pin 20V8–4 Output Current into Outputs (LOW)............................. 24 mA DC Programming Voltage............................................. 12.5V (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current ..................................................... >200 mA Storage Temperature ..................................... −65°C to +150°C Operating Range Ambient Temperature with Power Applied.................................................. −55°C to +125°C Range Supply Voltage to Ground Potential (Pin 24 to Pin 12).................................................−0.5V to +7.0V DC Input Voltage .................................................−0.5V to +7.0V 0°C to +75°C 5V ±5% −40°C to +85°C 5V ±10% Military[1] −55°C to +125°C 5V ±10% Note: 1. TA is the “instant on” case temperature. 3 VCC Industrial Commercial DC Voltage Applied to Outputs in High Z State .....................................................−0.5V to +7.0V Ambient Temperature PALCE20V8 Electrical Characteristics Over the Operating Range[2] Parameter VOH VOL Description Output HIGH Voltage Output LOW Voltage Test Conditions Min. VCC = Min., VIN = VIH or VIL IOH = −3.2 mA Com’l IOH = −2 mA Mil/Ind VCC = Min., VIN = VIH or VIL IOL = 24 mA Com’l IOL = 12 mA Mil/Ind Unit 2.4 V 0.5 VIH Input HIGH Level Guaranteed Input Logical HIGH Voltage for All Inputs[3] 2.0 VIL[4] Input LOW Level Guaranteed Input Logical LOW Voltage for All Inputs[3] −0.5 IIH Input or I/O HIGH Leakage Current 3.5V < VIN < VCC IIL[5] Input or I/O LOW Leakage Current 0V < VIN < VIN (Max.) ISC Output Short Circuit Current VCC = Max., VOUT = 0.5V[6,7] ICC Operating Power Supply Current VCC = Max., VIL = 0V, VIH = 3V, Output Open, f = 15 MHz (counter) Max. V V 0.8 V 10 µA −100 µA −150 mA 115 mA 15, 25 ns 90 mA 15L, 25L ns 55 mA 5, 7, 10 ns −30 Com’l 10, 15, 25 ns Mil/Ind 130 mA 15L, 25L ns Mil/Ind 65 mA Capacitance[7] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Typ. Unit VIN = 2.0V @ f = 1 MHz 5 pF VOUT = 2.0V @ f = 1 MHz 5 pF Endurance Characteristics[7] Parameter N Description Minimum Reprogramming Cycles Test Conditions Min. Normal Programming Conditions 100 Max. Unit Cycles Notes: 2. See the last page of this specification for Group A subgroup testing information. 3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 4. VIL (Min.) is equal to −3.0V for pulse durations less than 20 ns. 5. The leakage current is due to the internal pull-up resistor on all pins. 6. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation. 7. Tested initially and after any design or process changes that may affect these parameters. 4 PALCE20V8 AC Test Loads and Waveforms ALL INPUT PULSES 3.0V 90% GND 90% 10% 10% ≤ 2 ns ≤ 2 ns 20V8–5 5V S1 R1 OUTPUT TEST POINT R2 CL 20V8–6 Commercial Specification S1 tPD, tCO Closed tPZX, tEA Z ➧ H: Open Z ➧ L: Closed tPXZ, tER H ➧ Z: Open L ➧ Z: Closed Military CL R1 R2 R1 R2 Measured Output Value 50 pF 200Ω 390Ω 390Ω 750Ω 1.5V 1.5V H ➧ Z: VOH − 0.5V L ➧ Z: VOL + 0.5V 5 pF 5 PALCE20V8 Commercial and Industrial Switching Characteristics[2] 20V8−5 Parameter Description 20V8−7 20V8−10 20V8−15 20V8−25 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit 1 5 1 7.5 1 10 1 15 1 25 ns 15 20 ns 15 20 ns 10 15 25 ns 10 15 25 ns 12 ns tPD Input to Output Propagation Delay[8] tPZX OE to Output Enable 5 6 10 tPXZ OE to Output Disable 5 6 10 tEA Input to Output Enable Delay[7] 6 9 tER Input to Output Disable Delay[7,9] 6 9 tCO Clock to Output Delay[8] 1 tS Input or Feedback Set-Up Time 3 tH Input Hold Time 0 0 0 tP External Clock Period (tCO + tS) 7 12 17 tWH Clock Width HIGH[7] 3 5 8 tWL Clock Width LOW [7] 3 5 8 fMAX1 External Maximum Frequency (1/(tCO + tS))[7,10] 143 83 fMAX2 Data Path Maximum Frequency (1/(tWH + tWL))[7, 11] 166. 6 fMAX3 Internal Feedback Maximum Frequency (1/(tCF + tS))[7,12] 166. 6 tCF Register Clock to Feedback Input[7, 13] tPR Power-Up Reset Time[7] 4 1 1 7 10 1 10 ns 0 0 ns 22 27 ns 8 12 ns 8 12 ns 58 45.5 37 MHz 100 62.5 62.5 41.6 MHz 100 62.5 50 40 MHz 3 1 12 1 15 3 1 5 7 6 1 8 1 10 1 ns µs Shaded area contains preliminary information. Notes: 8. Min. times are tested initially and after any design or process changes that may affect these parameters. 9. This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max. 10. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate. 11. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode. 12. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate. 13. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note 7 above) minus tS. 6 PALCE20V8 Military Switching Characteristics[2] 20V8−10 Parameter Description Max. Min. Max. Min. Max. Unit 1 10 1 15 1 25 ns 15 20 ns 15 20 ns 10 15 25 ns 10 15 25 ns 20 ns Input to Output Propagation Delay[8] tPZX OE to Output Enable 10 tPXZ OE to Output Disable 10 [7] [7,9] tER Input to Output Enable Delay Input to Output Disable Delay [8] 20V8−25 Min. tPD tEA 20V8−15 tCO Clock to Output Delay 1 tS Input or Feedback Set-Up Time 10 10 12 1 12 20 1 ns tH Input Hold Time 0 0 0 ns tP External Clock Period (t CO + tS) 20 24 40 ns tWH Clock Width HIGH[7] 8 10 15 ns tWL Clock Width LOW[7] 8 10 15 ns fMAX1 External Maximum Frequency (1/(tCO + tS)[7,10] 50 41.7 25 MHz fMAX2 Data Path Maximum Frequency (1/(tWH + tWL))[7, 11 ] 62.5 50 33.3 MHz fMAX3 Internal Feedback Maximum Frequency (1/(tCF + tS))[7,12] 62.5 50 33.3 MHz tCF Register Clock to Feedback Input[7, 13] tPR Power-Up Reset Time[7] 6 1 Shaded area contains preliminary information. 7 8 1 10 1 ns µs PALCE20V8 Switching Waveform INPUTS, I/O, REGISTERED FEEDBACK tS t WH tH t WL CP t CO tP tPXZ, tER[10] tEA, tPZX[10] [10] tEA, tPZX[10] REGISTERED OUTPUTS t PD tPXZ, tER COMBINATORIAL OUTPUTS 20V8–7 Power-Up Reset Waveform POWER SUPPLY VOLTAGE 10% VCC 90% t PR REGISTERED ACTIVE LOW OUTPUTS tS CLOCK tPR MAX = 1 µs 8 t WL 20V8–8 PALCE20V8 Functional Logic Diagram for PALCE20V8 PIN NUMBERS DIP(PLCC) PACKAGE PIN NUMBERS DIP(PLCC)PACKAGE 1 (2) 0 4 8 12 16 20 24 28 32 32 PTD 1 0 2 (3) 23 (27) CG0 0 MC7 CL1=2560 CL0=2632 22 (26) MC6 CL1=2561 CL0=2633 21 (25) MC5 CL1=2562 CL0=2634 20 (24) MC4 CL1=2563 CL0=2635 19 (23) MC3 CL1=2564 CL0=2636 18 (21) MC2 CL1=2565 CL0=2637 17 (20) MC1 CL1=2566 CL0=2638 16 (19) 280 3 (4) 320 600 4 (5) 640 920 5 (6) 960 1240 6 (7) 1280 1560 7 (9) 1600 1880 8 (10) 1920 2200 9 (11) 2240 MC0 CL1=2567 CL0=2639 15 (18) 2520 10 (12) 11 (13) 0 1 14 (17) CG0 13 (16) ELECTRONIC SIGNATURE ROW 2568 2569 . . . BYTE7 BYTE6 . . . . . . 2630 . . . BYTE1 2631 BYTE0 CG0=2704 CG1=2705 20V8–9 MSB LSB 9 PALCE20V8 Ordering Information for PALCE20V8 ICC (mA) tPD (ns) tS (ns) tCO (ns) 115 5 3 4 PALCE20V8−5JC 115 7.5 7 5 115 130 90 130 90 130 10 10 15 15 25 25 10 10 12 12 15 20 7 10 10 12 12 20 Ordering Code Package Name Package Type Operating Range J64 28-Lead Plastic Leaded Chip Carrier Commercial PALCE20V8−7JC J64 28-Lead Plastic Leaded Chip Carrier Commercial PALCE20V8−7PC P13 24-Lead (300-Mil) Molded DIP PALCE20V8−10JC J64 28-Lead Plastic Leaded Chip Carrier PALCE20V8−10PC P13 24-Lead (300-Mil) Molded DIP PALCE20V8−10QC Q13 24-Lead Quarter-Size Outline PALCE20V8−10JI J64 28-Lead Plastic Leaded Chip Carrier PALCE20V8−10PI P13 24-Lead (300-Mil) Molded DIP PALCE20V8−10DMB D14 24-Lead (300-Mil) CerDIP PALCE20V8−10LMB L64 28-Pin Square Leadless Chip Carrier PALCE20V8−15JC J64 28-Lead Plastic Leaded Chip Carrier PALCE20V8−15PC P13 24-Lead (300-Mil) Molded DIP PALCE20V8−15QC Q13 24-Lead Quarter-Size Outline PALCE20V8−15JI J64 28-Lead Plastic Leaded Chip Carrier PALCE20V8−15PI P13 24-Lead (300-Mil) Molded DIP PALCE20V8−15QI Q13 24-Lead Quarter-Size Outline PALCE20V8−15DMB D14 24-Lead (300-Mil) CerDIP PALCE20V8−15LMB L64 28-Pin Square Leadless Chip Carrier PALCE20V8−25JC J64 28-Lead Plastic Leaded Chip Carrier PALCE20V8−25PC P13 24-Lead (300-Mil) Molded DIP PALCE20V8−25QC Q13 24-Lead Quarter-Size Outline PALCE20V8−25JI J64 28-Lead Plastic Leaded Chip Carrier PALCE20V8−25PI P13 24-Lead (300-Mil) Molded DIP PALCE20V8−25QI Q13 24-Lead Quarter-Size Outline PALCE20V8−25DMB D14 24-Lead (300-Mil) CerDIP PALCE20V8−25LMB L64 28-Pin Square Leadless Chip Carrier Shaded area contains preliminary information. 10 Industrial Military Commercial Industrial Military Commercial Industrial Military PALCE20V8 Ordering Information for PALCE20V8L ICC (mA) tPD (ns) tS (ns) tCO (ns) 55 15 12 10 65 55 65 15 25 25 12 15 20 12 12 20 Ordering Code PALCE20V8L−15JC Package Name Package Type J64 28-Lead Plastic Leaded Chip Carrier PALCE20V8L−15PC P13 24-Lead (300-Mil) Molded DIP PALCE20V8L−15QC Q13 24-Lead Quarter-Size Outline PALCE20V8L−15JI J64 28-Lead Plastic Leaded Chip Carrier PALCE20V8L−15PI P13 24-Lead (300-Mil) Molded DIP PALCE20V8L−15QI Q13 24-Lead Quarter-Size Outline PALCE20V8L−15DMB D14 24-Lead (300-Mil) CerDIP PALCE20V8L−15LMB L64 28-Pin Square Leadless Chip Carrier PALCE20V8L−25JC J64 28-Lead Plastic Leaded Chip Carrier PALCE20V8L−25PC P13 24-Lead (300-Mil) Molded DIP PALCE20V8L−25QC Q13 24-Lead Quarter-Size Outline PALCE20V8L−25JI J64 28-Lead Plastic Leaded Chip Carrier PALCE20V8L−25PI P13 24-Lead (300-Mil) Molded DIP PALCE20V8L−25QI Q13 24-Lead Quarter-Size Outline PALCE20V8L−25DMB D14 24-Lead (300-Mil) CerDIP PALCE20V8L−25LMB L64 28-Pin Square Leadless Chip Carrier MILITARY SPECIFICATIONS Group A Subgroup Testing Switching Characteristics Parameter DC Characteristics Parameter Subgroups Subgroups tPD 9, 10, 11 tCO 9, 10, 11 9, 10, 11 9, 10, 11 VOH 1, 2, 3 tS VOL 1, 2, 3 tH VIH 1, 2, 3 VIL 1, 2, 3 IIX 1, 2, 3 IOZ 1, 2, 3 ICC 1, 2, 3 Document #: 38−00367−D 11 Operating Range Commercial Industrial Military Commercial Industrial Military PALCE20V8 Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL −STD−1835 D− 9 Config.A 28-Lead Plastic Leaded Chip Carrier J64 28-Square Leadless Chip Carrier L64 MIL−STD −1835 C−4 12 PALCE20V8 Package Diagrams (continued) 24-Lead (300-Mil) Molded DIP P13/P13A 24-Lead Quarter Size Outline Q13 © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.