19-4375; Rev 1; 5/10
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PART
TEMP RANGE
PIN-PACKAGE
MAX2038CCQ+D
0°C to +70°C
100 TQFP-EP*
MAX2038CCQ+TD
0°C to +70°C
100 TQFP-EP*
+ܭာᇄ)Qc*0९SpITܪᓰࡼॖᓤă
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U! >! ௳ࡒ۞ᓤă
*FQ! >! ൡă
*༿ݬఠ።ቧᇦᒦࡼިဉਖपࢾፃࡼJNE4 ݝॊă
୭ᒙᏴၫᓾ೯ࡼᔢઁ߲ă
________________________________________________________________ Maxim Integrated Products
1
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NBY3149
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NBY3149
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ABSOLUTE MAXIMUM RATINGS
VCC, VREF to GND .................................................-0.3V to +5.5V
Any Other Pins to GND...............................-0.3V to (VCC + 0.3V)
CW Mixer Output Voltage to GND (CW_IOUT+, CW_IOUT-,
CW_QOUT+, CW_QOUT-) ................................................13V
VGA Differential Input Voltage (VGIN_+, VGIN_-)............8.0VP-P
Analog Gain Control Differential Input Voltage
(VG_CTL+, VG_CTL-) ..................................................8.0VP-P
CW Mixer Differential Input Voltage
(CWIN_+, CWIN_-).......................................................8.0VP-P
CW Mixer LVDS LO Differential Input Voltage..................8.0VP-P
Continuous Power Dissipation (TA = +70°C)
100-Pin TQFP (derated 45.5mW/°C above +70°C)...3636.4mW
Operating Temperature Range...............................0°C to +70°C
Junction Temperature ......................................................+150°C
θJC (Note 1) .....................................................................+2°C/W
θJA (Note 1) ...................................................................+22°C/W
Storage Temperature Range .............................-40°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to china.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS—VGA MODE
(Typical Application Circuit, Figure 7. VCC = VREF = 4.75V to 5.25V, VCM = (3/5)VREF, TA = 0°C to +70°C, VGND = 0V, LOW_PWR = 0,
M4_EN = 0, CW_FILTER = 0 or 1, TEST_MODE = 0, PD = 0, CW_VG = 1, CW_M1 = 0, CW_M2 = 0, no RF signals applied, capacitance to GND at each of the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF,
RL = 1kΩ, CW mixer outputs pulled up to +11V through four separate ±0.1% 115Ω resistors, all CW channels programmed off.
Typical values are at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDTIONS
MIN
TYP
MAX
UNITS
4.75
5
5.25
V
4.75
5
5.25
V
PD = 0
204
231
PD = 1
27
33
VGA MODE
Supply Voltage Range
VCC
VCC External Reference
VREF
(Note 3)
Refers to VCC supply
current plus VREF current
Total Power-Supply Current
mA
VCC Supply Current
IVCC
192
216
mA
VREF Current
IREF
12
15
mA
Refers to VCC supply current
24
27
mA
Minimum gain
+2
Maximum gain
-2
Current Consumption per
Amplifier Channel
Differential Analog Control
Voltage Range
Differential Analog Control
Common-Mode Voltage
VCM
2.85
Analog Control Input
Source/Sink Current
VP-P
3
3.15
V
4.5
5
mA
LOGIC INPUTS
CMOS Input High Voltage
VIH
CMOS Input Low Voltage
VIL
2
2.3
_______________________________________________________________________________________
V
0.8
V
ૹ߅೫ڭവDXຫࡼ
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(Typical Application Circuit, Figure 7. V CC = V REF = 4.75V to 5.25V, T A = 0°C to +70°C, V GND = 0V, LOW_PWR = 0,
M4_EN = 0, CW_FILTER = 0 or 1, TEST_MODE = 0, PD = 0, CW_VG = 0, CW_M1 = 0, CW_M2 = 0, no RF signals applied,
capacitance to GND at each of the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF,
RL = 1kΩ, CW mixer outputs pulled up to +11V through four separate ±0.1% 115Ω resistors. Typical values are at VCC = VREF = 5V,
TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDTIONS
MIN
TYP
MAX
UNITS
CW MIXER MODE
Current in Full-Power Mode
5V VCC Supply
ICC_FP
Refers to VCC supply current (all 8 channels)
245
265
mA
Current in Full-Power Mode
11V VMIX Supply
IMIX_FP
Refers to VMIX supply current (all 8 channels)
106
120
mA
Current in Full-Power Mode
5V VREF Supply
IREF_FP
Refers to VREF supply current (all 8 channels)
17
21
mA
PDISS_FP
Total power dissipation (all 8 channels
including both 5V (VCC and VREF) and 11V
mixer pullup supply power dissipation in the
device) (Note 4)
2.15
2.41
W
Current in Low-Power Mode
5V VCC Supply
ICC_LP
LOW_PWR = 1; refers to VCC supply current
(all 8 channels)
245
265
mA
Current in Low-Power Mode
11V VMIX Supply
IMIX_LP
LOW_PWR = 1; refers to VMIX supply current
(all 8 channels)
53
60
mA
Current in Low-Power Mode
5V VREF Supply
IREF_LP
LOW_PWR = 1; refers to VREF supply current
(all 8 channels)
17
21
mA
PDISS_LP
LOW_PWR = 1; total power dissipation
(all 8 channels including both 5V (VCC and
VREF) and 11V mixer pullup supply power
dissipation in the device) (Note 4)
1.81
2.06
W
Mixer LVDS LO Input CommonMode Voltage
Modes 1 and 2 (Note 5)
1.25
±0.2
V
LVDS LO Differential Input
Voltage
Modes 1 and 2
700
mVP-P
LVDS LO Input
Common-Mode Current
Per pin
150
LVDS LO Differential
Input Resistance
Modes 1 and 2 (Note 6)
30
Mixer IF Common-Mode Output
Current
Common-mode current in each of the
differential mixer outputs (Note 7)
DATA Output High Voltage
DOUT voltage when terminated in DIN
(daisy chain) (Note 8)
DATA Output Low Voltage
DOUT voltage when terminated in DIN
(daisy chain) (Note 8)
Power Dissipation in Full-Power
Mode
Power Dissipation in Low-Power
Mode
200
3.25
200
μA
kΩ
3.75
4.5
mA
V
0.5
V
_______________________________________________________________________________________
3
NBY3149
DC ELECTRICAL CHARACTERISTICS—CW MIXER MODE
NBY3149
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AC ELECTRICAL CHARACTERISTICS—VGA MODE
(Typical Application Circuit, Figure 7. VCC = VREF = 4.75V to 5.25V, VCM = (3/5)VREF, TA = 0°C to +70°C, VGND = 0V, LOW_PWR = 0,
M4_EN = 0, CW_FILTER = 1, TEST_MODE = 0, PD = 0, CW_VG = 1, CW_M1 = 0, CW_M2 = 0, VG_CLAMP_MODE = 1, fRF = fLO/16
= 5MHz, capacitance to GND at each of the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is
10pF, RL = 1kΩ, CW mixer outputs pulled up to +11V through four separate ±0.1% 115Ω resistors, differential mixer inputs are driven
from a low impedance source. Typical values are at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
CW_VG set from logic 1 to 0 or from 0 to 1
(Note 9)
Mode Select Response Time
TYP
MAX
2
UNITS
μs
VGA MODE
Full-Scale Bandwidth
Small-Signal Bandwidth
f-1.3dB
f-1.3dB
Differential Input Resistance
RIN
Input Effective Capacitance
CIN
Differential Output Resistance
VOUT = 1.5VP-P,
1.3dB bandwidth,
gain = 10dB
Differential output
capacitance is 10pF,
capacitance to GND
at each single-ended
output is 60pF,
RL = 1kΩ
18
No capacitive load
RL = 1kΩ
29
MHz
VOUT = 1.5mVP-P, 3dB bandwidth,
gain = 10dB
30
170
fRF = 10MHz, each input to ground
ROUT
200
MHz
230
Ω
15
pF
100
Ω
Maximum Gain
+29.5
dB
Minimum Gain
-12.5
dB
42
dB
Gain Range
Absolute Gain Error
TA = +25°C, full gain range 0% to 100%,
VREF = 5V
VGA Gain Response Time
40dB gain change to within 1dB final value
1
μs
Input-Referred Noise
VG_CTL set for maximum gain,
no input signal
2
nV/√Hz
Output-Referred Noise
VG_CTL set for
+10dB of gain
Second Harmonic
Third-Order Intermodulation
Distortion
HD2
IMD3
±0.25
No input signal
22
VOUT = 1.5VP-P, 1kHz
offset
55
VG_CLAMP_MODE = 1, VG_CTL set for
+10dB of gain, fRF = 5MHz, VOUT = 1.5VP-P
±1.5
dB
nV/√Hz
-70
dBc
VG_CLAMP_MODE = 1, VG_CTL set for
+10dB of gain, fRF = 10MHz, VOUT = 1.5VP-P
-55
-65
VG_CLT set for +10dB of gain, fRF1 = 5MHz,
fRF2 = 5.01MHz, VOUT = 1.5VP-P,
VREF = 5V (Note 3)
-40
-52
dBc
Channel-to-Channel Crosstalk
VOUT = 1VP-P differential, fRF = 10MHz,
VG_CTL set for +10dB of gain
-80
dB
Maximum Output Voltage at
Clamp ON
VG_CLAMP_MODE = 0, VG_CTL set for
+20dB of gain, 350mVP-P differential input
2.4
VP-P
differential
4
_______________________________________________________________________________________
ૹ߅೫ڭവDXຫࡼ
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(Typical Application Circuit, Figure 7. VCC = VREF = 4.75V to 5.25V, TA = 0°C to +70°C, VGND = 0V, LOW_PWR = 0, M4_EN = 0,
CW_FILTER = 1, TEST_MODE = 0, PD = 0, CW_VG = 0, CW_M1 = 0, CW_M2 = 0, VG_CLAMP_MODE = 1, fRF = fLO/16 = 5MHz,
capacitance to GND at each of the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF, RL =
1kΩ, CW mixer outputs pulled up to +11V through four separate ±0.1% 115Ω resistors, differential mixer inputs are driven from a low
impedance source. Typical values are at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
Maximum Output Voltage at
ClampOFF
CONDITIONS
MIN
VG_CLAMP_MODE = 1, VG_CTL set for
+20dB of gain, 350mVP-P differential input
TYP
MAX
UNITS
VP-P
differential
2.8
CW MIXER MODE
Mixer RF Frequency Range
0.9
7.6
MHz
Mixer LO Frequency Range
1
7.5
MHz
Mixer IF Frequency Range
100
kHz
Maximum Input Voltage Range
1.8
VP-P
differential
Differential Input Resistance
633
CW_FILTER = 1
1440
Mode 3, fRF = fLO/4 = 1.25MHz, measured at a
1kHz offset frequency; clutter tone at 0.9VP-P
differential measured at the mixer input
Input-Referred Noise Voltage
Third-Order Intermodulation
Distortion
CW_FILTER = 0
IMD3
Ω
6
nV/√Hz
Mode 3, RF terminated into 50Ω; fLO/4 =
1.25MHz, measured at 1kHz offset
4.6
Mode 1, fRF1 = 5MHz at 0.9VP-P differential
input, Doppler tone fRF2 = 5.01MHz at 25dBc
from clutter tone, fLO/16 = 5MHz (Note 10)
-50
Mixer Output Voltage Compliance
(Note 11)
Channel-to-Channel Phase
Matching
Measured under zero beat conditions,
fRF = 5MHz, fLO/16 = 5MHz (Note 12)
±3.0
Degrees
Channel-to-Channel Gain
Matching
Measured under zero beat conditions,
fRF = 5MHz, fLO/16 = 5MHz (Note 12)
±2
dB
CW_FILTER = 1
2.8
Transconductance (Note 13)
CW_FILTER = 0
4.75
dBc
fRF = 1.1MHz, 1VP-P
differential, fLO/16 = 1MHz
12
2.8
V
mS
_______________________________________________________________________________________
5
NBY3149
AC ELECTRICAL CHARACTERISTICS—CW MIXER MODE
NBY3149
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AC ELECTRICAL CHARACTERISTICS—CW MIXER MODE (continued)
(Typical Application Circuit, Figure 7. VCC = VREF = 4.75V to 5.25V, TA = 0°C to +70°C, VGND = 0V, LOW_PWR = 0, M4_EN = 0,
CW_FILTER = 1, TEST_MODE = 0, PD = 0, CW_VG = 0, CW_M1 = 0, CW_M2 = 0, VG_CLAMP_MODE = 1, fRF = fLO/16 = 5MHz,
capacitance to GND at each of the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF, RL =
1kΩ, CW mixer outputs pulled up to +11V through four separate ±0.1% 115Ω resistors, differential mixer inputs are driven from a low
impedance source. Typical values are at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
MHz
SERIAL SHIFT REGISTER
Serial Shift Register
Programming Rate
Minimum Data Set-Up Time
tDSU
30
ns
Minimum Data Hold Time
tHLD
2
ns
Minimum Data Clock Time
tDCLK
100
ns
Minimum Data Clock Pulse Width
High
tDCLKPWH
30
ns
Minimum Data Clock Pulse Width
Low
tDCLKPWL
30
ns
tLD
30
ns
tMIXCLK
30
ns
tCLH
30
ns
Minimum Load Line
Minimum Load Line High to
Mixer Clock On
Minimum Data Clock to Load
Line High
Note 2: Specifications at TA = +25°C and TA = +70°C are guaranteed by production test. Specifications at TA = 0°C are guaranteed by design and characterization.
Note 3: Noise performance of the device is dependent on the noise contribution from the supply to VREF. Use a low-noise supply for
VREF. VCC and VREF can be connected together to share the same supply voltage if the supply for VCC exhibits low noise.
Note 4: Total on-chip power dissipation is calculated as PDISS = VCC x ICC + VREF x IREF + [11V - (IMIX/4) x 115] x IMIX.
Note 5: Note that the LVDS CWD LO clocks are DC-coupled. This is to ensure immediate synchronization when the clock is first
turned on. An AC-coupled LO is problematic in that the RC time constant associated with the coupling capacitors and the
input impedance of the pin causes there to be a period of time (related to the RC time constant) when the DC level on the
chip side of the capacitor is outside the acceptable common-mode range and the LO swing does not exceed both the
logic thresholds required for proper operation. This problem associated with AC-coupling would cause an inability to
ensure synchronization among beam-forming channels. The LVDS signal is terminated differentially with an external 100Ω
resistor on the board.
Note 6: External 100Ω resistor terminates the LVDS differential signal path.
Note 7: The mixer common-mode current (3.25mA/channel) is specified as the common-mode current in each of the differential
mixer outputs (CW_QOUT+, CW_QOUT-, CW_IOUT+, CW_IOUT-).
Note 8: Specification guaranteed only for DOUT driving DIN of the next device in a daisy-chain fashion.
Note 9: This response time does not include the CW output highpass filter. When switching to VGA mode, the CW outputs stop
drawing current and the output voltage goes to the rail. If a highpass filter is used, the recovery time can be excessive and
a switching network is recommended as shown in the Applications Information section.
Note 10: See the Ultrasound-Specific IMD3 Specification in the Applications Information section.
Note 11: Mixer output-voltage compliance is the range of acceptable voltages allowed on the CW mixer outputs.
Note 12: Channel-to-channel gain-and-phase matching measured on 30 pieces during engineering characterization at room temperature. Each mixer is used as a phase detector and produces a DC voltage in the IQ plane. The phase is given by the
angle of the vector drawn on that plane. Multiple channels from multiple parts are compared to each other to produce the
phase variation.
Note 13: Transconductance is defined as the quadrature summing of the CW differential output current at baseband divided by the
mixer’s input voltage.
6
_______________________________________________________________________________________
ૹ߅೫ڭവDXຫࡼ
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-50
0
VOUT = 1VP-P DIFFERENTIAL
-10
-20
3.0
2.5
2.0
-60
IMD3 (dBc)
PSMR (dBc)
3.5
-70
-30
f = 10MHz
-40
-50
-80
1.5
-60
1.0
-90
0
-100
7.5 10.0 12.5 15.0 17.5 20.0
-80
0
25
FREQUENCY (MHz)
50
75
100 125 150 175 200
-15
-5
5
FREQUENCY (kHz)
15
25
35
GAIN (dB)
SECOND HARMONIC DISTORTION
vs. GAIN
THIRD HARMONIC DISTORTION
vs. GAIN
0
-10
f = 2MHz
VOUT = 1VP-P DIFFERENTIAL
0
-20
-10
MAX2038 toc05
5.0
VOUT = 1VP-P DIFFERENTIAL
-20
-30
-30
f = 12MHz
-40
HD3 (dBc)
2.5
MAX2038 toc04
0
f = 5MHz
-70
0.5
HD2 (dBc)
OVERDRIVE PHASE DELAY (ns)
VOUT = 1.5VP-P DIFFERENTIAL
VMOD = 50mVP-P, fCARRIER = 5MHz,
GAIN = 10dB
MAX2038 toc02
VIN1 = 35mVP-P DIFFERENTIAL
VIN2 = 87.5mVP-P DIFFERENTIAL
GAIN = 20dB
4.0
-40
MAX2038 toc01
5.0
4.5
TWO-TONE ULTRASOUND-SPECIFIC
IMD3 vs. GAIN
POWER-SUPPLY MODULATION RATIO
MAX2038 toc03
OVERDRIVE PHASE DELAY
vs. FREQUENCY
-50
-60
-70
f = 12MHz
-40
f = 5MHz
-50
-60
-70
f = 5MHz
-80
-80
-90
f = 2MHz
-90
f = 2MHz
-100
-100
-15
-5
5
15
25
35
-15
GAIN (dB)
-5
5
15
35
OVERLOAD RECOVERY TIME
OVERLOAD RECOVERY TIME
MAX2038 toc07
MAX2038 toc06
f = 5MHz
f = 5MHz
DIFFERENTIAL
OUTPUT
1.0V/div
OUTPUT 1VP-P TO OVERLOAD AND BACK TO 1VP-P
DIFFERENTIAL
OUTPUT
2.0V/div
DIFFERENTIAL
INPUT
2.0V/div
DIFFERENTIAL
INPUT
1.0V/div
400ns/div
25
GAIN (dB)
OUTPUT 100mVP-P TO OVERLOAD
AND BACK TO 100mVP-P
400ns/div
_______________________________________________________________________________________
7
NBY3149
``````````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ
(Figure 7, VCC = VREF = 4.75V to 5.25V, VGND = 0V, PD = 0V, VG_CLAMP_MODE = 1, fRF = 5MHz, capacitance to GND at each of
the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF, RL = 1kΩ, TA = 0°C to +70°C. Typical
values are at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.)
``````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ*
(Figure 7, VCC = VREF = 4.75V to 5.25V, VGND = 0V, PD = 0, VG_CLAMP_MODE = 1, fRF = 5MHz, capacitance to GND at each of
the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF, RL = 1kΩ, TA = 0°C to +70°C. Typical
values are at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.)
-85
-70
-80
-90
-90
-95
-100
-5
5
15
25
30
20
10
0
1
35
10
-15
100
GAIN vs. DIFFERENTIAL ANALOG
CONTROL VOLTAGE (VG_CTL)
40
MAX2038 toc11
25
35
GAIN (dB)
15
5
VOUT = 1.5VP-P DIFFERENTIAL
VG_CTL = -2VP-P DIFFERENTIAL
-5
-15
-25
30
30
20
25
15
20
0.5
1.5
5
10
0
5
-5
-10
0.1
2.5
1
LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
15
10
MAX2038 toc14
VOUT = 1.5VP-P DIFFERENTIAL
VG_CTL = +0.6VP-P DIFFERENTIAL
10
100
5
-10
GAIN (dB)
-5
GAIN (dB)
5
-10
-5
-15
-20
-25
-15
-25
-30
-20
-30
10
FREQUENCY (MHz)
100
1000
1000
-15
-10
1
VOUT = 1VP-P DIFFERENTIAL
VG_CTL = +1.7VP-P DIFFERENTIAL
0
-5
0.1
100
LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
0
-20
10
LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
10
0
1
FREQUENCY (MHz)
VOUT = 1.5VP-P DIFFERENTIAL
VG_CTL = +1.5VP-P
5
0.1
1000
FREQUENCY (MHz)
VG_CTL (VP-P DIFFERENTIAL)
20
35
10
15
MAX2038 toc15
-0.5
25
VOUT = 1.5VP-P DIFFERENTIAL
VG_CTL = -1VP-P DIFFERENTIAL
25
0
-1.5
15
LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
GAIN (dB)
f = 5MHz
5
GAIN (dB)
LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
35
-2.5
-5
FREQUENCY (MHz)
GAIN (dB)
MAX2038 toc12
-15
MAX2038 toc10
40
-110
-100
GAIN (dB)
f = 5MHz
MAX2038 toc13
-80
-60
50
MAX2038 toc16
-75
OUTPUT-REFERRED NOISE VOLTAGE (nV/√Hz)
-50
CROSSTALK (dB)
CROSSTALK (dB)
VOUT = 1VP-P DIFFERENTIAL
GAIN = 10dB, ADJACENT CHANNELS
-40
-70
8
MAX2038 toc09
VOUT = 1.5VP-P DIFFERENTIAL
f = 10MHz, ADJACENT CHANNELS
-65
-30
MAX2038 toc08
-60
OUTPUT-REFERRED NOISE VOLTAGE
vs. GAIN
CHANNEL-TO-CHANNEL CROSSTALK
vs. FREQUENCY
CHANNEL-TO-CHANNEL CROSSTALK
vs. GAIN
GAIN (dB)
NBY3149
ૹ߅೫ڭവDXຫࡼ
ިဉWHB
-35
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
FREQUENCY (MHz)
_______________________________________________________________________________________
100
1000
ૹ߅೫ڭവDXຫࡼ
ިဉWHB
-10
-20
-25
-30
THIRD HARMONIC
-40
-50
-60
-70
SECOND HARMONIC
-80
-50
-55
-65
-70
-75
-85
-90
-95
-100
10
100
1000
0
0.5
1.0
1.5
2.0
SECOND HARMONIC
-80
-100
1
THIRD HARMONIC
-60
-40
2.5
3.0
200
500
800
1100
1400
1700
2000
FREQUENCY (MHz)
DIFFERENTIAL OUTPUT VOLTAGE (VP-P)
DIFFERENTIAL OUTPUT LOAD (Ω)
HARMONIC DISTORTION
vs. DIFFERENTIAL OUTPUT LOAD CAPACITANCE
HARMONIC DISTORTION
vs. FREQUENCY
TWO-TONE ULTRASOUND-SPECIFIC IMD3
vs. FREQUENCY
-55
THIRD HARMONIC
-60
-65
-70
-75
SECOND HARMONIC
-80
-85
-90
25
45
65
85
-20
-30
THIRD HARMONIC
-40
-50
-60
-70
SECOND HARMONIC
-30
-40
-50
-80
-60
-70
0
105
10
20
30
40
50
0
5
10
15
20
25
DIFFERENTIAL OUTPUT LOAD (pF)
FREQUENCY (MHz)
FREQUENCY (MHz)
GAIN ERROR HISTOGRAM
OUTPUT COMMON-MODE OFFSET VOLTAGE
vs. GAIN
DIFFERENTIAL OUTPUT IMPEDANCE
MAGNITUDE vs. FREQUENCY
15
35
30
25
20
15
160
5
0
-15
0
-20
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
140
120
-5
5
GAIN ERROR (dB)
180
10
100
-10
10
200
|ZOUT|
OFFSET VOLTAGE (mV)
40
20
MAX2038 toc24
SAMPLE SIZE = 202 UNITS,
fIN_ = 5MHz, GAIN = 10dB
MAX2038 toc23
5
MAX2038 toc22
-20
VOUT = 1VP-P DIFFERENTIAL
GAIN = 10dB
-10
-100
-100
45
0
-90
-95
50
VOUT = 1VP-P DIFFERENTIAL
GAIN = 10dB
MAX2038 toc25
-50
0
-10
IMD3 (dBc)
VOUT = 1VP-P DIFFERENTIAL
f = 5MHz, GAIN = 10dB
-45
MAX2038 toc21
MAX2038 toc20
-40
HARMONIC DISTORTION (dBc)
-30
VOUT = 1VP-P DIFFERENTIAL
f = 5MHz, GAIN = 10dB
-45
-90
0.1
% OF UNITS
-20
-40
-35
HARMONIC DISTORTION (dBc)
GAIN (dB)
-15
VOUT = 1VP-P DIFFERENTIAL
f = 5MHz, GAIN = 10dB
HARMONIC DISTORTION (dBc)
-5
0
-10
HARMONIC DISTORTION
vs. DIFFERENTIAL OUTPUT LOAD RESISTANCE
MAX2038 toc18
VOUT = 0.5VP-P DIFFERENTIAL
VG_CTL = +2VP-P DIFFERENTIAL
HARMONIC DISTORTION (dBc)
MAX2038 toc17
0
HARMONIC DISTORTION
vs. DIFFERENTIAL OUTPUT VOLTAGE
MAX2038 toc19
LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
80
60
-15
-5
5
15
GAIN (dB)
25
35
0.1
1
10
100
FREQUENCY (MHz)
_______________________________________________________________________________________
9
NBY3149
``````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ*
(Figure 7, VCC = VREF = 4.75V to 5.25V, VGND = 0V, PD = 0, VG_CLAMP_MODE = 1, fRF = 5MHz, capacitance to GND at each of
the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF, RL = 1kΩ, TA = 0°C to +70°C. Typical
values are at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.)
``````````````````````````````````````````````````````````````````` ࢜ቯᔫᄂቶ)ኚ*
(Figure 7, VCC = VREF = 4.75V to 5.25V, VGND = 0V, LOW_PWR = 0, M4_EN = 0, CW_FILTER = 1, TEST_MODE = 0, PD = 0, CW_VG
= 0, CW_M1 = 0, CW_M2 = 0, CW mixer outputs pulled up to 11V through four separate ±0.1% 115Ω resistors, differential mixer
inputs are driven from a low-impedance source.
CW FILTER RESPONSE
(CW_FILTER = 1)
CW FILTER RESPONSE
(CW_FILTER = 0)
2
0
MAX2038 toc27
5
MAX2038 toc26
4
0
-5
LOSS (dB)
LOSS (dB)
-2
-4
-6
-8
-10
-15
-20
-10
-25
-12
-30
-14
0
2
4
6
8
10
12
14
2
4
6
8
10
12
14
16
FREQUENCY (MHz)
FREQUENCY (MHz)
CW IMD3 vs. FREQUENCY
(MODE 1, VRF = 900mVP-P DIFF, VCC = VREF)
INPUT-REFERRED NOISE vs. CLUTTER VOLTAGE
(MODE 4, F_CLUTTER = 1.25MHz AT 1kHz OFFSET)
-48
-49
-50
-51
-52
4.75
5.00
5.25
-53
MAX2038 toc29
14
INPUT-REFERRED NOISE (nV/√Hz)
MAX2038 toc28
-47
12
10
8
6
4
2
-54
0
0
2
4
FREQUENCY (MHz)
10
0
16
-46
CW IMD3 (dBc)
NBY3149
ૹ߅೫ڭവDXຫࡼ
ިဉWHB
6
8
0
0.5
1.0
1.5
2.0
CLUTTER VOLTAGE (VP-P DIFF)
______________________________________________________________________________________
ૹ߅೫ڭവDXຫࡼ
ިဉWHB
୭
߂
ถ
1
CWIN2-
DXຫᄰࡸ3नሤތॊၒྜྷă
2
CWIN2+
DXຫᄰࡸ3ᄴሤތॊၒྜྷă
3
VGIN3-
WHBᄰࡸ4नሤތॊၒྜྷă
4
VGIN3+
WHBᄰࡸ4ᄴሤތॊၒྜྷă
5, 10, 19,
24, 29, 34,
58, 79,
81, 96
GND
ă
6
CWIN3-
DXຫᄰࡸ4नሤތॊၒྜྷă
7
CWIN3+
DXຫᄰࡸ4ᄴሤތॊၒྜྷă
8
VGIN4-
WHBᄰࡸ5नሤތॊၒྜྷă
9
VGIN4+
WHBᄰࡸ5ᄴሤތॊၒྜྷă
11
CWIN4-
DXຫᄰࡸ5नሤތॊၒྜྷă
12
CWIN4+
DXຫᄰࡸ5ᄴሤތॊၒྜྷă
13
EXT_C1
ᅪޡݗݝăᏴభถణத୭ࡼᆡᒙೌጙৈ5/8μG࢟ྏࡵLj᎖വดݝມᒙ࢟വă
14
EXT_C2
ᅪޡݗݝăᏴభถణத୭ࡼᆡᒙೌጙৈ5/8μG࢟ྏࡵLj᎖വดݝມᒙ࢟വă
15
EXT_C3
ᅪޡݗݝăᏴభถణத୭ࡼᆡᒙೌጙৈ5/8μG࢟ྏࡵLj᎖വดݝມᒙ࢟വă
16, 42, 46,
54, 72,
82, 87
VCC
17
VGIN5-
WHBᄰࡸ6नሤތॊၒྜྷă
18
VGIN5+
WHBᄰࡸ6ᄴሤތॊၒྜྷă
20
CWIN5-
DXຫᄰࡸ6नሤތॊၒྜྷă
21
CWIN5+
DXຫᄰࡸ6ᄴሤތॊၒྜྷă
22
VGIN6-
WHBᄰࡸ7नሤތॊၒྜྷă
23
VGIN6+
WHBᄰࡸ7ᄴሤތॊၒྜྷă
25
CWIN6-
DXຫᄰࡸ7नሤތॊၒྜྷă
26
CWIN6+
DXຫᄰࡸ7ᄴሤތॊၒྜྷă
27
VGIN7-
WHBᄰࡸ8नሤތॊၒྜྷă
28
VGIN7+
WHBᄰࡸ8ᄴሤތॊၒྜྷă
30
CWIN7-
DXຫᄰࡸ8नሤތॊၒྜྷă
31
CWIN7+
DXຫᄰࡸ8ᄴሤތॊၒྜྷă
32
VGIN8-
WHBᄰࡸ9नሤތॊၒྜྷă
33
VGIN8+
WHBᄰࡸ9ᄴሤތॊၒྜྷă
35
CWIN8-
DXຫᄰࡸ9नሤތॊၒྜྷă
36
CWIN8+
DXຫᄰࡸ9ᄴሤތॊၒྜྷă
6W࢟ᏎLjೌᒗ,6Wᅪ࢟ݝᏎăݧ1/2μG࢟ྏവWDD ࢟ᏎᒗLjభถణத୭ڔᓤ࢟ྏă
______________________________________________________________________________________
11
NBY3149
``````````````````````````````````````````````````````````````````````````` ୭ႁී
NBY3149
ૹ߅೫ڭവDXຫࡼ
ިဉWHB
``````````````````````````````````````````````````````````````````````` ୭ႁී)ኚ*
12
୭
߂
ถ
37, 93
VREF
,6Wᓰ࢟ᏎLjೌᒗࢅᐅဉ࢟ᏎăᏴభถణத୭ࡼᆡᒙݧ1/2μG࢟ྏവᒗHOEăᓖፀLj
ୈࡼᐅဉቶถᎧWSFG ࢟Ꮞᐅဉࡼ፬ሰᎌਈăWSFG ኍဧࢅᐅဉ࢟ᏎăྙਫWDD ᆐࢅᐅဉ࢟ᏎLjభጲ
WDD ਜ਼WSFG ೌᏴጙৢጙৈ࢟Ꮞă
38
EXT_RES
39
CW_VG
40
PD
41
CW_FILTER
43
M4_EN
44
LOW_PWR
45
DOUT
47
N.C.
ᇄೌLjক୭ॳహ)ᏴNBY3149ຶৰۇၫᓾ೯ᒦLjক୭ᆐUFTU`NPEF୭*ă
48
LO8
ᄰࡸ9ࡼDX! MPၒྜྷLjෝါ4ਜ਼5ࡼMPဟᒩၒྜྷă
49
VGOUT8+
WHBᄰࡸ9ᄴሤތॊၒ߲ă
50
VGOUT8-
WHBᄰࡸ9नሤތॊၒ߲ă
51
LO7
52
VGOUT7+
WHBᄰࡸ8ᄴሤތॊၒ߲ă
53
VGOUT7-
WHBᄰࡸ8नሤތॊၒ߲ă
55
LO6
56
VGOUT6+
57
VGOUT6-
59
LO5
60
VGOUT5+
WHBᄰࡸ6ᄴሤތॊၒ߲ă
61
VGOUT5-
WHBᄰࡸ6नሤތॊၒ߲ă
62
VG_CTL-
63
VG_CTL+
WHBෝผᐐፄ఼ᒜތॊၒྜྷăތॊ఼ᒜ࢟ኹᒙᏴ.3WဟLjᄋᔢࡍᐐፄ),3:/6eC*Ǘތॊ఼ᒜ࢟ኹᒙ
Ᏼ,3WဟLjᄋᔢቃᐐፄ).23/6eC*ă
64
LO_LVDS-
DX! MWET! MPनሤތॊၒྜྷăෝါ2ਜ਼3ࡼMPဟᒩनሤၒྜྷă
65
LO_LVDS+
66
LO4
67
VGOUT4+
68
VGOUT4-
69
LO3
ᅪ࢟ݝᔜăᏴభถణத୭ࡼᆡᒙೌጙৈ1/2&ࡼ8/6lΩ࢟ᔜᒗLjೂดݝມᒙ࢟വࡼມኹă
DXຫWHBဧถLjኡᐋWHBDXຫᔫෝါăDX`WHᒙᆐ൝࢟ຳLjဧถWHBLjᄴဟ
ਈࣥDXຫăDX`WHᒙᆐ൝ࢅ࢟ຳLjဧถDXຫLjᄴဟਈࣥWHBă
ਈࣥఎਈăདࣅQEᒗ࢟ຳLjୈᒙᆐਈࣥෝါăདࣅQEᒗࢅ࢟ຳLjᐌྜྷܪᓰᔫෝါă
DX݆୯ຫൈኡᐋLjኡᐋDXᄰࡸดࢅݝᄰ݆ࡼ୯ຫൈăDX`GJMUFSᒙ᎖൝࢟ຳဟLj୯ຫ
ൈᆐ:/6NI{ǗDX`GJMUFSᒙ᎖൝ࢅ࢟ຳဟLj୯ຫൈᆐ5/6NI{ă
ෝါ5ဧถLjN5`FOᒙ᎖൝࢟ຳணᒏࠈቲ࣡ాLj݀ఎཝݝ9ৈDXᄰࡸă
ࢅဧถLjᒙᆐ࢟ຳဟဧถୈDXຫࡼࢅෝါă
ࠈాၫၒ߲ăၫၒ଼߲છ೫DXᄰࡸࡼೌLjᑽߒෝผ݆ၦ߅ተ߈ܠă
ᄰࡸ8ࡼDX! MPၒྜྷăෝါ4ਜ਼5ࡼMPဟᒩၒྜྷă
ᄰࡸ7ࡼDX! MPၒྜྷăෝါ4ਜ਼5ࡼMPဟᒩၒྜྷă
WHBᄰࡸ7ᄴሤތॊၒ߲ă
WHBᄰࡸ7नሤތॊၒ߲ă
ᄰࡸ6ࡼDX! MPၒྜྷLjෝါ4ਜ਼5ࡼMPဟᒩၒྜྷă
DX! MWET! MPᄴሤތॊၒྜྷăෝါ2ਜ਼3ࡼMPဟᒩᄴሤၒྜྷă
ᄰࡸ5ࡼDX! MPၒྜྷăෝါ4ਜ਼5ࡼMPဟᒩၒྜྷă
WHBᄰࡸ5ᄴሤތॊၒ߲ă
WHBᄰࡸ5नሤތॊၒ߲ă
ᄰࡸ4ࡼDX! MPၒྜྷLjෝါ4ਜ਼5ࡼMPဟᒩၒྜྷă
______________________________________________________________________________________
ૹ߅೫ڭവDXຫࡼ
ިဉWHB
୭
߂
ถ
70
VGOUT3+
WHBᄰࡸ4ᄴሤތॊၒ߲ă
71
VGOUT3-
WHBᄰࡸ4नሤތॊၒ߲ă
ᄰࡸ3ࡼDX! MPၒྜྷLjෝါ4ਜ਼5ࡼMPဟᒩၒྜྷă
73
LO2
74
VGOUT2+
WHBᄰࡸ3ᄴሤތॊၒ߲ă
75
VGOUT2-
WHBᄰࡸ3नሤތॊၒ߲ă
76
LO1
77
VGOUT1+
WHBᄰࡸ2ᄴሤތॊၒ߲ă
78
VGOUT1-
WHBᄰࡸ2नሤތॊၒ߲ă
80
DIN
ࠈాၫၒྜྷLjࠈ߈ܠቲጤᆡࡀࡼၫၒྜྷă
83
CLK
ࠈాၫဟᒩLjࠈ߈ܠቲጤᆡࡀࡼဟᒩၒྜྷă
84
CW_M1
DXෝါኡᐋၒྜྷ2ă᎖ᒙ݆ၦ߅ተෝါ2Ă3Ă4ਜ਼5ࡼၒྜྷLjਈ᎖ෝါࡼ߈ܠሮᇼቧᇦ༿ݬఠܭ2ă
85
CW_M2
DXෝါኡᐋၒྜྷ3ă᎖ᒙ݆ၦ߅ተෝါ2Ă3Ă4ਜ਼5ࡼၒྜྷLjਈ᎖ෝါࡼ߈ܠሮᇼቧᇦ༿ݬఠܭ2ă
86
VG_CLAMP_
MODE
WHBὥᆡෝါဧถăདࣅWH`DMBNQ`NPEFᒗࢅ࢟ຳLjဧถWHBὥᆡෝါLjWHBၒ߲ۻὥᆡᒗ3/5WQ.Q
ތॊ࢟ኹǗདࣅWH`DMBNQ`NPEFᒗ࢟ຳLjணᒏWHBὥᆡෝါă
88
LOAD
89
CW_QOUT+
DXຫᑵୣ)R*ᄰࡸᄴሤތॊၒ߲Lj9വຫᑵୣᄰࡸࡼDXຫၒ߲ă
90
CW_QOUT-
DXຫᑵୣ)R*ᄰࡸनሤތॊၒ߲Lj9വຫᑵୣᄰࡸࡼDXຫၒ߲ă
91
CW_IOUT-
DXຫᄴሤᄰࡸ)J*ࡼތॊनሤၒ߲Lj9വຫᄴሤᄰࡸࡼDXຫၒ߲ă
92
CW_IOUT+
DXຫᄴሤᄰࡸ)J*ࡼތॊᄴሤၒ߲Lj9വຫᄴሤᄰࡸࡼDXຫၒ߲ă
ᄰࡸ2ࡼDX! MPၒྜྷLjෝါ4ਜ਼5ࡼMPဟᒩၒྜྷă
ࠈాᓤᏲăᄰਭࠈቲጤᆡࡀၫᓤᏲࡵJ0RॊሤăMPBEᔐሣᎅ࢟ຳ౯ᒗࢅ࢟ຳLjઁ
Ᏻᎅࢅ࢟ຳ౯ᒗ࢟ຳઁLjభ࣪J0Rॊሤቲ߈ܠă
94
VGIN1-
WHBᄰࡸ2नሤތॊၒྜྷă
95
VGIN1+
WHBᄰࡸ2ᄴሤތॊၒྜྷă
97
CWIN1-
DXຫᄰࡸ2नሤތॊၒྜྷă
98
CWIN1+
DXຫᄰࡸ2ᄴሤތॊၒྜྷă
99
VGIN2-
WHBᄰࡸ3नሤތॊၒྜྷă
100
VGIN2+
WHBᄰࡸ3ᄴሤތॊၒྜྷă
—
EP
ൡLjดೌݝᒗHOEăFQೌᒗࡍෂ૩QDCຳෂLjጲᔢࡍሢࣞᄋྲེถೆă
______________________________________________________________________________________
13
NBY3149
``````````````````````````````````````````````````````````````````````` ୭ႁී)ኚ*
NBY3149
ૹ߅೫ڭവDXຫࡼ
ިဉWHB
``````````````````````````````` ሮᇼႁී
NBY3149ဵጙ9ᄰࡸWHBLjૹ߅೫9വభ߈ܠᑵୣຫ
ᑫLjᓜᆐިဉ߅ስਜ਼໋ࣶಗ።ऎଐăୈளਭ
ᎁછᎌࢅĂࣅზपᆍਜ਼ިࢅᐅဉᒎܪăWHBᄰ
ࡸᎌތॊၒྜྷĂෝผభܤᐐፄ఼ᒜĂభᒇདࣅBED
ࡼތॊၒ߲ጲૺభኡᐋࡼၒ߲࢟ኹὥᆡLjጲऴᒏBEDਭ
དࣅăૹ߅9ᄰࡸᑵୣຫᑫ۞౪ࠈቲభ߈ܠMPሤᆡ
खညLj᎖DXE݆ၦ߅ተăMPॊሤభጲᒙᆐ5Ă9Ă
27ৈᑵୣሤᆡăࢅᄰ݆ૹ߅᎖ඛৈDXຫࡼၒྜྷ
ᄰࡸăຫၒ߲ሤଝࡵJ0Rތॊ࢟ഗၒ߲ă
NBY3149ૹ߅೫9ᄰࡸᑵୣຫᑫਜ਼భ߈ܠMPሤᆡ
खညLjభ৩ᅲᑳࡼೌኚ݆)DX*໋ࣶಗ݆ၦ߅ተऱښă
ඛৈᄰࡸࡼMPሤᆡኡᐋభᄰਭၫᔊࠈాਜ਼ৈຫဟᒩ
߈ܠLjऎඛৈআຫ࣪ࡼMPభݧࣖೂࡼ5! y! MPဟ
ᒩᒇདࣅăࠈቲాဧࣶৈୈ༵႕ဣሚLj࠭ऎ
ᔢࡍሢࣞିೌా߈ܠሣăMPॊሤభጲᒙᆐ5Ă
9Ă27ৈᑵୣሤᆡăඛৈDXຫࡼၒྜྷ۞భኡᐋࡼ
ࢅᄰ݆Lj᎖ᎁછDXEᐅဉᒎܪăຫၒ߲ሤଝ
ࡵJਜ਼Rތॊ࢟ഗၒ߲ăຫਜ਼MPखညଐᑽߒᎁፊ
ࡼᐅဉቶถǖ2/36NI{ Ᏺ݆Ă:11nW Q.Q ތॊᏭྲቧĂ
2lI{ຫມဟ.266eCd0I{ă
భܤᐐፄहࡍ)WHB*
NBY3149ࡼWHBளਭᎁછᎌሣቶࣞĂࣅზपᆍਜ਼ࢅ
ၒ߲ᐅဉᒎܪLjऻޟးިဉ߅ስᇹᄻăWHBᄰവᏴ21NI{
ဟᎌ.91eCࡼᄰࡸମࠈཷਜ਼ࢅ᎖±1/36eCࡼ࣪ᐐፄᇙ
ތLjถ৫Ᏼިဉᇹᄻᒦᄋᔢቃࡼᄰࡸମୡᇙތăඛവ
WHB۞ෝผᐐፄࢯஂ࢟വLj᎖དࣅBEDࡼތॊၒ߲
)WHPVU`,ĂWHPVU`.*દߡጲૺభጲᒇᎧNBY3145
႐ᄰࡸMOBᒇೌࡼތॊၒྜྷ)WHJO`,ĂWHJO`.*ăሮ
ᇼቧᇦ༿ݬఠ ݆ተຫਜ਼భ݆߈ܠၦ߅ተถ
ౖᅄă
WHBᎌ.23/6eCᒗ,3:/6eCభࢯᐐፄपᆍLjᎌ53eC! )࢜
ቯᒋ*ᔐࣅზपᆍăWHBᐐፄభጲᄰਭތॊᐐፄ఼ᒜၒྜྷ
WH`DUM,ਜ਼WH`DUM.ࢯஂăތॊᐐፄ఼ᒜၒྜྷ࢟ኹ
ᒙᆐ,3WဟᄋᔢቃᐐፄǗᒙᆐ.3Wဟᄋᔢࡍᐐፄă
ތॊෝผ఼ᒜৢෝ࢟ኹᆐ4W! )࢜ቯᒋ*ă
14
݆ተຫਜ਼
``````````````` భ݆߈ܠၦ߅ተถౖᅄ
+5V
+5V (LOW NOISE)
VCC
VREF
MAX2038
VG_CTL+
VG_CTL-
VG_CLAMP_MODE
50Ω
VGIN1+
VGIN1-
VGOUT1+
VGA
VGOUT150Ω
•
•
•
•
•
•
• •
• •
• •
•
•
•
•
•
•
50Ω
VGIN8+
VGOUT8+
VGA
VGIN8-
VGOUT850Ω
LOW_PWR
PD
CWIN1+
CW_IOUT+
CW_IOUT-
I&Q
CWIN1•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CWIN8+
I&Q
CWIN8-
CW_QOUT+
CW_QOUT-
CW_VG
CW_FILTER
GND
______________________________________________________________________________________
ૹ߅೫ڭവDXຫࡼ
ިဉWHB
ὥᆡถ᎖ሢᒜWHBၒ߲ቧLjܜBEDਭདࣅBED
ۥਜ਼ăᒙWH`DMBNQ`NPEFᒗࢅ࢟ຳLjWHBތॊၒ
߲ὥᆡᒗ3/5WQ.Q ǗᒙWH`DMBNQ`NPEFᒗ࢟ຳLjண
ὥᆡถă
ڭᄰࡸೌኚ݆ተ)DX*ຫ
ਈࣥ
ୈથభጲಽQEྜྷਈࣥෝါăQEᒙ᎖൝࢟ຳLj
ྜྷਈࣥෝါăਈࣥෝါሆLjୈஞሿ38nBࡼᔐ࢟ഗă
QEᒙ᎖൝ࢅ࢟ຳLjྜྷᑵޟᔫෝါă
NBY3149 DXຫଐݧᎌᏎၷຳੰଆၣăຫ
ᎌ୷ࡼࣅზपᆍਜ਼ሣቶࣞᒎܪLjᄴဟᎌऻࡼࢅޟ
ᐅဉLjభಯሯ᎖ިဉDXEቧ၃ăڭᄰࡸᑵୣ
ຫᑫᏴ2/36NI{Ᏺ݆Ă2lI{ຫມဟᎌ.266eCd0I{ࡼ
ᐅဉᒎܪLjથభᄋ࢜ቯᒋᆐ.61eCdࡼၷፒྯୣࢯࡼި
ဉᒎܪLj༿ݬఠ።ቧᇦݝॊࡼިဉਖपࢾፃࡼJNE4ă
ڭᄰࡸᑫࡒᎌᑵୣਜ਼ᄴሤތॊ࢟ഗၒ߲)DX`RPVU,Ă
DX`RPVU.ĂDX`JPVU,ਜ਼DX`JPVU.*LjޘညᔐࡼDXE
݆ၦ߅ተቧăᔢࡍތॊ࢟ഗၒ߲ᆐ4nB Q.Q ࢜ቯᒋLj
ຫၒ߲ରྏ᎖5/86Wᒗ23W࢟ኹपᆍă
ਭᏲૂআ
ୈளਭᎁછଐᎌႥਭᏲૂআถLjऻޟး࢜
ቯࡼ߅ስᇹᄻLjᑚቋᇹᄻࡼިဉၒྜྷદߡᄰޟᎌ୷
DXຫਜ਼
````````````````````````````````````````````````````````````` భ݆߈ܠၦ߅ተถౖᅄ
VCC
CWIN8
•
•
•
CWIN2
VREF
CW_FILTER
M4_EN
MAX2038
•
•
•
CW_IOUT+
CW_IOUTCW_IOUT2+
I Q
I Q
CHANNEL 1
I/Q
DIVIDER
PHASE
SELECTOR
CHANNEL 2
I/Q
DIVIDER
PHASE
SELECTOR
•
•
•
• •
•
CW_QOUT2-
CW_QOUT•
•
•
• •
•
CWIN1
CW_QOUT+
I Q
LOAD
5
DIN
•
•
•
• •
•
5
5-BIT
SR
5-BIT
SR
CW_M1
CW_M2
LO2
•
•
•
LO8
5
5-BIT
SR
•
•
•
LO_LVDS-
•
•
•
LO_LVDS+
•
•
•
• •
•
LO1
CHANNEL 8
I/Q
DIVIDER
PHASE
SELECTOR
DOUT
CLK
GND
LOW_PWR
PD
______________________________________________________________________________________
15
NBY3149
ࡍࡼၒྜྷቧLj༿ݬఠ ࢜ቯᔫᄂቶ ᒦਈ᎖ख႙ਭᏲࡼ
Ⴅૂআဟମာፀᅄă
WHBὥᆡ
NBY3149
ૹ߅೫ڭവDXຫࡼ
ިဉWHB
DXຫၒ߲߅
ڭവຫᑫࡼၒ߲Ᏼดݝ߅LjጲޘညᔐࡼDXE
߅݆ၦ߅ተቧăڭവᑫޘညڭവᑵୣᄰࡸ)R*ࡼތॊ
ၒ߲ਜ਼ڭവᄴሤ)J*ᄰࡸࡼތॊၒ߲ăჅᎌᑵୣĂᄴሤၒ
߲ᎧവJਜ਼Rތॊ࢟ഗၒ߲)DX`RPVU,ĂDX`RPVU.Ă
DX`JPVU,ਜ਼DX`JPVU.*ሤଝă
ܭ3/! ෝါ2൝)ܭC5! >! 1ǖᄰࡸࡴᄰ0
C5! >! 2ǖᄰࡸਈࣥ*
MODE 1
CW_M1 = 0
CW_M2 = 0
DXE݆ၦ߅ተෝါ
LSB
SHUTDOWN
PHASE
(DEG)
D
C
B
A
SD
(B0)
(B1)
(B2)
(B3)
(B4)
0
0
0
0
0
0/1
22.5
0
0
0
1
0/1
45
0
0
1
0
0/1
67.5
0
0
1
1
0/1
MPሤᆡኡᐋ
MPॊሤభᄰਭጤᆡࡀᒙᏴ5Ă9Ă27ৈᑵୣሤᆡLj
৩߅ᅲᑳࡼDX݆ၦ߅ተऱښă
MSB
90
0
1
0
0
0/1
DXE݆ၦ߅ተᎌ႐ᒬࣖೂෝါLjਈ᎖ݙᄴᔫෝါࡼႁ
ී༿ݬఠܭ2ăᔫෝါభᎅDX`N2ਜ਼DX`N3൝ၒྜྷ
ኡᐋLjሤᆡखညᄰਭࠈా఼ᒜăਈ᎖ݙᄴᑵୣሤᆡܠ
߈ቧᇦ༿ݬఠ።ቧᇦᒦࡼࠈాݝॊă
112.5
0
1
0
1
0/1
135
0
1
1
0
0/1
ෝါ2
ෝါ2ሆLjMP`MWETၒྜྷຫൈᄰޟᆐ27 y g MPăDXE MP
ຫൈपᆍᆐ2NI{ᒗ8/6NI{Ljᐌၒྜྷຫൈपᆍᆐ27NI{ᒗ
231NI{ăຫMPဟᒩገཇݧތॊMWETၒྜྷLj27! y! gMP
ၒྜྷளਭ27ॊຫLjޘည27ৈሤᆡăᑚ27ৈሤᆡ᎖9ৈᄰ
ࡸLjᄰਭጤᆡࡀኡᐋሤᆡ߈ܠăඛৈᄰࡸᎌሤ።
ࡼ6ᆡጤᆡࡀLj᎖ᒙ27ॊຫ࢟വࡼၒ߲ሤᆡăጤ
ᆡࡀࡼ༄5ᆡ᎖ᒙ27ৈሤᆡLj6ᆡࣖ᎖ඛ
ৈᄰࡸࡼᄰ0఼ࣥᒜă࣪᎖ෝါ2LjDX`N2ਜ਼DX`N3
ᒙᆐࢅ࢟ຳLjݬܭ3ă
157.5
0
1
1
1
0/1
180
1
0
0
0
0/1
202.5
1
0
0
1
0/1
0/1
225
1
0
1
0
247.5
1
0
1
1
0/1
270
1
1
0
0
0/1
292.5
1
1
0
1
0/1
315
1
1
1
0
0/1
337.5
1
1
1
1
0/1
NO. OF
DON’TCARE BITS
IN SSR
ܭ2/! DXE݆ၦ߅ተෝါ
LO INPUT
MODE
FREQUENCY
CLOCK
INTERFACE
PHASE
RESOLUTION
NO. OF
CLOCK
INPUTS
PER CHIP
PROGRAM
BY SERIAL
SHIFT
REGISTER
(SSR)
NO. OF
USEFUL
BITS IN
SSR
CW_M1
CW_M2
0
0
1
16 x
LVDS
16 phases
1
Yes
4
0
0
1
2
8x
LVDS
8 phases
1
Yes
3
1 MSB
1
0
3
4x
3V CMOS
4 phases
8
Yes
2
2 MSBs
3V CMOS
Quadrature
provided
8
No
N/A
N/A
1
1
4
4x
O0B! >! ݙభă
16
______________________________________________________________________________________
ૹ߅೫ڭവDXຫࡼ
ިဉWHB
ܭ4/! ෝါ3൝)ܭED! >! ᇄਈLjC5! >! 1ǖ
ᄰࡸࡴᄰ0C5! >! 2ǖᄰࡸਈࣥ*
MODE 2
CW_M1 = 0
CW_M2 = 1
MSB
LSB
SHUTDOWN
PHASE
(DEG)
D
C
B
A
SD
(B0)
(B1)
(B2)
(B3)
(B4)
0
DC
0
0
0
0/1
45
DC
0
0
1
0/1
90
DC
0
1
0
0/1
135
DC
0
1
1
0/1
180
DC
1
0
0
0/1
225
DC
1
0
1
0/1
270
DC
1
1
0
0/1
315
DC
1
1
1
0/1
ෝါ4
ࠥෝါݙኊገMP`MWETၒྜྷLjࣖೂࡼ5 y gMP ဟᒩၒྜྷᄰ
ਭMP2–MP9ᄋৈᄰࡸăDXE MPຫൈपᆍᆐ2NI{
ᒗ8/6NI{Ljᐌၒྜྷຫൈपᆍᆐ5NI{ᒗ41NI{ăᓖፀLjMP
ဟᒩຫൈభݧ4W! DNPTၒྜྷă5 y gMP MP2–MP9ၒྜྷள
ਭ5ॊຫޘည5ৈሤᆡăᑚ5ৈሤᆡ᎖9ৈᄰࡸLjభᄰਭ
ܭ5/! ෝါ4൝)ܭED! >! ᇄਈLjC5! >! 1ǖ
ᄰࡸࡴᄰ0C5! >! 2ǖᄰࡸਈࣥ*
MODE 3
CW_M1 = 1
CW_M2 = 0
MSB
LSB
SHUTDOWN
PHASE
(DEG)
D
C
B
A
SD
(B0)
(B1)
(B2)
(B3)
(B4)
0
DC
DC
0
0
0/1
90
DC
DC
0
1
0/1
180
DC
DC
1
0
0/1
270
DC
DC
1
1
0/1
ࠈቲጤᆡࡀኡᐋሤᆡă࣪᎖ෝါ4Ljᎅ᎖ᒑޘည5ৈ
ሤᆡLjፐࠥ5ৈሤᆡᒙᆡᒑ೫3ᆡLjऎᅪೝৈᆡ
Đᇄđă࣪᎖ෝါ4LjDX`N2ᒙ᎖൝࢟ຳLjDX`N3
ᒙ᎖൝ࢅ࢟ຳLj༿ݬఠܭ5ă
ෝါ5
কෝါݙးMP`MWETၒྜྷLjಽᅪࣖݝೂࡼ5 y gMP MP2–
MP9ၒྜྷᆐඛৈᄰࡸᄋးࡩࡼሤᆡăገཇݧ5! y! gMP ၒ
ྜྷLjጲܣୈดޘݝညறཀྵࡼĂᎧᐴహ܈ᇄਈࡼᑵୣMPད
ࣅăᓖፀLjࠥෝါݙဧࠈቲጤᆡࡀăDXE! MPຫൈ
पᆍᆐ2NI{ᒗ8/6NI{Ljၒྜྷຫൈपᆍᆐ5NI{ᒗ41NI{Lj
ಢ႒ၒྜྷᄰਭMP2ᒗMP9ᄋăᆐઓᄋআᆡ఼ᒜLjጲ
ۣߒჅᎌDXEᄰࡸᄴݛăআᆡ఼ᒜᄰਭSFTFUဣሚă࣪
᎖ෝါ5LjᒙDX`N2ਜ਼DX`N3ᒗ൝࢟ຳLj༿ݬఠ
ܭ6ă
ܭ6/! ෝါ5൝ܭ
MODE 4
CW_M1 = 1
CW_M2 = 1
PHASE
(DEG)
Serial bus
not used in
mode 4
MSB
LSB
SHUTDOWN
D
C
B
A
SD
(B0)
(B1)
(B2)
(B3)
(B4)
N/A
N/A
N/A
N/A
N/A
O0B! >! ݙభă
______________________________________________________________________________________
17
NBY3149
ෝါ3
ෝါ3ሆLjMP`MWETၒྜྷຫൈᆐ9 y g MP )࢜ቯᒋ*ăDXE
MPຫൈपᆍᆐ2NI{ᒗ8/6NI{Ljᐌၒྜྷຫൈपᆍᐌᆐ9NI{
ᒗ71NI{LjᑚጙຫMPဟᒩገཇݧތॊMWETၒྜྷă9 y
gMP ၒྜྷۻ9ॊຫLjޘည9ৈሤᆡăᑚ9ৈሤᆡ᎖9ৈᄰࡸLj
ᄰਭጤᆡࡀኡᐋሤᆡᒙăᓖፀLjࠈቲጤᆡࡀᏴ
ෝါ2Ă3Ă4ሆሤᄴLjᒦඛৈᄰࡸᎌሤ።ࡼ6ᆡጤᆡ
ࡀLj᎖ᒙၒ߲ሤᆡăᎅ᎖ෝါ3ஞޘည9ৈሤᆡLj
5ৈሤᆡᒙᆡᒦஞ೫4ᆡLjࡣጤᆡࡀ྆ᓤᏲ6ᆡ
ၫLjሤᆡࡼ߈ܠNTCᆡᇄăጤᆡࡀࡼ6ᆡᔐဵ
᎖ॊ఼ܰᒜඛৈᄰࡸࡼᄰ0ࣥă࣪᎖ෝါ3LjDX`N2
ᆡᒙᆐ൝ࢅ࢟ຳLj݀DX`N3ᒙᆐ൝࢟ຳLj༿ݬ
ఠܭ4ă
NBY3149
ૹ߅೫ڭവDXຫࡼ
ިဉWHB
DATA_IN
CLOCK
CHANNEL 1
A B C D SD
CHANNEL 2
A B C D SD
CHANNEL 3
A B C D SD
CHANNEL 4
A B C D SD
B3 B2 B1 B0 B4
B3 B2 B1 B0 B4
B3 B2 B1 B0 B4
B3 B2 B1 B0 B4
CHANNEL 5
A B C D SD
CHANNEL 6
A B C D SD
CHANNEL 7
A B C D SD
CHANNEL 8
A B C D SD
B3 B2 B1 B0 B4
B3 B2 B1 B0 B4
B3 B2 B1 B0 B4
B3 B2 B1 B0 B4
DATA_OUT
ᅄ2/! ࠈቲጤᆡࡀࡼၫഗ
ᄴݛ
ᅄ2߲೫ᄰਭࠈቲၫ࣡ా࣪9ৈࣖೂᄰࡸࠈቲࡼ߈ܠ
ഗ߈ăᓖፀLjࠈቲၫถ৫ጲऱါೌLjᄰਭጙᄟ
ၫሣဣሚᇹᄻࡼࣶበຢ߈ܠă
DXࢅᄰ݆
NBY3149ࡼඛৈDXތॊၒྜྷ࣪ਜ਼ሤ።ࡼຫၒྜྷᒄମ
થࡒᎌభኡᐋࡼࢅᄰ݆ăຢૹ߅೫݀ೊ࢟ྏਜ਼࢟ᔜLj
း᎖ࡒਜ਼ᐥࡒᒙă݀ೊ࢟ྏ0࢟ᔜᆀోᏴඛവDX
ތॊၒྜྷ࣡LjభᄰਭDX`GJMUFSኡᐋăདࣅDX`GJMUFS
ᒗ࢟ຳLj݆୯ຫൈᒙᆐǖgD >! :/6NI{ăདࣅDX`
GJMUFSᒗࢅ࢟ຳLj݆୯ຫൈᒙᆐǖg D > 5/6NI{ă
DX`WHᏤ݆ࡼၒྜྷᎧၒྜྷஂ࢛)በຢดࣥ*ݝఎLj࠭
ऎऴᒏMOBၒ߲ਭᏲLj݀༦ݙখܤWHBၒྜྷৢෝ࢟ኹă
WHBਜ਼DXຫᔫᏇಯ
ܪᓰᔫෝါLjNBY3149ᒙᆐWHBᄰࡸဧถऎຫ
ᑫਈࣥ)WHBෝါ*Ljᑗᒙᆐᑵୣຫᑫဧถऎ
WHBᄰࡸਈࣥ)DXෝါ*ăWHBෝါሆLj߹೫DXຫ
ᑫਈࣥᅪLjࢅᄰ݆ਜ਼DXຫࡼތॊၒྜྷᏴดݝ
Ꭷၒྜྷஂ࢛ࣥఎLjဧDXތॊၒྜྷ)DXJO`,ĂDXJO`.*ܤ
ᆐᔜზăDXෝါࣥఎWHBၒྜྷᎧୈၒྜྷ࣡ాࡼೌ
ăWHBෝါሆLjDX`WHᆐ൝࢟ຳǗDXෝါ
ሆLjᐌDX`WHᆐ൝ࢅ࢟ຳă
ਈࣥਜ਼ࢅෝါ
ୈਈࣥෝါሆLjᇄ൙DX`WHࠀ᎖ੜᒬ൝ᓨზLjWHB
ਜ਼DXຫਈࣥăᎅ᎖ೌࡵၒྜྷࡼดݝఎਈࠀ᎖
ਈࣥᓨზLjWHBਜ਼DXຫၒྜྷࠀ᎖ᔜზăୈࡼ
ᔐ࢟Ꮞ࢟ഗଢ଼ᒗ38nBăQEᒙᆐ൝࢟ຳဟLjୈࠀ᎖
ਈࣥᓨზă
ୈᄋࢅෝါLjጲଢ଼ࢅDXEෝါࡼăኡᐋࢅ
ෝါဟLjআຫᔫᏴৎࢅࡼஸზ࢟ഗሆLjඛ
ᄰࡸᔐ࢟ഗଢ଼ᒗ64nBăᓖፀLjᔫᏴࠥෝါဟLjୈࡼ
ࣅზቶถᎌଢ଼ࢅLjܭ7߲ܪᓰᔫෝါࡼ൝ၫă
ܭ7/! ܪᓰᔫෝါࡼ൝ၫ
PD
CW_VG
INPUT INPUT
LOW_PWR
VGA
CW
MIXER
INTERNAL
SWITCH
TO VGA
INTERNAL
SWITCH TO LPF
AND CW MIXER
5V VCC CURRENT
CONSUMPTION
(mA)
11V VMIX CURRENT
CONSUMPTION
(mA)
1
1
N/A
Off
Off
Off
Off
27
0
1
0
N/A
Off
Off
Off
Off
27
0
0
0
0
Off
On
Off
On
245
106
0
0
1
Off
On
Off
On
245
53
0
1
N/A
On
Off
On
Off
204
0
O0B! >! ݙభă
18
______________________________________________________________________________________
ૹ߅೫ڭവDXຫࡼ
ިဉWHB
ෝါኡᐋሰ።ဟମ
ෝါኡᐋሰ።ဟମܭာୈᏴDXਜ਼WHBෝါମ༤ધဟኊ
ገࡼဟମăᅄ3߲೫DXၒ߲ᎧጥܭहࡍೌLj᎖
དࣅBEDࡼጙᒬऱښăকऱښᒦLjඛৈDX`JPVU,ĂDX`
JPVU.ĂDX`RPVU,ĂDX`RPVU.Ꭷདࣅ࢟വᒄମৢᎌ
႐ৈࡍ࢟ྏ)᎖581oGᒗ2μGᒄମ*ăDXຫၒ߲ᄰޟ
᎖དࣅጥܭहࡍࡼၒྜྷLjᑚቋጥܭहࡍᎅᏥႯहࡍ
ᔝ߅Ljၒྜྷᔜఝᎅৢෝ࢟ኹᒙ࢟ᔜࢾă
115Ω
50Ω
ᆰᄌᏴ᎖Ljຫၒ߲Ꭷጥܭहࡍᒄମྀੜࡍቃးࡼ
ᒇഗ࢟ྏ્࣒ྜྷීመࡼဟମޟၫLj࠭ऎଢ଼ࢅෝါኡᐋ
ࡼ༤ધႥࣞă
ᅄ5߲೫ጙৈᅄ3ࡼᄐࡔऱښLjถ৫ဣሚႥෝါኡᐋࡼ
ሰ።ဟମă
115Ω
1μF
CW_IOUT-
ᑚಱࡼᄰ݆࢛ᆐgQ >! 20)3! y! π y! SD*LjࡍᏖᆐ6I{ă
ᓖፀLj୷ࢅࡼᄰ݆୯ຫൈ᎖߹ሆܤຫࡼᏭྲຫ
ൈLj߲ሚᏴᒇഗএதLjࡣ્ݙছཷࢅᒗ511I{ࡼDXE߅
ስቧăಿྙLjྙਫኊገݧࢅᒗ511I{ࡼDXELjᄰ݆
࢛ࡼᔢଛኡᐋ።কᒗᆐকຫൈࡼလॊᒄጙ)= 51I{*Lj
ۣᑺক્࢛࣪ݙᎌቧޘညၱିăᓖፀLjྙਫᄰ
݆࢛ᒙᆐ511I{Lj୯ຫൈࠀࡼຫሰ્ሆଢ଼4eCă
ಿᒦᄰ݆ࡼ࢛ݧ6I{Lj൸ᔗၤᄀ൙ᒇഗᒗ
51I{ࡼሢᒜă
31.6kΩ
0.022μF
+11V
31.6kΩ
CW_IOUT+
1μF
ᅄ3/! DXຫၒ߲࢟വࡼ࢜ቯपಿ
੪ීመLjᑚጙၒ߲ᆀࡒᎌᄰ݆ਜ਼ࢅᄰ݆ăࢅ
ᄰ݆ࡼ୯ຫൈᓍገᎅ226Ωຫ౯࢟ᔜĂ61Ωࠈೊ
࢟ᔜጲૺ1/133μG݀ೊ࢟ྏࢾăࢅᄰ݆᎖߹MP
ቛധਜ਼ࡼࡒܟᔝᐅဉăᄰ݆ࡼ୯ຫൈᓍገᎅ
2μGᒇഗ࢟ྏਜ਼42/7lΩ݀ೊ࢟ᔜࢾLjኊገடဇఠă
଼છઁࡼᄰ݆ྙᅄ4Ⴥာă
+5V
ᅄ5/! ᒇഗẮၒྜྷᒗጥܭहࡍLjጲখ࿖ෝါኡᐋࡼሰ።ဟମ
1μF
31.6kΩ
ᅄ5ᒦLjDXEຫࡼၒ߲ᎧጥܭहࡍᒇഗẮăፐࠥ
ᏥႯहࡍܘኍถ৫ᑽߒຫၒ߲ࡼཝݝपᆍLjࡩຫ
ணᒏဟᔢࡍᆐ22WLjࡩຫဧถဟࢅᒗ6WࡼNBY3149
࢟Ꮞ࢟ኹăᏥႯहࡍభᎅኹ22Wጲૺࢅኹ6W࢟Ljፐ
ࠥኊገ7WᏥႯहࡍă
ᅄ4/! ཀྵࢾᄰ݆࢛ࡼ଼છ࢟വ
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19
NBY3149
``````````````````````````````` ።ቧᇦ
NBY3149
ૹ߅೫ڭവDXຫࡼ
ިဉWHB
ࠈా
݆߈ܠၦ߅ተ
ᄰਭNBY3149ࡼࠈాLjಽࠈቲጤᆡࡀMPᒙᆐ
27Ă95ৈᑵୣሤᆡăၫᄰਭEJOጤྜྷୈLjࠈቲጤᆡ
ࡀဟᒩೌᒗDMLၒྜྷă࣪᎖ඛৈᄰࡸLjࠈቲጤᆡ
ࡀᎌ6ᆡၫă༄5ᆡ᎖ᒙሤᆡLj6ᆡ᎖ဧถ
ணᒏຫᑫࡼৈᄰࡸă
ඛৈຫభᒙࡵ2027ሤᆡǗፐࠥඛৈᄰࡸࡼ߈ܠኊገ
5ᆡăᓍ૦ຫຫဟᒩೌࡵތॊၒྜྷMP`MWET,ਜ਼
MP`MWET.! )ෝါ2ਜ਼3*MP`! )ෝါ4ਜ਼5*ăMPBEၒྜྷᏤ
ઓᓤᏲሤᆡଐၫLjၫᒋభ߈ܠLj᎖ޘညᑵཀྵࡼMPሤ
ᆡăຫၒྜྷቧೌࡵڭവތॊၒྜྷLjDXJO`,ਜ਼DXJO`.ă
J0Rࡒތॊၒ߲ᒄਜ਼ೌࡵDX`JPVU,0.ਜ਼DX`RPVU,0.ă
DX`N2ਜ਼DX`N3᎖ኡᐋ႐ᒬభถࡼᔫෝါLjݬ
ܭ2ă
ܪᓰDXEෝါሆLjMP`MP`MWET,0.ࡼຫဟᒩఎLj
ऎEJOĂDMLਜ਼MPBEࡼ߈ܠቧਈ)ܕMPBE > ࢟ຳ <
DML > ࢅ࢟ຳǗEJO > ᇄਈLjࡣৼࢾᆐࢅ࢟ຳ*ăఎ
ဪ߈ܠဟLjਈܕຫဟᒩăၫږᑍᅎୀࡼ21NI{ܠ
߈Ⴅൈ211otᔢቃၫဟᒩᒲ໐0ဟମጤྜྷጤᆡࡀLj
ဟኔሮᇼቧᇦݬᅄ6ă
ጤᆡࡀઁ߈ܠLjMPBEᔐሣ౯ᒗ൝ࢅ࢟ຳLjႲઁ
ऩૄ൝࢟ຳLjดݝଐၫࡼၫᒋᓤᏲࡵJ0Rॊሤ0
ኡᐋăMPBEۣߒࢅ࢟ຳဟମܘኍࡉࡵuDMIăઓఎ
ຫဟᒩࣅ݆ၦ߅ተLjܘኍఎဟᒩઁݣถࣅ
ຫă
ࠈాᏤࣶৈୈဣሚೌLj࠭ऎᔢࡍ߈ࣞିܠ
߈ೌሣăEPVUᑽߒถă
tDSU tHLD
tCLH
DIN
CLK
LOAD
tDCLKPWH
tDCLKPWL
tDCLK
MIXER
CLOCK ON
tLD
tLDMIXCLK
MIXER
CLOCK OFF
MIXER
CLOCK ON
MIXER
CLOCK OFF
MIXER
CLOCK ON
MIXER
CLOCK OFF
MIXER
CLOCK ON
ᅄ6/! ጤᆡࡀဟኔᅄ
20
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ૹ߅೫ڭവDXຫࡼ
ިဉWHB
ިဉਖपࢾፃࡼJNE4
ᔢࡍތॊ࢟ഗၒ߲ᄰޟᆐ4nBQ.QLjऎඛৈຫᄰࡸࡼ
ຫ࢟ኹपᆍᆐ5/86Wᒗ23Wăඛৈތॊຫၒ߲ࡼຫ
ৢෝ࢟ഗᄰޟᆐ4/36nBăᏴඛৈ226ΩঌᏲ࢟ᔜሆLjᔐ࢟ഗ
ၒ߲ࢀ᎖O y 4/36nB )ᒦO > ᄰࡸၫ*ă۾ಿᒦLj,WTVN ਜ਼
.WTVN ࡼஸზၒ߲࢟ኹᆐ22W . )O y 4/36nB y 226* > 22W .
)9! y! 4/36nB! y! 226*! >! 9/16Wăࡩጙৈᄰࡸᎅᔢࡍၒ߲࢟ഗ
)ތॊ4nBQ.Q*དࣅLjऎᄰࡸᎌདࣅဟLjඛৈၒ߲ࡼ
࢟ኹڼ७ᆐ2/6nBQ.Q y 226ΩLj285nWQ.QLjऎތॊ࢟ኹ
ᆐ459nWQ.Qă۾ಿᒦLj࢟ኹपᆍᆐ,WTVN ਜ਼.WTVN ࡼᎌ
पᆍă
Ꭷ࢜ቯࡼᄰቧਖपݙᄴLjިဉਖपࢾፃࡼၷፒJNE4ᒎ࣪ܪ
።ࡼೝৈၒྜྷፒᎌݙᄴࡼ७ࣞăހ၂ᒦLjg2 ࡔܭ૫ྔࢀ
ᔝᒅࡼन݆Ljg3 ࡔܭኪጘࡼन݆ăઁᑗጙ܈ۅ༄ᑗࡼ
७ࣞࢅ36eCLjჅጲᑚᒬހऱါᒦLjၷፒၒྜྷࡼᒦጙৈ
܈ጙৈࢅ36eCăᏴިဉ።ᒦLjJNE4ޘᇕ)g2 . )g3 . g2**
ܭሚᆐݙᇧᆃ߲ሚࡼ໋ࣶಗᇙތቧLjᅄ7ă
-25dB
ᅪޡݗݝ
ኊገݧᅪޡݗݝവดݝມᒙ࢟വăᏴభถణத୭
FYU`D2ĂFYU`D3ਜ਼FYU`D4 )୭24Ă25Ă26*ࠀॊܰೌ
5/8μG࢟ྏᒗă
ULTRASOUND
IMD3
ᅪݝມᒙ࢟ᔜ
FYU`SFTࠀࡼᅪݝມᒙ࢟ᔜ᎖ᒙดݝມኹLjFYU`
SFT! )୭49*ᄰਭ8/6lΩ )1/2&*࢟ᔜLj࢟ᔜኍభถ
ణத୭हᒙă
ෝผၒྜྷਜ਼ၒ߲Ắ
࢜ቯ።ᒦLjNBY3149ᎅጙৈࢅᐅဉहࡍ)ྙNBY3145*
དࣅLj݀ᄰਭWHBདࣅॊೂࡼތॊၒ߲Ăఝࢶ݆Lj
ক݆ೌᒗBED )ྙNBY2547 9വBED*ăNBY3149
ࡼތॊၒྜྷᔜఝ࢜ቯᒋᆐ351ΩăWHBࡼތॊၒ߲భདࣅ
71qGࡼ࣪ތॊঌᏲ࢟ྏLjऎWHBၒ߲ތॊ࢟ྏᆐ21qGLj
SM > 2lΩăތॊၒ߲ᎌࡍᏖ4/86Wࡼৢෝມᒙăྙਫሆ
ጙᎌݙᄴࡼৢෝၒྜྷपᆍLjᐌ࣪ᑚቋތॊၒ߲ݧ
ୣഗẮă
f1 - (f2 - f1)
f1
f2
f2 + (f2 - f1)
ᅄ7/! ިဉJNE4ހଆၣ
࢟വݚۇ
NBY3149ࡼ୭ளਭᎁછઁLjถ৫੪ऱܣᎧሤਈ
ॊೂᏄୈೌLjဣሚஜࡼᇕಯݚăᄰޟLjকୈᎧ
ଂৈಢ႒ୈጙ৩߅ࣶᄰࡸቧࠀಯᇹᄻă
NBY3149ݧURGQ.FQॖᓤLjൡ)FQ*ᄋ೫ጙৈᎧ
በᒄମࡼࢅེᔜᄰࡸăଐ࢟വ)ۇQDC*ဟLjஐᓐNBY3149
ࡼൡྲེऻޟᒮገăࠥᅪLjൡᄰਭጙৈࢅ࢟
ঢവೌᒗ࢟ăൡܘኍᒇᄰਭጙᇹ࢟
ࣜਭᒗQDCࡼށă
______________________________________________________________________________________
21
NBY3149
DXຫၒ߲߅
+VIN
22
-V
+V
100nF
100nF
100nF
MAX2034
ONE CHANNEL
ZIN IN CONTROL
D2, D1, D0
100nF
100nF
CW_FILTER
CW_VG
12μH
CWIN_-
CWIN_+
12μH
VGIN_-
VGIN_+
MAX2038
ONE CHANNEL
VCC
VG_CTL-
GND
LO DIVIDER
VG_CTL+
CWD I/Q LO
50Ω
50Ω
VREF
CW_QOUT+
CW_QOUT-
CW_IOUT-
CW_IOUT+
VGOUT_-
0.1μF
0.1μF
VGOUT_+
115Ω
115Ω
TO 12-BIT
IMAGING
ADC
+VMIX
115Ω
ADC
CWD
TO Q CHANNEL
CWD
Q CHANNELS
IN
CWD
I CHANNELS
IN
ADC
CWD
115Ω
TO I CHANNEL
+VMIX
THIRD-ORDER BUTTERWORTH
ANTI-ALIAS FILTER
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VGOUT7-
VGOUT7+
LO7
53
52
51
54
VGOUT6+
LO6
VCC
55
56
57
LO5
GND
VGOUT659
58
VGOUT5VGOUT5+
61
60
VG_CTL+
VG_CTL63
62
LO_LVDS+
LO_LVDS65
64
VGOUT4+
LO4
66
67
68
69
71
70
VCC
VGOUT3VGOUT3+
LO3
VGOUT4-
72
VGOUT2-
VGOUT2+
LO2
75
74
73
TOP VIEW
LO1
76
50
VGOUT8-
VGOUT1+
VGOUT1-
77
49
78
48
VGOUT8+
LO8
GND
DIN
GND
VCC
79
47
80
46
81
45
82
44
N.C.
VCC
DOUT
LOW_PWR
CLK
83
43
CW_M1
CW_M2
84
42
85
41
VG_CLAMP_MODE
VCC
86
40
M4_EN
VCC
CW_FILTER
PD
39
CW_VG
LOAD
CW_QOUT+
CW_QOUT-
88
38
90
36
EXT_RES
VREF
CWIN8+
CW_IOUT-
91
35
CWIN8-
CW_IOUT+
VREF
VGIN1-
92
34
93
33
GND
VGIN8+
94
32
VGIN8-
VGIN1+
GND
CWIN1-
95
31
96
30
CWIN7+
CWIN7-
97
29
CWIN1+
98
28
VGIN2VGIN2+
100
87
MAX2038
89
37
99
27
26
CWIN6+
*EP = EXPOSED PAD
GND
CWIN6-
VGIN6VGIN6+
VGIN5+
GND
CWIN5CWIN5+
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VCC
VGIN5-
8
EXT_C1
7
EXT_C2
EXT_C3
6
GND
CWIN4CWIN4+
5
VGIN4+
4
CWIN3CWIN3+
VGIN4-
3
VGIN3VGIN3+
2
CWIN2CWIN2+
1
GND
*EP
GND
VGIN7+
VGIN7-
TQFP
``````````````````````````````` በຢቧᇦ
``````````````````````````````` ॖᓤቧᇦ
PROCESS: Silicon Complementary Bipolar
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100 TQFP-EP
C100E+3
21-0116
______________________________________________________________________________________
23
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MAX2038 集成了八路CW混频器的超声VGA - 概述
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Maxim > 产品 > 放大器和比较器 > MAX2038
MAX2038
集成了八路CW混频器的超声VGA
首款8通道VGA + CW多普勒波束成型IC，具有业内最高的集成度
概述 技术文档 定购信息 相关产品 用户说明 (0) 所有内容 状况
状况：生产中。
概述
数据资料
8通道可变增益放大器(VGA)和可编程8路混频器阵列MAX2038是针对高线性度、高动态范围以及低噪 声性能的超声成像和多普勒应用而设计的。每一个放大器都具有差分输入和输出，总增益范围为42dB
(典型值)。此外，VGA还具有极低的输出参考噪声，适合与12位ADC连接。
MAX2038 VGA经设计优化，绝对增益误差小于±0.25dB，以确保超声波束形成时的通道间聚集误差最
小。器件的差分输出可通过外部无源抗混叠滤波器直接驱动超声波用ADC。每个放大器的输出还提供
可使能或禁止的箝位功能，以限制输出信号，从而防止ADC过驱动或饱和。
完整的数据资料
英文
下载 Rev. 1 (PDF, 332kB)
中文
下载 Rev. 1 (PDF, 832kB)
器件的动态性能经过了优化，从而大大降低了失真，支持二次谐波成像。在VOUT = 1.5VP-P 和fIN =
5MHz时，器件的二次谐波失真为-70dBc；在VOUT = 1.5VP-P 和fIN = 5MHz时，超声规范*双音3阶交
调失真为-52dBc。
MAX2038还集成了8路积分混频器阵列和可编程LO相位发生器，用于实现完备的CW波束方案。每通
道的LO相位选择可以通过数字串行接口和单个高频时钟进行设置，或者每个复杂混频器对的LO均可直
接由分离的4 x LO时钟直接驱动。串行接口允许多个器件方便地进行菊链连接，以减少编程接口线的
数量。LO相位分配器可以编程至4、8、16正交相位。每个CW混频器的输入通路包含可选的低通滤波
器，用于优化CWD噪声性能。这些混频器输出相加到I和Q差分电流输出。混频器和LO发生器设计用
于实现优异的噪声性能：1.25MHz载波、1kHz偏移时为-155dBc/Hz。
MAX2038工作于+5.0V电源，VGA模式下每通道功耗仅为120mW，正常功率CW模式下每通道功耗仅
为269mW。此外还提供低功耗CW模式，每通道功耗仅为226mW。器件提供带裸焊盘的100引
脚TQFP (14mm x 14mm x 1mm)无铅封装。在0°C至+70°C温度范围内能保证其电气性能。
现备有评估板：MAX2038EVKIT
关键特性
8通道架构
高集成度适合超声成像应用
与超声VGA MAX2037引脚兼容
VGA特性
最大增益、增益范围以及输出参考噪声性能均经过优化，适合与12位ADC连接
最大增益为29.5dB
总增益范围为42dB
5MHz时，具有22nV/
的超低输出参考噪声
绝对增益误差为±0.25dB
每通道功耗为120mW
可使能或禁止的输出VGA箝位功能，消除ADC过驱动
全差分VGA输出，可直接驱动ADC
可变增益范围可实现42dB动态范围
VOUT = 1.5VP-P ，fIN = 5MHz时，HD2为-70dBc
VOUT = 1.5VP-P ，fIN = 5MHz时，双音超声规范* IMD3为-52dBc
CW多普勒混频器特性
1.25MHz载波、1kHz偏移时的混频器噪声低至-155dBc/Hz
串行可编程LO相位发生器，可实现4、8、16 LO积分相位分辨率
可选的独立通道4 x fLO LO输入驱动
每通道功耗为269mW (正常功率模式)和226mW (低功耗模式)
图表
http://china.maxim-ic.com/datasheet/index.mvp/id/6015[2011-1-14 6:33:34]
应用/使用
声纳系统
超声成像
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MAX2038 集成了八路CW混频器的超声VGA - 概述
引脚配置
注释、注解
*参见应用信息部分中的超声规范IMD3。
更多信息
新品发布
[ 2009-08-06 ]
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参考文献： 19- 4375 Rev. 1; 2010- 08- 06
本页最后一次更新: 2011- 01- 10
http://china.maxim-ic.com/datasheet/index.mvp/id/6015[2011-1-14 6:33:34]
MAX2038 集成了八路CW混频器的超声VGA - 概述
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http://china.maxim-ic.com/datasheet/index.mvp/id/6015[2011-1-14 6:33:34]
19-4375; Rev 1; 5/10
KIT
ATION
EVALU
E
L
B
AVAILA
Ultrasound VGA Integrated
with CW Octal Mixer
Features
The MAX2038 8-channel variable-gain amplifier (VGA)
and programmable octal mixer array is designed for
high linearity, high dynamic range, and low noise performance targeting ultrasound imaging and Doppler
applications. Each amplifier features differential inputs
and outputs and a total gain range of 42dB (typ). In
addition, the VGAs offer very low output-referred noise
performance suitable for interfacing with 12-bit ADCs.
The MAX2038 VGA is optimized for less than ±0.25dB
absolute gain error to ensure minimal channel-to-channel ultrasound beamforming focus error. The device’s
differential outputs are designed to directly drive ultrasound ADCs through an external passive anti-aliasing
filter. A switchable clamp is also provided at each
amplifier’s output to limit the output signals, thereby
preventing ADC overdrive or saturation.
Dynamic performance of the device is optimized to
reduce distortion to support second-harmonic imaging.
The device achieves a second-harmonic distortion
specification of -70dBc at VOUT = 1.5VP-P and fIN =
5MHz and an ultrasound-specific*, two-tone, third-order
intermodulation distortion specification of -52dBc at
VOUT = 1.5VP-P and fIN = 5MHz.
The MAX2038 also integrates an octal quadrature mixer
array and programmable LO phase generators for a
complete CW beamforming solution. The LO phase
selection for each channel can be programmed using a
digital serial interface and a single high-frequency clock
or the LOs for each complex mixer pair can be directly
driven using separate 4 x LO clocks. The serial interface
is designed to allow multiple devices to be easily daisy
chained to minimize program interface wiring. The LO
phase dividers can be programmed to allow 4, 8, or 16
quadrature phases. The input path of each CW mixer
consists of a selectable lowpass filter for optimal CWD
noise performance. The outputs of the mixers are
summed into I and Q differential current outputs. The
mixers and LO generators are designed to have exceptionally low noise performance of -155dBc/Hz at 1kHz
offset from a 1.25MHz carrier.
The MAX2038 operates from a +5.0V power supply,
consuming only 120mW/channel in VGA mode and
269mW/channel in normal power CW mode. A lowpower CW mode is also available and consumes only
226mW/channel. The device is available in a lead-free
100-pin TQFP package (14mm x 14mm x 1mm) with an
exposed pad. Electrical performance is guaranteed
over a 0°C to +70°C temperature range.
o 8-Channel Configuration
o High Integration for Ultrasound Imaging
Applications
o Pin Compatible with the MAX2037 Ultrasound VGA
VGA Features
o Maximum Gain, Gain Range, and Output-Referred
Noise Optimized for Interfacing with 12-Bit ADCs
Maximum Gain of 29.5dB
Total Gain Range of 42dB
22nV/√Hz Ultra-Low Output-Referred Noise at
5MHz
o ±0.25dB Absolute Gain Error
o 120mW Consumption per Channel
o Switchable Output VGA Clamp Eliminating ADC
Overdrive
o Fully Differential VGA Outputs for Direct ADC
Drive
o Variable Gain Range Achieves 42dB Dynamic
Range
o -70dBc HD2 at VOUT = 1.5VP-P and fIN = 5MHz
o Two-Tone Ultrasound-Specific* IMD3 of
-52dBc at VOUT = 1.5VP-P and fIN = 5MHz
CW Doppler Mixer Features
o Low Mixer Noise of -155dBc/Hz at 1kHz Offset
from 1.25MHz Carrier
o Serial-Programmable LO Phase Generator for 4, 8,
16 LO Quadrature Phase Resolution
o Optional Individual Channel 4 x fLO LO Input
Drive Capability
o 269mW Power Consumption per Channel (Normal
Power Mode) and 226mW Power Consumption
per Channel (Low-Power Mode)
Applications
Ultrasound Imaging
Sonar
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX2038CCQ+D
0°C to +70°C
100 TQFP-EP*
MAX2038CCQ+TD
0°C to +70°C
100 TQFP-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
D = Dry packing.
T = Tape and reel.
*EP = Exposed pad.
*See the Ultrasound-Specific IMD3 Specification in the
Applications Information section.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX2038
General Description
MAX2038
Ultrasound VGA Integrated
with CW Octal Mixer
ABSOLUTE MAXIMUM RATINGS
VCC, VREF to GND .................................................-0.3V to +5.5V
Any Other Pins to GND...............................-0.3V to (VCC + 0.3V)
CW Mixer Output Voltage to GND (CW_IOUT+, CW_IOUT-,
CW_QOUT+, CW_QOUT-) ................................................13V
VGA Differential Input Voltage (VGIN_+, VGIN_-)............8.0VP-P
Analog Gain Control Differential Input Voltage
(VG_CTL+, VG_CTL-) ..................................................8.0VP-P
CW Mixer Differential Input Voltage
(CWIN_+, CWIN_-).......................................................8.0VP-P
CW Mixer LVDS LO Differential Input Voltage..................8.0VP-P
Continuous Power Dissipation (TA = +70°C)
100-Pin TQFP (derated 45.5mW/°C above +70°C)...3636.4mW
Operating Temperature Range...............................0°C to +70°C
Junction Temperature ......................................................+150°C
θJC (Note 1) .....................................................................+2°C/W
θJA (Note 1) ...................................................................+22°C/W
Storage Temperature Range .............................-40°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS—VGA MODE
(Typical Application Circuit, Figure 7. VCC = VREF = 4.75V to 5.25V, VCM = (3/5)VREF, TA = 0°C to +70°C, VGND = 0V, LOW_PWR = 0,
M4_EN = 0, CW_FILTER = 0 or 1, TEST_MODE = 0, PD = 0, CW_VG = 1, CW_M1 = 0, CW_M2 = 0, no RF signals applied, capacitance to GND at each of the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF,
RL = 1kΩ, CW mixer outputs pulled up to +11V through four separate ±0.1% 115Ω resistors, all CW channels programmed off.
Typical values are at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDTIONS
MIN
TYP
MAX
UNITS
4.75
5
5.25
V
V
VGA MODE
Supply Voltage Range
VCC
VCC External Reference
VREF
(Note 3)
Refers to VCC supply
current plus VREF current
Total Power-Supply Current
5
5.25
PD = 0
4.75
204
231
PD = 1
27
33
mA
VCC Supply Current
IVCC
192
216
mA
VREF Current
IREF
12
15
mA
Refers to VCC supply current
24
27
mA
Minimum gain
+2
Maximum gain
-2
Current Consumption per
Amplifier Channel
Differential Analog Control
Voltage Range
Differential Analog Control
Common-Mode Voltage
VCM
2.85
Analog Control Input
Source/Sink Current
VP-P
3
3.15
V
4.5
5
mA
LOGIC INPUTS
CMOS Input High Voltage
VIH
CMOS Input Low Voltage
VIL
2
2.3
_______________________________________________________________________________________
V
0.8
V
Ultrasound VGA Integrated
with CW Octal Mixer
( Typical Application Circuit , Figure 7. V CC = V REF = 4.75V to 5.25V, T A = 0°C to +70°C, V GND = 0V, LOW_PWR = 0,
M4_EN = 0, CW_FILTER = 0 or 1, TEST_MODE = 0, PD = 0, CW_VG = 0, CW_M1 = 0, CW_M2 = 0, no RF signals applied,
capacitance to GND at each of the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF,
RL = 1kΩ, CW mixer outputs pulled up to +11V through four separate ±0.1% 115Ω resistors. Typical values are at VCC = VREF = 5V,
TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDTIONS
MIN
TYP
MAX
UNITS
CW MIXER MODE
Current in Full-Power Mode
5V VCC Supply
ICC_FP
Refers to VCC supply current (all 8 channels)
245
265
mA
Current in Full-Power Mode
11V VMIX Supply
IMIX_FP
Refers to VMIX supply current (all 8 channels)
106
120
mA
Current in Full-Power Mode
5V VREF Supply
IREF_FP
Refers to VREF supply current (all 8 channels)
17
21
mA
PDISS_FP
Total power dissipation (all 8 channels
including both 5V (VCC and VREF) and 11V
mixer pullup supply power dissipation in the
device) (Note 4)
2.15
2.41
W
Current in Low-Power Mode
5V VCC Supply
ICC_LP
LOW_PWR = 1; refers to VCC supply current
(all 8 channels)
245
265
mA
Current in Low-Power Mode
11V VMIX Supply
IMIX_LP
LOW_PWR = 1; refers to VMIX supply current
(all 8 channels)
53
60
mA
Current in Low-Power Mode
5V VREF Supply
IREF_LP
LOW_PWR = 1; refers to VREF supply current
(all 8 channels)
17
21
mA
PDISS_LP
LOW_PWR = 1; total power dissipation
(all 8 channels including both 5V (VCC and
VREF) and 11V mixer pullup supply power
dissipation in the device) (Note 4)
1.81
2.06
W
Mixer LVDS LO Input CommonMode Voltage
Modes 1 and 2 (Note 5)
1.25
±0.2
V
LVDS LO Differential Input
Voltage
Modes 1 and 2
700
mVP-P
LVDS LO Input
Common-Mode Current
Per pin
150
LVDS LO Differential
Input Resistance
Modes 1 and 2 (Note 6)
30
Mixer IF Common-Mode Output
Current
Common-mode current in each of the
differential mixer outputs (Note 7)
DATA Output High Voltage
DOUT voltage when terminated in DIN
(daisy chain) (Note 8)
DATA Output Low Voltage
DOUT voltage when terminated in DIN
(daisy chain) (Note 8)
Power Dissipation in Full-Power
Mode
Power Dissipation in Low-Power
Mode
200
3.25
200
µA
kΩ
3.75
4.5
mA
V
0.5
V
_______________________________________________________________________________________
3
MAX2038
DC ELECTRICAL CHARACTERISTICS—CW MIXER MODE
MAX2038
Ultrasound VGA Integrated
with CW Octal Mixer
AC ELECTRICAL CHARACTERISTICS—VGA MODE
(Typical Application Circuit, Figure 7. VCC = VREF = 4.75V to 5.25V, VCM = (3/5)VREF, TA = 0°C to +70°C, VGND = 0V, LOW_PWR = 0,
M4_EN = 0, CW_FILTER = 1, TEST_MODE = 0, PD = 0, CW_VG = 1, CW_M1 = 0, CW_M2 = 0, VG_CLAMP_MODE = 1, fRF = fLO/16
= 5MHz, capacitance to GND at each of the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is
10pF, RL = 1kΩ, CW mixer outputs pulled up to +11V through four separate ±0.1% 115Ω resistors, differential mixer inputs are driven
from a low impedance source. Typical values are at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
CW_VG set from logic 1 to 0 or from 0 to 1
(Note 9)
Mode Select Response Time
TYP
MAX
2
UNITS
µs
VGA MODE
Full-Scale Bandwidth
Small-Signal Bandwidth
Differential Input Resistance
Input Effective Capacitance
f-1.3dB
f-1.3dB
VOUT = 1.5VP-P,
1.3dB bandwidth,
gain = 10dB
Differential output
capacitance is 10pF,
capacitance to GND
at each single-ended
output is 60pF,
RL = 1kΩ
18
No capacitive load
RL = 1kΩ
29
VOUT = 1.5mVP-P, 3dB bandwidth,
gain = 10dB
RIN
CIN
MHz
30
170
fRF = 10MHz, each input to ground
200
MHz
230
15
Ω
pF
100
Ω
Maximum Gain
+29.5
dB
Minimum Gain
-12.5
dB
42
dB
Differential Output Resistance
ROUT
Gain Range
Absolute Gain Error
TA = +25°C, full gain range 0% to 100%,
VREF = 5V
VGA Gain Response Time
40dB gain change to within 1dB final value
1
µs
Input-Referred Noise
VG_CTL set for maximum gain,
no input signal
2
nV/√Hz
Output-Referred Noise
VG_CTL set for
+10dB of gain
Second Harmonic
Third-Order Intermodulation
Distortion
HD2
IMD3
±0.25
No input signal
22
VOUT = 1.5VP-P, 1kHz
offset
55
VG_CLAMP_MODE = 1, VG_CTL set for
+10dB of gain, fRF = 5MHz, VOUT = 1.5VP-P
±1.5
dB
nV/√Hz
-70
dBc
VG_CLAMP_MODE = 1, VG_CTL set for
+10dB of gain, fRF = 10MHz, VOUT = 1.5VP-P
-55
-65
VG_CLT set for +10dB of gain, fRF1 = 5MHz,
fRF2 = 5.01MHz, VOUT = 1.5VP-P,
VREF = 5V (Note 3)
-40
-52
dBc
Channel-to-Channel Crosstalk
VOUT = 1VP-P differential, fRF = 10MHz,
VG_CTL set for +10dB of gain
-80
dB
Maximum Output Voltage at
Clamp ON
VG_CLAMP_MODE = 0, VG_CTL set for
+20dB of gain, 350mVP-P differential input
2.4
VP-P
differential
4
_______________________________________________________________________________________
Ultrasound VGA Integrated
with CW Octal Mixer
(Typical Application Circuit, Figure 7. VCC = VREF = 4.75V to 5.25V, TA = 0°C to +70°C, VGND = 0V, LOW_PWR = 0, M4_EN = 0,
CW_FILTER = 1, TEST_MODE = 0, PD = 0, CW_VG = 0, CW_M1 = 0, CW_M2 = 0, VG_CLAMP_MODE = 1, fRF = fLO/16 = 5MHz,
capacitance to GND at each of the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF, RL =
1kΩ, CW mixer outputs pulled up to +11V through four separate ±0.1% 115Ω resistors, differential mixer inputs are driven from a low
impedance source. Typical values are at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
Maximum Output Voltage at
ClampOFF
CONDITIONS
MIN
VG_CLAMP_MODE = 1, VG_CTL set for
+20dB of gain, 350mVP-P differential input
TYP
MAX
UNITS
VP-P
differential
2.8
CW MIXER MODE
Mixer RF Frequency Range
0.9
7.6
MHz
Mixer LO Frequency Range
1
7.5
MHz
Mixer IF Frequency Range
100
kHz
Maximum Input Voltage Range
1.8
VP-P
differential
Differential Input Resistance
633
CW_FILTER = 1
1440
Mode 3, fRF = fLO/4 = 1.25MHz, measured at a
1kHz offset frequency; clutter tone at 0.9VP-P
differential measured at the mixer input
Input-Referred Noise Voltage
Third-Order Intermodulation
Distortion
CW_FILTER = 0
IMD3
Ω
6
nV/√Hz
Mode 3, RF terminated into 50Ω; fLO/4 =
1.25MHz, measured at 1kHz offset
4.6
Mode 1, fRF1 = 5MHz at 0.9VP-P differential
input, Doppler tone fRF2 = 5.01MHz at 25dBc
from clutter tone, fLO/16 = 5MHz (Note 10)
-50
Mixer Output Voltage Compliance
(Note 11)
Channel-to-Channel Phase
Matching
Measured under zero beat conditions,
fRF = 5MHz, fLO/16 = 5MHz (Note 12)
±3.0
Degrees
Channel-to-Channel Gain
Matching
Measured under zero beat conditions,
fRF = 5MHz, fLO/16 = 5MHz (Note 12)
±2
dB
CW_FILTER = 1
2.8
Transconductance (Note 13)
CW_FILTER = 0
4.75
dBc
fRF = 1.1MHz, 1VP-P
differential, fLO/16 = 1MHz
12
2.8
V
mS
_______________________________________________________________________________________
5
MAX2038
AC ELECTRICAL CHARACTERISTICS—CW MIXER MODE
MAX2038
Ultrasound VGA Integrated
with CW Octal Mixer
AC ELECTRICAL CHARACTERISTICS—CW MIXER MODE (continued)
(Typical Application Circuit, Figure 7. VCC = VREF = 4.75V to 5.25V, TA = 0°C to +70°C, VGND = 0V, LOW_PWR = 0, M4_EN = 0,
CW_FILTER = 1, TEST_MODE = 0, PD = 0, CW_VG = 0, CW_M1 = 0, CW_M2 = 0, VG_CLAMP_MODE = 1, fRF = fLO/16 = 5MHz,
capacitance to GND at each of the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF, RL =
1kΩ, CW mixer outputs pulled up to +11V through four separate ±0.1% 115Ω resistors, differential mixer inputs are driven from a low
impedance source. Typical values are at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
MHz
SERIAL SHIFT REGISTER
Serial Shift Register
Programming Rate
Minimum Data Set-Up Time
tDSU
30
ns
Minimum Data Hold Time
tHLD
2
ns
Minimum Data Clock Time
tDCLK
100
ns
Minimum Data Clock Pulse Width
High
tDCLKPWH
30
ns
Minimum Data Clock Pulse Width
Low
tDCLKPWL
30
ns
tLD
30
ns
tMIXCLK
30
ns
tCLH
30
ns
Minimum Load Line
Minimum Load Line High to
Mixer Clock On
Minimum Data Clock to Load
Line High
Note 2: Specifications at TA = +25°C and TA = +70°C are guaranteed by production test. Specifications at TA = 0°C are guaranteed by design and characterization.
Note 3: Noise performance of the device is dependent on the noise contribution from the supply to VREF. Use a low-noise supply for
VREF. VCC and VREF can be connected together to share the same supply voltage if the supply for VCC exhibits low noise.
Note 4: Total on-chip power dissipation is calculated as PDISS = VCC x ICC + VREF x IREF + [11V - (IMIX/4) x 115] x IMIX.
Note 5: Note that the LVDS CWD LO clocks are DC-coupled. This is to ensure immediate synchronization when the clock is first
turned on. An AC-coupled LO is problematic in that the RC time constant associated with the coupling capacitors and the
input impedance of the pin causes there to be a period of time (related to the RC time constant) when the DC level on the
chip side of the capacitor is outside the acceptable common-mode range and the LO swing does not exceed both the
logic thresholds required for proper operation. This problem associated with AC-coupling would cause an inability to
ensure synchronization among beam-forming channels. The LVDS signal is terminated differentially with an external 100Ω
resistor on the board.
Note 6: External 100Ω resistor terminates the LVDS differential signal path.
Note 7: The mixer common-mode current (3.25mA/channel) is specified as the common-mode current in each of the differential
mixer outputs (CW_QOUT+, CW_QOUT-, CW_IOUT+, CW_IOUT-).
Note 8: Specification guaranteed only for DOUT driving DIN of the next device in a daisy-chain fashion.
Note 9: This response time does not include the CW output highpass filter. When switching to VGA mode, the CW outputs stop
drawing current and the output voltage goes to the rail. If a highpass filter is used, the recovery time can be excessive and
a switching network is recommended as shown in the Applications Information section.
Note 10: See the Ultrasound-Specific IMD3 Specification in the Applications Information section.
Note 11: Mixer output-voltage compliance is the range of acceptable voltages allowed on the CW mixer outputs.
Note 12: Channel-to-channel gain-and-phase matching measured on 30 pieces during engineering characterization at room temperature. Each mixer is used as a phase detector and produces a DC voltage in the IQ plane. The phase is given by the
angle of the vector drawn on that plane. Multiple channels from multiple parts are compared to each other to produce the
phase variation.
Note 13: Transconductance is defined as the quadrature summing of the CW differential output current at baseband divided by the
mixer’s input voltage.
6
_______________________________________________________________________________________
Ultrasound VGA Integrated
with CW Octal Mixer
-50
0
VOUT = 1VP-P DIFFERENTIAL
-10
-20
3.0
2.5
2.0
-60
IMD3 (dBc)
PSMR (dBc)
3.5
-70
-30
f = 10MHz
-40
-50
-80
1.5
-60
1.0
-90
0
-100
7.5 10.0 12.5 15.0 17.5 20.0
-80
0
25
FREQUENCY (MHz)
50
75
100 125 150 175 200
-15
-5
5
FREQUENCY (kHz)
15
25
35
GAIN (dB)
SECOND HARMONIC DISTORTION
vs. GAIN
THIRD HARMONIC DISTORTION
vs. GAIN
0
-10
f = 2MHz
VOUT = 1VP-P DIFFERENTIAL
0
-20
-10
MAX2038 toc05
5.0
VOUT = 1VP-P DIFFERENTIAL
-20
-30
-30
f = 12MHz
-40
HD3 (dBc)
2.5
MAX2038 toc04
0
f = 5MHz
-70
0.5
HD2 (dBc)
OVERDRIVE PHASE DELAY (ns)
VOUT = 1.5VP-P DIFFERENTIAL
VMOD = 50mVP-P, fCARRIER = 5MHz,
GAIN = 10dB
MAX2038 toc02
VIN1 = 35mVP-P DIFFERENTIAL
VIN2 = 87.5mVP-P DIFFERENTIAL
GAIN = 20dB
4.0
-40
MAX2038 toc01
5.0
4.5
TWO-TONE ULTRASOUND-SPECIFIC
IMD3 vs. GAIN
POWER-SUPPLY MODULATION RATIO
MAX2038 toc03
OVERDRIVE PHASE DELAY
vs. FREQUENCY
-50
-60
-70
f = 12MHz
-40
f = 5MHz
-50
-60
-70
f = 5MHz
-80
-80
-90
f = 2MHz
-90
f = 2MHz
-100
-100
-15
-5
5
15
25
35
-15
GAIN (dB)
-5
5
15
35
OVERLOAD RECOVERY TIME
OVERLOAD RECOVERY TIME
MAX2038 toc07
MAX2038 toc06
f = 5MHz
f = 5MHz
DIFFERENTIAL
OUTPUT
1.0V/div
OUTPUT 1VP-P TO OVERLOAD AND BACK TO 1VP-P
DIFFERENTIAL
OUTPUT
2.0V/div
DIFFERENTIAL
INPUT
2.0V/div
DIFFERENTIAL
INPUT
1.0V/div
400ns/div
25
GAIN (dB)
OUTPUT 100mVP-P TO OVERLOAD
AND BACK TO 100mVP-P
400ns/div
_______________________________________________________________________________________
7
MAX2038
Typical Operating Characteristics
(Figure 7, VCC = VREF = 4.75V to 5.25V, VGND = 0V, PD = 0V, VG_CLAMP_MODE = 1, fRF = 5MHz, capacitance to GND at each of
the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF, RL = 1kΩ, TA = 0°C to +70°C. Typical
values are at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Figure 7, VCC = VREF = 4.75V to 5.25V, VGND = 0V, PD = 0, VG_CLAMP_MODE = 1, fRF = 5MHz, capacitance to GND at each of
the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF, RL = 1kΩ, TA = 0°C to +70°C. Typical
values are at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.)
-85
-70
-80
-90
-90
-95
-100
5
15
25
30
20
10
0
1
35
10
GAIN vs. DIFFERENTIAL ANALOG
CONTROL VOLTAGE (VG_CTL)
40
MAX2038 toc11
25
35
GAIN (dB)
15
5
-5
-15
-25
-0.5
0.5
1.5
VOUT = 1.5VP-P DIFFERENTIAL
VG_CTL = -2VP-P DIFFERENTIAL
25
15
20
5
10
0
5
-5
0
-10
1
LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
15
10
MAX2038 toc14
VOUT = 1.5VP-P DIFFERENTIAL
VG_CTL = +0.6VP-P DIFFERENTIAL
10
100
0.1
1000
LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
5
-10
GAIN (dB)
-5
GAIN (dB)
5
-10
-15
-10
-20
-25
-15
-25
-30
-20
-30
FREQUENCY (MHz)
100
1000
1000
-15
-5
10
VOUT = 1VP-P DIFFERENTIAL
VG_CTL = +1.7VP-P DIFFERENTIAL
0
-5
1
100
LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
0
0.1
10
FREQUENCY (MHz)
10
0
1
FREQUENCY (MHz)
VOUT = 1.5VP-P DIFFERENTIAL
VG_CTL = +1.5VP-P
5
35
10
15
0.1
25
VOUT = 1.5VP-P DIFFERENTIAL
VG_CTL = -1VP-P DIFFERENTIAL
25
20
VG_CTL (VP-P DIFFERENTIAL)
20
30
30
2.5
15
LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
GAIN (dB)
f = 5MHz
5
GAIN (dB)
LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
35
-1.5
-5
FREQUENCY (MHz)
GAIN (dB)
-2.5
-15
100
MAX2038 toc12
-5
MAX2038 toc15
-15
MAX2038 toc10
40
-110
-100
GAIN (dB)
f = 5MHz
MAX2038 toc13
-80
-60
50
MAX2038 toc16
-75
OUTPUT-REFERRED NOISE VOLTAGE (nV/√Hz)
-50
CROSSTALK (dB)
CROSSTALK (dB)
VOUT = 1VP-P DIFFERENTIAL
GAIN = 10dB, ADJACENT CHANNELS
-40
-70
8
MAX2038 toc09
VOUT = 1.5VP-P DIFFERENTIAL
f = 10MHz, ADJACENT CHANNELS
-65
-30
MAX2038 toc08
-60
OUTPUT-REFERRED NOISE VOLTAGE
vs. GAIN
CHANNEL-TO-CHANNEL CROSSTALK
vs. FREQUENCY
CHANNEL-TO-CHANNEL CROSSTALK
vs. GAIN
GAIN (dB)
MAX2038
Ultrasound VGA Integrated
with CW Octal Mixer
-20
-35
0.1
1
10
FREQUENCY (MHz)
100
1000
0.1
1
10
FREQUENCY (MHz)
_______________________________________________________________________________________
100
1000
Ultrasound VGA Integrated
with CW Octal Mixer
-10
-20
-25
-30
THIRD HARMONIC
-40
-50
-60
-70
SECOND HARMONIC
-80
-55
-65
-70
-75
-85
-90
-95
100
1000
0
0.5
1.0
1.5
2.0
SECOND HARMONIC
-80
-100
10
THIRD HARMONIC
-60
-100
1
MAX2038 toc19
-50
-40
2.5
200
3.0
500
800
1100
1400
1700
2000
FREQUENCY (MHz)
DIFFERENTIAL OUTPUT VOLTAGE (VP-P)
DIFFERENTIAL OUTPUT LOAD (Ω)
HARMONIC DISTORTION
vs. DIFFERENTIAL OUTPUT LOAD CAPACITANCE
HARMONIC DISTORTION
vs. FREQUENCY
TWO-TONE ULTRASOUND-SPECIFIC IMD3
vs. FREQUENCY
-55
THIRD HARMONIC
-60
-65
-70
-75
SECOND HARMONIC
-80
-85
-90
25
45
65
85
-20
-30
THIRD HARMONIC
-40
-50
-60
-70
SECOND HARMONIC
-30
-40
-50
-80
-60
-70
0
105
10
20
30
40
50
0
5
10
15
20
25
DIFFERENTIAL OUTPUT LOAD (pF)
FREQUENCY (MHz)
FREQUENCY (MHz)
GAIN ERROR HISTOGRAM
OUTPUT COMMON-MODE OFFSET VOLTAGE
vs. GAIN
DIFFERENTIAL OUTPUT IMPEDANCE
MAGNITUDE vs. FREQUENCY
35
30
25
20
15
160
5
0
-15
0
-20
-0.40
-0.35
-0.30
-0.25
-0.20
-0.15
-0.10
-0.05
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
140
120
-5
5
GAIN ERROR (dB)
180
10
100
-10
10
200
MAX2038 toc24
15
OFFSET VOLTAGE (mV)
40
20
|ZOUT|
SAMPLE SIZE = 202 UNITS,
fIN_ = 5MHz, GAIN = 10dB
MAX2038 toc23
5
MAX2038 toc22
-20
VOUT = 1VP-P DIFFERENTIAL
GAIN = 10dB
-10
-100
-100
45
0
-90
-95
50
VOUT = 1VP-P DIFFERENTIAL
GAIN = 10dB
MAX2038 toc25
-50
0
-10
IMD3 (dBc)
VOUT = 1VP-P DIFFERENTIAL
f = 5MHz, GAIN = 10dB
-45
MAX2038 toc21
MAX2038 toc20
-40
HARMONIC DISTORTION (dBc)
-30
VOUT = 1VP-P DIFFERENTIAL
f = 5MHz, GAIN = 10dB
-45
-90
0.1
% OF UNITS
-20
-40
-35
HARMONIC DISTORTION (dBc)
GAIN (dB)
-15
VOUT = 1VP-P DIFFERENTIAL
f = 5MHz, GAIN = 10dB
-10
HARMONIC DISTORTION (dBc)
-5
0
MAX2038 toc18
VOUT = 0.5VP-P DIFFERENTIAL
VG_CTL = +2VP-P DIFFERENTIAL
HARMONIC DISTORTION (dBc)
MAX2038 toc17
0
HARMONIC DISTORTION
vs. DIFFERENTIAL OUTPUT LOAD RESISTANCE
HARMONIC DISTORTION
vs. DIFFERENTIAL OUTPUT VOLTAGE
LARGE-SIGNAL BANDWIDTH
vs. FREQUENCY
80
60
-15
-5
5
15
GAIN (dB)
25
35
0.1
1
10
100
FREQUENCY (MHz)
_______________________________________________________________________________________
9
MAX2038
Typical Operating Characteristics (continued)
(Figure 7, VCC = VREF = 4.75V to 5.25V, VGND = 0V, PD = 0, VG_CLAMP_MODE = 1, fRF = 5MHz, capacitance to GND at each of
the VGA differential outputs is 60pF, differential capacitance across the VGA outputs is 10pF, RL = 1kΩ, TA = 0°C to +70°C. Typical
values are at VCC = VREF = 5V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Figure 7, VCC = VREF = 4.75V to 5.25V, VGND = 0V, LOW_PWR = 0, M4_EN = 0, CW_FILTER = 1, TEST_MODE = 0, PD = 0, CW_VG
= 0, CW_M1 = 0, CW_M2 = 0, CW mixer outputs pulled up to 11V through four separate ±0.1% 115Ω resistors, differential mixer
inputs are driven from a low-impedance source.
CW FILTER RESPONSE
(CW_FILTER = 1)
CW FILTER RESPONSE
(CW_FILTER = 0)
2
0
MAX2038 toc27
5
MAX2038 toc26
4
0
-5
LOSS (dB)
LOSS (dB)
-2
-4
-6
-8
-10
-15
-20
-10
-25
-12
-14
-30
0
2
4
6
8
10
12
14
16
2
4
6
8
10
12
14
16
FREQUENCY (MHz)
CW IMD3 vs. FREQUENCY
(MODE 1, VRF = 900mVP-P DIFF, VCC = VREF)
INPUT-REFERRED NOISE vs. CLUTTER VOLTAGE
(MODE 4, F_CLUTTER = 1.25MHz AT 1kHz OFFSET)
-48
-49
-50
-51
-52
4.75
5.00
5.25
-53
MAX2038 toc29
14
INPUT-REFERRED NOISE (nV/√Hz)
MAX2038 toc28
-47
12
10
8
6
4
2
0
-54
0
2
4
FREQUENCY (MHz)
10
0
FREQUENCY (MHz)
-46
CW IMD3 (dBc)
MAX2038
Ultrasound VGA Integrated
with CW Octal Mixer
6
8
0
0.5
1.0
1.5
2.0
CLUTTER VOLTAGE (VP-P DIFF)
______________________________________________________________________________________
Ultrasound VGA Integrated
with CW Octal Mixer
PIN
NAME
1
CWIN2-
FUNCTION
2
CWIN2+
3
VGIN3-
VGA Channel 3 Inverting Differential Input
4
VGIN3+
VGA Channel 3 Noninverting Differential Input
5, 10, 19,
24, 29, 34,
58, 79,
81, 96
GND
CW Mixer Channel 2 Inverting Differential Input
CW Mixer Channel 2 Noninverting Differential Input
Ground
6
CWIN3-
CW Mixer Channel 3 Inverting Differential Input
7
CWIN3+
CW Mixer Channel 3 Noninverting Differential Input
8
VGIN4-
VGA Channel 4 Inverting Differential Input
9
VGIN4+
VGA Channel 4 Noninverting Differential Input
11
CWIN4-
CW Mixer Channel 4 Inverting Differential Input
12
CWIN4+
CW Mixer Channel 4 Noninverting Differential Input
13
EXT_C1
External Compensation. Connect a 4.7µF capacitor to ground as close as possible to the pin to
bypass the internal biasing circuitry.
14
EXT_C2
External Compensation. Connect a 4.7µF capacitor to ground as close as possible to the pin to
bypass the internal biasing circuitry.
15
EXT_C3
External Compensation. Connect a 4.7µF capacitor to ground as close as possible to the pin to
bypass the internal biasing circuitry.
16, 42, 46,
54, 72,
82, 87
VCC
5V Power Supply. Connect to an external +5V power supply. Bypass each VCC supply to ground
with 0.1µF capacitors as close as possible to the pins.
17
VGIN5-
VGA Channel 5 Inverting Differential Input
18
VGIN5+
VGA Channel 5 Noninverting Differential Input
20
CWIN5-
CW Mixer Channel 5 Inverting Differential Input
21
CWIN5+
22
VGIN6-
VGA Channel 6 Inverting Differential Input
23
VGIN6+
VGA Channel 6 Noninverting Differential Input
25
CWIN6-
CW Mixer Channel 6 Inverting Differential Input
26
CWIN6+
27
VGIN7-
VGA Channel 7 Inverting Differential Input
28
VGIN7+
VGA Channel 7 Noninverting Differential Input
30
CWIN7-
CW Mixer Channel 7 Inverting Differential Input
31
CWIN7+
32
VGIN8-
VGA Channel 8 Inverting Differential Input
33
VGIN8+
VGA Channel 8 Noninverting Differential Input
35
CWIN8-
CW Mixer Channel 8 Inverting Differential Input
36
CWIN8+
CW Mixer Channel 8 Noninverting Differential Input
CW Mixer Channel 5 Noninverting Differential Input
CW Mixer Channel 6 Noninverting Differential Input
CW Mixer Channel 7 Noninverting Differential Input
______________________________________________________________________________________
11
MAX2038
Pin Description
Ultrasound VGA Integrated
with CW Octal Mixer
MAX2038
Pin Description (continued)
PIN
12
NAME
FUNCTION
37, 93
VREF
+5V Reference Supply. Connect to a low-noise power supply. Bypass to GND with a 0.1µF capacitor
as close as possible to the pins. Note that noise performance of the device is dependent on the noise
contribution from the supply to VREF. Use a low-noise supply for VREF. VCC and VREF can be
connected together to share the same supply voltage if the supply for VCC exhibits low noise.
38
EXT_RES
39
CW_VG
40
PD
41
CW_FILTER
CW Filter Mode Corner Frequency Select. Selects in corner frequency of the internal lowpass filter for
the CW path. Set CW_FILTER to a logic-high for a corner frequency of 9.5MHz. Set CW_FILTER to a
logic-low for a corner frequency of 4.5MHz.
43
M4_EN
Mode 4 Enable. Set M4_EN to a logic-high to override the serial port and activate all 8 channels of the
CW path.
44
LOW_PWR
45
DOUT
47
N.C.
No Connect. Leave this pin unconnected (this pin is the TEST_MODE pin called out in the MAX2038
EV kit data sheet).
48
LO8
CW LO Input for Channel 8. LO clock input for modes 3 and 4.
49
VGOUT8+
VGA Channel 8 Noninverting Differential Output
50
VGOUT8-
VGA Channel 8 Inverting Differential Output
External Resistor. Connect a 0.1% 7.5kΩ resistor to ground as close as possible to the pin to set the
bias for the internal biasing circuitry.
CW Mixer VGA Enable. Selects for VGA or CW mixer operation. Set CW_VG to a logic-high to enable
the VGAs while the CW mixers are powered down. Set CW_VG to a logic-low to enable the CW mixers
while the VGAs are powered down.
Power-Down Switch. Drive PD high to set the device in power-down mode. Drive PD low for normal
operation.
Low-Power Enable. Set high to enable low-power CW mixer mode for the device.
Serial Port Data Output. Data output for ease of daisy-chaining CW channels for analog beamforming
programming.
51
LO7
52
VGOUT7+
CW LO Input for Channel 7. LO clock input for modes 3 and 4.
VGA Channel 7 Noninverting Differential Output
53
VGOUT7-
VGA Channel 7 Inverting Differential Output
55
LO6
56
VGOUT6+
CW LO Input for Channel 6. LO clock input for modes 3 and 4.
VGA Channel 6 Noninverting Differential Output
57
VGOUT6-
VGA Channel 6 Inverting Differential Output
59
LO5
60
VGOUT5+
CW LO Input for Channel 5. LO clock input for modes 3 and 4.
VGA Channel 5 Noninverting Differential Output
61
VGOUT5-
VGA Channel 5 Inverting Differential Output
62
VG_CTL-
63
VG_CTL+
VGA Analog Gain Control Differential Input. Set the differential voltage to -2V for maximum gain
(+29.5dB), and to +2V for minimum gain (-12.5dB).
64
LO_LVDS-
CW LVDS LO Inverting Differential Input. LO clock inverting input for modes 1 and 2.
65
LO_LVDS+
CW LVDS LO Noninverting Differential Input. LO clock noninverting input for modes 1 and 2.
66
LO4
67
VGOUT4+
VGA Channel 4 Noninverting Differential Output
68
VGOUT4-
VGA Channel 4 Inverting Differential Output
69
LO3
CW LO Input for Channel 4. LO clock input for modes 3 and 4.
CW LO Input for Channel 3. LO clock input for modes 3 and 4.
______________________________________________________________________________________
Ultrasound VGA Integrated
with CW Octal Mixer
PIN
NAME
FUNCTION
70
VGOUT3+
VGA Channel 3 Noninverting Differential Output
71
VGOUT3-
VGA Channel 3 Inverting Differential Output
73
LO2
74
VGOUT2+
VGA Channel 2 Noninverting Differential Output
75
VGOUT2-
VGA Channel 2 Inverting Differential Output
76
LO1
77
VGOUT1+
VGA Channel 1 Noninverting Differential Output
78
VGOUT1-
VGA Channel 1 Inverting Differential Output
CW LO Input for Channel 2. LO clock input for modes 3 and 4.
CW LO Input for Channel 1. LO clock input for modes 3 and 4.
80
DIN
Serial Port Data Input. Data input to program the serial shift registers.
83
CLK
Serial Port Data Clock. Clock input for programming the serial shift registers.
84
CW_M1
CW Mode Select Input 1. Input for programming beamforming mode 1, 2, 3, or 4. See Table 1 for
mode programming details.
85
CW_M2
CW Mode Select Input 2. Input for programming beamforming mode 1, 2, 3, or 4. See Table 1 for
mode programming details.
86
VG_CLAMP_ VGA Clamp Mode Enable. Drive VG_CLAMP_MODE low to enable VGA clamp mode. VGA output is
MODE
clamped at typically 2.4VP-P differential. Drive VG_CLAMP_MODE high to disable VGA clamp mode.
88
LOAD
Serial Port Load. Loads the data from the serial shift registers into the I/Q phase dividers. Pull LOAD
bus from high to low and from low to high for programming the I/Q phase dividers.
89
CW_QOUT+
CW Mixer Noninverting Differential Quadrature Output. CW Mixer output for eight quadrature mixers
combined.
90
CW_QOUT-
CW Mixer Inverting Differential Quadrature Output. CW mixer output for eight quadrature mixers
combined.
91
CW_IOUT-
CW Mixer Inverting Differential In-Phase Output. CW mixer output for eight in-phase mixers combined.
92
CW_IOUT+
CW Mixer Noninverting Differential In-Phase Output. CW Mixer output for eight in-phase mixers
combined.
94
VGIN1-
95
VGIN1+
VGA Channel 1 Noninverting Differential Input
97
CWIN1-
CW Mixer Channel 1 Inverting Differential Input
98
CWIN1+
CW Mixer Channel 1 Noninverting Differential Input
VGA Channel 1 Inverting Differential Input
99
VGIN2-
VGA Channel 2 Inverting Differential Input
100
VGIN2+
VGA Channel 2 Noninverting Differential Input
—
EP
Exposed Pad. Internally connected to GND. Connect EP to a large PCB ground plane to maximize
thermal performance.
______________________________________________________________________________________
13
MAX2038
Pin Description (continued)
MAX2038
Ultrasound VGA Integrated
with CW Octal Mixer
Detailed Description
The MAX2038 is an 8-channel VGA integrated with a
programmable octal quadrature mixer array designed
for ultrasound imaging and Doppler applications. The
device is optimized for efficient power consumption,
high dynamic range, and for exceptionally low noise
performance. The VGA path features differential inputs,
analog variable gain control, differential outputs for
direct ADC drive, and a selectable output voltage
clamp to avoid ADC overdrive. The integrated octal
quadrature mixer array includes serial programmable
LO phase generators for CWD beamforming applications. The LO phase dividers can be programmed for 4,
8, or 16 quadrature phases. Lowpass filters are integrated at the input paths of each CW mixer. The outputs for the mixers are summed into single I/Q
differential current outputs.
The MAX2038 also integrates an octal quadrature mixer
array and programmable LO phase generators for a
complete continuous wave (CW) Doppler beamforming
solution. The LO phase selection for each channel is
programmed using a digital serial interface and a single high-frequency clock, or the LOs for each complex
mixer pair can be directly driven using separate 4 x LO
clocks. The serial interface is designed to allow multiple
devices to be easily daisy chained in order to minimize
program interface wiring. The LO phase dividers can
be programmed to allow 4, 8, or 16 quadrature phases.
The input path of each CW mixer consists of a selectable lowpass filter for optimal CWD noise performance.
The outputs of the mixers are summed into single I and
Q differential current outputs. The mixers and LO generators are designed to have exceptionally low noise
performance of -155dBc/Hz at 1kHz offset from a
1.25MHz carrier, measured with 900mVP-P differential
clutter signal.
Variable Gain Amplifier (VGA)
The MAX2038’s VGAs are optimized for high linearity,
high dynamic range, and low output-noise performance,
making this component ideal for ultrasound imaging
applications. The VGA paths also exhibit a channel-tochannel crosstalk of -80dB at 10MHz and an absolute
gain error of less than ±0.25dB for minimal channel-tochannel focusing error in an ultrasound system. Each
VGA path includes circuitry for adjusting analog gain, an
output buffer with differential output ports (VGOUT_+,
VGOUT_-) for driving ADCs, and differential input ports
(VGIN_+, VGIN_-), which are ideal for directly interfacing to the MAX2034 quad LNA. See the High-Level
Wave Mixer and Programmable Beamformer Functional
Diagram for details.
14
High-Level Wave Mixer and
Programmable Beamformer
_Functional Diagram
+5V
+5V (LOW NOISE)
VCC
VREF
MAX2038
VG_CTL+
VG_CTL-
VG_CLAMP_MODE
50Ω
VGIN1+
VGIN1-
VGOUT1+
VGA
VGOUT150Ω
•
•
•
•
•
•
• •
• •
• •
•
•
•
•
•
•
50Ω
VGIN8+
VGOUT8+
VGA
VGIN8-
VGOUT850Ω
LOW_PWR
PD
CWIN1+
CW_IOUT+
CW_IOUT-
I&Q
CWIN1•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CWIN8+
I&Q
CWIN8-
CW_QOUT+
CW_QOUT-
CW_VG
CW_FILTER
GND
The VGA has an adjustable gain range from -12.5dB to
+29.5dB, achieving a total dynamic range of 42dB
(typ). The VGA gain can be adjusted through the differential gain control inputs VG_CTL+ and VG_CTL-. Set
the differential gain-control input voltage at +2V for minimum gain and -2V for maximum gain. The differential
analog control common-mode voltage is 3V (typ).
______________________________________________________________________________________
Ultrasound VGA Integrated
with CW Octal Mixer
Octal Continuous Wave (CW) Mixer
The MAX2038 CW mixers are designed using an active
double-balanced topology. The mixers achieve high
dynamic range and high linearity performance, with
exceptionally low noise, which is ideal for ultrasound
CWD signal reception. The octal quadrature mixer
array provides noise performance of -155dBc/Hz at
1kHz from a 1.25MHz carrier, and a two-tone thirdorder ultrasound specific intermodulation product of
typically -50dBc. See the Ultrasound-Specific IMD3
Specification in the Applications Information section.
Power-Down
The device can also be powered down with PD. Set PD
to logic-high for power-down mode. In power-down
mode, the device draws a total supply current of 27mA.
Set PD to a logic-low for normal operation.
The octal array exhibits quadrature and in-phase differential current outputs (CW_QOUT+, CW_QOUT-,
CW_IOUT+, CW_IOUT-) to produce the total CWD
beamformed signal. The maximum differential current
output is typically 3mAP-P and the mixer output-compliance voltage ranges from 4.75V to 12V.
Overload Recovery
The device is also optimized for quick overload recovery
for operation under the large input-signal conditions that
are typically found in ultrasound input buffer imaging
applications. See the Typical Operating Characteristics
for an illustration of the rapid recovery time from a transmit-related overload.
High-Level CW Mixer and Programmable
Beamformer Functional Diagram
VCC
CWIN8
•
•
•
CWIN2
VREF
CW_FILTER
M4_EN
MAX2038
•
•
•
CW_IOUT+
CW_IOUTCW_IOUT2+
I Q
I Q
CHANNEL 1
I/Q
DIVIDER
PHASE
SELECTOR
CHANNEL 2
I/Q
DIVIDER
PHASE
SELECTOR
•
•
•
• •
•
CW_QOUT2-
CW_QOUT•
•
•
• •
•
CWIN1
CW_QOUT+
I Q
LOAD
5
DIN
•
•
•
• •
•
5
5-BIT
SR
5-BIT
SR
CW_M1
CW_M2
LO2
•
•
•
LO8
5
5-BIT
SR
•
•
•
LO_LVDS-
•
•
•
LO_LVDS+
•
•
•
• •
•
LO1
CHANNEL 8
I/Q
DIVIDER
PHASE
SELECTOR
DOUT
CLK
GND
LOW_PWR
PD
______________________________________________________________________________________
15
MAX2038
VGA Clamp
A clamp is provided to limit the VGA output signals to
avoid overdriving the ADC or to prevent ADC saturation. Set VG_CLAMP_MODE low to clamp the VGA differential outputs at 2.4VP-P. Set the VG_CLAMP_MODE
high to disable the clamp.
MAX2038
Ultrasound VGA Integrated
with CW Octal Mixer
CW Mixer Output Summation
The outputs from the octal mixer array are summed
internally to produce the total CWD summed beamformed signal. The octal array produces eight differential quadrature (Q) outputs and eight differential
in-phase (I) outputs. All quadrature and in-phase outputs are summed into single I and Q differential current
outputs (CW_QOUT+, CW_QOUT-, CW_IOUT+,
CW_IOUT-).
LO Phase Select
The LO phase dividers can be programmed through the
shift registers to allow for 4, 8, or 16 quadrature phases
for a complete CW beamforming solution.
register, which is used to program the output phase of
the divide-by-16 circuit. The first 4 bits of the shift register are for programming the 16 phases, the fifth bit
turns each channel on/off individually. For mode 1, set
both CW_M1 and CW_M2 to a logic-low.
Table 2. Mode 1 Logic Table (B4 = 0:
Channel On/B4 = 1: Channel Off)
MODE 1
CW_M1 = 0
CW_M2 = 0
Mode 1
For mode 1 operation, the LO_LVDS input frequency is
typically 16 x fLO. As the CWD LO frequency range is
1MHz to 7.5MHz, the input frequency ranges from
16MHz to 120MHz. This high LO clock frequency
requires a differential LVDS input. The 16 x fLO input is
then divided by 16 to produce 16 phases. These 16
phases are generated for each of the 8 channels and
programmed for the selected phase by a serial shift
register. Each channel has a corresponding 5-bit shift
LSB
SHUTDOWN
PHASE
(DEG)
D
C
B
A
SD
(B0)
(B1)
(B2)
(B3)
(B4)
0
0
0
0
0
0/1
22.5
0
0
0
1
0/1
CWD Beamforming Modes
There are four separate modes of operating the CWD
beamformer. See Table 1 for a summary of the different
modes of operation. The mode of operation can be
selected by the CW_M1 and CW_M2 logic inputs. Phase
generation is controlled through the serial interface. See
the Serial Interface section in the Applications
Information section for details on how to program for different quadrature phases.
MSB
45
0
0
1
0
0/1
67.5
0
0
1
1
0/1
90
0
1
0
0
0/1
112.5
0
1
0
1
0/1
135
0
1
1
0
0/1
157.5
0
1
1
1
0/1
0/1
180
1
0
0
0
202.5
1
0
0
1
0/1
225
1
0
1
0
0/1
247.5
1
0
1
1
0/1
270
1
1
0
0
0/1
292.5
1
1
0
1
0/1
315
1
1
1
0
0/1
337.5
1
1
1
1
0/1
NO. OF
DON’TCARE BITS
IN SSR
Table 1. Summary of CWD Beamforming Methods
LO INPUT
MODE
FREQUENCY
CLOCK
INTERFACE
PHASE
RESOLUTION
NO. OF
CLOCK
INPUTS
PER CHIP
PROGRAM
BY SERIAL
SHIFT
REGISTER
(SSR)
NO. OF
USEFUL
BITS IN
SSR
CW_M1
CW_M2
0
0
1
16 x
LVDS
16 phases
1
Yes
4
0
0
1
2
8x
LVDS
8 phases
1
Yes
3
1 MSB
1
0
3
4x
3V CMOS
4 phases
8
Yes
2
2 MSBs
1
1
4
4x
3V CMOS
Quadrature
provided
8
No
N/A
N/A
N/A = Not applicable.
16
______________________________________________________________________________________
Ultrasound VGA Integrated
with CW Octal Mixer
Table 3. Mode 2 Logic Table (DC = Don’t
Care, B4 = 0: Channel On/B4 = 1: Channel
Off)
MODE 2
CW_M1 = 0
CW_M2 = 1
MSB
LSB
SHUTDOWN
PHASE
(DEG)
D
C
B
A
SD
(B0)
(B1)
(B2)
(B3)
(B4)
0
DC
0
0
0
0/1
45
DC
0
0
1
0/1
90
DC
0
1
0
0/1
135
DC
0
1
1
0/1
180
DC
1
0
0
0/1
225
DC
1
0
1
0/1
270
DC
1
1
0
0/1
315
DC
1
1
1
0/1
Mode 3
The LO_LVDS input is not used in this mode. Separate
4 x fLO clock inputs are provided using LO1–LO8 for
each channel. The CWD LO frequency range is 1MHz
to 7.5MHz, and the input frequency provides ranges
from 4MHz to 30MHz. Note that the LO clock frequency
can utilize 3V CMOS inputs. The 4 x f LO LO1–LO8
inputs are divided by 4 to produce 4 phases. These
4 phases are generated for each of the 8 channels and
Table 4. Mode 3 Logic Table (DC = Don’t
Care, B4 = 0: Channel On/B4 = 1: Channel
Off)
MODE 3
CW_M1 = 1
CW_M2 = 0
MSB
LSB
SHUTDOWN
PHASE
(DEG)
D
C
B
A
SD
(B0)
(B1)
(B2)
(B3)
(B4)
0
DC
DC
0
0
0/1
90
DC
DC
0
1
0/1
180
DC
DC
1
0
0/1
270
DC
DC
1
1
0/1
programmed for the selected phase by the serial shift
register. For mode 3, 4 phases are generated, and only
2 of the 4 phase-programming bits are required where
the 2-phase programming MSBs are “don’t-care” bits.
For mode 3, set CW_M1 to a logic-high and set CW_M2
to a logic-low. See Table 4.
Mode 4
The LO_LVDS input is not used in this mode. The
appropriate phases are externally provided using separate 4 x fLO LO1–LO8 inputs for each channel. A 4 x fLO
input is required so the device can internally generate
accurate duty-cycle independent quadrature LO drives.
Note that the serial shift register is not used in this
mode. The CWD LO frequency range is 1MHz to
7.5MHz and the input frequency ranges from 4MHz to
30MHz. The appropriate inputs are provided at LO1 to
LO8. A reset line is provided to the customer so that
they can synchronize all the CWD channels. The reset
line is implemented through the RESET. For mode 4, set
both CW_M1 and CW_M2 to logic-high. See Table 5.
Table 5. Mode 4 Logic Table
MODE 4
CW_M1 = 1
CW_M2 = 1
PHASE
(DEG)
Serial bus
not used in
mode 4
MSB
LSB
SHUTDOWN
D
C
B
A
SD
(B0)
(B1)
(B2)
(B3)
(B4)
N/A
N/A
N/A
N/A
N/A
N/A = Not applicable.
______________________________________________________________________________________
17
MAX2038
Mode 2
The LO_LVDS input frequency is 8 x fLO (typ) for mode
2 operation. The CWD LO frequency range is 1MHz to
7.5MHz, and the input frequency ranges from 8MHz to
60MHz. This high LO clock frequency requires a differential LVDS input. The 8 x fLO input is then divided by 8
to produce 8 phases. These 8 phases are generated
for each of the 8 channels and programmed for the
selected phase by the serial shift register. Note that the
serial shift register is common to modes 1, 2, 3, and
where each channel has a corresponding 5-bit shift
register, which is used to program the output phase.
However, since mode 2 generates 8 phases only, 3 of
the 4 phase-programming bits are used; 5 bits are still
loaded per channel using the serial shift register, but
the phase-programming MSB is a don’t-care bit. The
fifth bit in the shift register always turns each channel
on/off individually. For mode 2, set CW_M1 to a logiclow and set CW_M2 to a logic-high. See Table 3.
MAX2038
Ultrasound VGA Integrated
with CW Octal Mixer
DATA_IN
CLOCK
CHANNEL 1
A B C D SD
CHANNEL 2
A B C D SD
CHANNEL 3
A B C D SD
CHANNEL 4
A B C D SD
B3 B2 B1 B0 B4
B3 B2 B1 B0 B4
B3 B2 B1 B0 B4
B3 B2 B1 B0 B4
CHANNEL 5
A B C D SD
CHANNEL 6
A B C D SD
CHANNEL 7
A B C D SD
CHANNEL 8
A B C D SD
B3 B2 B1 B0 B4
B3 B2 B1 B0 B4
B3 B2 B1 B0 B4
B3 B2 B1 B0 B4
DATA_OUT
Figure 1. Data Flow of Serial Shift Register
Synchronization
Figure 1 illustrates the serial programming of the 8 individual channels through the serial data port. Note that
the serial data can be daisy chained from one part to
another, allowing a single data line to be used to program multiple chips in the system.
CW Lowpass Filter
The MAX2038 also includes selectable lowpass filters
between each CW differential input pair and corresponding mixer input. Shunt capacitors and resistors
are integrated on chip for high band and low band. The
parallel capacitor/resistor networks, which appear differentially across each of the CW differential inputs, are
selectable through the CW_FILTER. Drive CW_FILTER
high to set the corner frequency of the filter to be fC =
9.5MHz. Drive CW_FILTER low to set the corner frequency equal to fC = 4.5MHz. The CW_VG allows the filter inputs to be disconnected from input nodes (internal
to chip) to prevent overloading the LNA output and to
not change the VGA input common-mode voltage.
VGA and CW Mixer Operation
During normal operation, the MAX2038 is configured
such that either the VGA path is enabled while the mixer
array is powered down (VGA mode), or the quadrature
mixer array is enabled while the VGA path is powered
down (CW mode). During VGA mode, besides powering
down the CW mixer array, the differential inputs to the
lowpass filters and CW mixers also are internally disconnected from the input nodes, making the CW differential
inputs (CWIN_+, CWIN_-) high impedance. The CW
mode disconnects the VGA inputs internally from the
input ports of the device. For VGA mode, set CW_VG to a
logic-high, while for CW mode, set CW_VG to a logic-low.
Power-Down and Low-Power Modes
During device power-down, both the VGA and CW
mixer are disabled regardless of the logic set at
CW_VG. Both the VGA and CW mixer inputs are high
impedance since the internal switches to the inputs are
all disconnected. The total supply current of the device
reduces to 27mA. Set PD to a logic-high for device
power-down.
A low-power mode is available to lower the required
power for CWD operation. When selected, the complex
mixers operate at lower quiescent currents and the total
per-channel current is lowered to 53mA. Note that operation in this mode slightly reduces the dynamic performance of the device. Table 6 shows the logic function
of standard operating modes.
Table 6. Logic Function of Standard Operating Modes
PD
CW_VG
INPUT INPUT
LOW_PWR
VGA
CW
MIXER
INTERNAL
SWITCH
TO VGA
INTERNAL
SWITCH TO LPF
AND CW MIXER
5V VCC CURRENT
CONSUMPTION
(mA)
11V VMIX CURRENT
CONSUMPTION
(mA)
1
1
N/A
Off
Off
Off
Off
27
0
1
0
N/A
Off
Off
Off
Off
27
0
0
0
0
Off
On
Off
On
245
106
0
0
1
Off
On
Off
On
245
53
0
1
N/A
On
Off
On
Off
204
0
N/A = Not applicable.
18
______________________________________________________________________________________
Ultrasound VGA Integrated
with CW Octal Mixer
Mode Select Response Time
The mode select response time is the time that the
device takes to switch between CW and VGA modes.
One possible approach to interfacing the CW outputs to
an instrumentation amplifier used to drive an ADC is
shown in Figure 2. In this implementation, there are four
large-value (in the range of 470nF to 1µF) capacitors
between each of the CW_IOUT+, CW_IOUT-,
CW_QOUT+, CW_QOUT- outputs and the circuitry they
are driving. The output of the CW mixer usually drives
the input of an instrumentation amplifier made up of op
amps whose input impedance is set by common-mode
setting resistors.
115Ω
115Ω
1µF
CW_IOUT-
50Ω
The highpass pole in this case is at fP = 1/(2 x pi x RC)
~ 5Hz. Note that this low highpass corner frequency is
required in order to filter the downconverted clutter tone,
which appears at DC, without interfering with CWD imaging at frequencies as low as 400Hz. For example, if one
wanted to use CWD down to 400Hz, then a good choice
for the highpass pole would be at least a decade below
this (< 40Hz) as not to incur rolloff due to pole. Remember,
if the highpass pole is put at 400Hz, the response is 3dB
down at that corner frequency. The placement of the highpass pole at 5Hz in the above example is between the DC
and 40Hz limitations just discussed.
The bottom line is that any reasonably sized DC block
between the output of the mixer and the instrumentation
amplifier will pose a significant time constant that slows
the mode select switching speed.
An alternative solution to the approach in Figure 2,
which enables faster mode select response time, is
shown in Figure 4.
31.6kΩ
+11V
0.022µF
31.6kΩ
CW_IOUT+
1µF
Figure 2. Typical Example of a CW Mixer’s Output Circuit
There are clearly both a highpass corner and a lowpass
corner present in this output network. The lowpass corner is set primarily by the 115Ω mixer pullup resistors,
the series 50Ω resistors, and the shunt 0.022µF capacitor. This lowpass corner is used to filter a combination
of LO leakage and upper sideband. The highpass corner, however, is of a larger concern due to the fact that
it is dominated by the combination of a 1µF DC-blocking capacitor and the pair of shunt 31.6kΩ resistors.
If drawn, the simplified dominant highpass network
would look like Figure 3.
1µF
31.6kΩ
+5V
Figure 4. Improved Mode Select Response Time Achieved with
DC-Coupled Input to Instrumentation Amplifier
In Figure 4, the outputs of the CWD mixers are DCcoupled into the inputs of the instrumentation amplifiers. Therefore, the op amps must be able to accommodate the full compliance range of the mixer outputs,
which is a maximum of 11V when the mixers are disabled, down to the 5V supply of the MAX2038 when the
mixers are enabled. The op amps can be powered from
11V for the high rail and 5V for the low rail, requiring a
6V op amp.
Figure 3. Simplified Circuit of Highpass Pole
______________________________________________________________________________________
19
MAX2038
Applications Information
MAX2038
Ultrasound VGA Integrated
with CW Octal Mixer
Serial Interface
The serial interface of the MAX2038 programs the LO for
16, 8, or 4 quadrature phases using a serial shift register
implementation. Data is shifted into the device on DIN.
The serial shift register clock is applied to the CLK input.
The serial shift register has 5 bits per channel. The first 4
bits are for phase programming, and the fifth bit enables
or disables each channel of the mixer array.
Each mixer can be programmed to 1 of 16 phases;
therefore, 4 bits are required for each channel for programming. The master high-frequency mixer clock is
applied to differential inputs LO_LVDS+ and LO_LVDS(for modes 1 and 2) and LO_ (for modes 3 and 4). The
LOAD input is provided to allow the user to load the
phase counters with the programming values to generate the correct LO phases. The input signals for mixing
are applied to the eight differential inputs, CWIN_+ and
CWIN_-. The summed I/Q baseband differential outputs
are provided on CW_IOUT+/- and CW_QOUT+/-.
CW_M1 and CW_M2 are used to select one of the four
possible modes of operation. See Table 1.
The serial interface is designed to allow multiple
devices to be easily daisy chained in order to minimize
program interface wiring. DOUT is available for this
daisy-chain function.
Programming the Beamformer
During normal CWD operation, the mixer clock at LO_ or
LO_LVDS+/- is on and the programming signals on DIN,
CLK, and LOAD are off. (LOAD = high, CLK = low, and
DIN = don’t care, but fixed to a high or low). To start the
programming sequence, turn off the mixer clock. Data is
shifted into the shift register at a recommended 10MHz
programming rate or 100ns minimum data clock
period/time. See Figure 5 for timing details.
After the shift registers are programmed, pull the LOAD
bus to logic-low and then back to logic-high to load the
internal counters into I/Q phase divider/selectors with
the proper values. LOAD must remain low for a minimum time of tCLH. The user turns on the mixer clock to
start beamforming. The clock must turn on such that it
starts at the beginning of a mixer clock cycle.
tDSU tHLD
tCLH
DIN
CLK
LOAD
tDCLKPWH
tDCLKPWL
tDCLK
MIXER
CLOCK ON
tLD
tLDMIXCLK
MIXER
CLOCK OFF
MIXER
CLOCK ON
MIXER
CLOCK OFF
MIXER
CLOCK ON
MIXER
CLOCK OFF
MIXER
CLOCK ON
Figure 5. Shift Register Timing Diagram
20
______________________________________________________________________________________
Ultrasound VGA Integrated
with CW Octal Mixer
Ultrasound-Specific IMD3 Specification
Unlike typical communications specifications, the two
input tones are not equal in magnitude for the ultrasound-specific IMD3 two-tone specification. In this
measurement, f1 represents reflections from tissue and
f2 represents reflections from blood. The latter reflections are typically 25dB lower in magnitude, and hence
the measurement is defined with one input tone 25dB
lower than the other. The IMD3 product of interest (f1 (f2 - f1)) presents itself as an undesired Doppler error
signal in ultrasound applications. See Figure 6.
-25dB
External Compensation
External compensation is required for bypassing internal biasing circuitry. Connect as close as possible a
4.7µF capacitor from EXT_C1, EXT_C2, and EXT_C3
(pins 13, 14, 15) to ground.
ULTRASOUND
IMD3
External Bias Resistor
An external resistor at EXT_RES is required to set the
bias for the internal biasing circuitry. Connect, as close
as possible, a 7.5kΩ (0.1%) resistor from EXT_RES (pin
38) to ground.
Analog Input and Output Coupling
In typical applications, the MAX2038 is being driven from
a low-noise amplifier (such as the MAX2034) and the
VGA is typically driving a discrete differential anti-alias filter into an ADC (such as the MAX1436 octal ADC). The
differential input impedance of the MAX2038 is typically
240Ω. The differential outputs of the VGA are capable of
driving a differential load capacitance to GND at each of
the VGA differential outputs of 60pF, and differential
capacitance across the VGA outputs is 10pF, RL =
1kΩ. The differential outputs have a common-mode
bias of approximately 3.75V. AC-couple these differential outputs if the next stage has a different commonmode input range.
f1 - (f2 - f1)
f1
f2
f2 + (f2 - f1)
Figure 6. Ultrasound IMD3 Measurement Technique
Board Layout
The pin configuration of the MAX2038 is optimized to
facilitate a very compact physical layout of the device
and its associated discrete components. A typical
application for this device might incorporate several
devices in close proximity to handle multiple channels
of signal processing.
The exposed pad (EP) of the MAX2038’s TQFP-EP
package provides a low thermal-resistance path to the
die. It is important that the PCB on which the MAX2038
is mounted be designed to conduct heat from the EP.
In addition, provide the EP with a low-inductance path
to electrical ground. The EP MUST be soldered to a
ground plane on the PCB, either directly or through an
array of plated via holes.
______________________________________________________________________________________
21
MAX2038
CW Mixer Output Summation
The maximum differential current output is typically
3mA P-P and the mixer output compliance voltage
ranges from 4.75V to 12V per mixer channel. The mixer
common-mode current in each of the differential mixer
outputs is typically 3.25mA. The total summed current
would equal N x 3.25mA in each of the 115Ω load resistors (where N = number of channels). In this case, the
quiescent output voltage at +VSUM and -VSUM outputs
would be 11V - (N x 3.25mA x 115) = 11V - (8 x 3.25mA
x 115) = 8.05V. The voltage swing at each output, with
one channel driven at max output current (differential
3mAP-P) while the other channels are not driven, would
be 1.5mAP-P x 115Ω or 174mVP-P and the differential
voltage would be 348mVP-P. The voltage compliance
range is defined as the valid range for +VSUM and VSUM in this example.
+VIN
22
-V
+V
100nF
100nF
100nF
MAX2034
ONE CHANNEL
ZIN IN CONTROL
D2, D1, D0
100nF
100nF
CW_FILTER
CW_VG
12µH
CWIN_-
CWIN_+
12µH
VGIN_-
VGIN_+
MAX2038
ONE CHANNEL
VCC
VG_CTL-
GND
LO DIVIDER
VG_CTL+
CWD I/Q LO
50Ω
50Ω
VREF
CW_QOUT+
CW_QOUT-
CW_IOUT-
CW_IOUT+
VGOUT_-
0.1µF
0.1µF
VGOUT_+
115Ω
115Ω
TO 12-BIT
IMAGING
ADC
+VMIX
115Ω
ADC
CWD
TO Q CHANNEL
CWD
Q CHANNELS
IN
CWD
I CHANNELS
IN
ADC
CWD
115Ω
TO I CHANNEL
+VMIX
THIRD-ORDER BUTTERWORTH
ANTI-ALIAS FILTER
MAX2038
Ultrasound VGA Integrated
with CW Octal Mixer
Figure 7. Typical Per-Channel Ultrasound Imaging Application
______________________________________________________________________________________
Ultrasound VGA Integrated
with CW Octal Mixer
VGOUT7+
LO7
51
52
53
54
VGOUT6+
LO6
VCC
VGOUT755
56
57
LO5
GND
VGOUT659
58
VGOUT5VGOUT5+
61
60
VG_CTL+
VG_CTL62
63
64
LO4
LO_LVDS+
LO_LVDS65
VGOUT4+
66
67
68
69
VGOUT3VGOUT3+
LO3
VGOUT471
70
VCC
72
VGOUT2-
VGOUT2+
LO2
75
74
73
TOP VIEW
LO1
76
50
VGOUT8-
VGOUT1+
VGOUT1GND
DIN
GND
VCC
77
49
78
48
VGOUT8+
LO8
79
47
80
46
81
45
82
44
N.C.
VCC
DOUT
LOW_PWR
M4_EN
VCC
CW_FILTER
PD
CLK
83
43
CW_M1
CW_M2
VG_CLAMP_MODE
84
42
85
41
86
40
VCC
LOAD
CW_QOUT+
CW_QOUT-
87
39
88
38
90
36
CWIN8+
CW_IOUT-
91
35
CWIN8-
CW_IOUT+
92
34
VREF
VGIN1VGIN1+
GND
CWIN1-
93
33
GND
VGIN8+
94
32
VGIN8-
95
31
96
30
97
29
CWIN1+
98
28
VGIN2VGIN2+
99
27
CWIN7+
CWIN7GND
VGIN7+
VGIN7-
26
CWIN6+
MAX2038
89
37
*EP
*EP = EXPOSED PAD
GND
CWIN6-
TQFP
Chip Information
PROCESS: Silicon Complementary Bipolar
VGIN6VGIN6+
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VGIN5+
GND
CWIN5CWIN5+
8
VCC
VGIN5-
7
EXT_C1
EXT_C2
EXT_C3
6
GND
CWIN4CWIN4+
5
VGIN4+
4
CWIN3+
VGIN4-
3
VGIN3VGIN3+
GND
2
CWIN2CWIN2+
1
CWIN3-
100
CW_VG
EXT_RES
VREF
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
100 TQFP-EP
C100E+3
21-0116
______________________________________________________________________________________
23
MAX2038
Pin Configuration
MAX2038
Ultrasound VGA Integrated
with CW Octal Mixer
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
0
1/09
Initial release
1
5/10
Implemented minor corrections
PAGES
CHANGED
—
2–10, 12, 13, 18
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.