19-4570; Rev 0; 6/09 Octal-Channel Ultrasound Front-End with CW Doppler Mixers Features The MAX2078 octal-channel ultrasound front-end is a fully integrated bipolar, high-density octal-channel ultrasound receiver optimized for low cost, high-channel count, high-performance portable and cart-based ultrasound systems. The easy-to-use IC allows the user to achieve high-end 2D, PW, and CW Doppler (CWD) imaging capability using substantially less space and power. The highly compact imaging receiver lineup, including low-noise amplifier (LNA), variable-gain amplifier (VGA), and anti-alias filter (AAF), achieves an ultra-low 2.4dB noise figure at RS = RIN = 200Ω at a very low 64.8mW per channel power dissipation. The full imaging receiver channel has been optimized for second-harmonic imaging with -64dBFS second-harmonic distortion performance with a 1VP-P 5MHz output signal. The bipolar front-end has also been optimized for excellent low-velocity PW and color-flow Doppler sensitivity with an exceptional near-carrier SNR of 140dBc/Hz at 1kHz offset from a 5MHz 1VP-P output clutter signal. A fully integrated high-performance, programmable CWD beamformer is also included. Separate I/Q mixers for each channel are available for optimal CWD sensitivity in high-clutter environments, yielding an impressive near-carrier SNR of 154dBc/Hz at 1kHz offset from a 1.25MHz 200mVP-P input clutter signal. The MAX2078 octal-channel ultrasound front-end is available in a small 10mm x 10mm, 68-pin thin QFN package with an exposed pad and is specified over a 0°C to +70°C temperature range. o 8 Full Channels of LNA, VGA, AAF, and CWD Mixers in a Small, 10mm x 10mm TQFN Package o Pin Compatible with MAX2077 with LNA, VGA, and AAF in 10mm x 10mm TQFN Variant o Ultra-Low Full-Channel Noise Figure of 2.4dB at RIN = RS = 200Ω o Low Output-Referred Noise of 23nV/√Hz at 5MHz, 20dB Gain, Yielding a Broadband SNR of 68dB** for Excellent Second-Harmonic Imaging o High Near-Carrier SNR of 140dBc/Hz at 1kHz Offset from a 5MHz, 1VP-P Output Signal, and 20dB of Gain for Excellent Low-Velocity PW and Color-Flow Doppler Sensitivity in a High-Clutter Environment o Ultra-Low-Power 64.8mW per Full-Channel (LNA, VGA, and AAF) Normal Imaging Mode (234mW per Channel in CWD Mode) o Selectable Active Input-Impedance Matching of 50Ω, 100Ω, 200Ω, and 1kΩ o Wide Input-Voltage Range of 330mVP-P in High LNA Gain Mode and 550mVP-P in Low LNA Gain Mode o Integrated Selectable 3-Pole 9MHz, 10MHz, 15MHz, and 18MHz Butterworth AAF o Fast-Recovery, Low-Power Modes (< 2µs) o Fully Integrated, High Dynamic Range CWD Beamformer with Near-Carrier SNR of 154dBc/Hz at 1kHz Offset from a 1.25MHz, 200mVP-P Input Clutter Signal Applications Pin Configuration Sonar MAX2078CTK+ VCC2 OUT1+ CLK DIN CS NP V/C CQ- CQ+ CI- CI+ VCC2 VCC1 ZF1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 Ordering Information PART IN1 ZF2 TOP VIEW INC1 Medical Ultrasound Imaging **When coupled with the MAX1437B ADC. TEMP RANGE PIN-PACKAGE 0°C to +70°C 68 Thin QFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. + 51 OUT1- IN2 1 INC2 2 50 OUT2+ ZF3 3 49 OUT2- IN3 4 48 OUT3+ INC3 5 47 OUT3- ZF4 6 46 OUT4+ IN4 7 INC4 8 GND 9 45 OUT444 VCC1 MAX2078 43 LO+ AG 10 42 LO- ZF5 11 41 OUT5+ IN5 12 40 OUT5- INC5 13 39 OUT6+ ZF6 14 38 OUT637 OUT7+ IN6 15 INC6 16 36 OUT7- *EP 35 OUT8+ ZF7 17 OUT8- VCC2 DOUT GND PD CLP GND VG- VG+ VREF VCC1 VCC2 INC8 IN8 ZF8 IN7 INC7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 THIN QFN *EP = EXPOSED PAD. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX2078 General Description MAX2078 Octal-Channel Ultrasound Front-End with CW Doppler Mixers ABSOLUTE MAXIMUM RATINGS VCC_ to GND .........................................................-0.3V to +5.5V VCC2 - VCC1 .....................................................................> -0.3V CI_, CQ_ to GND ....................................................-0.3V to +13V ZF_, IN_, AG to GND ..................................-0.3V to (VCC + 0.3V) INC_ ..............................................................................20mA DC VREF to GND.............................................................-0.3V to +3V IN_ to AG ...............................................................-0.6V to +0.6V OUT_, LO_, DIN, DOUT, VG_, NP, CS, CLK, PD, CLP, V/C to GND .....................................-0.3V to VCC1 + 0.3V CI_, CQ_, VCC_, VREF analog and digital control signals must Note 1A: Note 1B: Note 1C: Note 1D: be applied in this order Input Differential Voltage ................................2.0VP-P differential Continuous Power Dissipation (TA = +70°C) 68-Pin TQFN (derated 40mW/°C above +70°C) ..................4W Operating Temperature Range (Note 1A) ..............0°C to +70°C Junction Temperature ......................................................+150°C θJC (Note 1B, 1C) .........................................................+0.3°C/W θJA (Note 1C, 1D) ..........................................................+20°C/W Storage Temperature Range .............................-40°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C TC is the temperature on the exposed pad of the package. TA is the ambient temperature of the device and PCB. Junction temperature TJ = TC + (θJC x VCC x ICC). This formula can only be used if the component is soldered down to a printed circuit board pad containing multiple ground vias to remove the heat. The junction temperature must not exceed 150°C. Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Junction temperature TJ = TA + (θJA x VCC x ICC), assuming there is no heat removal from the exposed pad. The junction temperature must not exceed 150°C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0°C to +70°C, VGND = 0V, CLP = 0, PD = 0, no RF signals applied. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL 3.3V Supply Voltage VCC1 4.75V/5V Supply Voltage VCC2 External Reference Voltage Range VREF CONDITIONS (Note 3) MIN TYP MAX UNITS 3.13 3.3 3.47 V 4.5 4.75 2.475 5.25 V 2.525 V CMOS Input High Voltage VIH Applies to CMOS control inputs CMOS Input Low Voltage VIL Applies to CMOS control inputs 0.8 V IIN TA = +25oC, applies to CMOS control inputs; input current = 0V, output current = 3.47V 10 µA CMOS Input Leakage Current 2.5 V DATA Output High Voltage DOUT_HI 10MΩ load VCC1 V DATA Output Low Voltage DOUT_LO 10MΩ load 0 V DC ELECTRICAL CHARACTERISTICS—VGA MODE (Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0°C to +70°C, VGND = 0V, NP = 0, V/C = 1, CLP = 0, PD = 0, no RF signals applied. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL TYP MAX UNITS 4.75V/5V Supply Standby Current I_NP_5V_TOT NP = 1, all channels CONDITIONS MIN 3.9 6 mA 3V Supply Standby Current I_NP_3V_TOT NP = 1, all channels 1.7 3 mA 4.75V/5V Power-Down Current I_PD_5V_TOT PD = 1, all channels 0.4 10 µA 3V Power-Down Current I_PD_3V_TOT PD = VCC1, all channels 0.3 10 µA 3V Supply Current per Channel I_3V_NM Total I divided by 8, VG+ - VG1 = -2V 11 16 mA 4.75V/5V Supply Current per Channel I_5V_NM Total I divided by 8 6.0 8.3 mA 64.8 92.3 mW DC Power per Channel 2 P_NM _______________________________________________________________________________________ Octal-Channel Ultrasound Front-End with CW Doppler Mixers (Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0°C to +70°C, VGND = 0V, NP = 0, V/C = 1, CLP = 0, PD = 0, no RF signals applied. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS Differential Analog Control Voltage Range VGAIN_RANG VG+ - VG- Common-Mode Voltage for Difference Analog Control VGAIN_COMM Source/Sink Current for Gain Control Pins I_ACONTROL Reference Voltage Input VREF Reference Current IREF Output Common-Mode Level MIN TYP MAX UNITS ±3 V (VG+ + VG-)/2 1.65 ±5% V Per pin ±1.6 2.475 All channels 9.7 VCMO ±2.3 µA 2.525 V 13 µA 1.73 V DC ELECTRICAL CHARACTERISTICS—CW MODE (Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0°C to +70°C, VGND = 0V, NP = 0, PD = 0, CLP = 0, V/C = 0, no RF signals applied. CI_, CQ_ pulled up to 11V through four separate 0.1% 162Ω resistors. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER Reference Current SYMBOL CONDITIONS MIN IREF TYP MAX UNITS 82.7 µA 1.25 ±0.2 V 700 mVP-P 130 µA Mixer LVDS LO Input Common-Mode Voltage V_LVDS_CM LO+ and LO- LVDS LO Differential Input Voltage V_LVDS_DM Common-mode input voltage = 1.25V (Note 4) LVDS LO Input Common-Mode Current I_LVDS_CM Current out of each pin, V_LVDS_CM = 1.25V LVDS LO Differential Input Resistance R_DM_LVDS (Note 5) I_C_5V_P PD = 1 0.6 10 µA I_C_3_3V_P PD = 1 0.1 10 µA I_C_5V_N CLP = 1 27 30 mA 3.3V Supply Current per Channel I_C_3_3V_N CLP = 1 0.4 0.95 mA 11V Supply Current per Channel I_C_11V_N CLP = 1 6.8 8.4 mA On-Chip Power Dissipation (All 8 Channels) PDIS_FP_TOT_N CLP = 1 1.44 1.7 W 31 34 mA 200 4 kΩ POWER-DOWN MODE 4.75V/5V Supply Current per Channel 3.3V Supply Current per Channel LOW-POWER MODE 4.75V/5V Supply Current per Channel NORMAL POWER MODE 4.75V/5V Supply Current per Channel I_C_5V_L 3.3V Supply Current per Channel I_C_3_3V_L 0.4 0.95 mA 11V Supply Current per Channel I_C_11V_L 11.3 13 mA On-Chip Power Dissipation (All 8 Channels) PDIS_FP_TOT_L 1.87 2.2 W (Note 6) _______________________________________________________________________________________ 3 MAX2078 DC ELECTRICAL CHARACTERISTICS—VGA MODE (continued) MAX2078 Octal-Channel Ultrasound Front-End with CW Doppler Mixers AC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0°C to +70°C, VGND = 0V, NP = 0, PD = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200Ω, LNA gain = 18.5dB, D45/D44=1/1(fC = 18MHz), fRF = fLO/16 = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1kΩ differential, reference noise less than 10nV/√Hz from 1kHz to 20MHz, DOUT loaded with 10MΩ and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER Mode Select Response Time (Note 7) CONDITIONS MIN TYP V/C stepped from 0 to 1, DC stable within 10% 1 V/C stepped from 1 to 0, DC stable within 10% 1 MAX UNITS µs High LNA gain D43/D42/D41/D40 = 1/0/1/0 0.33 VP-P differential Low Gain Maximum Input-Voltage Low LNA gain D43/D42/D41/D40 = 0/0/0/1 Range 0.6 VP-P differential High Gain Maximum InputVoltage Range AC ELECTRICAL CHARACTERISTICS—VGA MODE (Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0°C to +70°C, VGND = 0V, V/C = 1, NP = 0, PD = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200Ω, LNA gain = 18.5dB), D45/D44 = 1/1(fC = 18MHz), fRF = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1kΩ differential, reference noise less than 10nV/√Hz from 1kHz to 20MHz, DOUT loaded with 10MΩ and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX 47.5 50 60 D42/D41/D40 = 0/0/1, RIN = 100Ω 90 100 110 D42/D41/D40 = 0/1/0, RIN = 200Ω 185 200 210 D42/D41/D40 = 0/1/1, RIN = 1000Ω, fRF = 2MHz 700 830 1000 D42/D41/D40 = 0/0/0, RIN = 50Ω Input Impedance Noise Figure Low-Gain Noise Figure RS = RIN = 50Ω, VG+ - VG- = +3V 4.5 RS = RIN =100Ω, VG+ - VG- = +3V 3.4 RS = RIN = 200Ω, VG+ - VG- = +3V 2.4 RS = RIN = 1000Ω, VG+ - VG- = +3V 2.1 D43/D42/D41/D40 = 0/0/0/1, LNA gain = 12.5dB, RS = RIN = 200Ω, VG+ - VG- = +3V 3.9 UNITS Ω dB dB Input-Referred Noise Voltage D43/D42/D41/D40 = 1/1/1/0 0.9 nV/√Hz Input-Referred Noise Current D43/D42/D41/D40 = 1/1/1/0 2.1 pA/√Hz Maximum Gain, High Gain Setting VG+ - VG- = +3V 41 42.8 45 dB Minimum Gain, High Gain Setting VG+ - VG- = -3V 8.5 10 11 dB Maximum Gain, Low Gain Setting D43/D42/D41/D40 = 0/0/0/1, VG+ - VG- = +3V 35 36.8 38 dB Minimum Gain, Low Gain Setting D43/D42/D41/D40 = 0/0/0/1, VG+ - VG- = -3V 2.5 4 6 dB Anti-Aliasing Filter 3dB Corner Frequency Gain Range 4 D45/D44 = 0/0, fC = 9MHz 9 D45/D44 = 0/1, fC = 10MHz 10 D45/D44 = 1/0, fC = 15MHz 15 D45/D44 = 1/1, fC = 18MHz 18 VG+ - VG- = -3V to +3V 33 _______________________________________________________________________________________ MHz dB Octal-Channel Ultrasound Front-End with CW Doppler Mixers (Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0°C to +70°C, VGND = 0V, V/C = 1, NP = 0, PD = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200Ω, LNA gain = 18.5dB), D45/D44 = 1/1(fC = 18MHz), fRF = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1kΩ differential, reference noise less than 10nV/√Hz from 1kHz to 20MHz, DOUT loaded with 10MΩ and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN Measured at TA = +25oC, VG+ - VG- = -2V Absolute Gain Error TYP MAX UNITS ±0.4 Measured at TA = +25oC, VG+ - VG- = 0V ±0.4 Measured at TA = +25oC, VG+ - VG- = +2V ±0.4 dB VG+ - VG- = -3V (VGA minimum gain), gain ratio with 330mVP-P/50mVP-P input tones 1.4 LNA low gain = 12.5dB, VG+ - VG- = -3V (VGA minimum gain), gain ratio with 600mVP-P/50mVP-P 0.8 Gain step up (VIN = 5mVP-P, gain changed from 10dB to 44dB, settling time is measured within 1dB final value) 1.4 Gain step down (VIN = 5mVP-P, gain changed from 44dB to 10dB, settling time is measured within 1dB final value) 1.6 VGA Output Offset Under Pulsed Overload Overdrive is ±10mA in clamping diodes, gain at 30dB, 16 pulses at 5MHz, repetition rate 20kHz; offset is measured at output when RF duty cycle is off 180 mV Small-Signal Output Noise 20dB of gain, VG+ - VG- = -0.85, no input signal 23 nV/√Hz Large-Signal Output Noise 20dB of gain, VG+ - VG- = -0.85, fRF = 5MHz, fNOISE = fRF + 1kHz, VOUT = 1VP-P differential 35 nV/√Hz VIN = 50mVP-P, fRF = 2MHz, VOUT = 1VP-P -67 VIN = 50mVP-P, fRF = 5MHz, VOUT = 1VP-P -64.2 Input Gain Compression dB µs VGA Gain Response Time Second Harmonic (HD2) dBc High-Gain IM3 Distortion VIN = 50mVP-P, fRF1 = 5MHz, fRF2 = 5.01MHz, VOUT = 1VP-P (Note 8) -52 -61 dBc Low-Gain IM3 Distortion D43/D42/D41/D40 = 0/0/0/1 (RIN = 200Ω, LNA gain = 12.5dB),VIN = 100mVP-P, fRF1 = 5MHz, fRF2 = 5.01MHz, VOUT = 1VP-P (Note 8) -50 -60 dBc Standby Mode Power-Up Response Time Gain set for 26dB fRF = 5MHz, VOUT = 1VP-P, settled with in 1dB from transition on NP pin 2.1 µs Standby Mode Power-Down Response Time To reach DC current target ±10% 2.0 µs Power-Up Response Time Gain set for 28dB, fRF = 5MHz, VOUT = 1VP-P, settled within 1dB from transition on PD 2.7 ms Power-Down Response Time Gain set for 28dB, fRF = 5MHz, DC power reaches 6mW/channel, from transition on PD 5 ns Adjacent Channel Crosstalk VOUT = 1VP-P differential, fRF = 10MHz, 28dB of gain -58 dBc Nonadjacent Channel Crosstalk VOUT = 1VP-P differential, fRF = 10MHz, 28dB of gain -71 dBc Phase Matching Between Channels Gain = 28dB, VG+ - VG- = 0.4V, VOUT = 1VP-P, fRF = 10MHz ±1.2 Degrees _______________________________________________________________________________________ 5 MAX2078 AC ELECTRICAL CHARACTERISTICS—VGA MODE (continued) MAX2078 Octal-Channel Ultrasound Front-End with CW Doppler Mixers AC ELECTRICAL CHARACTERISTICS—VGA MODE (continued) (Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0°C to +70°C, VGND = 0V, V/C = 1, NP = 0, PD = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200Ω, LNA gain = 18.5dB), D45/D44 = 1/1(fC = 18MHz), fRF = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1kΩ differential, reference noise less than 10nV/√Hz from 1kHz to 20MHz, DOUT loaded with 10MΩ and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS 3V Supply Modulation Ratio Gain = 28dB, VG+ - VG- = 0.4V, VOUT = 1VP-P, fRF = 5MHz, fMOD = 1kHz, VMOD = 50mVP-P, ratio of output sideband at 5.001MHz, 1VP-P -73 dBc 4.75V/5V Supply Modulation Ratio Gain = 28dB, VG+ - VG- = 0.4V, VOUT = 1VP-P, fRF = 5MHz, fMOD = 1kHz, VMOD = 50mVP-P, ratio of output sideband at 5.001MHz, 1VP-P -82 dBc Gain Control Lines CommonMode Rejection Ratio Gain = 28dB, VG+ - VG- = 0.4V, fMOD = 5MHz, VMOD = 50mVP-P, VOUT = 1.0VP-P -74 dBc Overdrive Phase Delay VG+ - VG- = -3V, delay between VIN = 300mVP-P and VIN = 30mVP-P differential 5 ns Output Impedance Differential 100 Ω AC ELECTRICAL CHARACTERISTICS—CW MODE (Typical Application Circuit, V/C = 0, PD = 0, NP = 0, CLP = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200Ω, LNA gain = 18.5dB), fRF = fLO/16 = 5MHz, RS = 200Ω, CI_, CQ_ pulled up to 11V through four separate 0.1% 162Ω resistors, the rise/fall time of the LVDS clock driving the LO_ is required to be 0.5ns, reference noise less than 10nV/√Hz from 1kHz to 20MHz (Note 9). Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS CW DOPPLER MIXER Mixer RF Frequency Range LO Frequency Range LO+ and LO- Mixer Output Frequency Range 0.9 7.6 MHz 16 120 MHz DC 100 kHz FULL-POWER MODE Noise Figure No carrier 3.4 dB Noise Figure at 100mVP-P Input 100mVP-P at input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset 3.6 dB Noise Figure at 200mVP-P Input 200mVP-P at input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset 4.1 dB SNR at 100mVP-P Input 100mVP-P at input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset -148.3 dBc/Hz SNR at 200mVP-P Input 200mVP-P at input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset -153.8 dBc/Hz 6 _______________________________________________________________________________________ Octal-Channel Ultrasound Front-End with CW Doppler Mixers (Typical Application Circuit, V/C = 0, PD = 0, NP = 0, CLP = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200Ω, LNA gain = 18.5dB), fRF = fLO/16 = 5MHz, RS = 200Ω, CI_, CQ_ pulled up to 11V through four separate 0.1% 162Ω resistors, the rise/fall time of the LVDS clock driving the LO_ is required to be 0.5ns, reference noise less than 10nV/√Hz from 1kHz to 20MHz (Note 9). Typical values are at VCC1 = 3.3V, VCC2 = 4.75V, TA = +25°C, unless otherwise noted.) (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS -50 -55 dBc -48.5 dBc Two-Tone Intermodulation IMD3 at 100mV fRF1 = 5MHz, 0.1VP-P, fRF2 = 5.01MHz at -25dBc, fLO = 80MHz (Note 8) Two-Tone Intermodulation IMD3 at 200mV fRF1 = 5MHz, 0.2VP-P, fRF2 = 5.01MHz at -25dBc, fLO = 80MHz (Note 8) Mixer Output-Voltage Compliance Valid voltage range (AC + DC) on summed mixer output pins Channel-to-Channel Phase Matching Measured under zero beat conditions, VRF = 100mVP-P, fRF = 5MHz, fLO = 80MHz (Note 10) ±0.4 Degrees Channel-to-Channel Gain Matching Measured under zero beat conditions, VRF = 100mVP-P, fRF = 5MHz, fLO = 80MHz (Notes 10, 11) ±0.2 dB Transconductance Calculated from LNA input voltage and twice the I or Q current 4.5 12 fRF = 0.9MHz, fLO/16 = 1MHz 19 23 26 fRF = 7.6MHz, fLO/16 = 7.5MHz 19 22.5 26 V mS LOW-POWER MODE (CLP = 1) Noise Figure No carrier 3.2 dB Noise Figure at 100mVP-P Input 100mVP-P on input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset 3.5 dB Noise Figure at 200mVP-P Input 200mVP-P on input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset 4.3 dB SNR at 100mVP-P Input 100mVP-P on input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset -148.2 dBc/Hz SNR at 200mVP-P Input 200mVP-P on input, fRF = fLO/16 = 1.25MHz, measured at 1kHz offset -153.6 dBc/Hz Two-Tone Intermodulation IMD3 fRF1 = 5MHz, 0.1VP-P, fRF2 = 5.01MHz at -25dBc, fLO = 80MHz (Note 8) -44 dBc Mixer Output-Voltage Compliance Valid voltage range on summed mixer output pins (Note 12) Transconductance (Note 13) Calculated from LNA input voltage and twice the I or Q current 4.5 fRF = 1.1MHz, fLO/16 = 1MHz 19 fRF = 7.6MHz, fLO/16 = 7.5MHz 19 12 21.5 V 26 mS 21.5 26 _______________________________________________________________________________________ 7 MAX2078 AC ELECTRICAL CHARACTERISTICS—CW MODE (continued) MAX2078 Octal-Channel Ultrasound Front-End with CW Doppler Mixers AC ELECTRICAL CHARACTERISTICS—SERIAL PERIPHERAL INTERFACE (DOUT loaded with 60pF and 10MΩ, 2ns rise and fall edges on CLK.) PARAMETER SYMBOL CONDITIONS MIN TYP Clock Speed MAX UNITS 10 MHz Mininimum Data-to-Clock Setup Time tCS 5 ns Mininimum Data-to-Clock Hold Time tCH 0 ns Mininimum Clock-to-CS Setup Time tES 5 ns CS Positive Mininimum Pulse Width tEW 1 ns Mininimum Clock Pulse Width tCW 2 ns Mininimum CS High to Mixer Clock on tMIXCS 2 ns Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: 8 Minimum and maximum limits at TA = +25°C and +70°C are guaranteed by design, characterization, and/or production test. Noise performance of the device is dependent on the noise contribution from VREF. Use a low-noise supply for VREF. Note that the LVDS CWD LO clocks are DC-coupled. This is to ensure immediate synchronization when the clock is first turned on. An AC-coupled LO is problematic in that the RC time constant associated with the coupling capacitors and the input impedance of the pin causes a period of time (related to the RC time constant) when the DC level on the chip side of the capacitor is outside the acceptable common-mode range and the LO swing does not excede both of the logic thresholds required for proper operation. This problem associated with AC-coupling causes an inability to ensure synchronization among beamforming channels. The LVDS signal is terminated differentially with an external 100Ω resistor on the board. An external 100Ω resistor terminates the LVDS differential signal path. Total on-chip power dissipation is calculated as PDISS = VCC1 x ICC1 + VCC2 x ICC2 + VREF x IREF + [11V - (I11V/4) x 162] x I11V. This response time does not include the CW output highpass filter. When switching to VGA mode, the CW outputs stop drawing current and the output voltage goes to the rail. If a highpass filter is used, the recovery time may be excessive and a switching network is recommended, as shown in the Applications Information section. See the Ultrasound-Specific IMD3 Specification section. The reference input noise is given for 8 channels, knowing that the reference-noise contributions are correlated in all 8 channels. If more channels are used, the reference noise must be reduced to get the best noise performance. Channel-to-channel gain and phase matching measured on 30 pieces during engineering characterization at room temperature. Each mixer is used as a phase detector and produces a DC voltage in the IQ plane. The phase is given by the angle of the vector drawn on that plane. Multiple channels from multiple parts are compared to each other to produce the phase variation. Voltage gain is measured by subtracting the output-voltage signal from the input-voltage signal. The output-voltage signal is obtained by taking the differential CW I output and summing it in quadrature with the differential CW Q output. The input voltage is defined as the differential voltage applied to the CW input pins. Mixer output-voltage compliance is the range of acceptable voltages allowed on the CW mixer outputs. Transconductance is defined as the quadrature-combined CW differential output current at baseband divided by the mixer’s input voltage. _______________________________________________________________________________________ Octal-Channel Ultrasound Front-End with CW Doppler Mixers COMPLEX INPUT IMPEDANCE MAGNITUDE vs. FREQUENCY 1kΩ 600 50Ω 100Ω 5 15 20 FREQUENCY (MHz) 0.275 CONTROL VOLTAGE (V) 10 0.225 5 0.175 0 0.125 3 0.075 2 0.025 1 -0.025 0 -0.175 -1 -0.075 0 0 -2 MAX2078 toc03 200Ω 200 -3 15 10 400 15 5 GAIN = 20dB 20 % UNITS 25 GAIN ERROR HISTOGRAM 25 MAX2078 toc02 800 INPUT IMPEDANCE (Ω) 35 GAIN (dB) 1000 MAX2078 toc01 45 -0.125 GAIN vs. DIFFERENTIAL ANALOG CONTROL VOLTAGE GAIN ERROR (dB) 5 90 60 VOUT = 1VP-P -40 fRF = 10MHz -50 4 HD2 (dBc) NOISE (nV/√Hz) 120 -30 MAX2078 toc05 MAX2078 toc04 150 NOISE (nV/√Hz) INPUT-REFERRED NOISE vs. GAIN 6 MAX2078 toc06 OUTPUT-REFERRED NOISE vs. GAIN 180 SECOND-HARMONIC DISTORTION vs. GAIN 3 -60 -70 fRF = 5MHz 2 30 -80 fRF = 2MHz 0 -90 1 8 17 26 GAIN (dB) 35 44 8 17 26 GAIN (dB) 35 44 20 26 32 38 44 GAIN (dB) _______________________________________________________________________________________ 9 MAX2078 Typical Operating Characteristics (Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0°C to +70°C, VGND = 0V, NP = 0, PD = 0, CLP = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200Ω, LNA gain = 18.5dB), D45/D44 = 1/1(fC = 18MHz), fRF = fLO/16 = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1kΩ differential, RS = 200Ω, CI_, CQ_ pulled up to 11V through four separate 0.1% 162Ω resistors, the rise/fall time of the LVDS clock driving the LO_ is required to be 0.5ns, reference noise less than 10nV/√Hz from 1kHz to 20MHz, DOUT loaded with 10MΩ and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 5V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0°C to +70°C, VGND = 0V, NP = 0, PD = 0, CLP = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200Ω, LNA gain = 18.5dB), D45/D44 = 1/1(fC = 18MHz), fRF = fLO/16 = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1kΩ differential, RS = 200Ω, CI_, CQ_ pulled up to 11V through four separate 0.1% 162Ω resistors, the rise/fall time of the LVDS clock driving the LO_ is required to be 0.5ns, reference noise less than 10nV/√Hz from 1kHz to 20MHz, DOUT loaded with 10MΩ and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 5V, TA = +25°C, unless otherwise noted.) VOUT = 1VP-P -40 -50 MAX2078 toc08 -10 MAX2078 toc07 -30 SECOND- AND THIRD-HARMONIC DISTORTION vs. VOUT_P-P TWO-TONE ULTRASOUND-SPECIFIC IMD3 vs. GAIN VOUT = 1VP-P HD2 and HD3 (dBc) IMD3 (dBc) HD3 (dBc) fRF = 10MHz fRF = 10MHz -60 GAIN = 26dB fRF = 5MHz -60 -30 fRF = 5MHz -50 MAX2078 toc09 THIRD-HARMONIC DISTORTION vs. GAIN -50 fRF = 5MHz -70 HD2 -70 HD3 -80 -70 -80 fRF = 2MHz fRF = 2MHz -90 26 32 38 44 20 26 32 38 0 44 0.2 0.4 0.8 1.0 VOUT_P-P (V) SECOND- AND THIRD-HARMONIC DISTORTION vs. FREQUENCY SECOND- AND THIRD-HARMONIC DISTORTION vs. DIFFERENTIAL OUTPUT RESISTANCE SECOND- AND THIRD-HARMONIC DISTORTION vs. DIFFERENTIAL OUTPUT LOAD CAPACITANCE -40 HD2 AND HD3 (dBc) HD2 -50 -60 -50 VOUT = 1VP-P GAIN = 26dB fRF = 5MHz HD2 -60 -70 VOUT = 1VP-P GAIN = 26dB fRF = 5MHz -40 HD2 AND DH3 (dBc) -40 -30 MAX2078 toc11 -30 MAX2078 toc12 GAIN (dB) VOUT = 1VP-P GAIN = 26dB -50 HD2 -60 -70 HD3 HD3 -70 -80 HD3 -80 -80 -90 0 0.6 GAIN (dB) MAX2078 toc10 -30 5 10 FREQUENCY (MHz) 10 -90 -90 20 HD2 AND HD3 (dBc) MAX2078 Octal-Channel Ultrasound Front-End with CW Doppler Mixers 15 20 -90 200 300 400 500 600 700 800 900 1000 RESISTANCE (Ω) 0 20 40 60 CAPACITANCE (pF) ______________________________________________________________________________________ 80 100 Octal-Channel Ultrasound Front-End with CW Doppler Mixers MAX2078 Typical Operating Characteristics (continued) (Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0°C to +70°C, VGND = 0V, NP = 0, PD = 0, CLP = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200Ω, LNA gain = 18.5dB), D45/D44 = 1/1(fC = 18MHz), fRF = fLO/16 = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1kΩ differential, RS = 200Ω, CI_, CQ_ pulled up to 11V through four separate 0.1% 162Ω resistors, the rise/fall time of the LVDS clock driving the LO_ is required to be 0.5ns, reference noise less than 10nV/√Hz from 1kHz to 20MHz, DOUT loaded with 10MΩ and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 5V, TA = +25°C, unless otherwise noted.) VOUT = 1VP-P GAIN = 26dB -55 -40 -60 0 VOUT = 1VP-P GAIN = 20dB ADJACENT CHANNEL 1 CROSSTALK (dBc) CROSSTALK (dBc) IMD3 (dBc) -20 VOUT = 1VP-P fRF = 10MHz MAX2078 toc15 -50 MAX2078 toc13 0 ADJACENT CHANNEL-TO-CHANNEL CROSSTALK vs. FREQUENCY ADJACENT CHANNEL-TO-CHANNEL CROSSTALK vs. GAIN MAX2078 toc14 TWO-TONE ULTRASOUND-SPECIFIC IMD3 vs. FREQUENCY -60 ADJACENT CHANNEL 2 -65 -30 ADJACENT CHANNEL 1 -60 ADJACENT CHANNEL 2 5 10 15 20 8 17 26 35 100 GAIN (dB) FREQUENCY (MHz) LARGE-SIGNAL BANDWIDTH vs. FREQUENCY COMMON-MODE OUTPUT VOLTAGE vs. GAIN DIFFERENTIAL OUTPUT IMPEDANCE vs. FREQUENCY 10 18MHz 9MHz 0 10MHz -10 -20 1.8 REAL COMPONENT (Ω) 15MHz 1.7 FREQUENCY (MHz) 100 REAL 40 60 20 IMAGINARY 0 0 8 17 26 GAIN (dB) 35 44 80 60 120 1.6 1.5 10 MAX2078 toc18 180 MAX2078 toc17 20 1.9 COMMON-MODE OUTPUT VOLTAGE (V) VOUT = 1VP-P GAIN = 20dB 1 10 1 44 FREQUENCY (MHz) MAX2078 toc16 30 GAIN (dB) -90 -70 0 0 10 20 30 40 50 FREQUENCY (MHz) ______________________________________________________________________________________ 11 IMAGINARY COMPONENT (Ω) -80 Octal-Channel Ultrasound Front-End with CW Doppler Mixers MAX2078 Typical Operating Characteristics (continued) (Typical Application Circuit, VREF = 2.475V to 2.525V, VCC1 = 3.13V to 3.47V, VCC2 = 4.5V to 5.25V, TA = 0°C to +70°C, VGND = 0V, NP = 0, PD = 0, CLP = 0, D43/D42/D41/D40 = 1/0/1/0 (RIN = 200Ω, LNA gain = 18.5dB), D45/D44 = 1/1(fC = 18MHz), fRF = fLO/16 = 5MHz, capacitance to GND at each of the VGA differential outputs is 25pF, differential capacitance across VGA outputs is 15pF, RL = 1kΩ differential, RS = 200Ω, CI_, CQ_ pulled up to 11V through four separate 0.1% 162Ω resistors, the rise/fall time of the LVDS clock driving the LO_ is required to be 0.5ns, reference noise less than 10nV/√Hz from 1kHz to 20MHz, DOUT loaded with 10MΩ and 60pF. Typical values are at VCC1 = 3.3V, VCC2 = 5V, TA = +25°C, unless otherwise noted.) MAX2078 toc19 1.25 VGA OVERLOAD RECOVERY TIME (VIN = 40mVP-P for 1μs TO 4mVP-P for 1μs AND BACK TO 40mVP-P for 1μs, GAIN = 42.5dB) 0.5 MAX2078 toc20 3 45 0.05 INPUT = 300mVP-P INPUT -0.5 -0.25 -1.0 0 1 -0.05 0 -0.10 -1 OUTPUT PHASE DELAY (ns) 0.25 36 2 INPUT (V) 0 OUTPUT (V) 0.75 INPUT (V) OUTPUT (V) INPUT OVERDRIVE PHASE DELAY vs. FREQUENCY MAX2078 toc21 LNA OVERLOAD RECOVERY TIME (VIN = 500mVP-P for 1μs TO 100mVP-P for 1μs AND BACK TO 500mVP-P for 1μs, GAIN = 10dB) 27 18 INPUT = 30mVP-P 9 OUTPUT GAIN = 10dB -0.75 500 1000 1500 -2 0 500 1000 1500 0 -0.15 2000 0 10 15 FREQUENCY (MHz) GROUP DELAY vs. FREQUENCY CW IMD3 vs. FREQUENCY INPUT-REFERRED NOISE vs. INPUT CLUTTER VOLTAGE MAX2078 toc22 -48 VIN = 100mVP-P 1.48 GAIN = 40dB GAIN = 30dB NOISE (nV/√Hz) CW IMD3 (dBc) 35 -56 fCLUTTER = 1.25MHz OFFSET = 1kHz 1.44 -52 20 MAX2078 toc24 TIME (ns) 45 GROUP DELAY (ns) 5 TIME (ns) MAX2078 toc23 0 -1.5 2000 1.40 NORMAL POWER MODE 1.36 25 -60 1.32 LOW-POWER MODE GAIN = 20dB GAIN = 10dB 15 5 10 FREQUENCY (MHz) 12 1.28 -64 0 15 20 0 2 4 FREQUENCY (MHz) 6 8 0 50 100 150 INPUT CLUTTER VOLTAGE (mVP-P) ______________________________________________________________________________________ 200 Octal-Channel Ultrasound Front-End with CW Doppler Mixers PIN NAME 1 IN2 FUNCTION 2 INC2 Channel 2 Clamp Input. Connect to a coupling capacitor. See the Typical Application Circuit for details. 3 ZF3 Channel 3 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. 4 IN3 Channel 3 Input 5 INC3 Channel 3 Clamp Input. Connect to a coupling capacitor. See the Typical Application Circuit for details. 6 ZF4 Channel 4 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. 7 IN4 Channel 4 Input 8 INC4 Channel 4 Clamp Input. Connect to the input coupling capacitor. See the Typical Application Circuit for details. 9, 28, 31 GND Ground Channel 2 Input 10 AG 11 ZF5 AC Ground. Connect a low-ESR 1µF capacitor to ground. Channel 5 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. 12 IN5 Channel 5 Input 13 INC5 Channel 5 Clamp Input. Connect to a coupling capacitor. See the Typical Application Circuit for details. 14 ZF6 Channel 6 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. 15 IN6 Channel 6 Input 16 INC6 Channel 6 Clamp Input. Connect to a coupling capacitor. See the Typical Application Circuit for details. 17 ZF7 Channel 7 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. 18 IN7 Channel 7 Input 19 INC7 20 ZF8 Channel 8 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. 21 IN8 Channel 8 Input 22 INC8 Channel 8 Clamp Input. Connect to a coupling capacitor. See the Typical Application Circuit for details. 23, 33, 53, 64 VCC2 4.75V Power Supply. Connect to an external 4.75V power supply. Connect all 4.75V supply pins together externally and bypass with 100nF capacitors as close as possible to the pin. 24 VREF External 2.5V Reference Supply. Connect to a low-noise power supply. Bypass to GND with a 0.1µF capacitor as close as possible to the pins. Note that noise performance of the device is dependent on the noise contribution from VREF. Use a low-noise supply for VREF. 25, 44, 63 VCC1 3.3V Power Supply. Connect to an external 3V power supply. Connect all 3.3V supply pins together externally and bypass with 100nF capacitors as close as possible to the pin. 26 VG+ 27 VG- VGA Analog Gain Control Differential Input. Set the differential voltage to -3V for maximum gain and to +3V for minimum gain. 29 CLP CW Low-Power Mode Select Input. Drive CLP high to place CW mixers in low-power mode. 30 PD Power-Down Mode Select Input. Set PD to VCC1 to place the entire device in power-down mode. Drive PD low for normal operation. This mode overrides the standby mode. Channel 7 Clamp Input. Connect to the input coupling capacitor. See the Typical Application Circuit for details. 32 DOUT Serial Port Data Output. Data output for ease of daisy-chain programming. The level is 3.3V CMOS. 34 OUT8- Channel 8 Negative Differential Output 35 OUT8+ Channel 8 Positive Differential Output 36 OUT7- Channel 7 Negative Differential Output ______________________________________________________________________________________ 13 MAX2078 Pin Description Octal-Channel Ultrasound Front-End with CW Doppler Mixers MAX2078 Pin Description (continued) PIN NAME 37 OUT7+ Channel 7 Positive Differential Output 38 OUT6- Channel 6 Negative Differential Output 39 OUT6+ Channel 6 Positive Differential Output 40 OUT5- Channel 5 Negative Differential Output 41 OUT5+ Channel 5 Positive Differential Output 42 LO- 43 LO+ Differential Local Oscillator Input. LO is divided in the beamformer. 45 OUT4- Channel 4 Negative Differential Output 46 OUT4+ Channel 4 Positive Differential Output 47 OUT3- Channel 3 Negative Differential Output 48 OUT3+ Channel 3 Positive Differential Output 49 OUT2- Channel 2 Negative Differential Output 50 OUT2+ Channel 2 Positive Differential Output 51 OUT1- Channel 1 Negative Differential Output 52 OUT1+ Channel 1 Positive Differential Output 54 CLK Serial Port Clock Input (Positive Edge Triggered). 3.3V CMOS. Clock input for programming the serial shift registers. 55 DIN Serial Port Data Input. 3.3V CMOS. Data input to program the serial shift registers. 56 CS Serial Port Chip Select Input. 3.3V CMOS. Used to store programming bits in registers, as well as in CW mode, synchronizing all channel phases (on a rising edge). 57 NP VGA Standby Mode Select Input. Set NP to 1 to place the entire device in standby mode. Overrides soft channel shutdown in serial shift register, but not general power-down (PD). 58 V/C VGA/CW Mode Select Input. Set V/C to a logic-high to enable the VGAs and disable CW mode. Set V/C to a logic-low to enable the CW mixers and disable the VGA mode. 59 CQ- 8-Channel CW Negative Quadrature Output. Connect to an external 11V power supply with a 162Ω external pullup resistor. 60 CQ+ 8-Channel CW Positive Quadrature Output. Connect to an external 11V power supply with a 162Ω external pullup resistor. 61 CI- 8-Channel CW Negative In-Phase Output. Connect to an external 11V power supply with a 162Ω external pullup resistor. 62 CI+ 8-Channel CW Positive In-Phase Output. Connect to an external 11V power supply with a 162Ω external pullup resistor. 65 ZF1 Channel 1 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. 66 IN1 Channel 1 Positive Differential Input 67 INC1 68 ZF2 Channel 2 Active Impedance Matching Line. AC-couple to source with a 10nF capacitor. EP Exposed Pad. Internally connected to ground. Connect to a large ground plane using multiple vias to maximize thermal and electrical performance. Not intended as an electrical connection point. — 14 FUNCTION Channel 1 Clamp Input. Connect to the input coupling capacitor. ______________________________________________________________________________________ Octal-Channel Ultrasound Front-End with CW Doppler Mixers CQCQ+ MAX2078 CICI+ V/C NP CS DIN CLK VCC2 OUT1+ VCC1 VCC2 ZF1 IN1 OUT1- INC1 LNA VGA LNA VGA LNA VGA ANTI-ALIAS ZF2 OUT2+ IN2 OUT2- INC2 ANTI-ALIAS ZF3 OUT3+ IN3 OUT3- INC3 ANTI-ALIAS ZF4 OUT4+ IN4 OUT4- INC4 LNA VGA ANTI-ALIAS VCC1 GND LO+ LOZF5 AG OUT5+ IN5 OUT5- INC5 LNA VGA ANTI-ALIAS ZF6 OUT6+ IN6 OUT6- INC6 LNA VGA ANTI-ALIAS ZF7 OUT7+ IN7 OUT7- INC7 LNA VGA LNA VGA ANTI-ALIAS ZF8 OUT8+ IN8 INC8 OUT8ANTI-ALIAS ______________________________________________________________________________________ 15 MAX2078 Block Diagram MAX2078 Octal-Channel Ultrasound Front-End with CW Doppler Mixers Detailed Description The MAX2078 also integrates an octal quadrature mixer array and programmable LO phase generators for a complete continuous-wave Doppler (CWD) beamforming solution. Separate mixers for each channel are available for optimal CWD sensitivity, yielding an impressive SNR of 154dBc/Hz at 1kHz offset from a 200mVP-P, 1.25MHz input signal. The LO phase selection for each channel is programmed using a digital serial interface and a single high-frequency clock. The serial interface is designed to allow multiple devices to be easily daisy-chained to minimize program interface wiring. The outputs of the mixers are summed into single I and Q differential current outputs. The MAX2078 is a high-density, octal-channel ultrasound receiver optimized for low cost, high-channel count, high-performance portable and cart-based ultrasound applications. The integrated octal LNA, VGA, AAF, and programmable CWD beamformer offer a complete multi-specialty, ultrasound receiver solution. Imaging path dynamic range has been optimized for exceptional second-harmonic performance. The complete imaging receive channel exhibits an exceptional 68dBFS** SNR at 5MHz. The bipolar front-end has also been optimized for exceptionally low near-carrier modulation noise for exceptional low-velocity pulsed and color-flow Doppler sensitivity under high-clutter conditions, achieving an impressive near-carrier SNR of 140dBc/Hz at 1kHz offset from a VOUT = 1VP-P, 5MHz clutter signal. Modes of Operation The MAX2078 requires programming before it can be used. The operating modes are controlled by 48 programming bits. Tables 1 and 2 show the functions of these programming bits. **When coupled with the MAX1437B ADC. Table 1. Summary of Programming Bits BIT NAME DESCRIPTION D40, D41, D42 Input impedance programming D43 LNA gain (D43 = 0 is low gain) D44, D45 Anti-alias filter fC programming D46 Don’t care D0–D39 Beamformer programming, from channel 1 to 8 Table 2. Logic Functions of Programming Bits D46 D45 D44 D43 D42 D41 D40 MODE X X X 1 0 0 0 RIN = 50Ω, LNA gain = 18.5dB X X X 1 0 0 1 RIN = 100Ω X X X 1 0 1 0 RIN = 200Ω X X X 1 0 1 1 RIN = 1000Ω X X X 0 0 0 0 RIN = 100Ω, LNA gain = 12.5dB X X X 0 0 0 1 RIN = 200Ω X X X 0 0 1 0 RIN = 400Ω X X X 0 0 1 1 RIN = 2000Ω X X X 1 1 X X Open feedback X 0 0 X X X X fC = 9MHz X 0 1 X X X X fC = 10MHz X 1 0 X X X X fC = 15MHz X 1 1 X X X X fC = 18MHz X = Don’t care. 16 ______________________________________________________________________________________ Octal-Channel Ultrasound Front-End with CW Doppler Mixers Overload Recovery The device is also optimized for quick overload recovery for operation under the large input signal conditions that are typically found in ultrasound input buffer imaging applications. See the Typical Operating Characteristics for an illustration of the rapid recovery time from a transmit-related overload. Octal Continuous-Wave (CW) Mixer The MAX2078 CW mixers are designed using an active double-balanced topology. The mixers achieve high dynamic range and high linearity performance, with exceptionally low thermal and jitter noise, ideal for ultrasound CWD signal reception. The octal quadrature mixer array provides noise performance of 154dBc/Hz at 1kHz offset from a 1.25MHz, 200mVP-P input clutter signal and a two-tone third-order ultrasound-specific intermodulation product of -48.5dBc (typ). See the Ultrasound-Specific IMD3 Specification section. The octal array exhibits quadrature and in-phase differential current outputs (CQ+, CQ-, CI+, CI-) to produce the total CWD beamformed signal. The maximum differential current output is typically 3mAP-P and the mixeroutput compliance voltage ranges from 4.5V to 12V. Variable-Gain Amplifier (VGA) The MAX2078’s VGAs are optimized for high linearity, high dynamic range, and low output-noise performance, all of which are critical parameters for ultrasound imaging applications. Each VGA path includes circuitry for adjusting analog gain, as well as an output buffer with differential output ports (OUT_+, OUT_-) for driving ADCs. See the High-Level CW Mixer and Programmable Beamformer Functional Diagram for details. The VGA gain can be adjusted through the differential gain control input VG+ and VG-. Set the differential gain control input voltage at -3V for minimum gain and +3V for maximum gain. The differential analog control commonmode voltage is 1.65V (typ). High-Level CW Mixer and Programmable Beamformer Functional Diagram CW_IN8 CW_IN7 CW_IN6 CW_IN5 MAX2078 CW_IN4 CW_IN3 CW_IN2 CW_IN1 CW_IOUT CW_QOUT I LO+ LO- Q CHANNEL 1 I/Q PHASE DIVIDER SELECTOR 5 DATA_IN I Q CHANNEL 2 I/Q PHASE DIVIDER SELECTOR 5 5-BIT SR I Q CHANNEL 3 I/Q PHASE DIVIDER SELECTOR 5 5-BIT SR I Q CHANNEL 4 I/Q PHASE DIVIDER SELECTOR 5 5-BIT SR I Q CHANNEL 5 I/Q PHASE DIVIDER SELECTOR 5 5-BIT SR I Q CHANNEL 6 I/Q PHASE DIVIDER SELECTOR I 5 5-BIT SR Q CHANNEL 7 I/Q PHASE DIVIDER SELECTOR 5 5-BIT SR I Q CHANNEL 8 I/Q PHASE DIVIDER SELECTOR 5 5-BIT SR 5-BIT SR DATA OUT CLK CS CLP PD ______________________________________________________________________________________ 17 MAX2078 Low-Noise Amplifier (LNA) The MAX2078’s LNA is optimized for excellent dynamic range and linearity performance characteristics, making it ideal for ultrasound imaging applications. When the LNA is placed in low-gain mode, the input resistance (RIN), being a function of the gain A (RIN = RF/(1+A)), increases by a factor of approximately 2. Consequently, the switches that control the feedback resistance (RF) have to be changed. For instance, the 100Ω mode in high gain becomes the 200Ω mode in low gain (see Table 2). MAX2078 Octal-Channel Ultrasound Front-End with CW Doppler Mixers Each mixer can be programmed to 1 of 16 phases; therefore, 4 bits are required for each channel for programming. Each CW channel can be programmed to an off state by setting bit Di to 1. The power-down mode (PD) line overrides this soft shutdown. After the serial shift registers have been programmed, the CS signal, when going high, loads the phase information in the form of 5 bits per channel into the I/Q phase divider/selectors. This presets the dividers, selecting the appropriate mixer phasing. See Table 3 for mixer phase configurations. CW Mixer Output Summation The outputs from the octal-channel mixer array are summed internally to produce the total CWD summed beamformed signal. The octal array produces eight differential quadrature (Q) outputs and eight differential in-phase (I) outputs. All quadrature and in-phase outputs are summed into single I and Q differential current outputs (CQ+, CQ-, CI+, CI-). LO Phase Select The LO phase dividers can be programmed through the shift registers to allow for 16 quadrature phases for a complete CW beamforming solution. Synchronization Figure 1 illustrates the serial programming of the eight individual channels through the serial data port. Note that the serial data can be daisy-chained from one part to another, allowing a single data line to be used to program multiple chips in the system. Table 3. Mixer Phase Configurations PER CHANNEL PHASE (DEGREE) 0 22.5 45 67.5 90 112.5 135 157.5 180 202.5 225 247.5 270 292.5 315 337.5 MSB Di + 4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Di + 3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DIN CLK LSB Di + 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Di + 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D46 D45 D44 D43 D42 D41 SHUTDOWN Di 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 D40 CHANNEL 1 A B C D SD CHANNEL 2 A B C D SD CHANNEL 3 A B C D SD CHANNEL 4 A B C D SD B4 B3 B2 B1 B0 B4 B3 B2 B1 B0 B4 B3 B2 B1 B0 B4 B3 B2 B1 B0 CHANNEL 5 A B C D SD CHANNEL 6 A B C D SD CHANNEL 7 A B C D SD CHANNEL 8 A B C D SD B4 B3 B2 B1 B0 B4 B3 B2 B1 B0 B4 B3 B2 B1 B0 B4 B3 B2 B1 B0 DOUT Figure 1. Data Flow of Serial Shift Register 18 ______________________________________________________________________________________ Octal-Channel Ultrasound Front-End with CW Doppler Mixers 162Ω 162Ω 1μF CI50Ω Applications Information Mode Select Response Time The mode select response time is the time that the device takes to switch between CW and VGA modes. Figure 2 depicts one possible approach to interfacing the CW outputs to an instrumentation amplifier, which is used to drive an ADC. In this implementation, there are four large-value (in the range of 470nF to 1µF) capacitors between each of the CQ+, CQ-, CI+, CI- outputs and the circuitry they are driving. The output of the CW 31.6kΩ 0.022μF Power-Down and Low-Power Mode The MAX2078 can also be powered down with PD. Set PD to V CC 1 for power-down mode. In power-down mode, the device draws a total supply current less than 1µA. Set PD to logic-low for normal operation. A low-power mode is available to lower the required power for CWD operation. When selected, the complex mixers operate at lower quiescent currents and the total per-channel current is lowered to 34.2mA. Note that operation in this mode slightly reduces the dynamic performance of the device. Table 4 shows the logic function of the standard operating modes. MAX2078 VGA and CW Mixer Operation During normal operation, the MAX2078 is configured so that either the VGA path is enabled while the mixer array is powered down (VGA mode), or the quadrature mixer array is enabled while the VGA path is powered down (CW mode). For VGA mode, set V/C to a logichigh and for CW mode, set V/C to a logic-low. 31.6kΩ CI+ 1μF Figure 2. Typical Example of a CW Mixer’s Output Circuit mixer usually drives the input of an instrumentation amplifier made up of op amps whose input impedance is set by common-mode setting resistors. There are clearly both a highpass corner and a lowpass corner present in this output network. The lowpass corner is set primarily by the 162Ω mixer pullup resistors, the series 50Ω resistors, and the shunt 0.022µF capacitor. This lowpass corner is used to filter a combination of LO leakage and upper sideband. The highpass corner, however, is of a larger concern since it is dominated by the combination of a 1µF DC-blocking capacitor and the pair of shunt 31.6kΩ resistors. Table 4. Logic Function of Standard Operating Modes VGA CW MIXER INTERNAL SWITCH TO VGA INTERNAL SWITCH TO CW MIXER N/A Off Off Off Off 0.3µA 0.4µA N/A Off Off Off Off 0.1µA 0.6µA 0 0 Off On Off On 3.2mA 248mA 90.4mA 0 1 Off On Off On 3.2mA 216mA 54.4mA 1 N/A On Off On Off 88mA 48mA 0 PD INPUT V/C CLP 1 1 1 0 0 0 0 0 3.3V VCC 5V VCC 11V VMIX CURRENT CURRENT CURRENT CONSUMPTION CONSUMPTION CONSUMPTION 0 N/A = Not applicable. ______________________________________________________________________________________ 19 MAX2078 Octal-Channel Ultrasound Front-End with CW Doppler Mixers If drawn, the simplified dominant highpass network would look like Figure 3. The highpass pole in this case is at fP = 1/(2 x pi x RC) ~ 5Hz. Note that this low highpass corner frequency is required to filter the downconverted clutter tone, which appears at DC, but not interfere with CWD imaging at frequencies as low as 400Hz. For example, if one wanted to use CWD down to 400Hz, then a good choice for the highpass pole would be at least a decade below this (< 40Hz) as not to incur rolloff due to the pole. Remember, if the highpass pole is set to 400Hz, the response is 3dB down at that corner frequency. The placement of the highpass pole at 5Hz in the above example is between the DC and 40Hz limitations just discussed. The bottom line is that any reasonably sized DC block between the output of the mixer and the instrumentation amplifier poses a significant time constant that slows the mode select switching speed. An alternative solution to the approach in Figure 2, which enables faster mode select response time, is shown in Figure 4. In Figure 4, the outputs of the CWD mixers are DC-coupled into the inputs of the instrumentation amplifiers. Therefore, the op amps must be able to accommodate the full compliance range of the mixer outputs, which is a maximum of 11V when the mixers are disabled, down to the 5V supply of the MAX2078 when the mixers are enabled. The op amps can be powered from 11V for the high rail and 5V for the low rail, requiring a 6V op amp. Figure 3. Simplified Circuit of Highpass Pole +11V +5V Serial Interface The MAX2078 is programmed using a serial shift register arrangement. This greatly simplifies the complexity of the program circuitry, reduces the number of IC pins necessary for programming, and reduces the PCB layout complexity. See Table 5 for the programming bit order. The data in (DIN) and data out (DOUT) can be daisy-chained from device to device and all front-ends can run off a single programming clock. The data can be entered after CS goes low. Once a whole word is entered, CS needs to rise. When programming the part, enter LSB first and MSB last. Programming the Beamformer During the normal CWD mode, the mixer clock (LO+, LO-) is on and the programming signals (DIN, CLK, CS) are off (CS = high, CLK = low, and DIN = don’t care, but fixed to a high or a low). To start the programming sequence, turn off the mixer clock. Data is shifted into 20 Figure 4. Improved Mode Select Response Time Achieved with DC-Coupled Input to Instrumentation Amplifier the shift register at a recommended 10MHz programming rate or 100ns minimum data clock period/time. Assuming a 64-channel CWD receiver, this takes about 30ms for 5 bits per channel. See Figure 5 for timing details. After the shift registers are programmed, pulling CS high loads the internal counters into I/Q phase divider/selectors with the proper values. The mixer clock needs to be off when this occurs or there may be timing issues between the load line timing and the mixer clock timing. The user turns on the mixer clock to start beamforming. The clock must turn on so that it starts at the beginning of a mixer clock cycle. A narrow glitch on the mixer clock is not acceptable and could cause metastability in the I/Q phase dividers. ______________________________________________________________________________________ Octal-Channel Ultrasound Front-End with CW Doppler Mixers 47 REGISTER BITS MSB LSB … CHANNEL 1 (i = 1) D46 D45 D44 D43 D42 D41 D40 D39 D38 D46 D45 D44 D43 D42 D41 D40 Di + 4 Di + 3 tCS D37 D36 Di + 2 Di + 1 CHANNEL 8 (i = 8) D35 … D4 D3 D2 D1 D0 Di … Di + 4 Di + 3 Di + 2 Di + 1 Di tCH tCW tCLH DIN CLK tCWS CS tCSBMIX MIXER CLOCK ON LO+ MIXER CLOCK OFF MIXER CLOCK ON MIXER CLOCK OFF LO- MIXER CLOCK ON LO+ MIXER CLOCK OFF MIXER CLOCK ON LO- Figure 5. Shift Register Timing Diagram ______________________________________________________________________________________ 21 MAX2078 Table 5. Programming Bit Order MAX2078 Octal-Channel Ultrasound Front-End with CW Doppler Mixers Ultrasound Front-End CWD Beamformer The user provides an LO frequency of 16MHz to 120MHz. This high clock frequency requires a differential LVDS input. Note that the LVDS CWD LO clocks are DCcoupled. This is to ensure immediate synchronization when the clock is first turned on. An AC-coupled LO is problematic in that the RC time constant associated with the coupling capacitors and the input impedance of the pin results in a period of time (related to the RC time constant) when the DC level on the chip side of the capacitor is outside the acceptable common-mode range and the LO swing cannot overcome both of the logic thresholds required for proper operation. This problem associated with AC coupling would cause an inability to ensure synchronization among beamforming channels. The LVDS signal is terminated differentially with an external 100Ω resistor on the board. The LO input is divided internally by 16 to produce 16 phases at a frequency of 1MHz to 7.5MHz. There is one divider per channel. Each channel has a corresponding 5-bit shift register (4 bits for phase programming and 1 bit for channel enable) that is used to program the output phase of the divide-by-16 circuit. The first 4 bits of the shift register are for programming the 16 phases, and the fifth bit can be used to turn on/off each channel individually through the serial bus. CW Mixer Output Summation The maximum differential current output is typically 3mA P-P and the mixer output-compliance voltage ranges from 4.5V to 12V per mixer channel. The mixer common-mode current in each of the differential mixer outputs is typically 2.83mA. The total summed current would equal N x 2.83mA in each of the 162Ω load resistors (where N = number of channels). In this case, the quiescent output voltage at +VSUM and -VSUM outputs would be 11V - (N x 2.83mA x 162) = 11 - (8 x 2.83mA x 162) = 7.34V. The voltage swing at each output, with one channel driven at maximum output current (differential 2.8mAP-P) while the other channels are not driven, would be 1.4mAP-P x 162Ω or 226mVP-P and the differential voltage would be 452mVP-P. The voltage compliance range is defined as the valid range for +VSUM and -VSUM in this example. Active Impedance Matching To provide exceptional noise-figure characteristics, the input impedance of each amplifier uses a feedback topology for active impedance matching. A feedback resistor of the value (1 + (A/2)) x RS is added between the inverting output of the amplifier to the input. The input impedance is the feedback resistor (ZF) divided by 1 + (A/2). The factor of two is due to the gain of the 22 Table 6. Noise Figure vs. Source and Input Impedances RS (Ω) RIN (Ω) NF (dB) 50 50 4.5 100 100 3.4 200 200 2.4 1000 1000 2.1 amplifier (A) being defined with a differential output. For common input impedances, the internal digitally programmed impedances can be used (see Table 1). For other input impedances, program the impedance for external resistor operation, and then use an externally supplied resistor to set the input impedance according to the above formula. Noise Figure The MAX2078 is designed to provide maximum input sensitivity with exceptionally low noise figure. The input active devices are selected for very-low-equivalent input noise voltage and current, optimized for source impedances from 50Ω to 1000Ω. Additionally, the noise contribution of the matching resistor is effectively divided by 1 + (A/2). Using this scheme, typical noise figure of the amplifier is approximately 2.4dB for RIN = RS = 200Ω. Table 6 illustrates the noise figure for other input impedances. Input Clamp The MAX2078 includes configurable integrated inputclamping diodes. The diodes are clamped to ground at ±0.8V. The input-clamping diodes can be used to prevent large transmit signals from overdriving the inputs of the amplifiers. Overdriving the inputs could possibly place charge on the input-coupling capacitor, causing longer transmit overload recovery times. Input signals are AC-coupled to the single-ended inputs IN1–IN8, but are clamped with the INC1–INC8 inputs. See the Typical Application Circuit. If external clamping devices are preferred, simply leave INC1–INC8 unconnected. Analog Output Coupling The differential outputs of the VGA are capable of driving a differential load capacitance to GND at each of the differential outputs of 25pF, and the differential capacitance across the VGA outputs is 15pF, RL = 1kΩ. The differential outputs have a common-mode bias of approximately 1.73V. AC-couple these differential outputs if the next stage has a different commonmode input range. ______________________________________________________________________________________ Octal-Channel Ultrasound Front-End with CW Doppler Mixers MAX2078 Ultrasound-Specific IMD3 Specification Unlike typical communications applications, the two input tones are not equal in magnitude for the ultrasound-specific IMD3 two-tone specification. In this measurement, f1 represents reflections from tissue and f2 represents reflections from blood. The latter reflections are typically 25dB lower in magnitude, and hence the measurement is defined with one input tone 25dB lower than the other. The IMD3 product of interest (f1 - (f2 - f1)) presents itself as an undesired Doppler error signal in ultrasound applications (see Figure 6). -25dB ULTRASOUND IMD3 PCB Layout The pin configuration of the MAX2078 is optimized to facilitate a very compact physical layout of the device and its associated discrete components. A typical application for this device might incorporate several devices in close proximity to handle multiple channels of signal processing. The exposed pad (EP) of the MAX2078’s TQFP-EP package provides a low thermal-resistance path to the die. It is important that the PCB on which the MAX2078 is mounted be designed to conduct heat from the EP. In addition, provide the EP with a low-inductance path to electrical ground. The EP MUST be soldered to a ground plane on the PCB, either directly or through an array of plated via holes. f1 - (f2 - f1) f1 f2 f2 + (f2 - f1) Figure 6. Ultrasound IMD3 Measurement Technique ______________________________________________________________________________________ 23 Octal-Channel Ultrasound Front-End with CW Doppler Mixers MAX2078 Typical Application Circuit 11V VCC2 R4 162Ω 68 C8 22nF ZF5 IN5 IN5 INC5 C9 10nF C10 22nF IN6 ZF6 IN6 INC6 C11 10nF C12 22nF IN7 ZF7 DIN CSB CLK OUT1+ CLK DIN CS NP V/C CQ- CQ+ CI- CI+ VCC1 VCC2 ZF1 IN1 VCC2 53 52 51 50 2 49 3 48 4 5 47 6 46 7 45 8 44 MAX2078 9 43 10 42 11 41 12 40 13 39 14 38 15 37 16 36 *EP 35 17 18 19 20 21 C13 10nF 22 23 25 26 27 28 29 30 31 32 33 OUT2+ C15 100nF REF C16 100nF VG+ VG- DOUT C17 100nF OUT2+ OUT2OUT3+ OUT2OUT3+ OUT3OUT4+ OUT3OUT4+ C25 100nF VCC1 C24 4.7nF OUT5+ OUT5OUT6+ C21 4.7nF OUT6- C20 4.7nF OUT7+ OUT7OUT8+ C23 4.7nF C22 4.7nF OUT6OUT7+ OUT4VCC1 LO- OUT5OUT6+ C26 4.7nF LO+ LOOUT5+ C28 4.7nF C27 4.7nF OUT4- LO+ C30 4.7nF C29 4.7nF 34 OUT8- ______________________________________________________________________________________ C19 4.7nF OUT7- C18 4.7nF *EP = EXPOSED PAD. 24 OUT1- C31 4.7nF C40 4.7nF C14 22nF IN8 24 C32 4.7nF OUT1- OUT8- C7 10nF 54 VCC2 AG 55 DOUT C6 10nF 56 GND GND 57 PD INC4 58 CLP IN4 IN4 59 GND ZF4 60 VG- C5 22nF OUT1+ C33 4.7nF VG+ C4 10nF 61 VCC1 INC3 62 VREF IN3 C34 100nF + VCC2 IN3 63 64 INC8 C3 22nF ZF3 65 IN8 C2 10nF 66 ZF8 IN2 1 67 INC7 INC2 IN7 IN2 R2 162Ω R1 162Ω C38 10nF INC1 ZF2 C1 22nF C35 100nF VCC1 NP C37 22nF C39 10nF R3 162Ω C36 100nF IN1 V/C VCC2 OUT8+ Octal-Channel Ultrasound Front-End with CW Doppler Mixers PROCESS: Complementary BiCMOS For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 68 Thin QFN-EP T6800+4 21-0142 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX2078 Package Information Chip Information