LINER LTC3831-1

LTC3831-1
High Power Synchronous
Switching Regulator Controller
for DDR Memory Termination
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FEATURES
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DESCRIPTIO
The LTC®3831-1 is a high power, high efficiency switching regulator controller designed for DDR memory termination. The LTC3831-1 generates an output voltage equal
to 1/2 of an external supply or reference voltage. The
LTC3831-1 uses a synchronous switching architecture
with N-channel MOSFETs. Additionally, the chip senses
output current through the drain-source resistance of the
upper N-channel FET, providing an adjustable current
limit without a current sense resistor.
VOUT as Low as 0.4V
High Power Switching Regulator Controller
for DDR Memory Termination
VOUT Tracks 1/2 of VIN or External VREF
No Current Sense Resistor Required
Low VCC Supply: 3V to 8V
Maximum Duty Cycle > 91% Over Temperature
Drives All N-Channel External MOSFETs
High Efficiency: Up to 95%
Programmable Fixed Frequency Operation:
100kHz to 500kHz
External Clock Synchronization Operation
Programmable Soft-Start
Low Shutdown Current: <10µA
Overtemperature Protection
Available in 16-Pin Narrow SSOP Package
The LTC3831-1 operates with input supply voltage as low
as 3V and with a maximum duty cycle of > 91%. It includes
a fixed frequency PWM oscillator for low output ripple
operation. The 300kHz free-running clock frequency can
be externally adjusted or synchronized with an external
signal from 100kHz to above 500kHz. In shutdown mode,
the LTC3831-1 supply current drops to <10µA.
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APPLICATIO S
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DDR SDRAM Termination
SSTL_2, SSTL_3 Interface
HSTL Interface
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, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATIO
0.75V DDR Memory Termination Application
Efficiency vs Load Current
VDDQ
1.5V
100
+
12V
TA = 25°C
90
220µF
VDDQ = 1.8V
80
0.1µF
PVCC2
PVCC1
VCC
2.2µF
TG
IMAX
SS
0.01µF
68pF
1.3µH
BG
SHDN
PGND
COMP
GND
+
VTT
(VOUT)
0.75V
±10A
R–
FB
VDDQ = 1.5V
70
60
50
40
30
20
180µF
10
R+
1k
22nF
1k
LTC3831-1 IFB
FREQSET
SHDN
4.7k
EFFICIENCY (%)
4.7µF
3.3V
0
0
38311 TA01a
1
2
3 4 5 6 7
LOAD CURRENT (A)
8
9
10
3831 TAO1b
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LTC3831-1
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
Supply Voltage
VCC ....................................................................... 9V
PVCC1,2 ................................................................ 14V
Input Voltage
IFB, IMAX ............................................... – 0.3V to 14V
R+, R–, FB, SHDN, FREQSET ..... – 0.3V to VCC + 0.3V
Junction Temperature (Note 9) ............................. 125°C
Operating Temperature Range (Note 4) .. – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
TG
1
16 BG
PVCC1
2
15 PVCC2
PGND
3
14 VCC
GND
4
13 IFB
R–
5
12 IMAX
FB
6
11 FREQSET
R+
7
10 COMP
SHDN
8
9
LTC3831EGN-1
GN PART MARKING
38311
SS
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC, PVCC1, PVCC2 = 5V, VR+ = 1.5V, VR– = GND, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
VCC
Supply Voltage
PVCC
PVCC1, PVCC2 Voltage
VUVLO
Undervoltage Lockout Voltage
VFB
Feedback Voltage
VR+ = 1.5V, VR– = 0V, VCOMP = 1.25V
∆VOUT
Output Load Regulation
Output Line Regulation
IOUT = 0A to 10A (Note 6)
VCC = 4.75V to 5.25V
IVCC
Supply Current
Figure 1, VSHDN = VCC
VSHDN = 0V
●
●
0.7
1
1.6
10
mA
µA
IPVCC
PVCC Supply Current
Figure 1, VSHDN = VCC (Note 3)
VSHDN = 0V
●
●
20
0.1
30
10
mA
µA
∆fOSC
Internal Oscillator Frequency
FREQSET Floating
●
300
360
kHz
VSAWL
VCOMP at Minimum Duty Cycle
1.2
V
VSAWH
VCOMP at Maximum Duty Cycle
2.2
V
VCOMPMAX
Maximum VCOMP
(Note 7)
MIN
TYP
●
3
5
●
3
●
0.738
230
VFB = 0V, PVCC1 = 7V
8
V
V
2.4
2.9
V
0.75
0.762
2.85
AV
Error Amplifier Open-Loop DC Gain
●
50
65
gm
Error Amplifier Transconductance
●
1600
2000
ICOMP
Error Amplifier Output Sink/Source Current
IMAX
IMAX Sink Current
V
kHz/µA
dB
2400
VIMAX = VCC (Notes 6, 10)
9
4
12
12
3300
µmho
µA
100
●
V
mV
mV
10
VIMAX = VCC
(Note 10)
UNITS
13.2
2
0.1
∆fOSC/∆IFREQSET Frequency Adjustment
IMAX Sink Current Tempco
MAX
15
20
µA
µA
ppm/°C
38311f
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LTC3831-1
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC, PVCC1, PVCC2 = 5V, VR+ = 1.5V, VR– = GND, unless otherwise noted. (Note 2)
SYMBOL
PARAMETER
VIH
SHDN Input High Voltage
CONDITIONS
●
MIN
VIL
SHDN Input Low Voltage
●
IIN
SHDN Input Current
VSHDN = VCC
●
ISS
Soft-Start Source Current
VSS = 0V, VIMAX = 0V, VIFB = VCC
●
ISSIL
Maximum Soft-Start Sink Current
Undercurrent Limit
VIMAX = VCC, VIFB = 0V, VSS = VCC (Note 8),
PVCC1 = 7V (Note 7)
R+
R+ Input Resistance
tr, tf
Driver Rise/Fall Time
Figure 1, PVCC1 = PVCC2 = 5V (Note 5)
●
tNOV
Driver Nonoverlap Time
Figure 1, PVCC1 = PVCC2 = 5V (Note 5)
●
DCMAX
Maximum TG Duty Cycle
Figure 1, VFB = 0V (Note 7), PVCC1 = 7V
●
TYP
MAX
2.4
V
0.8
–8
V
0.1
1
µA
–12
–16
µA
1.6
mA
53.3
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 3: Supply current in normal operation is dominated by the current
needed to charge and discharge the external FET gates. This will vary with
the LTC3831-1 operating frequency, operating voltage and the external
FETs used.
Note 4: The LTC3831EGN-1 is guaranteed to meet performance
specifications from 0°C to 70°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 5: Rise and fall times are measured using 10% and 90% levels. Duty
cycle and nonoverlap times are measured using 50% levels.
Note 6: Guaranteed by design, not subject to test.
UNITS
kΩ
80
250
ns
25
120
250
ns
91
95
%
Note 7: PVCC1 must be higher than VCC by at least 2V for TG to operate at
95% maximum duty cycle and for the current limit protection circuit to be
active.
Note 8: The current limiting amplifier can sink but cannot source current.
Under normal (not current limited) operation, the output current will be
zero.
Note 9: This IC includes overtemperature protection that is intended to protect
the device during momentary overload conditions. Junction temperature will
exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair
device reliability.
Note 10: The minimum and maximum limits for IMAX over temperature
includes the intentional temperature coefficient of 3300ppm/°C. This induced
temperature coefficient counteracts the typical temperature coefficient of the
external power MOSFET on-resistance. This results in a relatively flat current
limit over temperature for the application.
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LTC3831-1
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TYPICAL PERFOR A CE CHARACTERISTICS
0.760
0.762
TA = 25°C
REFER TO FRONT PAGE APPLICATION
0.758 NEGATIVE OUTPUT CURRENT
0.756 INDICATES CURRENT SINKING
0.760
VOUT (V)
0.750
0.748
0.746
0.744
0.742
0.740
0.756
6
0.754
4
0.752
2
0.750
0
0.748
–2
0.746
–4
0.744
–6
0.742
–8
0.740
0.738
–10 –8 –6 –4 –2 0 2 4 6
OUTPUT CURRENT (A)
8
8
10
4
3
6
7
5
VCC SUPPLY VOLTAGE (V)
8
8
0.756
6
0.754
4
0.752
2
0.750
0
0.748
–2
0.746
–4
0.744
–6
0.742
–8
0.740
–10
0.738
–50
–25
0
25
75
50
TEMPERATURE (°C)
100
–12
125
200
160
140
120
100
80
60
40
–50 –25
75
50
25
TEMPERATURE (°C)
0
100
1700
1600
–50
320
310
300
290
280
270
260
125
3831 G08
75
50
25
TEMPERATURE (°C)
0
100
125
65
60
55
75
0
25
50
TEMPERATURE (°C)
100
125
3831 G07
Oscillator (VSAWH – VSAWL)
vs External Sync Frequency
1.5
TA = 25°C
1.4
TA = 25°C
600
1.3
500
400
300
200
1.2
1.1
1.0
0.9
0.8
0.7
100
0.6
250
100
–25
50
–50 –25
125
VSAWH – VSAWL (V)
OSCILLATOR FREQUENCY (kHz)
OSCILLATOR FREQUENCY (kHz)
700
330
25
0
75
50
TEMPERATURE (°C)
1800
Oscillator Frequency
vs FREQSET Input Current
340
–25
1900
3831 G06
FREQSET FLOATING
240
–50
2000
70
180
Oscillator Frequency
vs Temperature
350
2100
Error Amplifier Open-Loop Gain
vs Temperature
3831 G05
360
2200
3831 G04
ERROR AMPLIFIER OPEN-LOOP GAIN (dB)
0.758
∆VOUT (mV)
VOUT (V)
10
ERROR AMPLIFIER SINK/SOURCE CURRENT (µA)
12
REFER TO FRONT PAGE APPLICATION
OUTPUT = NO LOAD
2300
Error Amplifier Sink/Source
Current vs Temperature
Output Voltage Temperature Drift
0.760
–10
2400
3831 G03
3831 G02
0.762
∆VOUT (mV)
0.752
10
TA = 25°C
0.758
0.754
VOUT (V)
Error Amplifier Transconductance
vs Temperature
Line Regulation
ERROR AMPLIFIER TRANSCONDUCTANCE (µmho)
Load Regulation
0
30
20
10
0
10
20
FREQSET INPUT CURRENT (µA)
30
3831 G09
0.5
100
300
200
400
EXTERNAL SYNC FREQUENCY (kHz)
500
3831 G10
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LTC3831-1
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TYPICAL PERFOR A CE CHARACTERISTICS
Maximum TG Duty Cycle
vs Temperature
VFB = 0V
REFER TO FRONT PAGE APPLICATION
98
IMAX SINK CURRENT (µA)
MAXIMUM G1 DUTY CYCLE (%)
99
97
96
95
94
93
92
91
–50
–25
25
0
75
50
TEMPERATURE (°C)
100
20
18
0.7
16
0.6
14
12
10
0.1
100
–9
1.75
SOFT-START SINK CURRENT (mA)
SOFT-START SOURCE CURRENT (µA)
OUTPUT CURRENT LIMIT (A)
2.00
–10
–11
–12
–13
–14
–15
75
50
25
TEMPERATURE (°C)
0
100
1.50
1.25
1.00
0.75
0.50
0.25
0
–150
125
2.5
2.4
2.3
2.2
2.1
125
3831 G17
–125
–100
–50
–75
VIFB – VIMAX (mV)
–25
1.5
PVCC Supply Current
vs Oscillator Frequency
90
FREQSET FLOATING
TA = 25°C
80
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
TG AND BG LOADED
WITH 6800pF,
PVCC1,2 = 12V
70
60
50
TG AND BG
LOADED
WITH 1000pF,
PVCC1,2 = 5V
40
30
TG AND BG
LOADED
WITH 6800pF,
PVCC1,2 = 5V
20
10
0.5
0.4
–50
0
3831 G16
PVCC SUPPLY CURRENT (mA)
VCC OPERATING SUPPLY CURRENT (mA)
UNDERVOLTAGE LOCKOUT THRESHOLD VOLTAGE (V)
1.6
14
TA = 25°C
3831 G15
3.0
2.6
12
Soft-Start Sink Current
vs (VIFB – VIMAX)
VCC Operating Supply Current
vs Temperature
2.7
8
6
10
4
OUTPUT CURRENT (A)
3831 G13
–8
–16
– 50 – 25
125
2.8
2
3831 G12
Undervoltage Lockout Threshold
Voltage vs Temperature
100
0
125
Soft-Start Source Current
vs Temperature
2.9
TA = 25°C
REFER TO FRONT PAGE APPLICATION
0
75
50
25
TEMPERATURE (°C)
0
3831 G14
50
25
0
75
TEMPERATURE (°C)
0.3
6
Output Current Limit Threshold
vs Temperature
2.0
–50 –25
0.4
0.2
3831 G11
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1 REFER TO FRONT PAGE APPLICATION
0
50
25
0
75 100
–50 –25
TEMPERATURE (°C)
0.5
8
4
– 50 – 25
125
Output Overcurrent Protection
0.8
OUTPUT VOLTAGE (V)
100
IMAX Sink Current
vs Temperature
–25
50
25
0
75
TEMPERATURE (°C)
100
125
3831 G18
0
0
400
100
300
200
OSCILLATOR FREQUENCY (kHz)
500
3831 G19
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LTC3831-1
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TYPICAL PERFOR A CE CHARACTERISTICS
PVCC Supply Current
vs Gate Capacitance
80
TG Rise/Fall Time
vs Gate Capacitance
200
TA = 25°C
VOUT
50mV/DIV
160
60
TG RISE/FALL TIME (ns)
PVCC SUPPLY CURRENT (mA)
TA = 25°C
180
70
PVCC1,2 = 12V
50
40
30
PVCC1,2 = 5V
20
140
120
tf AT PVCC1,2 = 5V
100
60
tf AT PVCC1,2 = 12V
20
0
1 2 3 4 5 6 7 8 9 10
GATE CAPACITANCE AT TG AND BG (nF)
ILOAD
2A/DIV
tr AT PVCC1,2 = 5V
80
40
10
0
Transient Response
0
50µs/DIV
3831 G22.tif
tr AT PVCC1,2 = 12V
0
1 2 3 4 5 6 7 8 9 10
GATE CAPACITANCE AT TG AND BG (nF)
3831 G20
3831 G21
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TG ( Pin 1): Top Driver Output. Connect this pin to the gate
of the upper N-channel MOSFET, Q1. This output swings
from PGND to PVCC1. It remains low if BG is high or during
shutdown mode.
tor divider. The FB pin is servoed to the ratiometric
reference under closed-loop conditions. The LTC3831-1
can operate with a minimum VFB of 0.4V and maximum
VFB of (VCC – 2V).
PVCC1 (Pin 2): Power Supply Input for TG. Connect this pin
to a potential of at least VIN + VGS(ON)(Q1). For normal
operation, PVCC1 must also be higher than VCC by at least
2V when TG is high. This allows the use of an external
charge pump to power PVCC1.
SHDN (Pin 8): Shutdown. A TTL compatible low level at
SHDN for longer than 100µs puts the LTC3831-1 into
shutdown mode. In shutdown, TG and BG go low, all
internal circuits are disabled and the quiescent current
drops to 10µA max. A TTL compatible high level at SHDN
allows the part to operate normally. This pin also double as
an external clock input to synchronize the internal oscillator with an external clock.
PGND (Pin 3): Power Ground. Both drivers return to this
pin. Connect this pin to a low impedance ground in close
proximity to the source of Q2. Refer to the Layout Consideration section for more details on PCB layout techniques.
GND (Pin 4): Signal Ground. All low power internal circuitry returns to this pin. To minimize regulation errors
due to ground currents, connect GND to PGND right at the
LTC3831-1.
R–, R+ (Pins 5, 7): These two pins connect to the internal
resistor divider that generate the internal ratiometric reference for the error amplifier. The reference voltage is set
at 0.5 • (VR+ – VR–).
SS (Pin 9): Soft-Start. Connect this pin to an external
capacitor, CSS, to implement a soft-start function. If the
LTC3831-1 goes into current limit, CSS is discharged to
reduce the duty cycle. CSS must be selected such that
during power-up, the current through Q1 will not exceed
the current limit level.
COMP (Pin 10): External Compensation. This pin internally connects to the output of the error amplifier and input
of the PWM comparator. Use a RC + C network at this pin
to compensate the feedback loop to provide optimum
FB (Pin 6): Feedback Voltage. FB senses the regulated
output voltage either directly or through an external resis38311f
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LTC3831-1
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transient response.
through a 1k resistor. The 1k resistor is required to prevent
voltage transients from damaging IFB.This pin is used for
sensing the voltage drop across the upper N-channel
MOSFET, Q1.
FREQSET (Pin 11): Frequency Set. Use this pin to adjust
the free-running frequency of the internal oscillator. With
the pin floating, the oscillator runs at about 300kHz. A
resistor from FREQSET to ground speeds up the oscillator;
a resistor to VCC slows it down.
VCC (Pin 14): Power Supply Input. All low power internal
circuits draw their supply from this pin. This pin requires
a 4.7µF bypass capacitor to GND.
IMAX (Pin 12): Current Limit Threshold Set. IMAX sets the
threshold for the internal current limit comparator. If IFB
drops below IMAX with TG on, the LTC3831-1 goes into
current limit. IMAX has an internal 12µA pull-down to GND.
Connect this pin to the main VIN supply at the drain of Q1,
through an external resistor to set the current limit threshold. Connect a 0.1µF decoupling capacitor across this
resistor to filter switching noise.
PVCC2 (Pin 15): Power Supply Input for BG. Connect this
pin to the main high power supply.
BG (Pin 16): Bottom Driver Output . Connect this pin to the
gate of the lower N-channel MOSFET, Q2. This output
swings from PGND to PVCC2. It remains low when TG is
high or during shutdown mode. To prevent output undershoot during a soft-start cycle, BG is held low until TG first
goes high (FFBG in the Block Diagram).
IFB (Pin 13): Current Limit Sense. Connect this pin to the
switching node at the source of Q1 and the drain of Q2
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BLOCK DIAGRA
DISABLE GATE DRIVE
LOGIC AND
THERMAL SHUTDOWN
100µs DELAY
SHDN
VCC
POWER DOWN
INTERNAL
OSCILLATOR
PVCC1
–
FREQSET
+
COMP
PWM
S
Q
TG
R
Q
PVCC2
BG
FFBG
12µA
S
QSS
SS
POR
Q
PGND
ENABLE
BG
R
FB
R+
ERR
+
MAX
+
–
–
24k
VREF + 10%
2.66k
VREF
VREF + 10%
VREF
2.66k
CC
2.2V
QC
DISABLE
ILIM
–
IFB
+
IMAX
24k
R–
12µA
+
1.2V
PVCC1
GND
38311 BD
V
–
VCC + 2V
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LTC3831-1
TEST CIRCUITS
PVCC
+
VSHDN VCC
10µF
SHDN
NC
NC
VFB
VCOMP
1.5V
PVCC2 PVCC1
VCC
SS
FREQSET
FB
COMP
R+
0.1µF
IFB
TG
TG RISE/FALL
6800pF
LTC3831-1
BG
R–
IMAX
GND
PGND
BG RISE/FALL
6800pF
38311 F01
Figure 1
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APPLICATIO S I FOR ATIO
OVERVIEW
THEORY OF OPERATION
The LTC3831-1 is a voltage mode feedback, synchronous
switching regulator controller (see Block Diagram) designed for use in high to medium power, DDR memory
termination. It includes an onboard PWM generator, a
ratiometric reference, two high power MOSFET gate drivers and all necessary feedback and control circuitry to
form a complete switching regulator circuit. The PWM
loop nominally runs at 300kHz.
Primary Feedback Loop
The LTC3831-1 is designed to generate an output voltage
that tracks at 1/2 of the external voltage connected between
the R+ and R– pins. The LTC3831-1 can be used to generate the termination voltage, VTT, for interface like the SSTL_2
where VTT is a ratio of the interface supply voltage, VDDQ.
It is a requirement in the SSTL_2 interface standard for VTT
to track the interface supply voltage to improve noise immunity. Using the LTC3831-1 to supply the interface termination voltage allows large current sourcing and sinking through the termination resistors during bus transitions.
The LTC3831-1 includes a current limit sensing circuit that
uses the topside external N-channel power MOSFET as a
current sensing element, eliminating the need for an
external sense resistor. Also included is an internal softstart feature that requires only a single external capacitor
to operate. In addition, the part features an adjustable
oscillator which can free run or synchronize to an external
signal with frequencies from 100kHz to 500kHz, allowing
added flexibility in external component selection.
The LTC3831-1 senses the output voltage of the circuit
through the FB pin and feeds this voltage back to the
internal transconductance error amplifier, ERR. The error
amplifier compares the output voltage to the internal
ratiometric reference, VREF, and outputs an error signal to
the PWM comparator. VREF is set to 0.5 multiplied by the
voltage difference between the R+ and R– pins, using an
internal resistor divider.
This error signal is compared with a fixed frequency ramp
waveform, from the internal oscillator, to generate a pulse
width modulated signal. This PWM signal drives the
external MOSFETs through the TG and BG pins. The
resulting chopped waveform is filtered by LO and COUT
which closes the loop. Loop compensation is achieved
with an external compensation network at the COMP pin,
the output node of the error amplifier.
MAX Feedback Loop
An additional comparator in the feedback loop provides
high speed output voltage correction in situations where
the error amplifier may not respond quickly enough. MAX
compares the feedback signal to a voltage 10% above
VREF. If the signal is above the comparator threshold, the
MAX comparator overrides the error amplifier and forces
the loop to minimum duty cycle, 0%. To prevent this
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LTC3831-1
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APPLICATIO S I FOR ATIO
comparator from triggering due to noise, the MAX
comparator’s response time is deliberately delayed by two
to three microseconds. This comparator helps prevent
extreme output perturbations with fast output load current
transients, while allowing the main feedback loop to be
optimally compensated for stability.
Thermal Shutdown
The LTC3831-1 has a thermal protection circuit that disables both gate drivers if activated. If the chip junction
temperature reaches 150°C, both TG and BG are pulled
low. TG and BG remain low until the junction temperature
drops below 125°C, after which, the chip resumes normal
operation.
Soft-Start and Current Limit
The LTC3831-1 includes a soft-start circuit that is used for
start-up and current limit operation. The SS pin requires
an external capacitor, CSS, to GND with the value determined by the required soft-start time. An internal 12µA
current source is included to charge CSS. During powerup, the COMP pin is clamped to a diode drop (B-E junction
of QSS in the Block Diagram) above the voltage at the SS
pin. This prevents the error amplifier from forcing the loop
to maximum duty cycle. The LTC3831-1 operates at low
duty cycle as the SS pin rises above 0.6V (VCOMP ≈ 1.2V).
As SS continues to rise, QSS turns off and the error
amplifier takes over to regulate the output.
The LTC3831-1 includes yet another feedback loop to
control operation in current limit. Just before every falling
edge of TG, the current comparator, CC, samples and
holds the voltage drop measured across the external
upper MOSFET, Q1, at the IFB pin. CC compares the voltage
at IFB to the voltage at the IMAX pin. As the peak current
rises, the measured voltage across Q1 increases due to the
drop across the RDS(ON) of Q1. When the voltage at IFB
drops below IMAX, indicating that Q1’s drain current has
exceeded the maximum level, CC starts to pull current out
of CSS, cutting the duty cycle and controlling the output
current level. The CC comparator pulls current out of the
SS pin in proportion to the voltage difference between IFB
and IMAX. Under minor overload conditions, the SS pin
falls gradually, creating a time delay before current limit
takes effect. Very short, mild overloads may not affect the
output voltage at all. More significant overload conditions
allow the SS pin to reach a steady state, and the output
remains at a reduced voltage until the overload is removed. Serious overloads generate a large overdrive at
CC, allowing it to pull SS down quickly and preventing
damage to the output components. By using the RDS(ON)
of Q1 to measure the output current, the current limiting
circuit eliminates an expensive discrete sense resistor that
would otherwise be required. This helps minimize the
number of components in the high current path.
The current limit threshold can be set by connecting an
external resistor RIMAX from the IMAX pin to the main VIN
supply at the drain of Q1. The value of RIMAX is determined
by:
RIMAX = (ILMAX)(RDS(ON)Q1)/IIMAX
where:
ILMAX = ILOAD + (IRIPPLE/2)
ILOAD= Maximum load current
IRIPPLE = Inductor ripple current
=
( VIN – VOUT )( VOUT )
(fOSC )(LO )(VIN)
fOSC = LTC3831-1 oscillator frequency = 300kHz
LO = Inductor value
RDS(ON)Q1 = On-resistance of Q1 at ILMAX
IIMAX = Internal 12µA sink current at IMAX
The RDS(ON) of Q1 usually increases with temperature. To
keep the current limit threshold constant, the internal
12µA sink current at IMAX is designed with a positive
temperature coefficient to provide first order correction
for the temperature coefficient of RDS(ON)Q1.
In order for the current limit circuit to operate properly and
to obtain a reasonably accurate current limit threshold, the
IIMAX and IFB pins must be Kelvin sensed at Q1’s drain and
source pins. In addition, connect a 0.1µF decoupling
capacitor across RIMAX to filter switching noise. Otherwise, noise spikes or ringing at Q1’s source can cause the
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actual current limit to be greater than the desired current
limit set point. Due to switching noise and variation of
RDS(ON), the actual current limit trip point is not highly
accurate. The current limiting circuitry is primarily meant
to prevent damage to the power supply circuitry during
fault conditions. The exact current level where the limiting
circuit begins to take effect will vary from unit to unit as the
RDS(ON) of Q1 varies. Typically, RDS(ON) varies as much as
±40% and with ±25% variation on the LTC3831-1’s IMAX
current, this can give a ±65% variation on the current limit
threshold.
where RFSET is a frequency programming resistor connected between FREQSET and the external voltage source
VEXT. Connecting an 82k resistor from FREQSET to ground
forces 15µA out of the pin, causing the internal oscillator
to run at approximately 450kHz. Forcing an external 20µA
current into FREQSET cuts the internal frequency to 100kHz.
An internal clamp prevents the oscillator from running
slower than about 50kHz. Tying FREQSET to VCC forces
the chip to run at this minimum speed.
The RDS(ON) is high if the VGS applied to the MOSFET is
low. This occurs during power up, when PVCC1 is ramping
up. To prevent the high RDS(ON) from activating the current
limit, the LTC3831-1 disables the current limit circuit if
PVCC1 is less than 2V above VCC. To ensure proper
operation of the current limit circuit, PVCC1 must be at
least 2V above VCC when TG is high. PVCC1 can go low
when TG is low, allowing the use of an external charge
pump to power PVCC1.
The LTC3831-1 includes a low power shutdown mode,
controlled by the logic at the SHDN pin. A high at SHDN
allows the part to operate normally. A low level at SHDN for
more than 100µs forces the LTC3831-1 into shutdown
mode. In this mode, all internal switching stops, the COMP
and SS pins pull to ground and Q1 and Q2 turn off. The
LTC3831-1 supply current drops to <10µA, although offstate leakage in the external MOSFETs may cause the total
VIN current to be somewhat higher, especially at elevated
temperatures. If SHDN returns high, the LTC3831-1 reruns a soft-start cycle and resumes normal operation.
VIN
LTC3831-1
RIMAX
+
+
0.1µF
CIN
12
12µA
CC
IMAX
IFB
–
TG
Q1
LO
1k
13
BG
Q2
+
VOUT
COUT
38311 F02
Figure 2. Current Limit Setting
Oscillator Frequency
The LTC3831-1 includes an onboard current controlled
oscillator that typically free-runs at 300kHz. The oscillator
frequency can be adjusted by forcing current into or out of
the FREQSET pin. With the pin floating, the oscillator runs
at about 300kHz. Every additional 1µA of current into/out
of the FREQSET pin decreases/increases the frequency by
10kHz. The pin is internally servoed to 1.265V. The frequency can be estimated as:
f = 300kHz +
10
Shutdown
1.265V – VEXT 10kHz
•
RFSET
1µA
External Clock Synchronization
The LTC3831-1 SHDN pin doubles as an external clock
input for applications that require a synchronized clock.
An internal circuit forces the LTC3831-1 into external
synchronization mode if a negative transition at the SHDN
pin is detected. In this mode, every negative transition on
the SHDN pin resets the internal oscillator and pulls the
ramp signal low. This forces the LTC3831-1 internal
oscillator to lock to the external clock frequency.
The LTC3831-1 internal oscillator can be externally synchronized from 100kHz to 500kHz. Frequencies above
300kHz can cause a decrease in the maximum obtainable
duty cycle as rise/fall time and propagation delay take up
a larger percentage of the switch cycle. The low period of
this clock signal must not be >100µs or else the LTC3831-1
enters into the shutdown mode.
Figure 3 describes the operation of the external synchronization function. A negative transition at the SHDN pin
forces the internal ramp signal low to restart a new PWM
cycle. Notice that the ramp amplitude is lowered as the
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external clock frequency goes higher. The effect of this
decrease in ramp amplitude increases the open-loop gain
of the controller feedback loop. As a result, the loop
crossover frequency increases and it may cause the feedback loop to be unstable if the phase margin is insufficient.
To overcome this problem, the LTC3831-1 monitors the
peak voltage of the ramp signal and adjust the oscillator
charging current to maintain a constant ramp peak.
SHDN
TRADITIONAL
SYNC METHOD
WITH EARLY
RAMP
TERMINATION
200kHz
FREE RUNNING
RAMP SIGNAL
supply must be above VIN by at least one power MOSFET
VGS(ON) for efficient operation. In addition, this supply
must be higher that VCC by at least 2V for normal operation. An internal level shifter allows PVCC1 to operate at
voltages above VCC and VIN, up to 14V maximum. This
higher voltage can be supplied with a separate supply, or
it can be generated using a charge pump.
Gate drive for the bottom MOSFET Q2 is provided through
PVCC2. This supply only needs to be above the power
MOSFET VGS(ON) for efficient operation. PVCC2 can also be
driven from the same supply/charge pump for the PVCC1,
or it can be connected to a lower supply to improve
efficiency.
In a typical low voltage DDR memory termination application, VIN or VDDQ can be a low as 1.5V. If the only available
supply for the LTC3831-1 is 3.3V, a tripling charge pump
circuit can be added to power the PVCC1 and PVCC2 pins.
This requires sub-logic level threshold power MOSFET
with RDS(ON) specified at VGS = 2.5V.
RAMP SIGNAL
WITH EXT SYNC
RAMP AMPLITUDE
ADJUSTED
LTC3831
KEEPS RAMP
AMPLITUDE
CONSTANT
UNDER SYNC
38311 F03
Figure 3. External Synchronization Operation
Input Supply Considerations/Charge Pump
The LTC3831-1 requires four supply voltages to operate:
VIN for the main power input, PVCC1 and PVCC2 for MOSFET gate drive and a clean, low ripple VCC for the LTC3831-1
internal circuitry (Figure 4). VIN is usually connected to
VDDQ in most DDR memory termination applications.
The VCC supply can be as low as 3V and the quiescent
current is typically 800µA. Place a 4.7µA bypass capacitor
as close as possible to this pin. Gate drive for the top
N-channel MOSFET Q1 is supplied from PVCC1. This
Figure 5 shows a tripling charge pump circuit that powers
the PVCC1 and PVCC2 pins. This circuit provides (VCC +
2VIN – 3VF) to PVCC1 while Q1 is ON and (VCC + VIN – 2VF)
to PVCC2 where VF is the ON voltage of the Schottky diode.
The circuit requires the use of Schottky diodes to minimize
forward drop across the diodes at start-up. The tripling
charge pump circuit will tend to rectify any ringing at the
drain of Q2 and can provide well more than (VCC + 2VIN)
at PVCC1. A 12V zener diode may be included from PVCC1
to PGND to prevent transients from damaging the circuitry
at PVCC1 or the gate of Q1.
VCC
PVCC2
PVCC1
VIN
TG
Q1
LO
INTERNAL
CIRCUITRY
VOUT
BG
+
Q2
LTC3831-1
COUT
38311 F04
Figure 4. Input Supplies
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The charge pump capacitors for PVCC1 refresh when the
BG pin goes high and the switch node is pulled low by Q2.
The BG on time becomes narrow when the LTC3831-1
operates at maximum duty cycle (95% typical) which can
occur if the input supply rises more slowly than the softstart capacitor or the input voltage droops during load
transients. If the BG on time gets so narrow that the switch
node fails to pull completely to ground, the charge pump
voltage may collapse or fail to start causing excessive
dissipation in external MOSFET Q1. This is most likely with
low VCC voltages and high switching frequencies, coupled
with large external MOSFETs that slow the BG and switch
node slew rates.
The LTC3831-1 overcomes this problem by sensing the
PVCC1 voltage when TG is high. If PVCC1 is less than 2V
above VCC, the maximum TG duty cycle is reduced to 70%
by clamping the COMP pin at 1.8V (QC in the Block
Diagram). This increases the BG on time and allows the
charge pump capacitors to be refreshed.
For applications using an external supply to power PVCC1,
this supply must also be higher than VCC by at least 2V to
ensure normal operation.
Connecting the Ratiometric Reference Input
The LTC3831-1 derives its ratiometric reference, V REF,
using an internal resistor divider. The top and bottom of
the resistor divider is connected to the R+ and R – pins
respectively. This permits the output voltage to track at a
ratio of the differential voltage at R+ and R –.
The LTC3831-1 can operate with a minimum VFB of 0.4V
and maximum VFB of (VCC – 2V). With R– connected to
GND, this gives a VR+ input range of 0.8V to (2 • VCC – 4V).
If VR+ is higher than the permitted input voltage, increase
the VCC voltage to raise the input range.
In a typical DDR memory termination, as shown in the
typical application on the front page, R+ is connected to
VDDQ, the supply voltage of the interface, and R – to GND.
The output voltage VTT is connected to the FB pin, so VTT
= 0.5 • VDDQ.
If a ratio greater than 0.5 is desired, it can be achieved
using an external resistor divider connected to VTT and FB
pin. Figure 6 shows an application that generates a VTT of
0.6 • VDDQ.
3.3V
VCC
DZ
12V
1N5242
1N5817
PVCC2
10µF
1N5817
1.5V
VIN
1N5817
PVCC1
0.1µF
0.1µF
TG
2.2µF
Q1
VCC
LO
VOUT
BG
+
Q2
LTC3831-1
COUT
38311 F05
Figure 5. Triple Charge Pump Configuration
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VDDQ
1.5V
+
12V
4.7µF
3.3V
PVCC2
PVCC1
VCC
0.01µF
IMAX
C1
33pF
RC
1k
CC
10nF
Q1
MBRS340T3
LO
1.2µH
1k
VTT
(VOUT)
0.9V
± 6A
LTC3831-1 IFB
FREQSET
SHDN
0.1µF
TG
SS
2.2µF
10k
CIN
220µF
SHDN
PGND
COMP
GND
R+
R–
MBRS340T3
Q2
BG
+
CIN: SANYO POSCAP 4TPB220M
COUT: SANYO POSCAP 4TPB470M
Q1, Q2: SILICONIX Si4410DY
COUT
470µF
2k
1%
FB
10k
1%
38311 F06
Figure 6. Typical Application with VTT = 0.6 • VDDQ
Power MOSFETs
Two N-channel power MOSFETs are required for most
LTC3831-1 circuits. These should be selected based primarily on threshold voltage and on-resistance considerations. Thermal dissipation is often a secondary concern
in high efficiency designs. The required MOSFET threshold should be determined based on the available power
supply voltages and/or the complexity of the gate drive
charge pump scheme. In 3.3V input designs where an
auxiliary 12V supply is available to power PVCC1 and PVCC2,
standard MOSFETs with RDS(ON) specified at VGS = 5V or
6V can be used with good results. The current drawn from
this supply varies with the MOSFETs used and the LTC38311’s operating frequency, but is generally less than 50mA.
LTC3831-1 applications that use 5V or lower VIN voltage
and tripling charge pumps to generate PVCC1 and PVCC2,
do not provide enough gate drive voltage to fully enhance
standard power MOSFETs. Under this condition, the effective MOSFET RDS(ON) may be quite high, raising the
dissipation in the FETs and reducing efficiency. Logiclevel or sub-logic level FETs are the recommended choice
for 5V or lower voltage systems. Logic-level FETs can be
fully enhanced with a tripling charge pump and will operate at maximum efficiency.
After the MOSFET threshold voltage is selected, choose
the RDS(ON) based on the input voltage, the output voltage,
allowable power dissipation and maximum output current. In a typical LTC3831-1 circuit operating in continuous mode, the average inductor current is equal to the
output load current. This current flows through either Q1
or Q2 with the power dissipation split up according to the
duty cycle:
VOUT
VIN
V
V –V
DC(Q2) = 1 – OUT = IN OUT
VIN
VIN
DC(Q1) =
The RDS(ON) required for a given conduction loss can now
be calculated by rearranging the relation P = I2R.
RDS(ON)Q1 =
RDS(ON)Q2 =
PMAX(Q1)
DC(Q1) • (ILOAD )2
PMAX(Q2 )
DC(Q2) • (ILOAD)2
=
=
VIN • PMAX(Q1)
VOUT • (ILOAD )2
VIN • PMAX(Q2 )
( VIN – VOUT ) • (ILOAD)2
PMAX should be calculated based primarily on required
efficiency or allowable thermal dissipation. A typical high
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efficiency circuit designed for 1.5V input and 0.75V at 5A
output might allow no more than 3% efficiency loss at full
load for each MOSFET. Assuming roughly 90% efficiency
at this current level, this gives a PMAX value of:
decreases the MOSFET cost and the circuit efficiency and
increases the MOSFET heat sink requirements.
Table 1 highlights a variety of power MOSFETs that are for
use in LTC3831-1 applications.
(0.75V)(5A/0.9)(0.03) = 0.125W per FET
Inductor Selection
and a required RDS(ON) of:
(1.5V) • (0.125W)
= 0.01Ω
(0.75V)(5A)2
(1.5V) • (0.125W)
= 0.01Ω
RDS(ON)Q2 =
(1.5V – 0.75V)(5A)2
RDS(ON)Q1 =
Note that while the required RDS(ON) values suggest large
MOSFETs, the power dissipation numbers are only 0.125W
per device or less; large TO-220 packages and heat sinks
are not necessarily required in high efficiency applications.
Siliconix Si4410DY or International Rectifier IRF7413 (both
in SO-8) or Siliconix SUD50N03-10 (TO-252) or ON Semiconductor MTD20N03HDL (DPAK) are small footprint
surface mount devices with RDS(ON) values below 0.03Ω at
5V of VGS that work well in LTC3831-1 circuits. Using a
higher PMAX value in the RDS(ON) calculations generally
The inductor is often the largest component in an
LTC3831-1 design and must be chosen carefully. Choose
the inductor value and type based on output slew rate requirements. The maximum rate of rise of inductor current
is set by the inductor’s value, the input-to-output voltage
differential and the LTC3831-1’s maximum duty cycle. In
a typical 1.5V input 0.75V output application, the maximum
rise time will be:
DCMAX • (VIN – VOUT ) 0.713 A
=
LO
LO µs
where LO is the inductor value in µH. With proper frequency compensation, the combination of the inductor
and output capacitor values determine the transient recovery time. In general, a smaller value inductor improves
transient response at the expense of ripple and inductor
core saturation rating. A 1µH inductor has a 0.713A/µs rise
Table 1. Recommended MOSFETs for LTC3831-1 Applications
PARTS
RDS(ON)
AT 25°C (mΩ)
RATED CURRENT (A)
TYPICAL INPUT
CAPACITANCE
CISS (pF)
θJC (°C/W)
TJMAX (°C)
1.8
175
Siliconix SUD50N03-10
TO-252
19
15 at 25°C
10 at 100°C
3200
Siliconix Si4410DY
SO-8
20
10 at 25°C
8 at 70°C
2700
ON Semiconductor MTD20N03HDL
D PAK
35
20 at 25°C
16 at 100°C
880
1.67
150
Fairchild FDS6670A
S0-8
8
13 at 25°C
3200
25
150
Fairchild FDS6680
SO-8
10
11.5 at 25°C
2070
25
150
ON Semiconductor MTB75N03HDL
DD PAK
9
75 at 25°C
59 at 100°C
4025
1
150
IR IRL3103S
DD PAK
19
64 at 25°C
45 at 100°C
1600
1.4
175
IR IRLZ44
TO-220
28
50 at 25°C
36 at 100°C
3300
1
175
Fuji 2SK1388
TO-220
37
35 at 25°C
1750
2.08
150
150
Note: Please refer to the manufacturer’s data sheet for testing conditions and detailed information.
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time in this application, resulting in a 7µs delay in responding to a 5A load current step. During this 7µs, the difference between the inductor current and the output current
is made up by the output capacitor. This action causes a
temporary voltage droop at the output. To minimize this
effect, the inductor value should usually be in the 1µH to
5µH range for most LTC3831-1 circuits. To optimize
performance, different combinations of input and output
voltages and expected loads may require different inductor values.
Once the required value is known, the inductor core type
can be chosen based on peak current and efficiency
requirements. Peak current in the inductor will be equal to
the maximum output load current plus half of the peak-topeak inductor ripple current. Ripple current is set by the
inductor value, the input and output voltage and the
operating frequency. The ripple current is approximately
equal to:
IRIPPLE =
( VIN − VOUT ) • ( VOUT )
fOSC • LO • VIN
fOSC = LTC3831-1 oscillator frequency = 300kHz
LO = Inductor value
Solving this equation with our typical 1.5V to 0.75V
application with 1µH inductor, we get:
(1.5V – 0.75V) • 0.75V
= 1.25AP-P
300kHz • 1µH • 1.5V
Peak inductor current at 5A load:
5A + (1.25A/2) = 5.625A
The ripple current should generally be between 10% and
40% of the output current. The inductor must be able to
withstand this peak current without saturating, and the
copper resistance in the winding should be kept as low as
possible to minimize resistive power loss. Note that in
circuits not employing the current limit function, the
current in the inductor may rise above this maximum
under short circuit or fault conditions; the inductor should
be sized accordingly to withstand this additional current.
Inductors with gradual saturation characteristics are often
the best choice.
Input and Output Capacitors
A typical LTC3831-1 design places significant demands
on both the input and the output capacitors. During normal
steady load operation, a buck converter like the LTC3831-1
draws square waves of current from the input supply at the
switching frequency. The peak current value is equal to the
output load current plus 1/2 the peak-to-peak ripple current. Most of this current is supplied by the input bypass
capacitor. The resulting RMS current flow in the input
capacitor heats it and causes premature capacitor failure
in extreme cases. Maximum RMS current occurs with
50% PWM duty cycle, giving an RMS current value equal
to IOUT/2. A low ESR input capacitor with an adequate
ripple current rating must be used to ensure reliable
operation. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours (3 months)
lifetime at rated temperature. Further derating of the input
capacitor ripple current beyond the manufacturer’s specification is recommended to extend the useful life of the
circuit. Lower operating temperature has the largest effect
on capacitor longevity.
The output capacitor in a buck converter under steadystate conditions sees much less ripple current than the
input capacitor. Peak-to-peak current is equal to inductor
ripple current, usually 10% to 40% of the total load
current. Output capacitor duty places a premium not on
power dissipation but on ESR. During an output load
transient, the output capacitor must supply all of the
additional load current demanded by the load until the
LTC3831-1 adjusts the inductor current to the new value.
ESR in the output capacitor results in a step in the output
voltage equal to the ESR value multiplied by the change in
load current. A 5A load step with a 0.05Ω ESR output
capacitor results in a 250mV output voltage shift; this is
20% of the output voltage for a 1.25V supply! Because of
the strong relationship between output capacitor ESR and
output load transient response, choose the output capacitor for ESR, not for capacitance value. A capacitor with
suitable ESR will usually have a larger capacitance value
than is needed to control steady-state output ripple.
Electrolytic capacitors, such as the Sanyo MV-WX series,
rated for use in switching power supplies with specified
ripple current ratings and ESR, can be used effectively in
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fZ = 1/[2π(RC)(CC)] and
fP = 1/[2π(RC)(C1)] respectively.
Figure 7b shows the Bode plot of the overall transfer
function.
Although a mathematical approach to frequency compensation can be used, the added complication of input and/or
output filters, unknown capacitor ESR, and gross operating point changes with input voltage, load current variations, all suggest a more practical empirical method. This
can be done by injecting a transient current at the load and
using an RC network box to iterate toward the final values,
or by obtaining the optimum loop response using a
network analyzer to find the actual loop poles and zeros.
LTC3831-1
VFB
COMP
10
Feedback Loop Compensation
]
VREF
C1
CC
38311 F07a
Figure 7a. Compensation Pin Connections
fSW = LTC3831 SWITCHING
FREQUENCY
fCO = CLOSED-LOOP CROSSOVER
FREQUENCY
fZ
LOOP GAIN
[
fLC = 1/ 2π (LO )(COUT )
ERR
RC
The LTC3831-1 voltage feedback loop is compensated at
the COMP pin, which is the output node of the error
amplifier. The feedback loop is generally compensated
with an RC + C network from COMP to GND as shown in
Figure 7a.
Loop stability is affected by the values of the inductor, the
output capacitor, the output capacitor ESR, the error
amplifier transconductance and the error amplifier compensation network. The inductor and the output capacitor
create a double pole at the frequency:
20dB/DECADE
The ESR of the output capacitor and the output capacitor
value form a zero at the frequency:
fESR = 1/ [2π (ESR)(COUT )]
VTT
(VOUT)
6
+
A common way to lower ESR and raise ripple current
capability is to parallel several capacitors. A typical
LTC3831-1 application might exhibit 5A input ripple current. Sanyo OS-CON capacitors, part number 10SA220M
(220µF/10V), feature 2.3A allowable ripple current at
85°C; three in parallel at the input (to withstand the input
ripple current) meet the above requirements. Similarly,
Sanyo POSCAP 4TPB470M (470µF/4V) capacitors have a
maximum rated ESR of 0.04Ω, three in parallel lower the
net output capacitor ESR to 0.013Ω.
frequency for the overall open-loop transfer function. The
zero and pole from the compensation network are:
–
LTC3831-1 applications. OS-CON electrolytic capacitors
from Sanyo and other manufacturers give excellent performance and have a very high performance/size ratio for
electrolytic capacitors. Surface mount applications can
use either electrolytic or dry tantalum capacitors. Tantalum capacitors must be surge tested and specified for use
in switching power supplies. Low cost, generic tantalums
are known to have very short lives followed by explosive
deaths in switching power supply applications. Other
capacitor series that can be used include Sanyo POSCAPs
and the Panasonic SP line.
fP
fLC
fESR
fCO
FREQUENCY
38311 F07b
The compensation network used with the error amplifier
must provide enough phase margin at the 0dB crossover
Figure 7b. Bode Plot of the LTC3831-1 Overall Transfer Function
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Table 2 shows the suggested compensation component
value for 1.5V to 0.75V applications based on the 470µF
Sanyo POSCAP 4TPB470M output capacitors.
LAYOUT CONSIDERATIONS
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3831-1. These items are also illustrated graphically in
the layout diagram of Figure 8. The thicker lines show the
high current paths. Note that at 5A current levels or above,
current density in the PC board itself is a serious concern.
Table 3 shows the suggested compensation component
values for 1.5V to 0.75V applications based on 1500µF
Sanyo MV-WX output capacitors.
Table 2. Recommended Compensation Network for 1.5V to
0.75V Applications Using Multiple Paralleled 470µF Sanyo
POSCAP 4TPB470M Output Capacitors
Table 3. Recommended Compensation Network for 1.5V to
0.75V Applications Using Multiple Paralleled 1500µF Sanyo
MV-WX Output Capacitors
L1 (µH)
COUT (µF)
RC (kΩ)
CC (nF)
C1 (pF)
L1 (µH)
COUT (µF)
RC (kΩ)
CC (nF)
C1 (pF)
1.2
1410
5.6
3.3
68
1.2
4500
15
2.2
120
1.2
2820
12
3.3
33
1.2
6000
18
2.2
82
1.2
4700
20
2.2
22
1.2
9000
30
1
56
2.4
1410
12
3.3
33
2.4
4500
30
1
56
2.4
2820
27
1.5
15
2.4
6000
39
1
33
2.4
4700
43
1.0
10
2.4
9000
62
1
27
4.7
1410
24
1.5
15
4.7
4500
62
1
27
4.7
2820
51
1.0
10
4.7
6000
82
1
22
4.7
4700
93
3.3
10
4.7
9000
130
1
10
PVCC
VCC
VIN/VDDQ
4.7µF
2.2µF
VCC
PVCC1
TG
LTC3831-1
IMAX
NC
FREQSET
IFB
SHDN
R+
COMP
BG
SS
C1
10k
+
PVCC2
PGND
CIN
0.1µF
Q1
OPTIONAL
MBRS340T3
1k
VOUT
MBRS340T3
Q2
FB
+
R–
RC
CC
GND
CSS
LO
COUT
PGND
PGND
GND
38311 F08
Figure 8. Typical Schematic Showing Layout Considerations
38311f
17
LTC3831-1
U
W
U U
APPLICATIO S I FOR ATIO
Traces carrying high current should be as wide as possible. For example, a PCB fabricated with 2oz copper
requires a minimum trace width of 0.15" to carry 5A.
1. In general, layout should begin with the location of the
power devices. Be sure to orient the power circuitry so that
a clean power flow path is achieved. Conductor widths
should be maximized and lengths minimized. After you are
satisfied with the power path, the control circuitry should
be laid out. It is much easier to find routes for the relatively
small traces in the control circuits than it is to find
circuitous routes for high current paths.
2. The GND and PGND pins should be shorted directly at
the LTC3831-1. This helps to minimize internal ground disturbances in the LTC3831-1 and prevents differences in
ground potential from disrupting internal circuit operation.
This connection should then tie into the ground plane at
a single point, preferably at a fairly quiet point in the circuit
such as close to the output capacitors. This is not always
practical, however, due to physical constraints. Another
reasonably good point to make this connection is between
the output capacitors and the source connection of the
bottom MOSFET Q2. Do not tie this single point ground in
the trace run between the Q2 source and the input capacitor ground, as this area of the ground plane will be very
noisy.
D1
D2
5. The (+) plate of CIN should be connected as close as
possible to the drain of the upper MOSFET, Q1. An additional 1µF ceramic capacitor between VIN and power ground
is recommended.
6. The VFB pin is very sensitive to pickup from the switching node. Care should be taken to isolate VFB from possible
capacitive coupling to the inductor switching signal.
7. In a typical SSTL application, if the R+ pin is to be connected to VDDQ, which is also the main supply voltage for
the switching regulator, do not connect R+ along the high
current flow path; it should be connected to the SSTL interface supply output. R– should be connected to the interface supply GND.
8. Kelvin sense IMAX and IFB at Q1’s drain and source pins.
VDDQ
1.5V
D3
0.1µF
Efficiency vs Load Current
+
0.1µF
100
CIN
220µF
90
0.1µF
4.7µF
PVCC1
PVCC2
VCC
2.2µF
IMAX
BG
SHDN
PGND
COMP
GND
RC
1k
CC
22nF
B320A
LO
1.3µH
1k
LTC3831-1 IFB
FREQSET
SHDN
Q1
10k
Q2
B320A
COUT
180µF
+
VTT
(VOUT)
0.75V
±10A
VDDQ = 1.5V
70
60
50
40
30
20
10
R+
R–
VDDQ = 1.8V
80
TG
SS
0.01µF
C1
68pF
4. The VCC, PVCC1 and PVCC2 decoupling capacitors should
be as close to the LTC3831-1 as possible. The 4.7µF and
2.2µF bypass capacitors shown at VCC, PVCC1 and PVCC2
will help provide optimum regulation performance.
EFFICIENCY (%)
3.3V
3. The small-signal resistors and capacitors for frequency
compensation and soft-start should be located very close
to their respective pins and the ground ends connected to
the signal ground pin through a separate trace. Do not
connect these parts to the ground plane!
38311 F09
FB
CIN: SANYO POSCAP 4TPB220M
COUT: PANASONIC EEFUE0G181R
D1, D2, D3: MBR0520LT1
Q1, Q2: SILICONIX Si9426DY
TA = 25°C
0
0
1
2
3 4 5 6 7
LOAD CURRENT (A)
8
9
10
38311 F10
Figure 9. DDR Memory Termination with Triple Charge Pump
38311f
18
LTC3831-1
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
16 15 14 13 12 11 10 9
.254 MIN
.009
(0.229)
REF
.150 – .165
.229 – .244
(5.817 – 6.198)
.0165 ± .0015
.150 – .157**
(3.810 – 3.988)
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
.015 ± .004
× 45°
(0.38 ± 0.10)
.007 – .0098
(0.178 – 0.249)
2 3
4
5 6
7
.0532 – .0688
(1.35 – 1.75)
8
.004 – .0098
(0.102 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
.008 – .012
(0.203 – 0.305)
TYP
.0250
(0.635)
BSC
GN16 (SSOP) 0204
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
38311f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3831-1
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1628/LTC3728 Dual High Efficiency 2-Phase Synchronous Step-Down Controllers Constant Frequency, Standby 5V and 3.3V LDOs, 3.5V ≤ VIN ≤ 36V
LTC1702
Dual High Efficiency 2-Phase Synchronous Step-Down Controller
550kHz, 25MHz GBW Voltage Mode, VIN ≤ 7V, No RSENSETM
LTC1703
Dual 550kHz Synchronous 2-Phase Switching Regulator
Controller with Mobile VID
LTC1702 with Mobile VID for Portable Systems
LTC1705
Dual 550kHz Synchronous 2-Phase Switching Regulator
Controller with 5-Bit VID Plus LDO
Provides Core, I/O and CLK Supplies for Portable Systems
LTC1709 Family
2-Phase, 5-Bit Desktop VID Synchronous Step-Down Controllers
Current Mode, VIN to 36V, IOUT Up to 42A, Various VID Tables
LTC1736
Synchronous Step-Down Controller with 5-Bit Mobile VID Control Fault Protection, Power Good, 3.5V to 36V Input, Current Mode
LTC1778
Wide Operating Range/Step-Down Controller, No RSENSE
VIN Up to 36V, Current Mode, Power Good
LTC1873
Dual Synchronous Switching Regulator with 5-Bit Desktop VID
1.3V to 3.5V Programmable Core Output Plus I/O Output
LTC1929/LTC3729 2-Phase, Synchronous High Efficiency Converter
with Mobile VID
Current Mode Ensures Accurate Current Sensing VIN Up to 36V,
IOUT Up to 40A
LTC3413
3A, Monolithic Synchronous Regulator for DDR/QDR
Memory Termination
Low RDS(ON) Internal Switch: 85mΩ, ±3A Output Current
(Sink and Source), VOUT = VREF/2
LTC3708
Dual, 2-Phase, No RSENSE Synchronous Controller with Tracking
Programmable Output Voltage Up/Down Tracking, Very Fast
Transient Response, 5V ≤ VIN ≤ 36V
LTC3713
Low Input Voltage, High Power, No RSENSE, Step-Down
Synchronous Controller
Minimum VIN: 1.5V, Uses Standard Logic-Level N-Channel
MOSFETs
LTC3778
Wide Operating Range, No RSENSE, Step-Down Controller
VIN Up to 36V, Current Mode, Power Good, Stable with
Ceramic COUT
LTC3717
Wide VIN Step-Down Controller for DDR Memory Termination
Current Mode Operation, VOUT = 1/2 VIN, VOUT (VTT)
Tracks VIN (VDDQ), No RSENSE, Symmetrical Sink and Source
Output Current Limit
LTC3718
Bus termination Supply for Low Votlage VIN
1.5V ≤ VIN, Generates 5V Gate Drive for Standard N-Ch MOSFETs,
2A ≤ IOUT ≤ 25A
LTC3831
High Power Synchronous Switching Regulator Controller
for DDR Memory Termination
VOUT Tracks 1/2 of VIN or External Reference
LTC3832
High Power Synchronous Switching Regulator Controller
VOUT as low as 0.6V
No RSENSE is a trademark of Linear Technology Corporation.
38311f
20
Linear Technology Corporation
LT/TP 0304 1K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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 LINEAR TECHNOLOGY CORPORATION 2004