LTC1553L 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium® II Processor U DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5-Bit Digitally Programmable 1.8V to 3.5V Fixed Output Voltage Provides All Features Required by the Intel Pentium® II Processor VRM 8.2 DC/DC Converter Specification Flags for Power Good, Over-Temperature and Overvoltage Fault 19A Output Current Capability from a 5V Supply Dual N-Channel MOSFET Synchronous Driver Initial Output Accuracy: ±1.5% Excellent Output Accuracy: ±2% Typ Over Line, Load and Temperature Variations High Efficiency: Over 95% Possible Adjustable Current Limit Without External Sense Resistors Fast Transient Response Available in 2O-Lead SSOP and SW Packages The LTC®1553L is a high power, high efficiency switching regulator controller optimized for a 5V input to 1.8V-3.5V output applications. It features a digitally programmable output voltage, a precision internal reference and an internal feedback system that provides output accuracy of ±1.5% at room temperature and typically ±2% over-temperature, load current and line voltage shifts. The LTC1553L uses a synchronous switching architecture with two external N-channel output devices, providing high efficiency and eliminating the need for a high power, high cost P-channel device. Additionally, it senses the output current across the on-resistance of the upper N-channel FET, providing an adjustable current limit without an external low value sense resistor. The LTC1553L free-runs at 300kHz and can be synchronized to a faster external clock if desired. It includes all the inputs and outputs required to implement a power supply conforming to the Intel Pentium® II Processor VRM 8.2 DC/DC Converter Specification. U APPLICATIONS ■ , LTC and LT are registered trademarks of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation. Power Supply for Pentium II, SPARC, ALPHA and PA-RISC Microprocessors High Power 5V to 1.8V-3.5V Regulators U ■ TYPICAL APPLICATION PVCC 12V VIN 5V + 0.1µF 5.6k 5.6k 10µF VCC PWRGD PENTIUM® II SYSTEM + 2.7k 0.1µF 5.6k IMAX 20Ω LTC1553L OUTEN COMP C1 150pF CSS 0.1µF G2 SS SGND GND LO† 2µH 18A IFB VID0 TO VID4 RC 8.2k CC 0.01µF Q1* G1 OT CIN** 1200µF ×4 PVCC FAULT 5 + 10µF SENSE 0.1µF Q2* COUT†† 330µF ×7 + *SILICONIX SUD50N03-10 **SANYO 10MV1200GX † COILTRONICS CTX02-13198 OR PANASONIC 12TS-2R5SP †† AVX TPSE337M006R0100 VOUT 1.8V TO 3.5V 14A 1553L F01 Figure 1. 5V to 1.8V-3.5V Supply Application 1 LTC1553L W U PACKAGE/ORDER INFORMATION U W W W (Note 1) Supply Voltage VCC ........................................................................ 7V PVCC ................................................................... 14V Input Voltage IFB (Note 2) ............................................ PVCC + 0.3V IMAX ........................................................ – 0.3V to 9V All Other Inputs ......................... – 0.3V to VCC + 0.3V Digital Output Voltage ................................. – 0.3V to 9V IFB Input Current (Notes 2, 3) .......................... – 100mA Operating Temperature Range ..................... 0°C to 70°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec.)................. 300°C U ABSOLUTE MAXIMUM RATINGS TOP VIEW G2 1 20 G1 PVCC 2 19 OUTEN GND 3 18 VID0 SGND 4 17 VID1 VCC 5 16 VID2 SENSE 6 15 VID3 IMAX 7 14 VID4 IFB 8 13 PWRGD SS 9 12 FAULT COMP 10 ORDER PART NUMBER LTC1553LCG LTC1553LCSW 11 OT G PACKAGE SW PACKAGE 20-LEAD PLASTIC SSOP 20-LEAD PLASTIC SO TJMAX = 125°C, θJA = 100°C/ W (G) TJMAX = 125°C, θJA = 100°C/ W (SW) Consult factory for Industrial and Military grade parts. ELECTRICAL CHARACTERISTICS VCC = 5V, PVCC = 12V, TA = 25°C, unless otherwise noted. (Note 3) SYMBOL PARAMETER VCC Supply Voltage PVCC Supply Voltage for G1, G2 VFB Internal Feedback Voltage (Note 4) VOUT 1.8V Initial Output Voltage 2.8V Initial Output Voltage 3.5V Initial Output Voltage 1.8V Initial Output Voltage 2.8V Initial Output Voltage 3.5V Initial Output Voltage With Respect to Rated Output Voltage (Figure 2) ∆VOUT Output Load Regulation Output Line Regulation IOUT = 0 to 14A (Note 4) (Figure 2) VIN = 4.75V to 5.25V, IOUT = 0 (Note 4)(Figure 2) VPWRGD Positive Power Good Trip Point Negative Power Good Trip Point % Above Output Voltage (Figure 2) % Below Output Voltage (Figure 2) ● ● 5 –5 7 –7 % % VFAULT FAULT Trip Point % Above Output Voltage (Figure 2) ● 12 15 20 % ICC Operating Supply Current Shutdown Supply Current OUTEN = VCC = 5V (Note 5)(Figure 3) OUTEN = 0, VID0 to VID4 Floating (Figure 3) ● ● 800 130 1200 250 µA µA IPVCC Supply Current PVCC = 12V, OUTEN = VCC (Note 6) (Figure 3) PVCC = 12V, OUTEN = 0, VID0 to VID4 Floating fOSC Internal Oscillator Frequency (Figure 4) VSAWL VCOMP at Minimum Duty Cycle (Note 4) 1.8 V VSAWH VCOMP at Maximum Duty Cycle (Note 4) 2.8 V GERR Error Amplifier Open-Loop DC Gain (Note 7) ● 40 53 gmERR Error Amplifier Transconductance (Note 7) ● 0.9 1.6 BWERR Error Amplifier –3dB Bandwidth COMP = Open (Note 4) 2 CONDITIONS MIN ● TYP 4.5 MAX 6 13.2 ● 1.260 – 27 (– 1.5%) – 42 (– 1.5%) – 52 (– 1.5%) ● – 36 (– 2%) ● – 56 (– 2%) ● – 70 (– 2%) 27 (+ 1.5%) 42 (+ 1.5%) 52 (+ 1.5%) 36 (+ 2%) 56 (+ 2%) 70 (+ 2%) 300 400 V mV mV mV mV mV mV mV mV 15 1 250 V V –5 ±1 ● UNITS mA µA 350 kHz dB 2.3 millimho kHz LTC1553L ELECTRICAL CHARACTERISTICS VCC = 5V, PVCC = 12V, TA = 25°C, unless otherwise noted. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS IIMAX IMAX Sink Current VIMAX = VCC ● 150 180 220 µA ISS Soft Start Source Current ISSIL Maximum Soft Start Sink Current Under Current Limit VSS = 0V, VIMAX = 0V, VIFB = VCC ● – 15 – 11 –8 µA VSENSE = VOUT, VIMAX = VCC, VIFB = 0V (Notes 8, 9), VSS = VCC ● 30 60 150 µA ISSHIL Soft Start Sink Current Under Hard Current Limit VSENSE = 0V, VIMAX = VCC, VIFB = 0V ● 20 45 mA tSSHIL Hard Current Limit Hold Time tPWRGD Power Good Response Time↑ VSENSE = 0V, VIMAX = 4V, VIFB↓ from 5V (Note 4) VSENSE↑ from 0V to Rated VOUT 500 µs ● 0.5 1 2 ms tPWRBAD Power Good Response Time↓ VSENSE↓ from Rated VOUT to 0V ● 200 500 1000 µs tFAULT FAULT Response Time VSENSE↑ from Rated VOUT to VCC ● 200 500 1000 µs tOT OT Response Time OUTEN↓, VID0 to VID4 = 0 (Note 10) (Figure 3) ● 15 40 60 µs VOT Over-Temperature Trip Point OUTEN↓, VID0 to VID4 = 0 (Note 10) (Figure 3) ● 1.9 2 2.12 V VOTDD Over-Temperature Driver Disable OUTEN↓, VID0 to VID4 = 0 (Note 10) (Figure 3) ● 1.6 1.7 1.8 V VSHDN Shutdown OUTEN↓, VID0 to VID4 = 0 (Note 10) (Figure 3) ● 0.8 V t r, t f Driver Rise and Fall Time (Figure 4) ● 90 150 ns t NOL Driver Nonoverlap Time (Figure 4) ● 30 100 DCMAX Maximum G1 Duty Cycle (Figure 4) ● 77 85 VIH VID0 to VID4 Input High Voltage ● 2 VIL VID0 to VID4 Input Low Voltage ● RIN VID0 to VID4 Internal Pull-Up Resistance ● 10 ISINK Digital Output Sink Current ● 10 The ● denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: When IFB is taken below GND, it will be clamped by an internal diode. This pin can handle input currents greater than 100mA below GND without latchup. In the positive direction, it is not clamped to VCC or PVCC. Note 3: All currents into device pins are positive; all currents out of the device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 4: This parameter is guaranteed by correlation and is not tested directly. Note 5: The LTC1553L goes into the shutdown mode if VID0 to VID4 are floating. Due to the internal pull-up resistors, there will be an additional 0.25mA/pin if any of the VID0 to VID4 pins are pulled low. ns 90 % V 0.8 20 V kΩ mA Note 6: Supply current in normal operation is dominated by the current needed to charge and discharge the external FET gates. This will vary with the LTC1553L operating frequency, supply voltage and the external FETs used. Note 7: The open-loop DC gain and transconductance from the SENSE pin to COMP pin will be (GERR)(1.260/3.3) and (gmERR)(1.260/3.3) respectively. Note 8: The current limiting amplifier can sink but cannot source current. Under normal (not current limited) operation, the output current will be zero. Note 9: Under typical soft current limit, the net soft start discharge current will be 60µA (ISSIL) + [–11µA(ISS)] ≅ 50µA. The soft start sink-to-source current ratio is designed to be 5.5:1. Note 10: When VID0 to VID4 are all HIGH, the LTC1553L will be forced to shut down internally. The OUTEN trip voltages are guaranteed by design for all other input codes. 3 LTC1553L U W TYPICAL PERFORMANCE CHARACTERISTICS Typical 2.8V VOUT Distribution TOTAL SAMPLE SIZE = 1500 90 120 A 80 100 80 25°C 100°C 60 60 50 40 40 20 20 10 0 2.785 2.825 2.815 2.795 2.805 OUTPUT VOLTAGE (V) B REFER TO TYPICAL APPLICATION CIRCUIT FIGURE 1 VIN = 5V, PVCC = 12V, VOUT = 2.8V, COUT = 330µF × 7, LO = 2µH A: Q1 = 1 × SUD50N03-10 Q2 = 1 × SUD50N03-10 B: Q1 = 2 × SUD50N03-10 Q2 = 1 × SUD50N03-10 NO FAN Q1 IS MOUNTED ON 1IN2 COPPER AREA 30 0 2.775 REFER TO TYPICAL APPLICATION 2.820 CIRCUIT FIGURE 1 V = 5V, PVCC = 12V, TA = 25°C 2.815 IN 70 EFFICIENCY (%) NUMBER OF UNITS Load Regulation 2.825 2.805 2.800 2.795 2.790 2.785 2 4 6 8 10 LOAD CURRENT (A) 12 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OUTPUT CURRENT (A) 14 1533L G03 Over-Temperature Trip Point vs Temperature 2.12 2.850 2.10 2.830 2.820 2.810 2.800 2.790 2.780 2.770 2.660 2.750 2.775 4.75 2.740 – 50 – 25 5.05 5.15 4.95 INPUT VOLTAGE (V) 5.25 50 0 75 25 TEMPERATURE (°C) 100 1.78 1.76 1.74 1.72 1.70 1.68 1.66 1.64 1.62 100 125 1553L G07 2.06 2.04 2.02 2.00 1.98 1.96 1.94 1.92 1.90 – 50 – 25 125 50 0 75 25 TEMPERATURE (°C) 2.1 1.9 1.7 1.5 1.3 1.1 0.9 – 50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 1553L G08 125 Error Amplifier Open-Loop DC Gain vs Temperature Error Amplifier Transconductance vs Temperature 2.3 100 1553L G06 ERROR AMPLIFIER OPEN-LOOP DC GAIN (dB) 1.80 ERROR AMPLIFIER TRANSCONDUCTANCE (millimho) Over-Temperature Driver Disable vs Temperature 2.08 1553L G05 1553L G04 OVER-TEMPERATURE DRIVER DISABLE (V) 2.780 2.860 2.780 4 2.790 OVER-TEMPERATURE TRIP POINT (V) 2.810 50 25 0 75 TEMPERATURE (°C) 2.795 2.785 2.840 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) REFER TO TYPICAL APPLICATION CIRCUIT FIGURE 1 OUTPUT = NO LOAD TA = 25°C 1.60 –50 –25 2.800 Output Temperature Drift 2.825 4.85 2.805 1533L G02 Line Regulation 2.815 2.810 2.775 0 0.3 1553L G01 2.820 OUTPUT VOLTAGE (V) 140 Efficiency vs Load Current 100 60 55 50 45 40 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 1553L G09 LTC1553L U W TYPICAL PERFORMANCE CHARACTERISTICS Oscillator Frequency vs Temperature 350 220 SOFT START SOURCE CURRENT (µA) –8 210 330 IMAX SINK CURRENT (µA) 320 310 300 290 280 200 190 180 170 270 160 260 250 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 150 –50 125 75 0 50 25 TEMPERATURE (°C) –25 1553L G10 VCC OPERATING SUPPLY CURRENT (mA) 90 86 2200pF 3300pF 5500pF 7700pF 84 82 80 78 – 50 – 25 –11 –12 –13 –14 –15 – 50 – 25 125 50 25 75 0 TEMPERATURE (°C) 100 50 25 75 0 TEMPERATURE (°C) 250 1.1 1.0 0.9 0.8 0.7 0.6 50 25 75 0 TEMPERATURE (°C) 1553L G13 100 125 225 200 175 150 125 100 75 50 – 50 – 25 0 50 75 25 TEMPERATURE (°C) Output Over Current Protection 70 100 125 1553L G15 1553L G14 PVCC Supply Current vs Gate Capacitance 125 VCC Shutdown Supply Current vs Temperature VCC = 5V fOSC = 300kHz 0.5 – 50 –25 125 100 1553L G12 1.2 OSCILLATOR FREQUENCY = 300kHz G1, G2 CAPACITANCE = 1100pF –10 VCC Operating Supply Current vs Temperature 92 88 –9 1553L G11 Maximum G1 Duty Cycle vs Temperature MAXIMUM G1 DUTY CYCLE (%) 100 VCC SHUTDOWN SUPPLY CURRENT (mA) OSCILLATOR FREQUENCY (kHz) 340 Transient Response 3.0 PVCC = 12V TA = 25°C Q1 CASE = 90°C, VOUT = 2.8V Q1 = 2 × MTD20N03HDL Q2 = 1 × MTD20N03HDL RIMAX = 2.7k, RIFB = 20Ω, SS CAP = 0.01µF 2.5 OUTPUT VOLTAGE (V) 60 PVCC SUPPLY CURRENT (mA) Soft Start Source Current vs Temperature IMAX Sink Current vs Temperature 50 40 30 20 2.0 50mV/DIV 1.5 5A/DIV 1.0 SHORT-CIRCUIT CURRENT 0.5 10 0 0 2000 4000 6000 GATE CAPACITANCE (pF) 8000 1553L G16 100µs/DIV 1553L G18 0 0 2 4 6 8 10 12 14 OUTPUT CURRENT (A) 16 18 1553L G17 5 LTC1553L U U U PIN FUNCTIONS G2 (Pin 1): Gate Drive for the Lower N-Channel MOSFET, Q2. This output will swing from PVCC to GND. It will always be low when G1 is high or when the output is disabled. To prevent undershoot during a soft start cycle, G2 is held low until G1 first goes high. PVCC (Pin 2): Power Supply for G1 and G2. PVCC must be connected to a potential of at least VIN + VGS(ON)Q1. If VIN = 5V, PVCC can be generated using a simple charge pump connected to the switching node between Q1 and Q2 (see Figure 7), or it can be connected to an auxiliary 12V supply if one exists. GND (Pin 3): Power Ground. GND should be connected to a low impedance ground plane in close proximity to the source of Q2. SGND (Pin 4): Signal Ground. SGND is connected to the low power internal circuitry and should be connected to the negative terminal of the output capacitor where it returns to the ground plane. GND and SGND should be shorted right at the LTC1553L. VCC (Pin 5): Power Supply. Power for the internal low power circuity. VCC should be wired separately from the drain of Q1 if they share the same supply. A 10µF bypass capacitor is recommended from this pin to SGND. SENSE (Pin 6): Output Voltage Pin. Connect to the positive terminal of the output capacitor. There is an internal 120k resistor connected from this pin to SGND. SENSE is a very sensitive pin; for optimum performance, connect an external 0.1µF capacitor from this pin to SGND. By connecting a small external resistor between the output capacitor and the SENSE pin, the initial output voltage can be raised slightly. Since the internal divider has a nominal impedance of 120kΩ, a 1200Ω series resistor will raise the nominal output voltage by 1%. If an external resistor is used, the value of the 0.1µF capacitor on the SENSE pin must be greatly reduced or loop phase margin will suffer. Set a time constant for the RC combination of approximately 0.1µs. So, for example, with a 1200Ω resistor, set C = 83pF. Use a standard 100pF capacitor. 6 IMAX (Pin 7): Current Limit Threshold. Current limit is set by the voltage drop across an external resistor connected between the drain of Q1 and IMAX. There is a 180µA internal pull-down at IMAX. IFB (Pin 8): Current Limit Sense Pin. Connect to the switching node between the source of Q1 and the drain of Q2. If IFB drops below IMAX when G1 is on, the LTC1553L will go into current limit. The current limit circuit can be disabled by floating IMAX and shorting IFB to VCC through an external 10k resistor. SS (Pin 9): Soft Start. Connect to an external capacitor to implement a soft start function. During moderate overload conditions, the soft start capacitor will be discharged slowly in order to reduce the duty cycle. In hard current limit, the soft start capacitor will be forced low immediately and the LTC1553L will rerun a complete soft start cycle. CSS must be selected such that during power-up the current through Q1 will not exceed the current limit value. COMP (Pin 10): External Compensation. The COMP pin is connected directly to the output of the error amplifier and the input of the PWM comparator. An RC + C network is used at this node to compensate the feedback loop to provide optimum transient response. OT (Pin 11): Over-Temperature Fault. OT is an open-drain output and will be pulled low if OUTEN is less than 2V. If OUTEN = 0, OT pulls low. FAULT (Pin 12): Overvoltage Fault. FAULT is an opendrain output. If VOUT reaches 15% above the nominal output voltage, FAULT will go low and G1 and G2 will be disabled. Once triggered, the LTC1553L will remain in this state until the power supply is recycled or the OUTEN pin is toggled. If OUTEN = 0, FAULT floats or is pulled high by an external resistor. PWRGD (Pin 13): Power Good. This is an open-drain signal to indicate validity of output voltage. A high indicates that the output has settled to within ±5% of the rated output for more than 1ms. PWRGD will go low if the output is out of regulation for more than 500µs. If OUTEN = 0, PWRGD pulls low. LTC1553L U U U PIN FUNCTIONS OT trips. As OUTEN drops below 1.7V, the drivers are internally disabled to prevent the MOSFETs from heating further. If OUTEN is less than 1.2V for longer than 30µs, the LTC1553L will enter shutdown mode. The internal oscillator can be synchronized to a faster external clock by applying the external clocking signal to the OUTEN pin. VID0, VID1, VID2, VID3, VID4 (Pins 18, 17, 16, 15, 14): Digital Voltage Select. TTL inputs used to set the regulated output voltage required by the processor (Table 3). There is an internal 20kΩ pull-up at each pin. When all five VIDn pins are high or floating, the chip will shut down. OUTEN (Pin 19): Output Enable. TTL input which enables the output voltage. The external MOSFET temperature can be monitored with an external thermistor as shown in Figure 11. When the OUTEN input voltage drops below 2V, G1 (Pin 20): Gate Drive for the Upper N-Channel MOSFET, Q1. This output will swing from PVCC to GND. It will always be low when G2 is high or the output is disabled. W BLOCK DIAGRAM + 115% VREF FC 12 FAULT 11 OT DELAY – 13 PWRGD DISDR LOGIC OUTEN 19 SYSTEM POWER DOWN – 2 PVCC R PWM 20 G1 S + COMP 10 1 G2 ISS QSS SS 9 BG ERR + MIN – MAX + – – 6 SENSE + FB VREF VREF – 5% 18 VID0 VREF + 5% 17 VID1 16 VID2 – 8 IFB + 7 IMAX 15 VID3 CC IMAX DAC + MHCL HCL MONO 14 VID4 VREF 0.5VREF / 0.7VREF LVC – 1553 BD 7 LTC1553L TEST CIRCUITS PVCC 12V VCC 5V + 3k 3k 3k + + 0.1µF 10µF 100pF 100pF OUTEN 0.1µF 10µF VCC LTC1553L VID0 TO VID4 COMP RC 8.2k CC 0.01µF C1 150pF LO† Q1* 2µH 15A SS VOUT NC IMAX OT VID0 TO VID4 IFB G1 FAULT GND COUT†† 330µF ×7 Q2* G2 SGND SENSE 0.1µF CIN** 1200µF ×4 10k PVCC PWRGD 100pF VIN 5V + *SILICONIX SUD50N03-10 **SANYO 10MV1200GX † COILTRONICS CTX02-13198 OR PANASONIC 12TS-2R5SP †† AVX TPSE337M006R0100 0.1µF 1553L F02 Figure 2 VCC VID0 VID1 VID2 VID3 VID4 VCC + 10k VCC VID0 VID1 VID2 VID3 VID4 IFB OUTEN NC FAULT NC OT NC COMP PVCC PVCC PWRGD NC + G1 NC IMAX NC G2 NC LTC1553L SS 10µF 0.1µF SGND GND 10µF 0.1µF SENSE NC 1553L F03 Figure 3 VCC 5V PVCC 12V tr + + 10µF 0.1µF 10k 0.1µF VCC 90% 10µF 50% PVCC G1 IFB tf 10% G1 RISE/FALL 90% 50% 10% 5000pF LTC1553L t NOL G2 SENSE SGND GND t NOL G2 RISE/FALL 5000pF 50% 50% 1553L F04 Figure 4 8 LTC1553L U U FU CTIO TABLES Table 1. OT Logic Table 3. Rated Output Voltage (cont) OUTEN (V) OT* <2 0 VID4 VID3 VID2 VID1 VID0 RATED OUTPUT VOLTAGE (V) >2 1 0 0 1 0 1 1.80 0 0 1 0 0 1.85 0 0 0 1 1 1.90 0 0 0 1 0 1.95 0 0 0 0 1 2.00 0 0 0 0 0 2.05 1 1 1 1 1 SHDN 1 1 1 1 0 2.1 1 1 1 0 1 2.2 1 1 1 0 0 2.3 1 1 0 1 1 2.4 1 1 0 1 0 2.5 1 1 0 0 1 2.6 1 1 0 0 0 2.7 INPUT PIN Table 2. PWRGD and FAULT Logic INPUT OUTPUT* OUTEN VSENSE** OT FAULT PWRGD 0 X 0 1 0 1 < 95% 1 1 0 1 > 95% < 105% 1 1 1 1 >105% 1 1 0 1 > 115% 1 0 0 Table 3. Rated Output Voltage INPUT PIN VID4 VID3 VID2 VID1 VID0 RATED OUTPUT VOLTAGE (V) 0 1 1 1 1 Disabled † (1.30) 1 0 1 1 1 2.8 0 1 1 1 0 Disabled † (1.35) 1 0 1 1 0 2.9 0 1 0 1 3.0 0 1 1 0 1 Disabled † (1.40) 1 0 1 1 0 0 Disabled † (1.45) 1 0 1 0 0 3.1 0 1 0 1 1 Disabled † (1.50) 1 0 0 1 1 3.2 0 0 1 0 3.3 0 1 0 1 0 Disabled † (1.55) 1 0 1 0 0 1 Disabled † (1.60) 1 0 0 0 1 3.4 0 1 0 0 0 Disabled † (1.65) 1 0 0 0 0 3.5 0 0 1 1 1 Disabled † (1.70) 0 0 1 1 0 Disabled † (1.75) * With external pull-up resistor ** With respect to the output voltage selected in Table 3 as required by Intel Specification VRM 8.2 † These code selections are disabled in LTC1553L X Don’t care 9 LTC1553L U W U U APPLICATIONS INFORMATION OVERVIEW The LTC1553L is a voltage feedback, synchronous switching regulator controller (see Block Diagram) designed for use in high power, low voltage step-down (buck) converters. It is designed to satisfy the requirements of the Intel Pentium II power supply specification. It includes an on-chip DAC to control the output voltage, a PWM generator, a precision reference trimmed to ±1%, two high power MOSFET gate drivers and all the necessary feedback and control circuitry to form a complete switching regulator circuit. Output regulation can be monitored with the PWRGD pin which in turn monitors the internal MIN and MAX comparators. If the output is ±5% beyond the selected value for more than 500µs, the PWRGD output will be pulled low. Once the output has settled within ±5% of the selected value for more than 1ms, PWRGD will return high. THEORY OF OPERATION Primary Feedback Loop The LTC1553L includes a current limit sensing circuit that uses the upper external power MOSFET as a current sensing element, eliminating the need for an external sense resistor. Once the current comparator, CC, detects an overcurrent condition, the duty cycle is reduced by discharging the soft start capacitor through a voltagecontrolled current source. Under severe overloads or output short circuit conditions, the chip will be repeatedly forced into soft start until the short is removed, preventing the external components from being damaged. Under output overvoltage conditions, the MOSFET drivers will be disabled permanently until the chip power supply is recycled or the OUTEN pin is toggled. The regulator output voltage at the SENSE pin is divided down internally by a resistor divider with a total resistance of approximately 120kΩ. This divided down voltage is subtracted from a reference voltage supplied by the DAC output. The resulting error voltage is amplified by the error amplifier and the output is compared to the oscillator ramp waveform by the PWM comparator. This PWM signal controls the external MOSFETs through G1 and G2. The resulting chopped waveform is filtered by LO and COUT closing the loop. Loop frequency compensation is achieved with an external RC + C network at the COMP pin, which is connected to the output node of the transconductance amplifier. OUTEN can optionally be connected to an external negative temperature coefficient (NTC) thermistor placed near the external MOSFETs or the microprocessor. Three threshold levels are provided internally. When OUTEN drops to 2V, OT will trip, issuing a warning to the external CPU. If the temperature continues to rise and the OUTEN input drops to 1.7V, the G1 and G2 pins will be forced low. If OUTEN is pulled below 1.2V, the LTC1553L will go into shutdown mode, cutting the supply current to a minimum. If thermal shutdown is not required, OUTEN can be connected to a conventional TTL enable signal. The freerunning 300kHz PWM frequency can be synchronized to a faster external clock connected to OUTEN. Adjusting the oscillator frequency can add flexibility in the external component selection. See the Clock Synchronization section. MIN, MAX Feedback Loops 10 Two additional comparators in the feedback loop provide high speed fault correction in situations where the ERR amplifier may not respond quickly enough. MIN compares the feedback signal FB to a voltage 60mV (5%) below the internal reference. If FB is lower than the threshold of this comparator, the MIN comparator overrides the ERR amplifier and forces the loop to full duty cycle which is set by the internal oscillator typically to 85%. Similarly, the MAX comparator forces the output to 0% duty cycle if FB is more than 5% above the internal reference. To prevent these two comparators from triggering due to noise, the MIN and MAX comparators’ response times are deliberately controlled so that they take two to three microseconds to respond. These two comparators help prevent extreme output perturbations with fast output transients, while allowing the main feedback loop to be optimally compensated for stability. LTC1553L U W U U APPLICATIONS INFORMATION Soft Start and Current Limit The LTC1553L includes a soft start circuit which is used for initial start-up and during current limit operation. The SS pin requires an external capacitor to GND with the value determined by the required soft start time. An internal 11µA current source is included to charge the external SS capacitor. During start-up, the COMP pin is clamped to a diode drop above the voltage at the SS pin. This prevents the error amplifier, ERR, from forcing the loop to maximum duty cycle. The LTC1553L will begin to operate at low duty cycle as the SS pin rises above about 1.2V (VCOMP ≈ 1.8V). As SS continues to rise, QSS turns off and the error amplifier begins to regulate the output. The MIN comparator is disabled when soft start is active to prevent it from overriding the soft start function. The LTC1553L includes yet another feedback loop to control operation in current limit. Just before every falling edge of G1, the current comparator, CC, samples and holds the voltage drop measured across the external MOSFET, Q1, at the IFB pin. CC compares the voltage at IFB to the voltage at the IMAX pin. As the peak current rises, the measured voltage across Q1 increases due to the drop across the RDS(ON) of Q1. When the voltage at IFB drops below IMAX, indicating that Q1’s drain current has exceeded the maximum level, CC starts to pull current out of the external soft start capacitor, cutting the duty cycle and controlling the output current level. The CC comparator pulls current out of the SS pin in proportion to the voltage difference between IFB and IMAX. Under minor overload conditions, the SS pin will fall gradually, creating a time delay before current limit takes effect. Very short, mild overloads may not affect the output voltage at all. More significant overload conditions will allow the SS pin to reach a steady state, and the output will remain at a reduced voltage until the overload is removed. Serious overloads will generate a large overdrive at CC, allowing it to pull SS down quickly and preventing damage to the output components. helps minimize the number of components in the high current path. Due to switching noise and variation of RDS(ON), the actual current limit trip point is not highly accurate. The current limiting circuitry is primarily meant to prevent damage to the power supply circuitry during fault conditions. The exact current level where the limiting circuit begins to take effect will vary from unit to unit as the RDS(ON) of Q1 varies. For a given current limit level, the external resistor from IMAX to VIN can be determined by: RIMAX = (ILMAX )(RDS(ON)Q1) IIMAX where, I ILMAX = ILOAD + RIPPLE 2 ILOAD = Maximum load current IRIPPLE = Inductor ripple current = (VIN − VOUT )(VOUT ) (fOSC )(L O)(VIN) fOSC = LTC1553L oscillator frequency = 300kHz LO = Inductor value RDS(ON)Q1 = Hot on-resistance of Q1 at ILMAX IIMAX = Internal 180µA sink current at IMAX VIN + LTC1553L IMAX + 7 180µA CC G1 IFB – CIN RIMAX Q1 LO 20Ω 8 VOUT + G2 Q2 COUT 1553L F05 By using the RDS(ON) of Q1 to measure the output current, the current limiting circuit eliminates an expensive discrete sense resistor that would otherwise be required. This Figure 5. Current Limit Setting 11 LTC1553L U U W U APPLICATIONS INFORMATION Table 4. Recommended Minimum RIMAX Resistor (kΩ) vs Maximum Operating Load Current and External MOSFET Q1 MAXIMUM OPERATING LOAD CURRENT (A) SUD50N03-10 SUD50N03-10 (TWO IN PARALLEL) MTD20N03HDL MTD20N03HDL (TWO IN PARALLEL) 12 2.4 1.2 4.3 2.2 14 2.7 1.3 5.1 2.7 16 3.0 1.5 6.2 3.0 18 3.6 1.8 6.8 3.3 20 3.9 2.0 7.5 3.6 OUTEN and Thermistor Input The LTC1553L includes a low power shutdown mode, controlled by the logic at the OUTEN pin. A high at OUTEN allows the part to operate normally. A low level at OUTEN stops all internal switching, pulls COMP and SS to ground internally and turns Q1 and Q2 off. OT and PWRGD are pulled low, and FAULT is left floating. In shutdown, the LTC1553L quiescent current will drop to about 130µA. The remaining current is used to keep the thermistor sensing circuit at OUTEN alive. Note that the leakage current of the external MOSFETs may add to the total shutdown current consumed by the circuit, especially at elevated temperature. OUTEN is designed with multiple thresholds to allow it to also be utilized for over-temperature protection. The power MOSFET operating temperature can be monitored with an external negative temperature coefficient (NTC) thermistor mounted next to the external MOSFET which is expected to run the hottest –– often the high-side device, Q1. Electrically, the thermistor should form a voltage divider with another resistor, R1, connected to VCC. Their midpoint should be connected to OUTEN (see Figure 6). As the temperature increases, the OUTEN pin voltage is reduced. Under normal operating conditions, the OUTEN pin should stay above 2V. All circuits will function normally, and the OT pin will remain in a high state. If the temperature gets abnormally high, the OUTEN pin voltage will eventually drop below 2V. OT will switch to a logic low, providing an over-temperature warning to the system. As OUTEN drops below 1.7V, the LTC1553L disables both FET drivers. If OUTEN is less than 1.2V, the LTC1553L will enter shutdown mode. To activate any of these three modes, the OUTEN voltage must drop below the respective threshold for longer than 30µs. 12 VIN VCC 5.6k PENTIUM II SYSTEM OT G1 Q1 LO VCC LTC1553L VOUT R1 R2 NTC THERMISTOR MOUNT IN CLOSE THERMAL PROXIMITY TO Q1 + OUTEN G2 Q2 COUT 1553L F06 Figure 6. OUTEN Pin as a Thermistor Input Clock Synchronization The internal oscillator can be synchronized to an external clock by applying the external clocking signal to the OUTEN pin. The synchronizing range extends from the initial operating frequency up to 500kHz. If the external frequency is much higher than the natural free-running frequency, the peak-to-peak sawtooth amplitude within the LTC1553L will decrease. Since the loop gain is inversely proportional to the amplitude of the sawtooth, the compensation network may need to be adjusted slightly. Note that the temperature sensing circuitry does not operate when external synchronization is used. MOSFET Gate Drive Power for the internal MOSFET drivers is supplied by PVCC. This supply must be above the input supply voltage by at least one power MOSFET VGS(ON) for efficient operation. This higher voltage can be supplied with a separate supply, or it can be generated using a simple charge pump as shown in Figure 7. The 85% typical maximum duty cycle ensures sufficient off-time to refresh the charge pump during each cycle. LTC1553L U U W U APPLICATIONS INFORMATION 1N5817 VIN OPTIONAL FOR VIN > 5V 1N5243B 13V + 2 PVCC CIN 0.1µF LTC1553L G1 20 Q1 LO VOUT G2 1 + Q2 COUT 1553L F07 Figure 7. Doubling Charge Pump If the OUTEN pin is low, G1 and G2 are both held low to prevent output voltage undershoot. As VCC and PVCC power up from a 0V condition, an internal undervoltage lockup circuit prevents G1 and G2 from going high until VCC reaches about 3.5V. If VCC powers up while PVCC is at ground potential, the SS is forced to ground potential internally. SS clamps the COMP pin low and prevents the drivers from turning on. On power-up or recovery from thermal shutdown, the drivers are designed such that G2 is held low until G1 first goes high. Power MOSFETs Two N-channel power MOSFETs are required for most LTC1553L circuits. Logic level MOSFETs should be used and they should be selected based on on-resistance considerations. RDS(ON) should be chosen based on input and output voltage, allowable power dissipation and maximum required output current. In a typical LTC1553L buck converter circuit the average inductor current is equal to the output load current. This current is always flowing through either Q1 or Q2 with the power dissipation split up according to the duty cycle: ( ) V DC Q1 = OUT VIN ( VIN − VOUT V DC Q2 = 1 − OUT = VIN VIN ( ) VIN)PMAX(Q1) ( RDS(ON)Q1 = = 2 2 [DC(Q1)](IMAX) (VOUT)(IMAX) VIN)PMAX(Q2) PMAX(Q2) ( RDS(ON)Q2 = = [DC(Q2)](IMAX)2 (VIN − VOUT)(IMAX)2 ( ) PMAX Q1 ) The RDS(ON) required for a given conduction loss can now be calculated by rearranging the relation P = I2R. PMAX should be calculated based primarily on required efficiency or allowable thermal dissipation. A typical high efficiency circuit designed for Pentium II with a 5V input and a 2.8V, 11.2A output might allow no more than 4% efficiency loss at full load for each MOSFET. Assuming roughly 90% efficiency at this current level, this gives a PMAX value of: [(2.8)(11.2A/0.9)(0.04)] = 1.39W per FET and a required RDS(ON) of: (5V)(1.39W) = 0.019Ω ( ) 2 (2.8V)(11.2A) (5V)(1.39W) = 0.025Ω RDS(ON)Q2 = 2 (5V − 2.8V)(11.2A) RDS ON Q1 = Note also that while the required RDS(ON) values suggest large MOSFETs, the dissipation numbers are only 1.39W per device or less––large TO-220 packages and heat sinks are not necessarily required in high efficiency applications. Siliconix Si4410DY or International Rectifier IRF7413 (both in SO-8) or Siliconix SUD50N03 or Motorola MTD20N03HDL (both in D PAK) are small footprint surface mount devices with RDS(ON) values below 0.03Ω at 5V of gate drive that work well in LTC1553L circuits. With higher output voltages, the RDS(ON) of Q1 may need to be significantly lower than that for Q2. These conditions can often be met by paralleling two MOSFETs for Q1 and using a single device for Q2. Note that using a higher PMAX value in the RDS(ON) calculations will generally decrease MOSFET cost and circuit efficiency while increasing MOSFET heat sink requirements. 13 LTC1553L U U W U APPLICATIONS INFORMATION Table 5. Recommended MOSFETs for LTC1553L Applications RDS(ON) AT 25°C (mΩ) PARTS RATED CURRENT (A) TYPICAL INPUT CAPACITANCE CISS (pF) θJC (°C/W) TJMAX (°C) Siliconix SUD50N03-10 TO-252 19 15 at 25°C 10 at 100°C 3200 1.8 175 Siliconix Si4410DY SO-8 20 10 at 25°C 8 at 75°C 2700 — 150 Motorola MTD20N03HDL D PAK 35 20 at 25°C 16 at 100°C 880 1.67 150 SGS-Thomson STD20N03L D PAK 23 20 at 25°C 14 at 100°C 2300 2.5 175 Motorola MTB75N03HDL DD PAK 7.5 75 at 25°C 59 at 100°C 4025 1.0 150 IRF IRL3103S DD PAK 14 56 at 25°C 40 at 100°C 1600 1.8 175 IRF IRLZ44 TO-220 28 50 at 25°C 36 at 100°C 3300 1.0 175 Fuji 2SK1388 TO-220 37 35 at 25°C 1750 2.08 150 Note: Please refer to the manufacturer’s data sheet for testing conditions and detail information. Inductor Selection The inductor is often the largest component in the LTC1553L design and should be chosen carefully. Inductor value and type should be chosen based on output slew rate requirements, output ripple requirements and expected peak current. Inductor value is primarily controlled by the required current slew rate. The maximum rate of rise of current in the inductor is set by its value, the input-tooutput voltage differential and the maximum duty cycle of the LTC1553L. In a typical 5V input, 2.8V output application, the maximum current slew rate will be: DCMAX (VIN − VOUT) = 1.83 L L A µs where L is the inductor value in µH. With proper frequency compensation, the combination of the inductor and output capacitor will determine the transient recovery time. In general, a smaller value inductor will improve transient response at the expense of increased output ripple voltage and inductor core saturation rating. A 2µH inductor would have a 0.9A/µs rise time in this application, resulting in a 5.5µs delay in responding to a 5A load current step. During 14 this 5.5µs, the difference between the inductor current and the output current must be made up by the output capacitor, causing a temporary voltage droop at the output. To minimize this effect, the inductor value should usually be in the 1µH to 5µH range for most typical 5V input LTC1553L circuits. To optimize performance, different combinations of input and output voltages and expected loads may require different inductor values. Once the required value is known, the inductor core type can be chosen based on peak current and efficiency requirements. Peak current in the inductor will be equal to the maximum output load current plus half of the peak-topeak inductor ripple current. Ripple current is set by the inductor value, the input and output voltage and the operating frequency. The ripple current is approximately equal to: IRIPPLE = (VIN − VOUT)(VOUT) (fOSC)(LO)(VIN) fOSC = LTC1553L oscillator frequency = 300kHz LO = Inductor value LTC1553L U W U U APPLICATIONS INFORMATION Solving this equation with our typical 5V to 2.8V application with a 2µH inductor, we get: (2.2)(0.56) = 2AP-P (300kHz)(2µH) Peak inductor current at 11.2A load: 11.2A + 2A = 12.2A 2 The ripple current should generally be between 10% and 40% of the output current. The inductor must be able to withstand this peak current without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. Note that in circuits not employing the current limit function, the current in the inductor may rise above this maximum under short circuit or fault conditions; the inductor should be sized accordingly to withstand this additional current. Inductors with gradual saturation characteristics are often the best choice. Input and Output Capacitors A typical LTC1553L design puts significant demands on both the input and the output capacitors. During constant load operation, a buck converter like the LTC1553L draws square waves of current from the input supply at the switching frequency. The peak current value is equal to the output load current plus 1/2 peak-to-peak ripple current, and the minimum value is zero. Most of this current is supplied by the input bypass capacitor. The resulting RMS current flow in the input capacitor will heat it up, causing premature capacitor failure in extreme cases. Maximum RMS current occurs with 50% PWM duty cycle, giving an RMS current value equal to IOUT /2. A low ESR input capacitor with an adequate ripple current rating must be used to ensure reliable operation. Note that capacitor manufacturers’ ripple current ratings are often based on only 2000 hours (three months) lifetime at rated temperature. Further derating of the input capacitor ripple current beyond the manufacturer’s specification is recommended to extend the useful life of the circuit. Lower operating temperature will have the largest effect on capacitor longevity. The output capacitor in a buck converter sees much less ripple current under steady-state conditions than the input capacitor. Peak-to-peak current is equal to that in the inductor, usually 10% to 40% of the total load current. Output capacitor duty places a premium not on power dissipation but on ESR. During an output load transient, the output capacitor must supply all of the additional load current demanded by the load until the LTC1553L can adjust the inductor current to the new value. Output capacitor ESR results in a step in the output voltage equal to the ESR value multiplied by the change in load current. An 11A load step with a 0.05Ω ESR output capacitor will result in a 550mV output voltage shift; this is 19.6% of the output voltage for a 2.8V supply! Because of the strong relationship between output capacitor ESR and output load transient response, the output capacitor is usually chosen for ESR, not for capacitance value; a capacitor with suitable ESR will usually have a larger capacitance value than is needed for energy storage. Electrolytic capacitors rated for use in switching power supplies with specified ripple current ratings and ESR can be used effectively in LTC1553L applications. OS-CON electrolytic capacitors from SANYO and other manufacturers give excellent performance and have a very high performance/size ratio for electrolytic capacitors. Surface mount applications can use either electrolytic or dry tantalum capacitors. Tantalum capacitors must be surge tested and specified for use in switching power supplies. Low cost, generic tantalums are known to have very short lives followed by explosive deaths in switching power supply applications. AVX TPS series surface mount devices are popular surge tested tantalum capacitors that work well in LTC1553L applications. A common way to lower ESR and raise ripple current capability is to parallel several capacitors. A typical LTC1553L application might exhibit 5A input ripple current. SANYO OS-CON part number 10SA220M (220µF/ 10V) capacitors feature 2.3A allowable ripple current at 85°C; three in parallel at the input (to withstand the input ripple current) will meet the above requirements. Similarly, AVX TPSE337M006R0100 (330µF/6V) have a rated maximum ESR of 0.1Ω; seven in parallel will lower the net output capacitor ESR to 0.014Ω. For low cost application, SANYO MV-GX series of capacitors can be used with acceptable performance. 15 LTC1553L U W U U APPLICATIONS INFORMATION Feedback Loop Compensation 6 SENSE The LTC1553L voltage feedback loop is compensated at the COMP pin, attached to the output node of the internal gm error amplifier. The feedback loop can generally be compensated properly with an RC + C network from COMP to GND as shown in Figure 8a. COMP 10 ERR + fLC = – Loop stability is affected by the values of the inductor, output capacitor, output capacitor ESR, error amplifier transconductance and error amplifier compensation network. The inductor and the output capacitor create a double pole at the frequency: LTC1553L RC C1 DAC CC 1553L F08a 1 2π√(LO)(COUT) Figure 8a. Compensation Pin Hook-Up The ESR of the output capacitor forms a zero at the frequency: 1 2π(ESR)(COUT) fZ LOOP GAIN fESR = The compensation network at the error amplifier output is to provide enough phase margin at the 0dB crossover frequency for the overall closed-loop transfer function. The zero and pole from the compensation network are: – 20dB/DECADE fP 1 1 fZ = and fP = respectively. 2π(RC)(CC) 2π(RC)(C1) Figure 8b shows the Bode plot of the overall transfer function. The compensation value used in this design is based on the following criteria: fSW = 12fCO, fZ = fLC and fP = 5fCO. At the closed-loop frequency fCO, the attenuation due the LC filter and the input resistor divider is compensated by the gain of the PWM modulator and the gain of the error amplifier (gmERR)(RC). Although a mathematical approach to frequency compensation can be used, the added complication of input and/or output filters, unknown capacitor ESR, and gross operating point changes with input voltage, load current variations, all suggest a more practical empirical method. This can be done by injecting a transient current at the load and using an RC network box to iterate toward the final compensation values, or by obtaining the optimum loop response using a network analyzer to find the actual loop poles and zeros. 16 fSW = LTC1553L SWITCHING FREQUENCY fCO = CLOSED-LOOP CROSSOVER FREQUENCY fLC fESR fCO FREQUENCY 1553L F08b Figure 8b. Bode Plot of the LTC1553L Overall Transfer Function Table 6. Suggested Compensation Network for 5V Input Application Using Multiple Paralleled 330µF AVX TPS Output Capacitors LO (µH) CO (µF) RC (kΩ) CC (µF) C1 (pF) 1 990 1.8 0.022 680 1 1980 3.6 0.01 330 1 4950 9.1 0.01 120 2.7 990 5.1 0.01 220 2.7 1980 10 0.01 120 2.7 4950 24 0.0047 47 5.6 990 10 0.01 120 5.6 1980 20 0.0047 56 5.6 4950 51 0.0036 22 LTC1553L U W U U APPLICATIONS INFORMATION Table 6 shows the suggested compensation components for 5V input applications based on the inductor and output capacitor values. The values were calculated using multiple paralleled 330µF AVX TPS series surface mount tantalum capacitors as the output capacitor. The optimum component values might deviate from the suggested values slightly because of board layout and operating condition differences. An alternate output capacitor is the Sanyo MV-GX series. Using multiple parallel 1500µF Sanyo MV-GX capacitors for the output capacitor, Table 7 shows the suggested compensation component value for a 5V input application based on the inductor and output capacitor values. Table 7. Suggested Compensation Network for 5V Input Application Using Multiple Paralleled 1500µF SANYO MV-GX Output Capacitors LO (µH) CO (µF) RC (kΩ) CC (µF) C1 (pF) 1 4500 4.3 0.022 270 1 6000 5.6 0.0047 220 1 9000 8.2 0.01 150 2.7 4500 11 0.01 100 2.7 6000 15 0.01 82 2.7 9000 22 0.01 56 5.6 4500 24 0.01 56 5.6 6000 30 0.0047 39 5.6 9000 47 0.0047 27 VID0 to VID4, PWRGD and FAULT The digital inputs (VID0 to VID4) program the internal DAC which in turn controls the output voltage. These digital input controls are intended to be static and are not designed for high speed switching. Forcing VOUT to step from a high to a low voltage by changing the VIDn pins quickly can cause FAULT to trip. Figure 9 shows the relationship between the VOUT voltage, PWRGD and FAULT. To prevent PWRGD from interrupting the CPU unnecessarily, the LTC1553L has a built-in tPWRBAD delay to prevent noise at the SENSE pin from toggling PWRGD. The internal time delay is designed to take about 500µs for PWRGD to go low and 1ms for it to recover. Once PWRGD goes low, the internal circuitry watches for the output voltage to exceed 115% of the rated voltage. If this happens, FAULT will be triggered. Once FAULT is triggered, G1 and G2 will be forced low immediately and the LTC1553L will remain in this state until VCC power supply is recycled or OUTEN is toggled. 15% VOUT 5% RATED VOUT –5% t PWRBAD t PWRGD t FAULT PWRGD FAULT 1553L F09 Figure 9. PWRGD and FAULT LAYOUT CONSIDERATIONS When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC1553L. These items are also illustrated graphically in the layout diagram of Figure 10. The thicker lines show the high current paths. Note that at 10A current levels or above, current density in the PC board itself is a serious concern. Traces carrying high current should be as wide as possible. For example, a PCB fabricated with 2oz copper requires a minimum trace width of 0.15" to carry 10A. 1. In general, layout should begin with the location of the power devices. Be sure to orient the power circuitry so that a clean power flow path is achieved. Conductor widths should be maximized and lengths minimized. After you are satisfied with the power path, the control circuitry should be laid out. It is much easier to find routes for the relatively small traces in the control circuits than it is to find circuitous routes for high current paths. 2. The GND and SGND pins should be shorted right at the LTC1553L. This helps to minimize internal ground disturbances in the LTC1553L and prevents differences in ground potential from disrupting internal circuit operation. This connection should then tie into the 17 LTC1553L U U W U APPLICATIONS INFORMATION ground plane at a single point, preferably at a fairly quiet point in the circuit such as close to the output capacitors. This is not always practical, however, due to physical constraints. Another reasonably good point to make this connection is between the output capacitors and the source connection of the low side FET Q2. Do not tie this single point ground in the trace run between the low side FET source and the input capacitor ground, as this area of the ground plane will be very noisy. capacitors shown at VCC and PVCC will help provide optimum regulation performance. 5. The (+) plate of CIN should be connected as close as possible to the drain of the upper MOSFET. An additional 1µF ceramic capacitor between VIN and power ground is recommended. 6. The SENSE pin is very sensitive to pickup from the switching node. Care should be taken to isolate SENSE from possible capacitive coupling to the inductor switching signal. A 0.1µF is required between the SENSE pin and the SGND pin next to the LTC1553L. 3. The small signal resistors and capacitors for frequency compensation and soft start should be located very close to their respective pins and the ground ends connected to the signal ground pin through a separate trace. Do not connect these parts to the ground plane! 7. OUTEN is a high impedance input and should be externally pulled up to a logic HIGH for normal operation. 4. The VCC and PVCC decoupling capacitors should be as close to the LTC1553L as possible. The 10µF bypass 8. Kelvin sense IMAX and IFB at Q1 drain and source pins. VIN + CIN Q1 LO 1 VOUT G2 LTC1553L G1 PVCC 2 + 0.1µF 10µF + COUT Q2 + 10µF 3 VID0 GND VID1 4 SGND 0.1µF VID2 5 6 RIMAX 7 RIFB 8 9 10 CSS BOLD LINES INDICATE HIGH CURRENT PATHS OUTEN PVCC C1 RC VCC VID3 SENSE IMAX IFB VID4 PWRGD SS COMP OT 19 18 17 16 15 14 VID0 VID1 5.6k VID2 5.6k VID3 5.6k VID4 13 12 11 1153L F10 0.1µF CC Figure 10. LTC1553L Layout Diagram 18 FAULT 20 LTC1553L U U W U APPLICATIONS INFORMATION VIN 5V + + 0.1µF 5.6k 5.6k 10µF 5.6k VCC PWRGD IMAX PVCC 0.1µF FAULT PENTIUM II SYSTEM 20Ω LTC1553L OUTEN G2 COMP 1.8k C1 150pF DALE NTHS-1206N02 MOUNT THERMISTER IN CLOSE THERMAL PROXIMITY TO Q1 SS SGND LO† 2µH 18A vOUT IFB VID0 TO VID4 5V Q1* G1 OT 5 CIN** 1200µF ×4 1N5817 2.7k GND COUT†† 330µF ×7 Q2* SENSE + RC 8.2k CC 0.01µF CSS 0.1µF 0.1µF *SILICONIX SUD50N03-10 **SANYO 10MV1200GX † COILTRONICS CTX02-13198 OR PANASONIC 12TS-2R5SP †† AVX TPSE337M006R0100 1553L F11 Figure 11. Single Supply LTC1553L 5V to 1.8V-3.5V Application with Thermal Monitor U PACKAGE DESCRIPTION Dimension in inches (millimeters) unless otherwise noted. G Package 20-Lead Plastic SSOP (0.209) (LTC DWG # 05-08-1640) 0.278 – 0.289* (7.07 – 7.33) 20 19 18 17 16 15 14 13 12 11 0.301 – 0.311 (7.65 – 7.90) 1 2 3 4 5 6 7 8 9 10 0.205 – 0.212** (5.20 – 5.38) 0.068 – 0.078 (1.73 – 1.99) 0° – 8° 0.005 – 0.009 (0.13 – 0.22) 0.022 – 0.037 (0.55 – 0.95) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.0256 (0.65) BSC 0.010 – 0.015 (0.25 – 0.38) Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 0.002 – 0.008 (0.05 – 0.21) G20 SSOP 0595 19 LTC1553L U PACKAGE DESCRIPTION Dimension in inches (millimeters) unless otherwise noted. SW Package 20-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620) 0.496 – 0.512* (12.598 – 13.005) 20 19 18 17 16 15 14 13 12 11 0.394 – 0.419 (10.007 – 10.643) NOTE 1 0.291 – 0.299** (7.391 – 7.595) 0.010 – 0.029 × 45° (0.254 – 0.737) 1 2 3 4 5 6 7 8 9 10 0.037 – 0.045 (0.940 – 1.143) 0.093 – 0.104 (2.362 – 2.642) 0° – 8° TYP 0.009 – 0.013 (0.229 – 0.330) NOTE 1 0.016 – 0.050 (0.406 – 1.270) 0.050 (1.270) TYP 0.004 – 0.012 (0.102 – 0.305) 0.014 – 0.019 (0.356 – 0.482) TYP S20 (WIDE) 0396 NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1142 Current Mode Dual Step-Down Switching Regulator Controller Dual Version of LTC1148 LTC1148 Current Mode Step-Down Switching Regulator Controller Synchronous, VIN ≤ 20V LTC1149 Current Mode Step-Down Switching Regulator Controller Synchronous, VIN ≤ 48V, for Standard Threshold FETs LTC1159 Current Mode Step-Down Switching Regulator Controller Synchronous, VIN ≤ 40V, for Logic Threshold FETs LTC1266 Current Mode Step-Up/Down Switching Regulator Controller Synchronous N- or P-Channel FETs, Comparator/Low-Battery Detector LTC1430 High Power Step-Down Switching Regulator Controller Synchronous N-Channel FETs, Voltage Mode LTC1435 High Efficiency Low Noise Synchronous Step-Down Switching Regulator Drive Synchronous N-Channel, VIN ≤ 36V LTC1438 Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator Dual LTC1435 with Power-On Reset LTC1553 5-Bit Programmable Synchronous Switching Regulator Controller for Pentium II Processor High Voltage Version of LTC1553L 20 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 ● (408) 432-1900 FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com 1553lf LT/TP 0198 4K • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 1998