CYPRESS CY62158EV30LL

CY62158EV30 MoBL®
8-Mbit (1024 K × 8) Static RAM
8-Mbit (1024 K × 8) Static RAM
Features
Functional Description
■
Very high speed: 45 ns
❐ Wide voltage range: 2.20 V–3.60 V
■
Pin compatible with CY62158DV30
■
Ultra low standby power
❐ Typical standby current: 2 A
❐ Maximum standby current: 8 A
■
Ultra low active power
❐ Typical active current: 1.8 mA at f = 1 MHz
■
Easy memory expansion with CE1, CE2, and OE features
■
Automatic power down when deselected
■
CMOS for optimum speed/power
■
Offered in Pb-free 48-ball VFBGA and 44-pin TSOP II
packages
The CY62158EV30 is a high performance CMOS static RAM
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption. Placing the device into standby mode reduces
power consumption significantly when deselected (CE1 HIGH or
CE2 LOW). The eight input and output pins (I/O0 through I/O7)
are placed in a high impedance state when the device is
deselected (CE1 HIGH or CE2 LOW), the outputs are disabled
(OE HIGH), or a write operation is in progress (CE1 LOW and
CE2 HIGH and WE LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A19).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and OE LOW while forcing the WE HIGH. Under these
conditions, the contents of the memory location specified by the
address pins appear on the I/O pins. See Truth Table on page 10
for a complete description of read and write modes.
Logic Block Diagram
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Cypress Semiconductor Corporation
Document #: 38-05578 Rev. *G
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 30, 2011
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CY62158EV30 MoBL®
Contents
Pin Configurations ...........................................................3
Product Portfolio ..............................................................3
Maximum Ratings .............................................................4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics .......................................6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ......................................................8
Read Cycle No. 1 (Address Transition Controlled) .....8
Read Cycle No. 2 (OE Controlled) ..............................8
Write Cycle No. 1 (WE Controlled) ..............................9
Document #: 38-05578 Rev. *G
Write Cycle No. 2 (CE1 or CE2 Controlled) .................9
Write Cycle No. 3 (WE Controlled, OE LOW) ............10
Truth Table ......................................................................10
Ordering Information ......................................................11
Ordering Code Definitions .........................................11
Package Diagrams ..........................................................12
Acronyms ........................................................................14
Document Conventions .................................................14
Units of Measure .......................................................14
Document History Page .................................................15
Sales, Solutions, and Legal Information ......................16
Worldwide Sales and Design Support .......................16
Products ....................................................................16
PSoC Solutions .........................................................16
Page 2 of 16
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CY62158EV30 MoBL®
Pin Configurations [1]
48-ball VFBGA
44-pin TSOP II
Top View
Top View
1
2
3
4
5
6
NC
OE
A0
A1
A2
CE2
A
NC
NC
A3
A4
CE1
NC
B
I/O0
NC
A5
A6
NC
I/O4
C
VSS
I/O1
A17
A7
I/O5
VCC
D
VCC
I/O2
NC
A16
I/O6
VSS
E
I/O3
NC
A14
A15
NC
I/O7
F
NC
NC
A12
A13
WE
NC
G
A11
A19
A18
A8
A9
A10
A4
A3
A2
A1
A0
CE1
NC
NC
I/O0
I/O1
VCC
VSS
I/O2
I/O3
NC
NC
WE
A19
A18
A17
A16
A15
H
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
37
36
35
34
33
32
31
30
29
28
27
13
14
15
16
17
18
19
20
21
22
26
25
24
23
A5
A6
A7
OE
CE2
A8
NC
NC
I/O7
I/O6
VSS
VCC
I/O5
I/O4
NC
NC
A9
A10
A11
A12
A13
A14
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62158EV30LL
Speed
(ns)
Min
Typ[2]
Max
2.2
3.0
3.6
45
Operating ICC (mA)
f = 1 MHz
Standby, ISB2 (μA)
f = fmax
Typ[2]
Max
Typ[2]
Max
Typ[2]
Max
1.8
3
18
25
2
8
Notes
1. NC pins are not connected on the die.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document #: 38-05578 Rev. *G
Page 3 of 16
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CY62158EV30 MoBL®
DC Input Voltage[3, 4] .................. –0.3 V to VCC(max) + 0.3 V
Maximum Ratings
Output Current into Outputs (LOW) ............................20 mA
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static Discharge Voltage ........................................> 2001 V
(MIL-STD-883, Method 3015)
Storage Temperature .............................. –65 °C to +150 °C
Latch up Current ....................................................> 200 mA
Ambient Temperature with
Power Applied ......................................... –55 °C to +125 °C
Operating Range
Supply Voltage to
Ground Potential ..........................–0.3 V to VCC(max) + 0.3 V
Product
Range
DC Voltage Applied to Outputs
in High Z State[3, 4] ..................... –0.3 V to VCC(max) + 0.3 V
CY62158EV30LL
Industrial
Ambient
Temperature
(TA)
VCC[5]
–40 °C to +85 °C 2.2 V–3.6 V
Electrical Characteristics
Over the Operating Range
Parameter
VOH
VOL
VIH
VIIL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
45 ns
Unit
Min
Typ[6]
Max
IOH = –0.1 mA
2.0
–
–
V
IOH = –1.0 mA, VCC > 2.70 V
2.4
–
–
V
IOL = 0.1 mA
–
–
0.4
V
IOL = 2.1 mA, VCC > 2.70 V
–
–
0.4
V
VCC = 2.2 V to 2.7 V
1.8
–
VCC + 0.3 V
V
VCC = 2.7 V to 3.6 V
2.2
–
VCC + 0.3 V
V
VCC = 2.2 V to 2.7 V
–0.3
–
0.6
V
VCC = 2.7 V to 3.6 V
–0.3
–
0.8
V
IIX
Input Leakage Current
GND < VI < VCC
–1
–
+1
A
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
–1
–
+1
A
ICC
VCC Operating Supply Current f = fmax = 1/tRC
–
18
25
mA
–
1.8
3
mA
f = 1 MHz
VCC = VCCmax
IOUT = 0 mA
CMOS levels
ISB1
Automatic CE Power down
Current — CMOS Inputs
CE1 > VCC – 0.2 V, CE2 < 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V,
f = fmax (Address and Data Only),
f = 0 (OE and WE), VCC = 3.60 V
–
2
8
A
ISB2[7]
Automatic CE Power down
Current — CMOS Inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–
2
8
A
Notes
3. VIL(min) = –2.0 V for pulse durations less than 20 ns.
4. VIH(max)= VCC + 0.75 V for pulse duration less than 20 ns.
5. Full device AC operation assumes a 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
6. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
7. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document #: 38-05578 Rev. *G
Page 4 of 16
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CY62158EV30 MoBL®
Capacitance
Parameter[8]
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max
Unit
10
pF
10
pF
Thermal Resistance
Parameter[8]
Description
JA
Thermal Resistance
(Junction to Ambient)
JC
Thermal Resistance
(Junction to Case)
Test Conditions
48-ball BGA 44-pin TSOP II Unit
72
76.88
C/W
8.86
13.52
C/W
Still Air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board
AC Test Loads and Waveforms
R1
ALL INPUT PULSES
VCC
VCC
OUTPUT
GND
30 pF
INCLUDING
JIG AND
SCOPE
R2
10%
90%
10%
90%
Fall time: 1 V/ns
Rise Time: 1 V/ns
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
RTH
VTH
Parameters
2.5 V
3.0 V
Unit
R1
16667
1103

R2
15385
1554

RTH
8000
645

VTH
1.20
1.75
V
Note
8. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05578 Rev. *G
Page 5 of 16
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CY62158EV30 MoBL®
Data Retention Characteristics
Over the Operating Range
Parameter
[10]
tCDR[11]
tR
Typ[9]
Max
Unit
1.5
–
–
V
–
2
5
A
Chip Deselect to Data Retention Time
0
–
–
ns
Operation Recovery Time
45
–
–
ns
Conditions
VCC for Data Retention
VDR
ICCDR
Min
Description
[12]
VCC = 1.5 V, CE1 > VCC 0.2 V
or CE2 < 0.2 V, VIN > VCC 0.2 V
or VIN < 0.2 V
Data Retention Current
Data Retention Waveform
VCC
VCC, min
tCDR
DATA RETENTI/ON MODE
VDR > 1.5 V
VCC, min
tR
CE1
or
CE2
Notes
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
10. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full Device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document #: 38-05578 Rev. *G
Page 6 of 16
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CY62158EV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter[13]
Description
45 ns
Unit
Min
Max
Read Cycle Time
45
–
ns
tAA
Address to Data Valid
–
45
ns
tOHA
Data Hold from Address Change
10
–
ns
tACE
CE1 LOW and CE2 HIGH to Data Valid
–
45
ns
tDOE
OE LOW to Data Valid
–
22
ns
5
–
ns
–
18
ns
10
–
ns
–
18
ns
ns
Read Cycle
tRC
Z[14]
tLZOE
OE LOW to Low
tHZOE
OE HIGH to High Z[14, 15]
tLZCE
CE1 LOW and CE2 HIGH to Low Z[14]
tHZCE
CE1 HIGH or CE2 LOW to High
Z[14, 15]
tPU
CE1 LOW and CE2 HIGH to Power Up
0
–
tPD
CE1 HIGH or CE2 LOW to Power Down
–
45
ns
45
–
ns
ns
Write Cycle[16]
tWC
Write Cycle Time
tSCE
CE1 LOW and CE2 HIGH to Write End
35
–
tAW
Address Setup to Write End
35
–
ns
tHA
Address Hold from Write End
0
–
ns
tSA
Address Setup to Write Start
0
–
ns
ns
tPWE
WE Pulse Width
35
–
tSD
Data Setup to Write End
25
–
ns
tHD
Data Hold from Write End
0
–
ns
WE LOW to High
Z[14, 15]
–
18
ns
WE HIGH to Low
Z[14]
10
–
ns
tHZWE
tLZWE
Notes
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 5.
14. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
15. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
16. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05578 Rev. *G
Page 7 of 16
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CY62158EV30 MoBL®
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[17, 18]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[18, 19]
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZCE
HIGH
IMPEDANCE
DATA VALID
tPD
tPU
50%
50%
ICC
ISB
Notes
17. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
18. WE is HIGH for read cycle.
19. Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.
Document #: 38-05578 Rev. *G
Page 8 of 16
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CY62158EV30 MoBL®
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[20, 21, 22]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
tPWE
WE
OE
tSD
DATA I/O
tHD
VALID DATA
NOTE 23
tHZOE
Write Cycle No. 2 (CE1 or CE2 Controlled)[20, 21, 22]
tWC
ADDRESS
tSCE
CE1
tSA
CE2
tAW
tHA
tPWE
WE
OE
tSD
DATA I/O
tHD
VALID DATA
Notes
20. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
21. Data I/O is high impedance if OE = VIH.
22. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
23. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 38-05578 Rev. *G
Page 9 of 16
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CY62158EV30 MoBL®
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[24]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tSA
tHA
tPWE
WE
tHD
tSD
DATA I/O
NOTE 25
VALID DATA
tLZWE
tHZWE
Truth Table
CE1
WE
OE
[26]
X
X
High Z
Deselect/Power down
Standby (ISB)
[26]
L
X
X
High Z
Deselect/Power down
Standby (ISB)
L
H
H
L
Data Out
Read
Active (ICC)
L
H
L
X
Data In
Write
Active (ICC)
L
H
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
H
X
CE2
X
Inputs/Outputs
Mode
Power
Notes
24. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.
25. During this period, the I/Os are in output state. Do not apply input signals.
26. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted.
Document #: 38-05578 Rev. *G
Page 10 of 16
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CY62158EV30 MoBL®
Ordering Information
Speed
(ns)
45
Ordering Code
Package
Diagram
Package Type
CY62158EV30LL-45BVXI
51-85150 48-ball Very Fine-Pitch Ball Grid Array (Pb-free)
CY62158EV30LL-45ZSXI
51-85087 44-pin Thin Small Outline Package Type II (Pb-free)
Operating
Range
Industrial
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
CY 621 5
8
E V30 LL - 45 XX X
I
Temperature Grade: I = Industrial
Pb-free
Package Type: XX = BV or ZS
BV = 48-ball VFBGA
ZS = 44-pin TSOP II
Speed Grade = 45 ns
LL = Low Power
Voltage Range = 3 V typical
E = Process Technology 90 nm
Buswidth = × 8
Density = 8-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Document #: 38-05578 Rev. *G
Page 11 of 16
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CY62158EV30 MoBL®
Package Diagrams
Figure 1. 48-ball VFBGA (6 × 8 × 1 mm) BV48/BZ48, 51-85150
51-85150 *F
Document #: 38-05578 Rev. *G
Page 12 of 16
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CY62158EV30 MoBL®
Package Diagrams (continued)
Figure 2. 44-pin TSOP Z44-II, 51-85087
51-85087 *C
Document #: 38-05578 Rev. *G
Page 13 of 16
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CY62158EV30 MoBL®
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
chip enable
CMOS
complementary metal oxide semiconductor
°C
degree Celcius
I/O
input/output
MHz
Mega Hertz
OE
output enable
μA
micro Amperes
RAM
random access memory
μs
micro seconds
SRAM
static random access memory
mA
milli Amperes
TTL
transistor-transistor logic
mm
milli meter
TSOP
thin small outline package
ns
nano seconds
VFBGA
very fine-pitch ball grid array

ohms
WE
write enable
%
percent
pF
pico Farad
V
Volts
W
Watts
Document #: 38-05578 Rev. *G
Symbol
Unit of Measure
Page 14 of 16
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CY62158EV30 MoBL®
Document History Page
Document Title: CY62158EV30 MoBL®, 8-Mbit (1024 K × 8) Static RAM
Document Number: 38-05578
Rev.
ECN No.
Issue Date
Orig. of
Change
**
270329
See ECN
PCI
New Data Sheet
*A
291271
See ECN
SYT
Converted from Advance Information to Preliminary
Changed ICCDR from 4 to 4.5 A
*B
444306
See ECN
NXR
Converted from Preliminary to Final.
Removed 35 ns speed bin
Removed “L” bin.
Removed 44 pin TSOP II package
Included 48 pin TSOP I package
Changed the ICC Typ value from 16 mA to 18 mA and ICC max value from 28 mA
to 25 mA for test condition f = fax = 1/tRC.
Changed the ICC max value from 2.3 mA to 3 mA for test condition f = 1MHz.
Changed the ISB1 and ISB2 max value from 4.5 A to 8 A and Typ value from 0.9
A to 2 A respectively.
Updated Thermal Resistance table
Changed Test Load Capacitance from 50 pF to 30 pF.
Added Typ value for ICCDR .
Changed the ICCDR max value from 4.5 A to 5 A
Corrected tR in Data Retention Characteristics from 100 s to tRC ns
Changed tLZOE from 3 to 5
Changed tLZCE from 6 to 10
Changed tHZCE from 22 to 18
Changed tPWE from 30 to 35
Changed tSD from 22 to 25
Changed tLZWE from 6 to 10
Updated the ordering Information and replaced the Package Name column with
Package Diagram.
*C
467052
See ECN
NXR
Included 44 pin TSOP II package in Product Offering.
Removed TSOP I package; Added reference to CY62157EV30 TSOP I
Updated the ordering Information table
*D
1015643
See ECN
VKN
Added footnote #8 related to ISB2 and ICCDR
*E
2934396
06/03/10
VKN
Added footnote #21 related to chip enable
Updated package diagrams
Updated template
*F
3110202
12/14/2010
PRAS
Updated Logic Block Diagram and Package Diagram.
Added Ordering Code Definitions.
*G
3269641
05/30/2011
RAME
Updated Features.
Removed the note “For best practice recommendations, refer to the Cypress
application note “System Design Guidelines” at http://www.cypress.com.” and its
reference in Functional Description.
Updated Data Retention Characteristics.
Added Acronyms and Units of Measure.
Updated in new template.
Document #: 38-05578 Rev. *G
Description of Change
Page 15 of 16
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CY62158EV30 MoBL®
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05578 Rev. *G
Revised May 30, 2011
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All products and company names mentioned in this document may be the trademarks of their respective holders.
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