CYPRESS CY62137EV30

CY62137EV30 MoBL®
2-Mbit (128K x 16) Static RAM
Features
Functional Description
■
Very high speed: 45 ns
■
Wide voltage range: 2.20 V to 3.60 V
■
Pin compatible with CY62137CV30
■
Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A
■
Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power-down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Byte power-down feature
■
Offered in Pb-free 48-ball very fine ball grid array (VFBGA)
and 44-pin thin small outline package (TSOPII) package
The CY62137EV30[1] is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption when deselected (CE HIGH or
both BLE and BHE are HIGH). The input and output pins (I/O0
through I/O15) are placed in a high impedance state when:
deselected (CE HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE
LOW).
Writing to the device is accomplished by asserting Chip
Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through
I/O7), is written into the location specified on the address pins
(A0 through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
Reading from the device is accomplished by asserting Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory appears on I/O8 to I/O15. See
the Truth Table on page 10 for a complete description of read
and write modes.
The CY62137EV30 is available in 48-ball VFBGA and 44-pin
TSOPII packages.
Logic Block Diagram
ROW DECODER
128K x 16
RAM Array
SENSE AMPS
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O0 – I/O7
I/O8 – I/O15
COLUMN DECODER
BHE
WE
CE
OE
BLE
BHE
BLE
A13
A14
A15
A16
A11
CE
A12
Power -Down
Circuit
Note
1. For best practice recommendations, refer to the Cypress application note “SRAM System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05443 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 17, 2011
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CY62137EV30 MoBL®
Contents
Pin Configurations ............................................................ 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
Data Retention Characteristics ....................................... 5
Data Retention Waveform................................................. 5
Switching Characteristics ................................................ 6
Switching Waveforms ...................................................... 7
Truth Table ...................................................................... 10
Document #: 38-05443 Rev. *D
Ordering Information ...................................................... 11
Ordering Code Definition ........................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Page 2 of 15
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CY62137EV30 MoBL®
Pin Configurations[2, 3]
VFBGA (Top View)
44 TSOP II (Top View)
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
D
E
VSS
I/O11
NC
A7
I/O3
Vcc
VCC
I/O12
NC
A16
I/O4
Vss
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
NC
A8
A9
A10
A11
NC
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
H
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
37
36
35
34
33
32
31
30
29
28
27
13
14
15
16
17
18
19
20
21
22
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
Product Portfolio
Product
CY62137EV30-45LL
Speed
(ns)
VCC Range (V)
Min
Typ[4]
Max
2.2 V
3.0 V
3.6 V
45 ns
Power Dissipation
Operating ICC (mA)
f = 1 MHz
f = fmax
Standby ISB2 (A)
Typ[4]
Max
Typ[4]
Max
Typ[4]
Max
2
2.5
15
20
1
7
Notes
2. NC pins are not connected on the die.
3. Pins D3, H1, G2, H6 and H3 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb and 64 Mb respectively
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C
Document #: 38-05443 Rev. *D
Page 3 of 15
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CY62137EV30 MoBL®
Maximum Ratings
DC input voltage[5, 6] ...................–0.3 V to (VCC(MAX) + 0.3 V)
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied ......................................... –55 °C to + 125 °C
Supply voltage to ground
potential ....................................–0.3 V to (VCC(MAX) + 0.3 V)
DC voltage applied to outputs
in High Z state[5, 6] ......................–0.3 V to (VCC(MAX) + 0.3 V)
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage ......................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch up current .................................................... > 200 mA
Operating Range
Device
Range
Ambient
Temperature
VCC[7]
CY62137EV30-45LL Industrial –40 °C to +85 °C 2.2 V to 3.6 V
Electrical Characteristics Over the Operating Range
Parameter
VOH
VOL
VIH
VIL
Description
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
45 ns
Test Conditions
Min
Typ[8]
Max
Unit
IOH = –0.1 mA
VCC = 2.20 V
2.0
–
–
V
IOH = –1.0 mA
VCC = 2.70 V
2.4
–
–
V
IOL = 0.1 mA
VCC = 2.20 V
–
–
0.4
V
IOL = 2.1 mA
VCC = 2.70 V
–
–
0.4
V
VCC = 2.2 V to 2.7 V
1.8
–
VCC + 0.3
V
VCC= 2.7 V to 3.6 V
2.2
–
VCC + 0.3
V
VCC = 2.2 V to 2.7 V
–0.3
–
0.6
V
VCC= 2.7 V to 3.6 V
–0.3
–
0.8
V
IIX
Input leakage current
GND < VI < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VO < VCC, Output disabled
–1
–
+1
A
ICC
VCC Operating supply
current
f = fmax = 1/tRC
–
15
20
mA
–
2.0
2.5
f = 1 MHz
VCC = VCCmax
IOUT = 0 mA
CMOS levels
ISB1[9]
Automatic CE
power-down current —
CMOS inputs
CE > VCC –0.2 V or (BHE and BLE) > VCC –0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V),,
f = fmax (address and data only), f = 0 (OE and WE),
VCC = 3.60 V
–
1
7
A
ISB2 [9]
Automatic CE
power-down current —
CMOS inputs
CE > VCC – 0.2 V or (BHE and BLE) > VCC –0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–
1
7
A
Notes
5. VIL(min.) = –2.0 V for pulse durations less than 20 ns.
6. VIH(max)=VCC+0.75 V for pulse durations less than 20 ns.
7. Full device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after VCC stabilization.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C.
9. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
Document #: 38-05443 Rev. *D
Page 4 of 15
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CY62137EV30 MoBL®
Capacitance
Parameter[10]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
TA = 25 °C, f = 1 MHz,
VCC = VCC(typ)
Unit
10
pF
10
pF
Thermal Resistance
Parameter[10]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
BGA
TSOP II
Unit
Still air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
75
77
C / W
10
13
C / W
Figure 1. AC Test Loads and Waveforms
R1
VCC
OUTPUT
30 pF
VCC
R2
10%
GND
Rise Time = 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THÉVENIN EQUIVALENT
RTH
OUTPUT
V
INCLUDING
JIG AND
SCOPE
Parameters
2.50 V
3.0 V
Unit
R1
R2
16667
1103

15385
1554

RTH
VTH
8000
645

1.20
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Conditions
VCC for data retention
VDR
ICCDR
Description
[12]
Data retention current
VCC= 1V ,
CE > VCC – 0.2 V or (BHE and BLE) > VCC –0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
Min
Typ[11]
Max
Unit
1
–
–
V
–
0.8
3
A
tCDR[10]
Chip deselect to data
retention time
0
–
–
ns
tR[13]
Operation recovery time
45
–
–
ns
Data Retention Waveform[14]
VCC
CE or
BHE.BLE
VCC(min)
tCDR
DATA RETENTION MODE
VDR > 1.5 V
VCC(min)
tR
Notes
10. Tested initially and after any design or process changes that may affect these parameters.
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C
12. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR specification. Other inputs can be left floating.
13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s.
14. BHE.BLE is the AND of both BHE and BLE. The chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
Document #: 38-05443 Rev. *D
Page 5 of 15
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CY62137EV30 MoBL®
Switching Characteristics
Over the Operating Range
Parameter[15, 16]
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
45
–
ns
tAA
Address to data valid
–
45
ns
tOHA
Data hold from address change
10
–
ns
tACE
CE LOW to data valid
–
45
ns
tDOE
OE LOW to data valid
–
22
ns
tLZOE
OE LOW to LOW Z
5
–
ns
tHZOE
OE HIGH to High Z
–
18
ns
tLZCE
CE LOW to Low Z[17]
10
–
ns
tHZCE
CE HIGH to High Z
–
18
ns
[17]
[17, 18]
[17, 18]
tPU
CE LOW to power-up
0
–
ns
tPD
CE HIGH to power-down
–
45
ns
tDBE
BLE/BHE LOW to data valid
–
45
ns
tLZBE
BLE/BHE LOW to Low Z
5
–
ns
tHZBE
BLE/BHE HIGH to HIGH Z[17, 18]
–
18
ns
tWC
Write cycle time
45
–
ns
[17]
Write Cycle[19]
tSCE
CE LOW to write end
35
–
ns
tAW
Address setup to write end
35
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
35
–
ns
tBW
BLE/BHE LOW to write end
35
–
ns
tSD
Data setup to write end
25
–
ns
tHD
Data hold from write end
0
–
ns
tHZWE
WE LOW to High-Z
–
18
ns
tLZWE
WE HIGH to Low-Z
10
–
ns
[17, 18]
[17]
Notes
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms.
16. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Refer application note, AN13842 for more information.
17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given
device.
18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and BLE = VIL. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05443 Rev. *D
Page 6 of 15
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CY62137EV30 MoBL®
Switching Waveforms
Figure 2. Read Cycle 1: Address Transition Controlled [20, 21]
tRC
ADDRESS
tOHA
DATA OUT
tAA
DATA VALID
PREVIOUS DATA VALID
Figure 3. Read Cycle No. 2: OE Controlled [21, 22]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
BHE/BLE
tLZOE
tHZBE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
50%
50%
ICC
ISB
Notes
20. The device is continuously selected. OE, CE = VIL, BHE and BLE = VIL.
21. WE is HIGH for read cycle.
22. Address valid prior to or coincident with CE and BHE, BLE transition LOW.
Document #: 38-05443 Rev. *D
Page 7 of 15
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CY62137EV30 MoBL®
Switching Waveforms (continued)
Figure 4. Write Cycle No. 1: WE Controlled [23, 24, 25]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tSD
DATA I/O
NOTE 26
tHD
DATAIN
tHZOE
Figure 5. Write Cycle No. 2: CE Controlled [23, 24, 25]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 26
tHZOE
Notes
23. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and BLE = VIL. All signals must be ACTIVE to initiate a write and any of
these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write
24. Data I/O is high impedance if OE = VIH.
25. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
26. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05443 Rev. *D
Page 8 of 15
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CY62137EV30 MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No. 3: WE Controlled, OE LOW [27]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATAI/O
NOTE 28
tHD
DATAIN
tHZWE
tLZWE
Figure 7. Write Cycle No. 4: BHE/BLE Controlled, OE LOW [27]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 28
tSD
tHD
DATAIN
tLZWE
Notes
27. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
28. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05443 Rev. *D
Page 9 of 15
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CY62137EV30 MoBL®
Truth Table
CE
WE
OE
H
BHE
BLE
X
X
Power
High Z
Deselect/power-down
Standby (ISB)
Data out (I/OO–I/O15)
Read
Active (ICC)
Data out (I/OO–I/O7);
I/O8–I/O15 in High Z
Read
Active (ICC)
H
Data out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
L
High Z
Output disabled
Active (ICC)
H
L
High Z
Output disabled
Active (ICC)
L
H
High Z
Output disabled
Active (ICC)
X
L
L
Data in (I/OO–I/O15)
Write
Active (ICC)
L
X
H
L
Data in (I/OO–I/O7);
I/O8–I/O15 in High Z
Write
Active (ICC)
L
X
L
H
Data in (I/O8–I/O15);
I/O0–I/O7 in High Z
Write
Active (ICC)
X
X
H
H
L
H
L
L
L
L
H
L
H
L
L
H
L
L
L
H
H
L
H
H
L
H
H
L
L
L
L
[29]
High Z
Mode
Standby (ISB)
X
X
Inputs/Outputs
Deselect/power-down
X
[29]
[29]
Note
29. Chip enable (CE) and Byte enables (BHE / BLE) must be at fixed CMOS levels (not floating). Intermediate voltage levels on these pins is not permitted
Document #: 38-05443 Rev. *D
Page 10 of 15
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CY62137EV30 MoBL®
Ordering Information
Speed
(ns)
Package
Diagram
Ordering Code
Package Type
45
CY62137EV30LL-45BVXI
51-85150 48-Ball Very Fine Pitch BGA (6 mm × 8mm × 1 mm) (Pb-free)
45
CY62137EV30LL-45ZSXI
51-85087 44-Pin TSOP II (Pb-free)
Operating
Range
Industrial
Ordering Code Definition
CY
621
3
7E
V30
LL
45
XXX
X
Temperature Grades
I = Industrial
Package Type BVX: VFBGA (Pb-free)
ZSX : TSOP II (Pb-free)
Speed Grade
Low Power
Voltage Range = 3 V typical
Bus Width = x16
E = 90nm Technology
Density = 2 Mbit
MoBL SRAM Family
Company ID: CY = Cypress
Document #: 38-05443 Rev. *D
Page 11 of 15
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CY62137EV30 MoBL®
Package Diagrams
Figure 8. 48-Pin VFBGA (6 x 8 x 1 mm) (51-85150)
51-85150-*F
Document #: 38-05443 Rev. *D
Page 12 of 15
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CY62137EV30 MoBL®
Package Diagrams (continued)
Figure 9. 44-Pin TSOP II (51-85087)
51-85087-*C
Acronyms
Document Conventions
Description
Units of Measure
CMOS
complementary metal oxide semiconductor
Symbol
I/O
input/output
SRAM
Acronym
Unit of Measure
°C
degrees Celsius
static random access memory
A
microamperes
VFBGA
very fine ball gird array
mA
milliampere
TSOP
thin small outline package
MHz
megahertz
Document #: 38-05443 Rev. *D
ns
nanoseconds
pF
picofarads
V
volts

ohms
W
watts
Page 13 of 15
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CY62137EV30 MoBL®
Document History Page
Document Title: CY62137EV30 MoBL® 2-Mbit (128K x 16) Static RAM
Document Number: 38-05443
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
203720
AJU
See ECN
New Data Sheet
*A
234196
AJU
See ECN
Changed ICC MAX at f=1MHz from 1.7 mA to 2.0 mA
Changed ICC TYP from 12 mA (35 ns speed bin) and 10 mA (45 ns speed
bin) to 15 mA and 12 mA respectively
Changed ICC MAX from 20 mA (35 ns speed bin) and 15 mA (45 ns speed
bin) to 25 mA and 20 mA respectively
Changed ISB1 and ISB2 TYP from 0.6 A to 0.7 A
Changed ISB1 and ISB2 MAX from 1.5 A to 2.5 A
Changed ICCDR from 1 A to 2 A
Fixed typos on TSOP II pinout:
Pin 18-22: address lines
Pin 23: NC
Added Pb-free information
*B
427817
NXR
See ECN
Converted from Advanced Information to Final.
Removed 35 ns Speed Bin
Removed “L” version
Changed ball E3 from DNU to NC.
Removed the redundant footnote on DNU.
Moved Product Portfolio from Page # 3 to Page #2.
Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from
1.5 mA to 2 mA at f=1 MHz
Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax=1/tRC
Changed ISB1 and ISB2 Typ. values from 0.7 A to 1 A and Max. values from
2.5 A to 7 A.
Changed VCC stabilization time in footnote #7 from 100 s to 200 s
Changed the AC test load capacitance from 50pF to 30pF on Page# 4
Changed VDR from 1.5V to 1V on Page# 4.
Changed ICCDR from 2 A to 3 A.
Added ICCDR typical value.
Corrected tR in Data Retention Characteristics from 100 s to tRC ns
Changed tOHA , tLZCE and tLZWE from 6 ns to 10 ns
Changed tLZBE from 6 ns to 5 ns
Changed tLZOE from 3 ns to 5 ns
Changed tHZOE, tHZCE, tHZBE and tHZWE from 15 ns to 18 ns
Changed tSCE,tAW and tBW from 40 ns to 35 ns
Changed tPWE from 30 ns to 35 ns
Changed tSD from 20 ns to 25 ns
Updated the Ordering Information table and replaced the Package Name
column with Package Diagram.
*C
2604685
VKN/PYRS
11/12/08
Added footnote 8 related to ISB2 and ICCDR
Added footnote 13 related to AC timing parameters
*D
3143896
RAME
01/17/2011
Added Acronyms and Units of Measure table
Added Ordering Code Definition
Added TOC
Converted all tablenote to footnotes
Updated Package Diagrams 51-85150 from *D to *F
Document #: 38-05443 Rev. *D
Description of Change
Page 14 of 15
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CY62137EV30 MoBL®
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© Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
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Document #: 38-05443 Rev. *D
Revised January 17, 2011
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