LTC4280 Hot Swap Controller with 2 I C Compatible Monitoring FEATURES DESCRIPTION n The LTC®4280 Hot Swap™ controller allows a board to be safely inserted and removed from a live backplane. Using an external N-channel pass transistor, board supply voltage and inrush current are ramped up at an adjustable rate. An I2C interface and onboard ADC allow for monitoring of load current, voltage and fault status. n n n n n n n n n n n Allows Safe Insertion into Live Backplane 8-Bit ADC Monitors Current and Voltage I2C/SMBus Interface Wide Operating Voltage Range: 2.9V to 15V Adjustable Overcurrent Filter Time High Side Drive for External N-Channel MOSFET No External Gate Capacitor Required Input Overvoltage/Undervoltage Protection Optional Latchoff or Auto-Retry After Faults Alerts Host After Faults Inrush Current Limit with Foldback Available in 24-Pin 4mm × 5mm QFN Package The device features adjustable analog foldback current limit and a FILTER pin which configures the time spent in overcurrent before declaring a fault. An I2C interface may configure the part to latch off or automatically restart after the LTC4280 detects a current limit fault. The controller has additional features to interrupt the host when a fault has occurred, notify when output power is good, detect insertion of a load card, and power-up either automatically upon insertion or wait for an I2C command to turn on. APPLICATIONS n n n n Live Board Insertion Electronic Circuit Breakers Computers, Servers Platform Management L, LT, LTC, LTM, Linear Technology, the Linear logo and Hot Swap are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 12V Application with 5A Circuit Breaker 0.005Ω Start-Up Waveform FDC653N 12V VOUT 12V + CONNECTOR 1 CONNECTOR 2 0.1μF CL 34.8k VDD 10V/DIV 10Ω CONTACT BOUNCE 3.57k 1.18k P6KE16A 3.4k SDA SCL ALERT 30.1k INTVCC UV VDD OV SDAO SDAI SCL ALERT SENSE+ SENSE– GATE SOURCE INTVCC ON TIMER FILTER INRUSH CURRENT 2.5A/DIV FB EN INTVCC LTC4280 ADIN 24k GPIO VOUT 10V/DIV VGPIO (POWERGOOD) 10V/DIV GND 4280 TA02 0.1μF GND CL = 12000μF 47nF 50ms/DIV 4280 TA01 BACKPLANE PLUG-IN CARD 4280f 1 LTC4280 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1, 2) SOURCE GATE SENSE– SENSE+ VDD TOP VIEW 24 23 22 21 20 UV 1 19 FB OV 2 18 GPIO FILTER 3 17 INTVCC 25 GND 4 16 TIMER ON 5 15 ADIN EN 6 14 ADR2 13 ADR1 NC ADR0 9 10 11 12 ALERT 8 SCL SDAO 7 SDAI Supply Voltage (VDD) ................................. –0.3V to 24V Supply Voltage (INTVCC) ........................... –0.3V to 6.5V Input Voltages GATE-SOURCE (Note 3) ........................... –0.3V to 5V SENSE+, SENSE– ................ VDD – 0.3V to VDD + 0.3V SOURCE.................................................... –5V to 24V EN, FB, ON, OV, UV ................................ –0.3V to 12V ADR0, ADR1, ADR2, TIMER, ADIN, FILTER .........................–0.3V to INTVCC + 0.3V ALERT SCL, SDA, SDAI, SDAO ............. –0.3V to 6.5V Output Voltages GATE, GPIO............................................ –0.3V to 24V Operating Temperature Range LTC4280C ................................................ 0°C to 70°C LTC4280I..............................................–40°C to 85°C Storage Temperature Range SSOP .................................................–65°C to 150°C QFN....................................................–65°C to 125°C Lead Temperature (Soldering, 10 sec) SSOP ................................................................ 300°C UFD PACKAGE 24-LEAD (4mm s 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 25) NOT GUARANTEED LOW IMPEDANCE TO GND, ELECTRICAL CONNECTION OPTIONAL ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4280CUFD#PBF LTC4280CUFD#TRPBF 4280 24-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C LTC4280IUFD#PBF LTC4280IUFD#TRPBF 4280 24-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4280CUFD LTC4280CUFD#TR 4280 24-Lead (4mm × 5mm) Plastic QFN 0°C to 70°C LTC4280IUFD LTC4280IUFD#TR 4280 24-Lead (4mm × 5mm) Plastic QFN –40°C to 85°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 4280f 2 LTC4280 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supplies VDD Input Supply Range l 2.9 15 VOV(VDD) Input Supply Overvoltage Threshold l IDD Input Supply Current l VDD(UVL) Input Supply Undervoltage Lockout VDD(HYST) Input Supply Undervoltage Lockout Hysteresis INTVCC Internal Regulator Voltage INTVCC(UVL) INTVCC Undervoltage Lockout INTVCC(HYST) INTVCC Undervoltage Lockout Hysteresis 15 15.6 16.5 3 5 V V mA l 2.75 2.84 2.89 V l 75 100 125 mV VDD ≥ 3.3V l 2.9 3.1 3.4 V INTVCC Rising l 2.55 2.64 2.79 l 20 55 75 mV l 22.5 25 27.5 mV VDD Rising V Current Limit and Circuit Breaker ΔVSENSE(TH) Circuit Breaker Threshold (VDD – VSENSE) ΔVSENSE Current Limit Voltage (VDD – VSENSE) VFB = 1.3V VFB = 0V l l 22.5 7 26 10 29.5 13.5 mV mV ISENSE(IN) SENSE +/– Input Current VSENSE = 12V l 10 20 35 μA V Gate Drive ΔVGATE External N-Channel Gate Drive (VGATE – VSOURCE) VDD = 2.9V to 15V (Note 3) l 4.7 5.9 6.5 IGATE(UP) External N-Channel Gate Pull-Up Current Gate On, VGATE = 0V l –15 –20 –30 μA IGATE(DN)SLOW External N-Channel Gate Pulldown Current Gate Off, VGATE = 15V l 0.8 1 1.6 mA IGATE(DN)FAST Pulldown Current From GATE to SOURCE During OC/UVLO VDD – SENSE = 100mV, VGS = 4V l 300 450 700 mA tPHL(SENSE) (VDD – SENSE) High to GATE Low VDD – SENSE = 100mV, CGS = 10nF l 0.5 1 μs VGS(POWERBAD) Gate-Source Voltage for Power Bad Fault VSOURCE = 2.9V – 15V l 3.8 4.3 4.7 V VON Rising l 1.210 1.235 1.26 V l 60 128 180 mV 0 ±1 μA V Comparator Inputs VON(TH) ON Pin Threshold Voltage ΔVON(HYST) ON Pin Hysteresis ION(IN) ON Pin Input Current VON = 1.2V l VEN(TH) EN Input Threshold VEN = Rising l 1.215 1.235 1.255 ΔVEN(HYST) EN Hysteresis l 50 128 200 mV IEN EN Pin Input Current EN = 3.5V l 0 ±1 μA VOV(TH) OV Pin Threshold Voltage VOV Rising l 1.215 1.235 1.255 V ΔVOV(HYST) OV Pin Hysteresis l 10 30 40 mV IOV(IN) OV Pin Input Current VOV = 1.8V l 0 ±1 μA VUV(TH) UV Pin Threshold Voltage VUV Rising l 1.215 1.235 1.255 V ΔVUV(HYST) UV Pin Hysteresis l 60 80 100 mV IUV(IN) UV Pin Input Current VUV = 1.8V l 0 ±1 μA VUV Falling l 0.33 0.4 0.47 V l 60 125 210 mV l 1.215 1.235 1.255 l 3 8 15 mV 0 ±1 μA 1 1.2 V VUV(RTH) UV Pin Reset Threshold Voltage ΔVUV(RHYST) UV Pin Reset Threshold Hysteresis VFB Foldback Pin Power Good Threshold FB Rising ΔVFB(HYST) FB Pin Power Good Hysteresis IFB Foldback Pin Input Current FB = 1.8V l VGPIO(TH) GPIO Pin Input Threshold VGPIO Rising l 0.8 V 4280f 3 LTC4280 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.25 0.5 V Other Pin Functions VGPIO(OL) GPIO Pin Output Low Voltage IGPIO = 5mA l IGPIO(OH) GPIO Pin Input Leakage Current VGPIO = 15V l ISOURCE SOURCE Pin Input Current SOURCE = 15V l tP(GATE) Input (ON, OV, UV, EN) to GATE Off Propagation Delay tD(GATE) Turn-On Delay 40 l ON UV, OV, EN Overcurrent Auto-Retry l l l 50 2.5 0 ±1 μA 80 120 μA 3 5 μs 1 100 5 2 150 75 μs ms s VTIMERL(TH) Timer Low Threshold l 0.17 0.2 0.23 V VTIMERH(TH) Timer High Threshold l 1.2 1.235 1.26 V ITIMER(UP) TIMER Pin Pull-Up Current l –80 –100 –120 μA ITIMER(DOWN) TIMER Pin Pulldown Current for OC Auto-Retry l 1.4 2 2.6 μA l 40 50 60 ITIMER(UP/DOWN) TIMER Current Up/Down Ratio VFILTER(TH) FILTER High Threshold IFILTER FILTER Timer Current l 1.2 1.235 1.27 V During OC FILTER = 0.5V l –7.5 –10 –12.5 μA After OC FILTER = 0.5V l 1 2 3.5 μA During Startup FILTER = 0.5V l .03 0.6 1.2 mA 0.5 0.2 0.2 2 1.25 1.25 LSB LSB LSB ADC RES Resolution (No Missing Codes) l 8 INL Integral Nonlinearity VDD – SENSE (Note 5) SOURCE ADIN l l l –2 –1.25 –1.25 VOS Offset Error (Note 4) VDD – SENSE SOURCE ADIN l l l ±2.0 ±1.0 ±1.0 LSB LSB LSB TUE Total Unadjusted Error VDD – SENSE SOURCE ADIN l l l ±5.5 ±5.0 ±5.0 LSB LSB LSB FSE Full-Scale Error VDD – SENSE SOURCE ADIN l l l ±5.5 ±5.0 ±5.0 LSB LSB LSB VFS Full-Scale Voltage (255 • VLSB) VDD – SENSE SOURCE ADIN l l l 37.625 15.14 1.205 38.45 15.44 1.23 39.275 15.74 1.255 mV V V RADIN ADIN Pin Sampling Resistance VADIN = 1.28V l 1 2 VADIN = 1.28V l IADIN ADIN Pin Input Current Conversion Rate Bits 0 10 MΩ ±0.1 μA Hz 4280f 4 LTC4280 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS INTVCC –0.8 INTVCC –0.4 INTVCC –0.2 V –3 μA μA 0.8 V I2C Interface VADR(H) ADR0, ADR1, ADR2 Input High Voltage IADR(IN,Z) ADR0, ADR1, ADR2 Hi-Z Input Current VADR(L) l l l 3 ADR0, ADR1, ADR2 Input Low Voltage l 0.2 –80 ADR0, ADR1, ADR2 = 0.8V ADR0, ADR1, ADR2 = INTVCC – 0.8V IADR(IN) ADR0, ADR1, ADR2 Input Current ADR0, ADR1, ADR2 = 0V, INTVCC l IALERT ALERT Input Current ALERT = 6.5V l VALERT(OL) ALERT Output Low Voltage IALERT = 3mA l VSDA,SCL(TH) SDA, SCL Input Threshold ISDA,SCL(OH) SDA, SCL Input Current SCL, SDA = 6.5V l VSDA(OL) SDA Output Low Voltage ISDA = 3mA l Operates with fSCL ≤ fSCL(MAX) l l 1.3 0.4 80 μA ±1 μA 0.2 0.4 V 1.7 1.9 V ±1 μA 0.4 V 0.2 I2C Interface Timing fSCL(MAX) SCL Clock Frequency tBUF(MIN) Bus Free Time Between Stop/Start Condition l 0.12 1.3 μs tHD,STA(MIN) Hold Time After (Repeated) Start Condition l 30 600 ns tSU,STA(MIN) Repeated Start Condition Set-Up Time l 30 600 ns tSU,STO(MIN) Stop Condition Set-Up Time l 140 600 ns tHD,DAT(MIN) Data Hold Time (Input) l 30 100 ns tHD,DATO Data Hold Time (Output) l tSU,DAT(MIN) Data Set-Up Time l tSP Suppressed Spike Pulse Width CX SCL, SDA Input Capacitance l SDAI Tied to SDAO (Note 6) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive; all voltages are referenced to GND unless otherwise specified. Note 3: An internal clamp limits the GATE pin to a minimum of 5V above SOURCE. Driving this pin to voltages beyond the clamp may damage the device. l 400 300 50 1000 kHz 500 900 ns 30 600 ns 110 250 ns 10 pF Note 4: Offset error is the offset voltage measured from 1LSB when the output code flickers between 0000 0000 and 0000 0001. Note 5: Integral nonlinearity is defined as the deviation of a code from a precise analog input voltage. Maximum specifications are limited by the LSB step size and the single shot measurement. Typical specifications are measured from the 1/4, 1/2 and 3/4 areas of the quantization band. Note 6: Guaranteed by design and not subject to test. 4280f 5 LTC4280 TYPICAL PERFORMANCE CHARACTERISTICS IDD vs VDD TA = 25°C, VDD = 12V unless otherwise noted INTVCC vs VDD INTVCC vs ILOAD 4.0 4 4 VDD = 12V, 5V 3 3 VDD = 3.3V 2 VCC (V) VDD (V) IDD (mA) 3.5 2 3.0 1 1 2.5 0 0 15 10 VDD (V) 5 20 25 0 3.0 2.5 3.5 VTH(UV) vs Temperature 1.234 ITIMER vs Temperature 90 110 85 105 ITIMER (μA) VHYST(UV) (mV) VTH (UV) RISING (V) 1.238 80 –25 50 25 0 TEMPERATURE (°C) 70 –50 100 75 –25 50 25 0 TEMPERATURE (°C) 75 4280 G04 15 10 5 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VFB (V) 75 26 25 100 100 VDD = 5V, 12V TPHL V(GATE) (μs) CIRCUIT BREAKER THRESHOLD (mV) 20 50 25 0 TEMPERATURE (°C) TPHL(GATE) vs Sense Voltage VTH Circuit Breaker vs Temperature 25 –25 4280 G06 27 30 ILIM (mV) 90 –50 100 4280 G05 Current Limit vs VFB 0 100 95 75 1.232 10 4280 G03 VHYST(UV) vs Temperature 1.236 8 4280 G02 1.240 1.230 –50 6 4 ILOAD (mA) 2 INTVCC (V) 4280 G01 0 0 4.0 VDD = 3.3V 24 10 1 23 22 –50 –25 50 25 0 TEMPERATURE (°C) 75 100 0.1 0 25 50 75 100 125 V(SENSE+) – V(SENSE–) (mV) 150 4280 G09 4280 G07 4280 G08 4280f 6 LTC4280 TYPICAL PERFORMANCE CHARACTERISTICS ΔVGATE vs Temperature ΔVGATE vs IGATE 6.1 IGATE Pull-Up vs Temperature –30 7 VDD = 5V –25 5 $VGATE (V) 5.9 VDD = 5V 6 VDD = 12V 5.8 5.7 VDD = 12V IGATE (μA) 6.0 $VGATE(SOURCE) (V) TA = 25°C, VDD = 12V unless otherwise noted 4 VDD = 3.3V 3 –20 VDD = 3.3V 5.6 2 5.5 1 5.4 –50 –15 0 –25 0 25 50 100 75 5 0 10 TEMPERATURE (°C) 15 –10 –50 25 20 50 25 0 TEMPERATURE (°C) –25 IGATE (μA) 4280 G10 75 4280 G11 4280 G12 Total Unadjusted Error vs Code (ADIN) VOL(GPIO) vs IGPIO 0.6 0.006 0.5 0.005 100 ADC INL vs Code (ADIN) 0.5 VDD = 3.3V, 5V, 12V 0.3 0.3 0.2 0.004 INL (LSB) ERROR (mV) 0.4 0.003 0.2 0.002 0.1 0.001 0 0 0.1 0 –0.1 –0.2 –0.3 –0.4 2 4 6 IGPIO1 (mA) 10 8 –0.5 0 4280 G13 64 128 CODE 0.4 0.8 0.3 0.6 0.2 0.1 0 –0.1 –0.2 –0.3 192 256 4280 G15 0.2 0 –0.2 –0.4 –0.6 –0.8 –0.5 –1.0 –50 192 128 CODE 0.4 –0.4 128 CODE 64 ADC Full-Scale Error vs Temperature 1.0 64 0 4280 G14 0.5 0 256 192 ADC DNL vs Code (ADIN) FULL-SCALE ERROR (LSB) 0 DNL (LSB) VOL(GPIO1) (V) 0.4 256 4280 G16 –25 50 25 0 TEMPERATURE (°C) 75 100 4280 G17 4280f 7 LTC4280 PIN FUNCTIONS ADIN: ADC Input. A voltage between 0V and 1.235V applied to this pin is measured by the onboard ADC. Tie to ground if unused. ADR0, ADR1, ADR2: Serial Bus Address Inputs. Tying these pins to ground, to the INTVCC pin or open configures one of 27 possible addresses. See Table 1 in Applications Information. ALERT: Fault Alert Output. Open-drain logic output that is pulled to ground when a fault occurs to alert the host controller. A fault alert is enabled by the ALERT register. See Applications Information. Tie to ground if unused. EN: Enable Input. Ground this pin to indicate a board is present and enable the N-channel MOSFET to turn on. When this pin is high, the MOSFET is not allowed to turn on. An internal 10μA current source pulls up this pin. Transitions on this pin are recorded in the Fault register. A high-to-low transition activates the logic to read the state of the ON pin and clear Faults. See Applications Information. EXPOSED PAD (Pin 25): Exposed pad may be left open or connected to device ground. FB: Foldback Current Limit and Power Good Input. A resistive divider from the output is tied to this pin. When the voltage at this pin drops below 1.235V, power is not considered good. The power bad condition may result in the GPIO pin pulling low or going high impedance depending on the configuration of control register bits A6 and A7. Also a power bad fault is logged in this condition if the LTC4280 has finished the start-up cycle and the GATE pin is high. See Applications Information. The current limit folds back from a 26mV sense voltage to 10mV as the FB pin voltage falls from 0.6V to 0V. GATE: Gate Drive for External N-Channel MOSFET. An internal 20μA current source charges the gate of the MOSFET. Often no compensation capacitor is required on the GATE pin, but a resistor and capacitor network from this pin to ground may be used to set the turn-on output voltage slew rate. See Applications Information. During turn-off there is a 1mA pulldown current. During a short-circuit or undervoltage lockout (VDD or INTVCC), a 450mA pulldown current source between GATE and SOURCE is activated. GND: Device Ground. GPIO: General Purpose Input/Output. Open-drain logic output or logic input. Defaults to an output set to pull low to indicate power is not good. Configure according to Table 2 and 3. INTVCC: Low Voltage Supply Decoupling Output. Connect a 0.1μF capacitor from this pin to ground. ON: On Control Input. A rising edge turns on the external N-channel MOSFET and a falling edge turns it off. This pin also configures the state of the FET On bit in the control register (and hence the external MOSFET) at power up. For example, if the ON pin is tied high, then the FET On bit (A3 in Table 2) goes high 100ms after power-up. Likewise if the ON pin is tied low then the part remains off after power-up until the FET On bit is set high using the I2C bus. A high-to-low transition on this pin clears the fault register. OV: Overvoltage Comparator Input. Connect this pin to an external resistive divider from VDD. If the voltage at this pin rises above 1.235V, an overvoltage fault is detected and the GATE turns off. Tie to GND if unused. FILTER: Fault Filter Input. Connect a capacitor between this pin and ground to set a 123ms/μF delay for overcurrent fault filtering after startup. 4280f 8 LTC4280 PIN FUNCTIONS SCL: Serial Bus Clock Input. Data at the SDA pin is shifted in or out on rising edges of SCL. This is a high impedance pin that is generally driven by an open-collector output from a master controller. An external pull-up resistor or current source is required. SOURCE: N-Channel MOSFET Source and ADC Input. Connect this pin to the source of the external N-channel MOSFET switch for gate drive return. This pin also serves as the ADC input to monitor output voltage. The pin provides a return for the gate pulldown circuit. SDAO: Serial Bus Data Output. Open-drain output for sending data back to the master controller or acknowledging a write operation. Normally tied to SDAI to form the SDA line. An external pull-up resistor or current source is required. TIMER: Start-Up Timer Input. Connect a capacitor between this pin and ground to set a 12.3ms/μF duration for start-up, after which an overcurrent fault is logged if the inrush is still current limited. The duration of the off time is 600ms/μF when overcurrent auto-retry is enabled, resulting in a 1:50 duty cycle. An internal timer provides a 100ms start-up time and 5 seconds auto-retry time if this pin is tied to INTVCC. SDAI: Serial Bus Data Input. A high impedance input for shifting in address, command or data bits. Normally tied to SDAO to form the SDA line. SENSE+: Positive Current Sense Input. Connect this pin to the input of the current sense resistor. Must be connected to the same trace as VDD. SENSE–: Negative Current Sense Input. Connect this pin to the output of the current sense resistor. This pin provides sense voltage feedback and monitoring for the current limit, circuit breaker and ADC. UV: Undervoltage Comparator Input. Connect this pin to an external resistive divider from VDD . If the voltage at this pin falls below 1.155V, an undervoltage fault is detected and the GATE turns off. Pulling this pin below 0.4V resets all faults and allows the GATE to turn back on. Tie to INTVCC if unused. VDD: Supply Voltage Input. This pin has an undervoltage lockout threshold of 2.84V and overvoltage lockout threshold of 15.6V. 4280f 9 LTC4280 FUNCTIONAL DIAGRAM SENSE– CB FOLDBACK 1.235V 0.6V FB 1.235V UV 0.4V OV INTVCC EN 1.235V 10μA 1.235V UV RST RESET + – OV1 1.235V 2.84V 15.6V + – + – + – – + +– GATE CS CHARGE PUMP AND GATE DRIVER SOURCE 26mV 25mV FET ON UV + – + – + – –+ FAULT 1.235V + – PG 10μA FILTER PWRGD 1.235V 2μA FAULT GP OV LOGIC EN ON ON UVLO1 VDD(UVLO) TM2 + – GPI0 1V + – 0.2V 100μA TIMER 2μA 3.1V GEN 1.235V UVLO2 OV2 + – EN TM1 ON VDD + – SENSE+ OV2 A/D CONVERTER ADIN + – INTVCC 2.64V 8 SOURCE SDAI SENSE+ - SENSE – SDAO I2C I2C ADDR 5 ADRO SCL ALERT 1 OF 27 ADR1 ADR2 4280 BD 4280f 10 LTC4280 TIMING DIAGRAM SDAI/SDAO tSU, DAT tHD, DATO, tHD, DATI tSU, STA tSP tHD, STA tSP tBUF tSU, STO 4280 TD01 SCL tHD, STA START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION 4280f 11 LTC4280 OPERATION The LTC4280 is designed to turn a board’s supply voltage on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. During normal operation, the charge pump and gate driver turn on an external N-channel MOSFET’s gate to pass power to the load. The gate driver uses a charge pump that derives its power from the VDD pin. Also included in the gate driver is an internal 6.5V gate-to-source clamp. During start-up the inrush current is tightly controlled by using current limit foldback and output dV/dt limiting. The current sense (CS) amplifier monitors the load current using the difference between the SENSE+ and SENSE– pin voltages. The CS amplifier limits the current in the load by pulling back on the gate-to-source voltage in an active control loop when the sense voltage exceeds the commanded value. The CS amplifier requires 20μA input bias current from both the SENSE+ and the SENSE– pins. A short-circuit on the output to ground results in excessive power dissipation during active current limiting. To limit this power, the CS amplifier regulates the voltage between the SENSE+ and SENSE– pins at 26mV with foldback to 10mV. If an overcurrent condition persists, the internal circuit breaker (CB) registers a fault when either the sense voltage exceeds 25mV or the current sense amplifier is in regulation for more than the time limit set by the capacitor on the FILTER pin. This indicates to the logic that it is time to turn off the GATE to prevent overheating. At this point the start-up TIMER pin voltage ramps down using the 2μA current source until the voltage drops below 0.2V (comparator TM1) which tells the logic that the pass transistor has cooled and it is safe to turn it on again if overcurrent auto-retry is enabled. If the TIMER pin is tied to INTVCC , the cool-down time defaults to 5 seconds on an internal system timer in the logic. The output voltage is monitored using the FB pin and the Power Good (PG) comparator to determine if the power is available for the load. The power good condition can be signaled by the GPIO pin using an open-drain pulldown transistor. The GPIO pin may also be configured to signal power bad, or as a general purpose input (GP comparator), or a general purpose open drain output. The Functional Diagram shows the monitoring blocks of the LTC4280. The group of comparators on the left side includes the undervoltage (UV), overvoltage (OV), reset (RST), enable (EN) and signal on (ON) comparators. These comparators determine if the external conditions are valid prior to turning on the GATE. But first the two undervoltage lockout circuits, UVLO1 and UVLO2, validate the input supply and the internally generated 3.1V supply, INTVCC. UVLO2 also generates the power-up initialization to the logic circuits as INTVCC crosses this rising threshold. If the fixed internal overvoltage comparator, OV2, detects that VDD is greater than 15.6V, the part immediately generates an overvoltage fault and turns the GATE off. Included in the LTC4280 is an 8-bit A/D converter. The converter has a 3-input multiplexer to select between the ADIN pin, the SOURCE pin and the SENSE+ – SENSE– voltage. An I2C interface is provided to read the A/D registers. It also allows the host to poll the device and determine if faults have occurred. If the ALERT line is configured as an interrupt, the host is enabled to respond to faults in real time. The typical SDA line is divided into an SDAI (input) and SDAO (output). This simplifies applications using an optoisolator driven directly from the SDAO output. An application which uses optoisolation is shown on the back cover. The I2C device address is decoded using the ADR0, ADR1 and ADR2 pins. These inputs have three states each that decode into a total of 27 device addresses. 4280f 12 LTC4280 APPLICATIONS INFORMATION A typical LTC4280 application is in a high availability system in which a positive voltage supply is distributed to power individual cards. The device measures card voltages and currents and records past and present fault conditions. The system queries each LTC4280 over the I2C periodically and reads status and measurement information. A basic LTC4280 application circuit is shown in Figure 1. The following sections cover turn-on, turn-off and various faults that the LTC4280 detects and acts upon. External component selection is discussed in detail in the Design Example section. Turn-On Sequence The power supply on a board is controlled by using an external N-channel pass transistor (Q1) placed in the power path. Note that resistor RS provides current detection. Resistors R1, R2 and R3 define undervoltage and overvoltage levels. R5 prevents high frequency oscillations in Q1 and R6 and C1 form an optional network that may be used to provide an output dV/dt limited start-up. Several conditions must be present before the external MOSFET turns on. First the external supply, VDD , must exceed its 2.84V undervoltage lockout level. Next the internally generated supply, INTVCC , must cross its 2.64V undervoltage threshold. This generates a 60μs to 120μs power-on-reset pulse. During reset the fault registers are cleared and the control registers are set or cleared as described in the register section. After a power-on-reset pulse, the LTC4280 goes through the following turn-on sequence. First the UV and OV pins indicate that input power is within the acceptable range, which is indicated by bits C0-C1 in Table 4. Second, the EN pin is externally pulled low. Finally, all of these conditions must be satisfied for the duration of 100ms to ensure that any contact bounce during insertion has ended. When these initial conditions are satisfied, the ON pin is checked and it’s state written to bit A3 in Table 2. If it is high, the external MOSFET is turned on. If the ON pin is low, the external MOSFET is turned on when the ON pin is brought high or if a serial bus turn-on command is sent by setting bit A3. The MOSFET is turned on by charging up the GATE with a 20μA current source. When the GATE voltage reaches the MOSFET threshold voltage, the MOSFET begins to turn on and the SOURCE voltage then follows the GATE voltage as it increases. RS 0.005Ω Q1 FDC653N 12V CONNECTOR 1 CONNECTOR 2 Z1 P6KE16A SDA SCL ALERT CF 0.1μF R1 34.8k 1% R2 1.18k 1% R3 3.4K 1% R5 10Ω R6 15k C1 6.8nF UV VDD SENSE+ SENSE– GATE SOURCE FB OV ON ADIN SDAI LTC4280 GPIO SDA0 EN SCL FILTER ALERT TIMER INTVCC ADR0 ADR1 ADR2 GND CTIMER 0.68μF GND R7 30.1k 1% R8 3.57k 1% C3 0.1μF + VOUT 12V CL 330μF R4 100k CF 47nF 4280 F01 BACKPLANE PLUG-IN CARD Figure 1. Typical Application 4280f 13 LTC4280 APPLICATIONS INFORMATION When the MOSFET is turning on, the inrush current follows the foldback profile as shown in Figure 2. Meanwhile the FILTER pin is held low with 0.6mA to prevent the FILTER pin from generating an overcurrent fault during start-up. The TIMER pin integrates at 100μA during start-up and once it reaches its threshold of 1.235V, the part checks to see if it is in current limit, which indicates that it has started up into a short-circuit condition. If this is the case, the overcurrent fault bit, D2 in Table 5, is set and the part turns off. If the part is not in current limit, the FILTER pin is released to enable circuit breaker and current limit based overcurrent faults. Alternately an internal 100ms start-up timer may be selected by tying the TIMER pin to INTVCC. VDD + 6V VGATE VDD GATE Pin Voltage A curve of gate-to-source drive vs VDD is shown in the Typical Performance Characteristics. At minimum input supply voltage of 2.9V, the minimum gate-to-source drive voltage is 4.7V. The gate-to-source voltage is clamped below 6.5V to protect the gates of logic level N-channel MOSFETs. VOUT GPIO1 (POWER GOOD) VSENSE a 20μA pull-up current from the gate pin slews the gate upwards and the part is not in current limit. The start-up TIMER may expire in this condition and an OC fault is not generated even though start-up has not completed. Either the sense voltage increases to the 25mV CB threshold or the current limit as set by the FB pin which generates an OC fault when the FILTER pin reaches its 1.235V threshold, or the FB pin voltage crosses its 1.235V power good threshold and the GPIO pin signals power good. tSTARTUP 25mV 10mV ILOAD • RSENSE 4280 F02 FB LIMITED TIMER EXPIRES Figure 2. Power-Up Waveforms As the SOURCE voltage rises, the FB pin follows as set by R7 and R8. Once FB crosses its 1.235V threshold, and the start-up timer has expired, the GPIO pin, in its default configuration, ceases to pull low and indicates that power is now good. If R6 and C1 are employed for a constant current during start-up, which produces a constant dV/dt at the output, Turn-Off Sequence The GATE is turned off by a variety of conditions. A normal turn-off is initiated by the ON pin going low or a serial bus turn-off command. Additionally, several fault conditions turn off the GATE. These include an input overvoltage (OV pin), input undervoltage (UV pin), overcurrent circuit breaker (SENSE– pin), or EN transitioning high. Writing a logic one into the UV, OV or OC fault bits (D0-D2 in Table 5) also latches off the GATE if their auto-retry bits are set to false. Normally the MOSFET is turned off with a 1mA current pulling down the GATE pin to ground. With the MOSFET turned off, the SOURCE and FB voltages drop as CL discharges. When the FB voltage crosses below its threshold, GPIO pulls low to indicate that the output power is no longer good. If the VDD pin falls below 2.74V for greater than 2μs or INTVCC drops below 2.60V for greater than 1μs, a fast shut down of the MOSFET is initiated. The GATE pin is pulled down with a 450mA current to the SOURCE pin. 4280f 14 LTC4280 APPLICATIONS INFORMATION Overcurrent Fault The LTC4280 features an adjustable current limit that protects against short-circuits or excessive load current until an overcurrent fault is generated. An overcurrent fault can occur in two different manners. First, at the end of start-up when the TIMER pin reaches its 1.235V threshold or the internal 100ms start-up timer expires, if the part is in current limit an overcurrent fault is generated. Second, after start-up the FILTER pin ramps up with 10μA if the sense voltage exceeds the 25mV circuit breaker threshold or the current limit circuit regulates the sense voltage. When the FILTER pin passes its 1.235V threshold the overcurrent present bit C2 is set and an overcurrent fault is generated. In both cases the external MOSFET is turned off and the overcurrent fault bit is set. VGATE 10V/DIV VSOURCE 10V/DIV VDD 10V/DIV ILOAD 10A/DIV RS = 5mΩ CL = 0 RSHORT = 1Ω R6 = 30k C1 = 0.1μF 5μs/DIV 4280 F03 Figure 3. Short-Circuit Waveforms After the MOSFET is turned off, the TIMER and FILTER capacitors begins discharging with 2μA pulldown currents. When the TIMER pin reaches its 0.2V threshold the MOSFET is allowed to turn on again if the overcurrent fault has been cleared. However, if the overcurrent auto-retry bit, A2 has been set then the MOSFET turns on again automatically without resetting the overcurrent fault. Use a minimum value of 10nF for CT . If the TIMER pin is bypassed by tying it to INTVCC , the part is allowed to turn on again after an internal 5 second timer has expired, in the same manner as the TIMER pin passing its 0.2V threshold. Overvoltage Fault An overvoltage fault occurs when either the OV pin rises above its 1.235V threshold, or the VDD pin rises above its 15.6V threshold, for more than 2μs. This shuts off the GATE with a 1mA current to ground and sets the overvoltage present bit C0 and the overvoltage fault bit D0. If the pin subsequently falls back below the threshold for 100ms, the GATE is allowed to turn on again unless overvoltage auto-retry has been disabled by clearing bit A0. Undervoltage Fault An undervoltage fault occurs when the UV pin falls below its 1.235V threshold for more than 2μs. This turns off the GATE with a 1mA current to ground and sets undervoltage present bit C1 and undervoltage fault bit D1. If the UV pin subsequently rises above the threshold for 100ms, the GATE is turned on again unless undervoltage auto-retry has been disabled by clearing bit A1. When power is applied to the device, if UV is below its 1.235V threshold after INTVCC crosses its 2.64V undervoltage lockout threshold, an undervoltage fault is logged in the fault register. Board Present Change of State Whenever the EN pin toggles, bit D4 is set to indicate a change of state. When the EN pin goes high, indicating board removal, the GATE turns off immediately (with a 1mA current to ground) and clears the board present bit, C4. If the EN pin is pulled low, indicating a board insertion, all fault bits except D4 are cleared and enable bit, C4, is set. If the EN pin remains low for 100ms the state of the ON pin is captured in ‘FET On’ control bit A3. This turns the switch on if the ON pin is tied high. There is an internal 10μA pull-up current source on the EN pin. 4280f 15 LTC4280 APPLICATIONS INFORMATION If the system shuts down due to a fault, it may be desirable to restart the system simply by removing and reinserting a load card. In cases where the LTC4280 and the switch reside on a backplane or midplane and the load resides on a plug-in card, the EN pin detects when the plug-in card is removed. Figure 4 shows an example where the EN pin is used to detect insertion. Once the plug-in card is reinserted the fault register is cleared (except for D4). After 100ms the state of the ON pin is latched into bit A3 of the control register. At this point the system starts up again. If a connection sense on the plug-in card is driving the EN pin, insertion or removal of the card may cause the pin voltage to bounce. This results in clearing the fault register when the card is removed. The pin may be debounced using a filter capacitor, CEN , on the ENpin as shown in Figure 4. The filter time is given by: tFILTER = CEN • 123 [ms/μF] OUT LTC4280 SOURCE 10μA EN + LOAD CEN – 1.235V GND 4280 F04 MOTHERBOARD CONNECTOR PLUG-IN CARD Figure 4. Plug-In Card Insertion/Removal Power Bad Fault A power bad fault is reported if the FB pin voltage drops below its 1.235V threshold for more than 2μs when the GATE is high. This pulls the GPIO pin low immediately when configured as power-good, and sets power-bad present bit, C3, and power bad fault bit D3. A circuit prevents power-bad faults if the gate-to-source voltage is low, eliminating false power-bad faults during power-up or power-down. If the FB pin voltage subsequently rises back above the threshold, the GPIO pin returns to a high impedance state and bit C3 is reset. Fault Alerts When any of the fault bits in FAULT register D are set, an optional bus alert is generated if the appropriate bit in the ALERT register B has been set. This allows only selected faults to generate alerts. At power-up the default state is to not alert on faults. If an alert is enabled, the corresponding fault causes the ALERT pin to pull low. After the bus master controller broadcasts the Alert Response Address, the LTC4280 responds with its address on the SDA line and releases ALERT as shown in Table 6. If there is a collision between two LTC4215s responding with their addresses simultaneously, then the device with the lower address wins arbitration and responds first. The ALERT line is also released if the device is addressed by the bus master. Once the ALERT signal has been released for one fault, it is not pulled low again until the FAULT register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults do not generate alerts until the associated FAULT register bit has been cleared. FET Short Fault Resetting Faults A FET short fault is reported if the data converter measures a current sense voltage greater than or equal to 1.6mV while the GATE is turned off. This condition sets FET short present bit, C5, and FET short fault bit D5. Faults are reset with any of the following conditions. First, a serial bus command writing zeros to the FAULT register D clears the associated faults. Second, the entire FAULT register is cleared when the switch is turned off by the ON 4280f 16 LTC4280 APPLICATIONS INFORMATION pin or bit A3 going from high to low, if the UV pin is brought below its 0.4V reset threshold for 2μs, or if INTVCC falls below its 2.64V undervoltage lockout threshold. Finally, when EN is brought from high to low, only FAULT bits D0-D3 are cleared, and bit D4, that indicates a EN change of state, is set. Note that faults that are still present, as indicated in STATUS Register C, cannot be cleared. The FAULT register is not cleared when auto-retrying. When auto-retry is disabled the existence of a D0, D1 or D2 fault keeps the switch off. As soon as the fault is cleared, the switch turns on. If auto-retry is enabled, then a high value in C0, C1 or C2 holds the switch off and the fault register is ignored. Subsequently, when bits C0, C1 and C2 are cleared by removal of the fault condition, the switch is allowed to turn on again. The LTC4280 will set bit D2 and turn off in the event of an overcurrent fault, preventing it from remaining in an overcurrent condition. If configured to auto-retry, the LTC4280 will continually attempt to restart after cool-down cycles until it succeeds in starting up without generating an overcurrent fault. Data Converter The LTC4280 incorporates an 8-bit Δ∑ A/D converter that continuously monitors three different voltages. The Δ∑ architecture inherently averages signal noise during the measurement period. The SOURCE pin has a 1/12.5 resistive divider to monitor a full-scale voltage of 15.4V with 60mV resolution. The ADIN pin is monitored with a 1.235V full-scale and 4.82mV resolution, and the voltage between the VDD and SENSE pins is monitored with a 38.6mV full-scale and 151μV resolution. Results from each conversion are stored in registers E (Sense), F (Source) and G (ADIN), as seen in Tables 6-8, and are updated 10 times per second. Setting CONTROL register bit A5 invokes a test mode that halts the data converter so that registers E, F, and G may be written to and read from for software testing. Configuring the GPIO Pin Table 2 describes the possible states of the GPIO pin using the control register bits A6 and A7. At power-up, the default state is for the GPIO pin to go high impedance when power is good (FB pin greater than 1.235V). Other applications for the GPIO pin are to pull down when power is good, a general purpose output and a general purpose input. Current Limit Stability For many applications the LTC4280 current limit will be stable without additional components. However there are certain conditions where additional components may be needed to improve stability. The dominant pole of the current limit circuit is set by the capacitance and resistance at the gate of the external MOSFET, and larger gate capacitance makes the current limit loop more stable. Usually a total of 8nF gate to source capacitance is sufficient for stability and is typically provided by inherent MOSFET CGS, however the stability of the loop is degraded by increasing RSENSE or by reducing the size of the resistor on a gate RC network if one is used, which may require additional gate to source capacitance. Board level shortcircuit testing in highly recommended as board layout can also affect transient performance, for stability testing the worst case condition for current limit stability occurs when the output is shorted to ground after a normal startup. There are two possible parasitic oscillations when the MOSFET operates as a source follower when ramping at power-up or during current limiting. The first type of oscillation occurs at high frequencies, typically above 1MHz. This high frequency oscillation is easily damped with R5 as shown in Figure 1. In some applications, one may find that R5 helps in short-circuit transient recovery as well. However, too large of an R5 value will slow down the turn-off time. The recommended R5 range is between 5Ω and 500Ω. The second type of source follower oscillation occurs at frequencies between 200kHz and 800kHz due to the load capacitance being between 0.2μF and 9μF, the presence 4280f 17 LTC4280 APPLICATIONS INFORMATION of R5 resistance, the absence of a drain bypass capacitor, a combination of bus wiring inductance and bus supply output impedance. To prevent this second type of oscillation avoid load capacitance below 10μF, alternately connect an external capacitor from the MOSFET gate to ground with a value greater than 1.5μF. Supply Transients The LTC4280 is designed to ride through supply transients caused by load steps. If there is a shorted load and the parasitic inductance back to the supply is greater than 0.5μH, there is a chance that the supply collapses before the active current limit circuit brings down the GATE pin. If this occurs, the undervoltage monitors pull the GATE pin low. The undervoltage lockout circuit has a 2μs filter time after VDD drops below 2.74V. The UV pin reacts in 2μs to shut the GATE off, but it is recommended to add a filter capacitor CF to prevent unwanted shutdown caused by a transient. Eventually either the UV pin or undervoltage lockout responds to bring the current under control before the supply completely collapses. Supply Transient Protection The LTC4280 is safe from damage with supply voltages up to 24V. However, spikes above 24V may damage the part. During a short-circuit condition, large changes in current flowing through power supply traces may cause inductive voltage spikes which exceed 24V. To minimize such spikes, the power trace inductance should be minimized by using wider traces or heavier trace plating. Also, a snubber circuit dampens inductive voltage spikes. Build a snubber by using a 100Ω resistor in series with a 0.1μF capacitor between VDD and GND. A surge suppressor, Z1 in Figure 1, at the input can also prevent damage from voltage surges. Design Example As a design example, take the following specifications: VIN = 12V, IMAX = 5A, IINRUSH = 1A, 5ms FILTER time, CL = 330μF, VUV(ON) = 10.75V, VOV(OFF) = 14.0V, VPWRGD(UP) = 11.6V, and I2C ADDRESS = 1010011. This completed design is shown in Figure 1. Selection of the sense resistor, RS , is set by the overcurrent threshold of 25mV: RS = 25mV = 0.005Ω IMAX The MOSFET is sized to handle the power dissipation during inrush when output capacitor COUT is being charged. A method to determine power dissipation during inrush is based on the principle that: Energy in CL = Energy in Q1 This uses: 1 1 2 Energy in CL = CV 2 = ( 0.33mF )(12) 2 2 or 0.024 joules. Calculate the time it takes to charge up COUT: t STARTUP = CL • VDD IINRUSH = 0.33mF • 12V = 4ms 1A The power dissipated in the MOSFET: PDISS = Energyin CL = 6W t STARTUP The SOA (safe operating area) curves of candidate MOSFETs must be evaluated to ensure that the heat capacity of the package tolerates 6W for 4ms. The SOA curves of the Fairchild FDC653N provide for 2A at 12V (24W) for 10ms, satisfying this requirement. Since the FDC653N has less than 8μF of gate capacitance and we are using a GATE RC network, the short-circuit stability of the current limit should be checked and improved by adding a capacitor from GATE to SOURCE if needed. The inrush current is set to 1A using C1: C1 = CL • IGATE IINRUSH C1 = 0.33mF • 20μA or C1 = 6.88nF 1A 4280f 18 LTC4280 APPLICATIONS INFORMATION For a start-up time of 4ms with a 2x safety margin we choose: t STARTUP 12.3ms/μF 8ms C TIMER = ≅ 0.68μF 12.3ms/μμF Layout Considerations VUV(ON) • R3 • UVTH(RISING) OVTHH(FALLING) VUV(ON) • (R3 + R2) UVTH(RISING) – R3 – R3 – R2 The FB divider is solved by picking R8 and solving for R7, choosing 3.57kΩ for R8 we get: R7 = VPWRGD(UP) • R8 FBTH(RISING) ILOAD SENSE RESISTOR RS In our case we choose R3 to be 3.4kΩ to give a resistor string current below 100μA. Then solving the equations results in R2 = 1.16kΩ and R1 = 34.6kΩ. R1 Z1 CF R2 UV OV – R8 R3 FILTER SOURCE R1 = VOV(OFF) GATE The UV and OV resistor string values can be solved in the following method. First pick R3 based on ISTRING being 1.235V/R3 at the edge of the OV rising threshold, where ISTRING > 40μA. Then solve the following equations: SENSE– CF = tFILTER/123ms/μF ≅ 47nF VDD For an overcurrent fault filter time of 5ms we choose: To achieve accurate current sensing, a Kelvin connection is required. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. Using 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 530μΩ/®. Small resistances add up quickly in high current applications. To improve noise immunity, put the resistive dividers to the UV, OV and FB pins close to the device and keep traces to VDD and GND short. It is also important to put the bypass capacitor for the INTVCC pin, C3, as close as possible between INTVCC and GND. A 0.1μF capacitor from the UV pin (and OV pin through resistor R2) to GND also helps reject supply noise. Figure 4 shows a layout that addresses these issues. Note that a surge suppressor, Z1, is placed between supply and ground using wide traces. SENSE+ C TIMER = 2 • R2 = In addition a 0.1μF ceramic bypass capacitor is placed on the INTVCC pin. INTVCC C3 GND ADIN SDAO ADR1 ADR0 ADR2 NC EN ALERT The address is set with the help of Table 1, which indicates binary address 1010011 corresponds to address 19. Address 19 is set by setting ADR2 high, ADR1 open and ADR0 high. ON SCL A 0.1μF capacitor, CF, is placed on the UV pin to prevent supply glitches from turning off the GATE via UV or OV. R8 TIMER LTC4280UFD SDAI resulting in R7 = 30kΩ. FB GPIO ILOAD 4280 F05 Next the value of R5 and R6 are chosen to be the default values 10Ω and 15k as discussed previously. Figure 5. Recommended Layout 4280f 19 LTC4280 APPLICATIONS INFORMATION SDA a6 - a0 SCL 1-7 b7 - b0 8 9 1-7 b7 - b0 8 9 1-7 8 9 P S START CONDITION ADDRESS R/W ACK DATA ACK DATA ACK STOP CONDITION 4280 F06 Figure 6. Data Transfer Over I2C or SMBus Digital Interface I2C Device Addressing The LTC4280 communicates with a bus master using a 2-wire interface compatible with I2C Bus and SMBus, an I2C extension for low power devices. Twenty-seven distinct bus addresses are available using three 3-state address pins, ADR0-ADR2. Table 1 shows the correspondence between pin states and addresses. Note that address bits B7 and B6 are internally configured to 10. In addition, the LTC4280 responds to two special addresses. Address (1011 111) is a mass write address that writes to all LTC4280s, regardless of their individual address settings. Mass write can be disabled by setting register A4 to zero. Address (0001 100) is the SMBus Alert Response Address. If the LTC4280 is pulling low on the ALERT pin, it acknowledges this address by broadcasting its address and releasing the ALERT pin. The LTC4280 is a read-write slave device and supports SMBus bus Read Byte, Write Byte, Read Word and Write Word commands. The second word in a Read Word command is identical to the first word. The second word in a Write Word command is ignored. Data formats for these commands are shown in Figures 6 to 11. START and STOP Conditions When the bus is idle, both SCL and SDA are high. A bus master signals the beginning of a transmission with a start condition by transitioning SDA from high to low while SCL is high, as shown in Figure 6. When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. Acknowledge The acknowledge signal is used in handshaking between transmitter and receiver to indicate that the last byte of data was received. The transmitter always releases the SDA line during the acknowledge clock pulse. When the slave is the receiver, it pulls down the SDA line so that it 4280f 20 LTC4280 APPLICATIONS INFORMATION remains LOW during this pulse to acknowledge receipt of the data. If the slave fails to acknowledge by leaving SDA high, then the master may abort the transmission by generating a STOP condition. When the master is receiving data from the slave, the master pulls down the SDA line during the clock pulse to indicate receipt of the data. After the last byte has been received the master leaves the SDA line HIGH (not acknowledge) and issues a stop condition to terminate the transmission. Write Protocol The master begins communication with a START condition followed by the seven bit slave address and the R/W bit set to zero, as shown in Figure 7. The addressed LTC4280 acknowledges this and then the master sends a command byte which indicates which internal register the master wishes to write. The LTC4280 acknowledges this and then latches the lower three bits of the command byte into its internal Register Address pointer. The master then delivers the data byte and the LTC4280 acknowledges once more and latches the data into its control register. The transmission is ended when the master sends a STOP condition. If the master continues sending a second data byte, as in a Write Word command, the second data byte is acknowledged by the LTC4280 but ignored, as shown in Figure 8. Read Protocol The master begins a read operation with a START condition followed by the seven bit slave address and the R/W bit set to zero, as shown in Figure 9. The addressed LTC4280 acknowledges this and then the master sends a command byte which indicates which internal register the master wishes to read. The LTC4280 acknowledges this and then latches the lower three bits of the command byte into its internal Register Address pointer. The master then sends a repeated START condition followed by the same seven bit address with the R/W bit now set to one. The LTC4280 acknowledges and send the contents of the requested register. The transmission is ended when the master sends a STOP condition. If the master acknowledges the transmitted data byte, as in a Read Word command, Figure 10, the LTC4280 repeats the requested register as the second data byte. Alert Response Protocol When any of the fault bits in FAULT register D are set, an optional bus alert is generated if the appropriate bit in the ALERT register B is also set. If an alert is enabled, the corresponding fault causes the ALERT pin to pull low. After the bus master controller broadcasts the Alert Response Address, the LTC4280 responds with its address on the SDA line and then release ALERT as shown in Figure 11. The ALERT line is also released if the device is addressed by the bus master. The ALERT signal is not pulled low again until the FAULT register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults do not generate alerts until the associated FAULT register bit has been cleared. 4280f 21 LTC4280 APPLICATIONS INFORMATION S ADDRESS W A 0 0 1 0 a4:a0 COMMAND A DATA A P X X X X X b2:b0 FROM MASTER TO SLAVE 0 b7:b0 0 A: ACKNOWLEDGE (LOW) A: NOT ACKNOWLEDGE (HIGH) R: READ BIT (HIGH) W: WRITE BIT (LOW) S: START CONDITION P: STOP CONDITION FROM SLAVE TO MASTER 4280 F07 Figure 7. LTC4280 Serial Bus SDA Write Byte Protocol S ADDRESS W A 1 0 a4:a0 0 0 COMMAND A DATA A DATA X X X X X b2:b0 0 b7:b0 0 XXXXXXXX A P 0 4280 F08 Figure 8. LTC4280 Serial Bus SDA Write Word Protocol S ADDRESS W A 1 0 a4:a0 0 0 COMMAND X X X X X b2:b0 A S ADDRESS R A DATA A P 0 1 0 a4:a0 1 0 b7:b0 1 4280 F09 Figure 9. LTC4280 Serial Bus SDA Read Byte Protocol S ADDRESS W A 1 0 a4:a0 0 0 COMMAND X X X X X b2:b0 A S ADDRESS R A DATA A DATA A P 0 1 0 a4:a0 1 0 b7:b0 0 b7:b0 1 4280 F10 Figure 10. LTC4280 Serial Bus SDA Read Word Protocol ALERT S RESPONSE R A ADDRESS 0001100 1 0 DEVICE ADDRESS A P 1 0 a4:a0 0 1 4280 F11 Figure 11. LTC4280 Serial Bus SDA Alert Response Protocol 4280f 22 LTC4280 APPLICATIONS INFORMATION Table 1. LTC4280 Device Addressing (UH24 Package) DESCRIPTION DEVICE ADDRESS LTC4280UH ADDRESS PINS Mass Write Alert Response 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 h BE 19 80 82 84 86 88 8A 8C 8E 90 92 94 96 98 9A 9C 9E A0 A2 A4 A6 A8 AA AC AE B0 7 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 4 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 3 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 2 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X ADR2 X X L L L L L L L L NC NC NC NC NC NC NC NC H H H H H H H H L ADR1 X X NC H NC NC L H L L NC H NC NC L H L L NC H NC NC L H L L H ADR0 X X L NC NC H L H NC H L NC NC H L H NC H L NC NC H L H NC H L 25 B2 1 0 1 1 0 0 1 X NC H L 26 B4 1 0 1 1 0 1 0 X H H L DEVICE ADDRESS 4280f 23 LTC4280 APPLICATIONS INFORMATION Table 2. CONTROL Register A (00h)—Read/Write BIT NAME A7:6 GPIO Configure OPERATION FUNCTION A6 A7 GPIO PIN Power Good (Default) 0 0 GPIO = C3 Power Good 0 1 GPIO = C3 General Purpose Output 1 0 GPIO = B6 General Purpose Input 1 1 C6 = GPIO A5 Test Mode Enable A4 Mass Write Enable Allows Mass Write Addressing; 1 = Mass Write Enabled (Default), 0 = Mass Write Disabled A3 FET On Control On Control Bit Latches the State of the ON Pin at the End of the Debounce Delay; 1 = FET On, 0 = FET Off A2 Overcurrent Auto-Retry Undervoltage Auto-Retry Overvoltage Auto-Retry Overcurrent Auto-Retry Bit; 1 = Auto-Retry After Overcurrent, 0 = Latch Off After Overcurrent A1 A0 Enables Test Mode to Disable the ADC; 1 = ADC Disable, 0 = ADC Enable (Default) Undervoltage Auto-Retry; 1 = Auto-Retry After Undervoltage (Default), 0 = Latch Off After Undervoltage Overvoltage Auto-Retry; 1 = Auto-Retry After Overvoltage (Default), 0 = Latch Off After Overvoltage Table 3. ALERT Register B (01h)—Read/Write BIT NAME OPERATION B7 Reserved Not Used B6 GPIO Output Output Data Bit to GPIO Pin when Configured as Output. Defaults to 0 B5 FET Short Alert Enables Alert for FET Short Condition; 1 = Enable Alert, 0 = Disable Alert (Default) B4 EN State Change Alert Power Bad Alert Overcurrent Alert Undervoltage Alert Overvoltage Alert Enables Alert when EN Changes State; 1 = Enable Alert, 0 Disable Alert (Default) B3 B2 B1 B0 Enables Alert when Output Power is Bad; 1 = Enable Alert, 0 Disable Alert (Default) Enables Alert for Overcurrent Condition; 1 = Enable Alert, 0 Disable Alert (Default) Enables Alert for Undervoltage Condition; 1 = Enable Alert, 0 Disable Alert (Default) Enables Alert for Overvoltage Condition; 1 = Enable Alert, 0 Disable Alert (Default) 4280f 24 LTC4280 APPLICATIONS INFORMATION Table 4. STATUS Register C (02h)—Read BIT NAME OPERATION C7 FET On 1 = FET On, 0 = FET Off C6 GPIO Input State of the GPIO Pin; 1 = GPIO High, 0 = GPIO Low C5 C4 FET Short Present EN Indicates Potential FET Short if Current Sense Voltage Exceeds 1mV While FET is Off; 1 = FET is Shorted, 0 = FET is Not Shorted Indicates if the LTC4280 is enabled when EN is low; 1 = EN Pin Low, 0 = EN Pin High C3 Power Bad Indicates Power is Bad when FB is low; 1 = FB Low, 0 = FB High C2 Overcurrent Indicates Overcurrent Condition During Cool Down Cycle; 1 = Overcurrent, 0 = Not Overcurrent C1 Undervoltage Indicates Input Undervoltage when UV is Low; 1 = UV Low, 0 = UV High C0 Overvoltage Indicates VDD or OV Input Overvoltage when OV is High; 1 = OV High, 0 = OV Low Table 5. FAULT Register D (03h)—Read/Write BIT NAME D7:6 Reserved D5 FET Short Fault Occurred EN Changed State Power Bad Fault Occurred Overcurrent Fault Occurred Undervoltage Fault Occurred Overvoltage Fault Occurred D4 D3 D2 D1 D0 OPERATION Indicates Potential FET Short was Detected when Measured Current Sense Voltage Exceeded 1mV while FET was Off; 1 = FET is Shorted, 0 = FET is Good Indicates That the LTC4280 was Enabled or Disabled when EN Changed State; 1 = EN Changed State, 0 = EN Unchanged Indicates Power was Bad when FB when Low; 1 = FB was Low, 0 = FB was High Indicates Overcurrent Fault Occurred; 1 = Overcurrent Fault Occurred, 0 = Not Overcurrent Faults Indicates Input Undervoltage Fault Occurred when UV went Low; 1 = UV was Low, 0 = UV was High Indicates Input Overvoltage Fault Occurred when OV went High; 1 = OV was High, 0 = OV was Low Table 6. SENSE Register E (04h)—Read/Write BIT NAME OPERATION E7:0 SENSE Voltage Measurement Sense Voltage Data. 8-Bit Data with 151μV LSB and 38.45mV Full Scale. Table 7. SOURCE Register F (05h)—Read/Write BIT NAME OPERATION F7:0 SOURCE Voltage Measurement Source Voltage Data. 8-Bit Data with 60.5mV LSB and 15.44V Full Scale. Table 8. ADIN Register G (06h)—Read/Write BIT NAME OPERATION G7:0 ADIN Voltage Measurement ADIN Voltage Data. 8-Bit Data with 4.82mV LSB and 1.23V Full Scale. 4280f 25 LTC4280 TYPICAL APPLICATIONS 5V Backplane Resident Application with Insertion Activated Turn-On and a 5A Circuit Breaker RS 0.005Ω VIN 5V R1 11.5k 1% CF 0.1μF R5 10Ω R2 1.74k 1% R3 2.67k 1% Q1 FDD3706 UV VDD SENSE+ SENSE– GATE SOURCE FB OV ON GPIO SDAI EN LTC4280UFD SDAO ADIN SCL ALERT FILTER INTVCC TIMER ADR0 ADR1 ADR2 GND R7 6.98k 1% R8 2.67k 1% VOUT 5V R4 100k LOAD CEN 1μF CF 47nF C3 0.1μF 4280 F13 BACKPLANE PLUG-IN CARD 4280f 26 LTC4280 PACKAGE DESCRIPTION UFD Package 24-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1696 Rev A) 0.70 p0.05 4.50 p 0.05 3.10 p 0.05 2.00 REF 2.65 p 0.05 3.65 p 0.05 PACKAGE OUTLINE 0.25 p0.05 0.50 BSC 3.00 REF 4.10 p 0.05 5.50 p 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 p 0.10 (2 SIDES) R = 0.05 TYP 2.00 REF R = 0.115 TYP 23 0.75 p 0.05 PIN 1 NOTCH R = 0.20 OR C = 0.35 24 0.40 p 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 p 0.10 (2 SIDES) 3.00 REF 3.65 p 0.10 2.65 p 0.10 (UFD24) QFN 0506 REV A 0.25 p 0.05 0.200 REF 0.50 BSC 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 4280f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC4280 TYPICAL APPLICATION –12V Card Resident Application with Optically Isolated I2C and a 16.6A Circuit Breaker RS 0.0015Ω Q1 Si7880DP OUTPUT GND –7V R10 3.3k –7V 5V 2 8 R9 10k 6 CF 0.1μF 3 HCPL-0300 5 –12V SDA R4 3.3k 6 8 R2 1.18k 1% R6 15k R3 3.4k 1% UV VDD SENSE + – SENSE GATE R7 30.1k 1% SOURCE FB OV R8 3.57k 1% ADIN LTC4280UFD GPIO EN CL 1000μF FILTER ADR0 INTVCC ADR1 ADR2 GND TIMER –7V C3 0.1μF R12 10k R13 3.3k C1 22nF –12V 2 5 HCPL-0300 3 SCL R5 10Ω SDAI SDAO SCL ON –7V D2 P6KE16A R1 34.8k 1% CTIMER 1μF CF 47nF –7V 2 8 6 3 HCPL-0300 5 R14 100k Q2 –7V VIN –12V D1 5.6V –12V 4280 F14 BACKPLANE PLUG-IN CARD RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC4151 High Voltage Current and Voltage Monitor with ADC and I2C 7V to 80V Single Voltage/Current Monitor with 12-Bit ADC LTC4210 Single Channel, Hot Swap Controller Operates from 2.7V to 16.5V, Active Current Limiting, SOT23-6 LTC4211 Single Channel, Hot Swap Controller Operates from 2.5V to 16.5V, Multifunction Current Control, MSOP-8 or MSOP-10 LTC4212 Single Channel, Hot Swap Controller Operates from 2.5V to 16.5V, Power-Up Timeout, MSOP-10 LTC4215 Single Channel, Hot Swap Controller with I2C Monitoring Operates from 2.9V to 15V, 8-Bit ADC Monitors Current and Voltage Operates from 0V to 6V, MSOP-10 or 12-Lead (4mm × 3mm) DFN LTC4216 Single Channel, Hot Swap Controller LTC4222 Dual Hot Swap Controller with ADC and I2C 2.9V to 29V Dual Controller with 10-Bit ADC, dl/dt Controlled Soft-Start LTC4245 Multiple Supply CompactPCI or PCI Express Internal 8-Bit ADC, dl/dt Controlled Soft-Start Hot Swap Controller with I2C LTC4260 Positive High Voltage Hot Swap Controller with ADC and I2C 8-Bit ADC Monitoring Current and Voltages, Supplies from 8.5V to 80V LTC4261 Negative High Voltage Hot Swap Controller with ADC and I2C 10-Bit ADC Monitoring Current and Voltages, Supplies from –12V to –100V 4280f 28 Linear Technology Corporation LT 0510 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2010