Rev 0; 1/03 Dual Temperature-Controlled Resistors with Two Monitors The DS1854 dual temperature-controlled nonvolatile (NV) variable resistors with two monitors consists of two 50kΩ 256-position linear variable resistors, two analog monitor inputs (MON1, MON2), and a direct-to-digital temperature sensor. The device provides an ideal method for setting and temperature-compensating bias voltages and currents in control applications using minimal circuitry. The variable resistor settings are stored in EEPROM memory and can be accessed over the 2-wire serial bus. Applications Optical Transceivers Optical Transponders Features ♦ Four Total Monitored Channels (Temperature, VCC, MON1, MON2) ♦ Two External Analog Inputs (MON1, MON2) ♦ Internal Direct-to-Digital Temperature Sensor ♦ Two 50kΩ, Linear, 256-Position, Nonvolatile Temperature-Controlled Variable Resistors ♦ Resistor Settings Changeable Every 2°C ♦ Access to Monitoring and ID Information Configurable with Separate Device Addresses ♦ Resistor Disable (Open-Circuit) Function ♦ 2-Wire Serial Interface ♦ Two Buffers with TTL/CMOS-Compatible Inputs and Open-Drain Outputs ♦ Operates from a 3.3V or 5V Supply ♦ SFF-8472 Compatible Instrumentation and Industrial Controls RF Power Amps Ordering Information PART Diagnostic Monitoring TEMP RANGE PIN-PACKAGE DS1854E-050 -40°C to +95°C 16 TSSOP DS1854E-050/T&R -40°C to +95°C DS1854B-050 -40°C to +95°C 16-Ball CSBGA Typical Operating Circuit 16 TSSOP (Tape-and-Reel) Pin Configurations VCC VCC = 3.3V 4.7kΩ 4.7kΩ 1 2-WIRE INTERFACE 2 3 TX-FAULT 4 5 LOS GROUND TO DISABLE WRITE PROTECT 6 7 8 0.1µF VCC SDA H1 SCL L1 OUT1 IN1 OUT2 DS1854 15 TO LASER BIAS CONTROL 14 TO LASER MODULATION CONTROL 13 H0 12 L0 IN2 MON2 WPEN MON1 GND 16 RHIZ DECOUPLING CAP 11 Rx POWER* 10 Tx BIAS* DIAGNOSTIC INPUTS 0 TO 2.5V FS TOP VIEW A B IN1 SCL OUT2 SDA VCC H0 H1 VCC 16 2 SCL H1 15 3 OUT1 L1 14 L1 4 IN1 C D WPEN GND IN2 OUT1 5 OUT2 MON2 L0 RHIZ MON1 2 3 4 9 Tx DISABLE 1 *Rx POWER AND Tx BIAS CAN BE ARBITRARILY ASSIGNED TO THE MON INPUTS 1 SDA H0 13 DS1854 L0 12 6 IN2 MON2 11 7 WPEN MON1 10 8 GND RHIZ 9 16-BALL CSBGA (4mm x 4mm) 1.0mm PITCH 16 TSSOP ______________________________________________ Maxim Integrated Products For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS1854 General Description DS1854 Dual Temperature-Controlled Resistors with Two Monitors ABSOLUTE MAXIMUM RATINGS Voltage on VCC Relative to Ground.......................-0.5V to +6.0V Voltage on Inputs Relative to Ground* ................................................-0.5V to VCC + 0.5V Voltage on Resistor Inputs Relative to Ground*...................................-0.5V to VCC + 0.5V Current into Resistors............................................................5mA Operating Temperature Range ...........................-40°C to +95°C Programming Temperature Range .........................0°C to +70°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature .......................................See IPC/JEDEC *Not to exceed 6.0V. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = -40°C to +95°C, unless otherwise noted.) MAX UNITS Supply Voltage PARAMETER SYMBOL VCC (Note 1) CONDITIONS 3.0 5.5 V Input Logic 1 (SDA, SCL, WPEN, RHIZ) VIH (Note 2) 0.7 x Vcc VCC + 0.3 V Input Logic 0 (SDA, SCL, WPEN, RHIZ) VIL (Note 2) -0.3 0.3 x VCC V -0.3 VCC + 0.3 V -3 +3 mA Resistor Inputs (L0, L1, H0, H1) Resistor Current IRES Input Logic Levels (IN1, IN2) VIH Input logic 1 VIL Input logic 0 MIN TYP 1.5 0.9 V DC ELECTRICAL CHARACTERISTICS (VCC = 3.0V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.) PARAMETER Supply Current Input Leakage SYMBOL ICC IIL Input Current each I/O Pin Low-Level Output Voltage (SDA) CONDITIONS MIN (Note 3) 0.4 x VCC < VI/O < 0.9 x VCC TYP 1 MAX 2 UNITS mA -1 +1 µA -10 +10 µA VOL1 3mA sink current 0 0.4 VOL2 6mA sink current 0 0.6 V Full-Scale Input (MON1, MON2) (Note 4) 2.4875 2.5000 2.5125 Full-Scale VCC Monitor (Note 5) 6.5208 6.5536 6.5864 V 10 pF I/O Capacitance CI/O V WPEN Pullup RWPEN 40 65 100 kΩ RHIZ Pullup RRHIZ 40 65 100 kΩ 0.4 V OUT1, OUT2 Voltage VOL1 3mA sink current VOL2 6mA sink current 0 0 0.6 V Digital Power-On Reset POD 1.0 2.2 V Analog Power-On Reset POA 2.0 2.6 V 2 _____________________________________________________________________ Dual Temperature-Controlled Resistors with Two Monitors (VCC = 3.0V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Position 00h Resistance TA = +25°C 0.7 1.0 1.25 kΩ Position FFh Resistance TA = +25°C 40 50 60 kΩ Absolute Linearity (Note 6) -2 +2 LSB Relative Linearity (Note 7) -1 +1 LSB Temperature Coefficient (Note 8) High-Z Resistor Current IRHIZ 50 ppm/°C RHIZ = VCC 0.1 µA ANALOG VOLTAGE MONITORING (VCC = 3.0V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ∆VMON 610 µV Supply Resolution ∆VCC 1.6 mV Input/Supply Accuracy ACC 0.25 0.5 % FS (full scale) tframe 20 30 ms Input Resolution Update Rate for MON1, MON2, Temp, or VCC DIGITAL THERMOMETER (VCC = 3.0V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.) PARAMETER Thermometer Error SYMBOL TERR CONDITIONS -40°C to +95°C TYP MAX UNITS ±3.0 °C _____________________________________________________________________ 3 DS1854 ANALOG RESISTOR CHARACTERISTICS DS1854 Dual Temperature-Controlled Resistors with Two Monitors AC ELECTRICAL CHARACTERISTICS (VCC = 3.0V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.) PARAMETER SYMBOL SCL Clock Frequency fSCL Bus Free Time Between STOP and START Condition tBUF Hold Time (Repeated) START Condition tHD:STA Low Period of SCL Clock tLOW High Period of SCL Clock tHIGH Data Hold Time tHD:DAT Data Setup Time tSU:DAT Start Setup Time tSU:STA Rise Time of Both SDA and SCL Signals tR Fall Time of Both SDA and SCL Signals tF Setup Time for STOP Condition tSU:STO CONDITIONS TYP MAX Fast mode (Note 9) 0 400 Standard mode (Note 9) 0 100 Fast mode (Note 9) 1.3 Standard mode (Note 9) 4.7 Fast mode (Notes 9, 10) 0.6 Standard mode (Notes 9, 10) 4.0 Fast mode (Note 9) 1.3 Standard mode (Note 9) 4.7 Fast mode (Note 9) 0.6 Standard mode (Note 9) 4.0 Fast mode (Notes 9, 11, 12) 0 Standard mode (Notes 9, 11, 12) 0 Fast mode (Note 9) 100 Standard mode (Note 9) 250 Fast mode (Note 9) 0.6 Standard mode (Note 9) 4.7 µs µs 0.9 µs 300 20 + 0.1CB 1000 Fast mode (Note 13) 20 + 0.1CB 300 Standard mode (Note 13) 20 + 0.1CB 300 Standard mode 4.0 CB (Note 13) EEPROM Write Time tW (Note 14) µs ns 20 + 0.1CB 0.6 kHz µs Standard mode (Note 13) Fast mode UNITS µs Fast mode (Note 13) Capacitive Load for Each Bus Line Note 1: MIN ns ns µs 400 10 pF ms All voltages are referenced to ground. Note 2: I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCC is switched off. Note 3: SDA and SCL are connected to VCC and all other input signals are connected to well-defined logic levels. Note 4: The maximum voltage the MON inputs will read is approximately 2.5V, even if the voltage on the inputs are greater than 2.5V. Note 5: This voltage is defining the maximum range of the analog-to-digital converter and not the maximum VCC voltage. Note 6: Absolute linearity is the difference of measured value from expected value at DAC position. The expected value is a straight line from measured minimum position to measured maximum position. Note 7: Relative linearity is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change is the slope of the straight line from measured minimum position to measured maximum position. Note 8: See the Typical Operating Characteristics. Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT > 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000ns + 250ns = 1250ns before the SCL line is released. 4 _____________________________________________________________________ Dual Temperature-Controlled Resistors with Two Monitors (VCC = 3.0V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.) Note 10: After this period, the first clock pulse is generated. Note 11: The maximum tHD:DAT only has to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 12: A device must internally provide a hold time of at least 300ns for the SDA signal (see the VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. Note 13: CB—total capacitance of one bus line, timing referenced to 0.9 x VCC and 0.1 x VCC. Note 14: EEPROM write begins after a STOP condition occurs. Typical Operating Characteristics (VCC = 5.0V, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. TEMPERATURE 620 580 540 600 550 500 450 500 400 -20 0 20 40 60 80 100 3.0 3.5 4.0 4.5 5.0 TEMPERATURE (°C) VOLTAGE (V) RESISTANCE vs. SETTING ACTIVE SUPPLY CURRENT vs. SCL FREQUENCY 50 40 30 20 10 0 700 5.5 DS1854 toc04 DS1854 toc03 60 SDA = 5V ACTIVE SUPPLY CURRENT (µA) -40 RESISTANCE (kΩ) DS1854 toc02 650 SUPPLY CURRENT (µA) 660 SUPPLY CURRENT (µA) SUPPLY CURRENT vs. VOLTAGE 700 DS1854 toc01 700 660 620 580 540 500 0 50 100 150 SETTING 200 250 300 0 100 200 300 400 SCL FREQUENCY (kHz) _____________________________________________________________________ 5 DS1854 AC ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VCC = 5.0V, TA = +25°C, unless otherwise noted.) RESISTOR 0 DNL (LSB) 0.15 0.2 0.1 0 -0.1 -0.2 0.4 0.3 RESISTOR 1 INL (LSB) RESISTOR 0 DNL (LSB) 0.05 -0.05 -0.15 -0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.4 -0.25 -0.5 -0.5 0 50 75 100 125 150 175 200 225 250 25 50 75 100 125 150 175 200 225 250 POSITION POSITION RESISTOR 1 DNL (LSB) RESISTANCE vs. POWER-UP VOLTAGE +25°C 0.05 -0.05 POSITION 00H RESISTANCE vs. TEMPERATURE 250 RESISTANCE (kΩ) 0.15 -0.15 1.00 0.99 200 150 100 25 50 75 100 125 150 175 200 225 250 0.97 0.95 0 0 0.98 0.96 50 -0.25 50 75 100 125 150 175 200 225 250 POSITION 300 DS1854 toc08 0.25 25 0 RESISTANCE (kΩ) 25 DS1854 toc09 0 DS1854 toc10 RESISTOR 0 INL (LSB) 0.3 0.5 DS1854 toc06 DS1854 toc05 0.4 RESISTOR 1 INL (LSB) 0.25 DS1854 toc07 RESISTOR 0 INL (LSB) 0.5 RESISTOR 1 DNL (LSB) 0 1 POSITION 2 3 -40 -25 -10 5 4 POSITION FFH RESISTANCE vs. TEMPERATURE 20 35 PPM vs. POSITION DS1854 toc12 340 DS1854 toc11 52.30 5 290 240 52.20 ppm/°C 190 52.10 140 +25°C TO +85°C 90 52.00 40 +25°C TO -40°C 51.90 -10 51.80 -60 -40 -25 -10 5 20 35 50 65 80 95 0 50 TEMPERATURE (°C) 6 50 TEMPERATURE (°C) POWER-UP VOLTAGE (V) 52.40 RESISTANCE (kΩ) DS1854 Dual Temperature-Controlled Resistors with Two Monitors _____________________________________________________________________ 100 150 POSITION 200 250 300 65 80 95 Dual Temperature-Controlled Resistors with Two Monitors PIN BALL NAME FUNCTION 1 B2 SDA 2 A2 SCL 3 C3 OUT1 4 A1 IN1 5 B1 OUT2 6 C2 IN2 7 C1 WPEN 8 D1 GND Ground 9 D3 RHIZ Resistor Disable Input. When high, this signal places both resistors in an off-state or high-impedance mode. When low, the resistors are on. This pin has an internal pullup (RRHIZ). 10 D4 MON1 External Analog Input 11 C4 MON2 External Analog Input 12 D2 L0 Low-End Resistor 0 Terminal. It is not required that the low-end terminals be connected to a potential less than the high-end terminals of the corresponding resistor. Voltage applied to any of the resistor terminals cannot exceed the power-supply voltage, VCC, or go below ground. 13 B3 H0 High-End Resistor 0 Terminal. It is not required that the high-end terminals be connected to a potential greater than the low-end terminals of the corresponding resistor. Voltage applied to any of the resistor terminals cannot exceed the power-supply voltage, VCC, or go below ground. 14 B4 L1 Low-End Resistor 1 Terminal 15 A4 H1 High-End Resistor 1 Terminal 16 A3 VCC Supply Voltage 2-Wire Serial Data I/O pin. This pin is for serial data transfer to and from the device. 2-Wire Serial Clock Input. The serial clock input is used to clock data into and out of the device. Open-Drain Buffer Output TTL/CMOS-Compatible Input to Buffer Open-Drain Buffer Output TTL/CMOS-Compatible Input to Buffer Write Protect Enable. The device is not write protected if WPEN is connected to ground. This pin has an internal pullup (RWPEN). See Table 6. Detailed Description The user can read the registers that monitor the VCC, MON1, MON2, and temperature analog signals. After each signal conversion, a corresponding bit is set that can be monitored to verify that a conversion has occurred. The signals also have alarm flags that notify the user when the signals go above or below the userdefined value. Interrupts can also be set for each signal. The position values of each resistor can be independently programmed. The user can assign a unique value to each resistor for every 2°C increment over the -40°C to +102°C range. Both resistors can also be put in a high-impedance mode using the RHIZ pin. Two buffers are provided to convert logic-level inputs into open-drain outputs. Typically these buffers are used to implement transmit (Tx) fault and loss-of-signal (LOS) alarms. Additionally, OUT1 can be asserted in the event that one or more of the monitored values go beyond user-defined limits. _____________________________________________________________________ 7 DS1854 Pin Descriptions DS1854 Dual Temperature-Controlled Resistors with Two Monitors PROT AUX PROT MAIN AD PROT MAIN MD MD AD (AUXILIARY DEVICE ENABLE A0h) TABLE SELECT DEVICE ADDRESS MD (MAIN DEVICE ENABLE) DEVICE ADDRESS EEPROM 128 x 8 BIT 00h-7Fh ADDRESS R/W ADDRESS ADEN ADFIX SDA EEPROM 72 x 8 BIT 80h-C7h ADDRESS TABLE 02 RESISTOR 0 LOOK-UP TABLE R/W STANDARDS TABLE SELECT EEPROM 72 x 8 BIT 80h-C7h TABLE 03 RESISTOR 1 LOOK-UP TABLE R/W ADDRESS 2-WIRE INTERFACE TEMP INDEX DATA BUS SCL TEMP INDEX R/W PROT MAIN TxF Tx FAULT RHIZ MD OUT1 MINT EEPROM 72 x 8 BIT 80h-C7h R/W MONITORS LIMIT LOW H0 REGISTER MONITORS LIMIT HIGH ADDRESS RESISTOR 0 50kΩ FULL SCALE 256 POSITIONS L0 RHIZ TEMP INDEX INV1 SRAM 32 x 8 BIT 60h-7Fh NOT PROTECTED TxF RxL OUT2 LOS H1 REGISTER IN1 MINT (BIT) RESISTOR 1 50kΩ FULL SCALE 256 POSITIONS L1 TABLE SELECT PROT MAIN MEASUREMENT INV2 MD R/W VCC ALARM FLAGS INV1 (BIT) RRHIZ IN2 INV2 (BIT) TABLE SELECT RHIZ VCC ADDRESS INTERNAL TEMP MUX MON1 A/D 12-BIT DEVICE ADDRESS MONITORS LIMIT HIGH VCC MUX CTRL VCC A/D CTRL APEN ADEN (BIT) MASKING (TMP, VCC, MON1, MON2) MONITORS LIMIT LOW MINT MEASUREMENT PROT AUX PROT MAIN MPEN COMP CTRL COMPARATOR ALARM FLAGS Figure 1. DS1854 Block Diagram 8 MPEN (BIT) VENDOR INTERRUPT RWPEN GND WPEN APEN (BIT) ADFIX (BIT) MON2 VCC TABLE 01 EEPROM 16 x 8 BIT 80h-8Fh _____________________________________________________________________ Dual Temperature-Controlled Resistors with Two Monitors SIGNAL +FS SIGNAL +FS -FS SIGNAL -FS Temperature 127.996°C 7FFF -128°C 8000 VCC 6.55V FFFF 0V 0000 MON1 2.5V FFFF 0V 0000 MON2 2.5V FFFF 0V 0000 Table 3. Look-up Table Address for Corresponding Temperature Values CORRESPONDING LOOK-UP TABLE ADDRESS TEMPERATURE Table 2. Signal Comparison <-40°C 80h -40°C 80h -38°C 81h -36°C 82h -34°C 83h FORMAT — — VCC Unsigned +98°C C5h MON1 Unsigned +100°C C6h Unsigned +102°C C7h Two’s complement >+102°C C7h SIGNAL MON2 Temperature Monitored Signals Each signal (VCC, MON1, MON2, and temperature) is available as a 16-bit value with 12-bit accuracy (left-justified) over the serial bus. See Table 1 for signal scales and Table 2 for signal format. The four LSBs should be masked when calculating the value. The signals are updated every frame rate (tframe) in a round-robin fashion. The comparison of all four signals with the high and low user-defined values are done automatically. The corresponding flags are set to 1 within a specified time of the occurrence of an out-of-limit condition. Calculating Signal Values The LSB = 100µV for VCC, and the LSB = 38.147µV for the MON signals. Monitor/VCC Bit Weights MSB 215 214 213 212 211 210 29 28 LSB 27 26 25 24 23 22 21 20 To calculate the value of the temperature, treat the two’s complement value binary number as an unsigned binary number then convert to decimal and divide by 256. If the result is greater than or equal to 128, then subtract 256 from the result. Temperature: high byte: -128°C to +127°C signed; low byte: 1/256°C. Monitor Conversion Example MSB (BIN) LSB (BIN) VOLTAGE (V) 11000000 00000000 1.875 10000000 10000000 1.255 Temperature Bit Weights S 26 25 24 23 22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 Temperature Conversion Example VCC Conversion Example MSB (BIN) LSB (BIN) VOLTAGE (V) MSB (BIN) LSB (BIN) 10000000 10000000 3.29 01000000 00000000 64 4.94 01000000 00001111 64.059 01011111 00000000 95 11110110 00000000 -10 11011000 00000000 -40 11000000 11111000 DS1854 Table 1. Scales for Monitor Channels To calculate the value of VCC, convert the unsigned 16bit value to decimal and multiply by 100µV. To calculate the value of MON1 or MON2, convert the unsigned 16-bit value to decimal and multiply by 38.147µV. TEMPERATURE (°C) _____________________________________________________________________ 9 DS1854 Dual Temperature-Controlled Resistors with Two Monitors Table 4. ADEN Address Configuration ADEN (ADDRESS ENABLE) NO. OF SEPARATE DEVICE ADDRESSES Table 5. ADEN and ADFIX Bits ADDITIONAL INFORMATION 0 2 See Figure 2 1 1 (Main Device only) See Figure 3 ADEN ADFIX AUXILIARY ADDRESS 0 0 A0h A2h EEPROM (Table 01, 8Ch) 0 1 A0h 1 0 N/A A2h N/A EEPROM (Table 01, 8Ch) 1 1 MAIN DEVICE ENABLE AUXILIARY DEVICE ENABLE 0 0 DEC EN MAIN DEVICE AUXILIARY DEVICE EN 0 5Fh 60h EN 7Fh 7Fh TABLE SELECT DECODER 95 96 127 128 TABLE 01 TABLE 02 TABLE 03 EN EN EN 80h 80h 80h MON LOOK-UP TABLE CONTROL R1 LOOK-UP R0 LOOK-UP TABLE TABLE SEL 8Fh SEL C7h SEL C7h 143 RESERVED 199 RESERVED MEMORY PARTITION WITH ADEN BIT = 0 Figure 2. Memory Organization, ADEN = 0 MAIN DEVICE ENABLE 0 DEC MAIN DEVICE 0 EN 5Fh 60h 95 96 EN 7Fh TABLE SELECT DECODER TABLE 00 127 128 80h 143 AUXILIARY DEVICE EN TABLE 01 TABLE 02 TABLE 03 EN EN EN 80h 80h 80h MON LOOK-UP TABLE CONTROL R1 LOOK-UP R0 LOOK-UP TABLE TABLE SEL 8Fh SEL C7h RESERVED 199 255 FFh MEMORY PARTITION WITH ADEN BIT = 1 Figure 3. Memory Organization, ADEN = 1 10 MAIN ADDRESS ____________________________________________________________________ SEL C7h RESERVED Dual Temperature-Controlled Resistors with Two Monitors Memory Description Main and auxiliary memories can be accessed by two separate device addresses. The Main Device address is A2h (or value in Table 01, byte 8Ch when ADFIX = 1) and the Auxiliary Device address is A0h. A user option is provided to respond to one or two device addresses. This feature can be used to save component count in SFF applications (Main Device address can be used) or other applications where both GBIC (Auxiliary Device address can be used) and monitoring functions are implemented and two device addresses are needed. The memory blocks are enabled with the corresponding device address. Memory space from 80h and up is accessible only through the Main Device address. This memory is organized as three tables; the desired table can be selected by the contents of memory location 7Fh, Main Device. The Auxiliary Device address has no access to the tables, but the Auxiliary Device address can be mapped into the Main Device’s memory space as a fourth table. Device addresses are programmable with two control bits in EEPROM. ADEN configures memory access to respond to different device addresses (see Tables 4 and 5). The default device address for EEPROM-generated addresses is A2h. If the ADEN bit is 1, additional 128 bytes of EEPROM are accessible through the Main Device, selected as Table 00 (see Figure 3). In this configuration, the Auxiliary Device address is not accessible. APEN controls the protection of Table 00 regardless of the setting of ADEN. ADFIX (address fixed) determines whether the Main Device address is determined by an EEPROM byte (Table 01, byte 8Ch, when ADFIX =1). There can be up to 128 devices sharing a common 2-wire bus, with each device having its own unique device address. Memory Protection Memory access from either device address can be either read/write or read only. Write protection is accomplished by a combination of control bits in EEPROM (APEN and MPEN in configuration register 89h) and a write-protect enable (WPEN) pin. Since the WPEN pin is often not accessible from outside the module, this scheme effectively allows the module to be locked by the manufacturer to prevent accidental writes by the end user. Separate write protection is provided for the Auxiliary and Main Device address through distinct bits APEN and MPEN. APEN and MPEN are bits from configuration register 89h, Table 01. Due to the location, the APEN and MPEN bits can only be written through the Main Device address. The control of write privileges through the Auxiliary Device address is dependent on the value of APEN. Care should be taken with the setting of MPEN, once set to a 1, assuming WPEN is high, access through the Main Device is thereafter denied unless WPEN is taken to a low level. By this means inadvertent end-user write access can be denied. Main Device address space 60h to 7Fh is SRAM and is not write protected by APEN, MPEN, or WPEN. For example, the user may reset flags set by the device. Bytes designated as “Reserved” may be used as scratchpad, but they will not be stored in a power cycle because of their volatility. These bytes are reserved for added functionality in future versions of this device. Note that in single device mode (ADEN bit = 1), APEN determines the protection level of Table 00, independent of WPEN. The write-protect operation, for both Main and Auxiliary Devices, is summarized in the Tables 6 and 7. Table 6. Main Device WPEN MPEN PROTECT MAIN 0 X No X 0 No 1 1 Yes Table 7. Auxiliary Device APEN WPEN 0 X No 1 X Yes PROTECT AUXILIARY ____________________________________________________________________ 11 DS1854 Variable Resistors The value of each variable resistor is determined by a temperature-addressed look-up table, which can assign a unique value (00h to FFh) to each resistor for every 2°C increment over the -40°C to +102°C range (see Table 3). See the Temperature Conversion section for more information. A resistor disable feature places both outputs in a highimpedance mode. This occurs when the RHIZ input is high. An internal pullup of RRHIZ is provided, readying this pin for input from the Tx Disable signal as specified in the SFF and SFP MSA. The variable resistors can also be used in manual mode. If the TEN bit equals 0, then the resistors are in manual mode and the temperature indexing is disabled. The user sets the resistors in manual mode by writing to addresses 82h and 83h in Table 01 to control resistors 0 and 1, respectively. DS1854 Dual Temperature-Controlled Resistors with Two Monitors Register Map A description of the registers is below. The registers are read only (R) or read/write (R/W). The R/W registers are writable only if write protect has not been asserted (see the Memory Description section). Auxiliary Device MEMORY LOCATION EEPROM/SRAM R/W DEFAULT SETTING NAME OF LOCATION 00 to 7F EEPROM R/W 00 Standards Data FUNCTION Main Device MEMORY LOCATION EEPROM/ SRAM R/W DEFAULT SETTING NAME OF LOCATION FUNCTION 00 to 01 EEPROM R/W 00 TMPlimhi (MSB to LSB) Contains upper limit settings for temperature. If the limit is violated, a flag in Main Device byte 70h is set. 02 to 03 EEPROM R/W 00 TMPlimlo (MSB to LSB) Contains lower limit settings for temperature. If the limit is violated, a flag in Main Device byte 70h is set. 04 to 07 EEPROM R 00 Reserved — 08 to 09 EEPROM R/W 00 VCClimhi (MSB to LSB) Contains upper limit settings for VCC. If the limit is violated, a flag in Main Device byte 70h is set. 0A to 0B EEPROM R/W 00 VCClimlo (MSB to LSB) Contains lower limit settings for VCC. If the limit is violated, a flag in Main Device byte 70h is set. 0C to 0F EEPROM 00 Reserved — 10 to 11 EEPROM R/W 00 Contains upper limit settings for MON1. If the MON1limhi (MSB to LSB) limit is violated, a flag in Main Device byte 70h is set. 12 to 13 EEPROM R/W 00 Contains lower limit settings for MON1. If the MON1limlo (MSB to LSB) limit is violated, a flag in Main Device byte 70h is set. 14 to 17 EEPROM 00 Reserved — Contains upper limit settings for MON2. If the 18 to 19 EEPROM R/W 00 MON2limhi (MSB to LSB) limit is violated, a flag in Main Device byte 70h is set. Contains lower limit settings for MON2. If the 1A to 1B EEPROM R/W 00 MON2limlo (MSB to LSB) limit is violated, a flag in Main Device byte 70h is set. Note: SRAM defaults are power-on defaults. EEPROM defaults are factory defaults. 12 ____________________________________________________________________ Dual Temperature-Controlled Resistors with Two Monitors DS1854 Main Device (continued) MEMORY LOCATION EEPROM/ SRAM 1C to 5F EEPROM R/W DEFAULT SETTING NAME OF LOCATION FUNCTION 00 Reserved Digitized measured value for temperature. See Table 1. — Digitized measured value for VCC. See Table 1. 60 to 61 SRAM R — Measured TMP (MSB to LSB) 62 to 63 SRAM R — Measured VCC (MSB to LSB) 64 to 65 SRAM R — Measured MON1 (MSB to LSB) Digitized measured value for MON1. See Table 1. 66 to 67 SRAM R — Measured MON2 (MSB to LSB) Digitized measured value for MON2. See Table 1. 68 to 6D SRAM R 6E SRAM — Reserved — — Logic states — Bit 7 — R X HIZSTA Resistor status bit. A high indicates that both resistors are in high-impedance mode. A low indicates that both resistors are operating normally. 6 — R/W 0 HIZCO Resistor control bit. Setting this bit high causes both resistors to go into a highimpedance state. 5 — X X — 4 — X X — 3 — X X — 2 — R X TXF This status bit is high when OUT1 is high assuming there is an external pullup resistor on OUT1. 1 — R X RXL This status bit is high when OUT2 is high assuming there is an external pullup resistor on OUT2. 0 — R X RDYB This status bit goes high when VCC has fallen below the POA level. 6F SRAM — — Conversion updates — TAU This bit goes high after a temperature and address update has occurred for the corresponding measurement in bytes 60h to 61h. This bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. Bit 7 — R/W 0 ____________________________________________________________________ 13 DS1854 Dual Temperature-Controlled Resistors with Two Monitors Main Device (continued) MEMORY LOCATION 6 5 14 EEPROM/ SRAM — — R/W R/W R/W DEFAULT SETTING 0 0 NAME OF LOCATION FUNCTION VCCU This bit goes high after a VCC update has occurred for the corresponding measurement in bytes 62h to 63h. This bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. MON1U This bit goes high after a MON1 update has occurred for the corresponding measurement in bytes 64h to 65h. This bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. 4 — R/W 0 MON2U This bit goes high after a MON2 update has occurred for the corresponding measurement in bytes 66h to 67h. This bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. 3 — — 0 0 — 2 — — 0 0 — 1 — — 0 X — 0 — — 0 X — 70 SRAM R — Alarm flags — Bit 7 — — — TMPhi This alarm flag goes high when the upper limit of the temperature setting is violated. 6 — — — TMPlo This alarm flag goes high when the lower limit of the temperature setting is violated. 5 — — — VCChi This alarm flag goes high when the upper limit of the VCC setting is violated. ____________________________________________________________________ Dual Temperature-Controlled Resistors with Two Monitors MEMORY LOCATION EEPROM/ SRAM R/W DEFAULT SETTING NAME OF LOCATION FUNCTION 4 — — — VCClo This alarm flag goes high when the lower limit of the VCC setting is violated. 3 — — — MON1hi This alarm flag goes high when the upper limit of the MON1 setting is violated. 2 — — — MON1lo This alarm flag goes high when the lower limit of the MON1 setting is violated. 1 — — — MON2hi This alarm flag goes high when the upper limit of the MON2 setting is violated. 0 — — — MON2lo This alarm flag goes high when the lower limit of the MON2 setting is violated. — 71 SRAM R — Alarm flags Bit 7 — — — X — 6 — — — X — 5 — — — X — 4 — — — X — 3 — — — X — 2 — — — X — 1 — — — X — 0 — — — MINT A mask of all flags located in Table 01 byte 88h determines the value of MINT. MINT is maskable to 0 if no interrupt is desired by setting Table 01 byte 88h to 0. 72 to 7E SRAM R 00 Reserved — 7F SRAM R/W Table select — Bit 7 — — 0 X — 6 — — 0 X — 5 — — 0 X — 4 — — 0 X — 3 — — 0 X — 2 — — 0 X — Table select bits Set bits = 00 to select Table 00, set bits = 01 to select Table 01, set bits = 10 to select Table 02, set bits = 11 to select Table 03. 1 — — 0 0 — — 0 ____________________________________________________________________ 15 DS1854 Main Device (continued) DS1854 Dual Temperature-Controlled Resistors with Two Monitors Table 01h MEMORY EEPROM/ LOCATION SRAM 16 R/W DEFAULT SETTING NAME OF LOCATION FUNCTION 80 SRAM R/W — Mode — Bit 7 — — 0 X — 6 — — 0 X — 5 — — 0 X — 4 — — 0 X — 3 — — 0 X — 2 — — 0 X — 1 — — 1 TEN If TEN = 0, the temperature conversions update and the resistors can be controlled manually. The user sets the resistor in manual mode by writing to addresses 82h and 83h in Table 01 to control resistors 0 and 1, respectively. 0 — — 1 AEN AEN = 0 provides manual control of the temperature index. 81 SRAM R — Temp index This byte is the temperature-calculated index used to select the address of resistor settings in the look-up tables. 82 SRAM R/W 00 Resistor 0 Resistor 0 position values from 00h to FFh. 83 SRAM R/W 00 Resistor 1 Resistor 1 position values from 00h to FFh. 84 to 87 SRAM 00 Reserved — This byte configures a maskable interrupt, determining which event asserts a buffer 1 output (MINT set to 1, see register 89h in Table 01). If any combination of temperature, VCC, MON1, or MON2 is desired to generate an interrupt, the corresponding bits are set to 1. If interrupt generation is not desired, set all bits to 0. 88 EEPROM R/W — Interrupt enable Bit 7 — — 1 TMP — 6 — — 1 VCC — 5 — — 1 MON1 — 4 — — 1 MON2 — 3 — — 0 X — 2 — — 0 X — 1 — — 0 X — 0 — — 0 X — — 89 EEPROM R/W — Configuration Bit 7 — — 0 X — 6 — — 0 X — ____________________________________________________________________ Dual Temperature-Controlled Resistors with Two Monitors MEMORY EEPROM/ LOCATION SRAM R/W DEFAULT SETTING NAME OF LOCATION FUNCTION 5 — — 0 ADEN Controls if the device responds to one or two device addresses (see the Memory Description section and Table 5). 4 — — 0 ADFIX Controls the means by which Main and Auxiliary Device addresses are set (see the Memory Description section and Table 5). 3 — — 0 APEN Controls auxiliary write protect. See Memory Description 2 — — 0 MPEN Controls Main Device write protect. See the Memory Description section. 1 — — 0 INV1 Configures buffer 1 with OUT1 = MINT + (INV1 [XOR] IN1) 0 — — 0 INV2 Configures buffer 2 with OUT2 = INV2 [XOR] IN2 8A to 8B EEPROM — 00 Reserved — 8C EEPROM R/W A2 Device address Contains Main Device address if the bit ADFIX = 1. If ADFIX = 0, then address A2h is used. 8D to 8F EEPROM — — Reserved — Table 02h MEMORY LOCATION EEPROM/ SRAM R/W DEFAULT SETTING NAME OF LOCATION 80 to C7 EEPROM F0 to FF EEPROM R/W FF Resistor 0 Temp LUT R FF Reserved — MEMORY LOCATION EEPROM/ SRAM R/W DEFAULT SETTING NAME OF LOCATION FUNCTION 80 to C7 EEPROM R/W FF Resistor 1 Temp LUT F0 to FF EEPROM R FF Reserved FUNCTION Look-up table for Resistor 0. Table 03h Look-up table for Resistor 1. — ____________________________________________________________________ 17 DS1854 Table 01h (continued) Temperature Conversion The direct-to-digital temperature sensor measures temperature through the use of an on-chip temperature measurement technique with an operating range from -40°C to +102°C. Temperature conversions are initiated upon power-up, and the most recent conversion is stored in memory locations 60h and 61h of the Main Device, which are updated every tframe. Temperature conversions do not occur during an active read or write to memory. The value of each resistor is determined by the temperature-addressed look-up table. The look-up table assigns a unique value to each resistor for every 2°C increment with a 1°C hysteresis at a temperature transition over the operating temperature range (see Figure 4). M6 M5 DECREASING TEMPERATURE MEMORY LOCATION DS1854 Dual Temperature-Controlled Resistors with Two Monitors M4 M3 INCREASING TEMPERATURE M2 M1 2 During power-up, the device is inactive until V CC exceeds the digital power-on-reset voltage (POD). At this voltage, the digital circuitry, which includes the 2-wire interface, becomes functional. However, EEPROM backed registers/settings cannot be internally read (recalled into shadow SRAM) until VCC exceeds the analog power-on-reset voltage (POA) at which time the remainder of the device becomes fully functional. Once VCC exceeds POA, the RDYB bit in byte 6Eh of the Main Device memory is timed to go from a 1 to a 0 and indicates when analog to digital conversions begin. If VCC ever dips below POA, the RDYB bit will read as a 1 again. Once a device exceeds POA and the EEPROM is recalled, the values remain active (recalled) until VCC falls below POD. For 2-wire device addresses sourced from EEPROM (ADFIX = 1), the device address defaults to A2h until VCC exceeds POA and the EEPROM values are recalled. The Auxiliary Device (A0h) is always available within this voltage window (between POD and the EEPROM recall) regardless of the programmed state of ADEN. Furthermore, as the device powers-up, the VCClo alarm flag (bit 4 of 70h in Main Device) will default to a 1 until the first VCC analog-to-digital conversion occurs and sets or clears the flag accordingly. 2-Wire Operation Clock and Data Transitions: The SDA pin is normally pulled high with an external resistor or device. Data on the SDA pin may only change during SCL-low time periods. Data changes during SCL-high periods will indicate a start or stop condition depending on the conditions discussed below. See the timing diagrams in Figures 5 and 6 for further details. 18 4 6 8 10 12 TEMPERATURE (°C) Power-Up and Low-Voltage Operation Figure 4. Look-Up Table Memory Hysteresis Start Condition: A high-to-low transition of SDA with SCL high is a start condition, which must precede any other command. See the timing diagrams in Figures 5 and 6 for further details. Stop Condition: A low-to-high transition of SDA with SCL high is a stop condition. After a read or write sequence, the stop command places the DS1854 into a low-power mode. See the timing diagrams in Figures 5 and 6 for further details. Acknowledge: All address and data bytes are transmitted through a serial protocol. The DS1854 pulls the SDA line low during the ninth clock pulse to acknowledge that it has received each word. Standby Mode: The DS1854 features a low-power mode that is automatically enabled after power-on, after a stop command, and after the completion of all internal operations. Device Addressing: The DS1854 must receive an 8-bit device address word following a start condition to enable a specific device for a read or write operation. The address word is clocked into this part’s MSB to LSB. The address byte consists of Ah followed by A2h or the value in Table 01 8Ch for the Main Device, or A0h for the Auxiliary Device then the R/W bit. This byte must match the address programmed into Table 01 8Ch or A0h (for the Auxiliary Device). If a device address match occurs, this part will output a zero for one clock cycle as an acknowledge and the corresponding block of memory is enabled (see the Memory Organization section). If the R/W bit is high, a read operation is initiated. If the R/W is low, a write operation is initiated (see the Memory Organization section). If ____________________________________________________________________ Dual Temperature-Controlled Resistors with Two Monitors be allowed to proceed if the internal write cycle has completed and the DS1854 responds with a zero. Write Operations Read Operations After receiving a matching address byte with the R/W bit set low, provided there is no write protect, the device goes into the write mode of operation (see the Memory Organization section). The master must transmit an 8-bit EEPROM memory address to the device to define the address where the data is to be written. After the byte has been received, the DS1854 transmits a zero for one clock cycle to acknowledge the address has been received. The master must then transmit an 8-bit data word to be written into this address. The DS1854 again transmits a zero for one clock cycle to acknowledge the receipt of the data. At this point, the master must terminate the write operation with a stop condition. The DS1854 then enters an internally timed write process tw to the EEPROM memory. All inputs are disabled during this byte write cycle. After receiving a matching address byte with the R/W bit set high, the device goes into the read mode of operation. There are three read operations: current address read, random read, and sequential address read. Page Write The DS1854 is capable of an 8-byte page write. A page is any 8-byte block of memory starting with an address evenly divisible by eight and ending with the starting address plus seven. For example, addresses 00h through 07h constitute one page. Other pages would be addresses 08h through 0Fh, 10h through 17h, 18h through 1Fh, etc. A page write is initiated the same way as a byte write, but the master does not send a STOP condition after the first byte. Instead, after the slave acknowledges the data byte has been received, the master can send up to seven more bytes using the same nine-clock sequence. The master must terminate the write cycle with a STOP condition or the data clocked into the DS1854 will not be latched into permanent memory. The address counter rolls on a page during a write. The counter does not count through the entire address space as during a read. For example, if the starting address is 06h and 4 bytes are written, the first byte goes into address 06h. The second goes into address 07h. The third goes into address 00h (not 08h). The fourth goes into address 01h. If more than 9 bytes or more are written before a STOP condition is sent, the first bytes sent are overwritten. Only the last 8 bytes of data are written to the page. Acknowledge Polling: Once the internally timed write has started and the DS1854 inputs are disabled, acknowledge polling can be initiated. The process involves transmitting a start condition followed by the device address. The R/W bit signifies the type of operation that is desired. The read or write sequence will only Current Address Read The DS1854 has an internal address register that maintains the address used during the last read or write operation, incremented by one. This data is maintained as long as VCC is valid. If the most recent address was the last byte in memory, then the register resets to the first address. Once the device address is clocked in and acknowledged by the DS1854 with the R/W bit set to high, the current address data word is clocked out. The master does not respond with a zero, but does generate a stop condition afterwards. Single Read A random read requires a dummy byte write sequence to load in the data byte address. Once the device and data address bytes are clocked in by the master, and acknowledged by the DS1854, the master must generate another start condition. The master now initiates a current address read by sending the device address with the R/W bit set high. The DS1854 acknowledges the device address and serially clocks out the data byte. Sequential Address Read Sequential reads are initiated by either a current address read or a random address read. After the master receives the first data byte, the master responds with an acknowledge. As long as the DS1854 receives this acknowledge after a byte is read, the master can clock out additional data words from the DS1854. After reaching address FFh, it resets to address 00h. The sequential read operation is terminated when the master initiates a stop condition. The master does not respond with a zero. For a more detailed description of 2-wire theory of operation, see the following section. 2-Wire Serial Port Operation The 2-wire serial port interface supports a bidirectional data transmission protocol with device addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are ____________________________________________________________________ 19 DS1854 the address does not match, this part returns to a lowpower mode. DS1854 Dual Temperature-Controlled Resistors with Two Monitors slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the start and stop conditions. The DS1854 operates as a slave on the 2-wire bus. Connections to the bus are made through the opendrain I/O lines SDA and SCL. The following I/O terminals control the 2-wire serial port: SDA, SCL. Timing diagrams for the 2-wire serial port can be found in Figures 5 and 6. Timing information for the 2-wire serial port is provided in the AC Electrical Characteristics table for 2-wire serial communications. The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. Start data transfer: A change in the state of the data line from high to low while the clock is high defines a start condition. Stop data transfer: A change in the state of the data line from low to high while the clock line is high defines the stop condition. Data valid: The state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line can be changed during the low period of the clock signal. There is one clock pulse per bit of data. Figures 5 and 6 detail how data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of data transfer are possible. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. The DS1854 works in both modes. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse, which is associated with this acknowledge bit. 20 A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the stop condition. 1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the command/control byte. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. 2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the command/control byte) to the slave. The slave then returns an acknowledge bit. Next follows a number of data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a not acknowledge can be returned. The master device generates all serial clock pulses and the start and stop conditions. A transfer is ended with a stop condition or with a repeated start condition. Since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. The DS1854 can operate in the following three modes: 1) Slave Receiver Mode: Serial data and clock are received through SDA and SCL, respectively. After each byte is received, an acknowledge bit is transmitted. Start and stop conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after the slave (device) address and direction bit have been received. 2) Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS1854 while the serial clock is input on SCL. Start and stop conditions are recognized as the beginning and end of a serial transfer. 3) Slave Address: Command/control byte is the first byte received following the start condition from the master device. The command/control byte consists of a 4-bit control code. They are used by the master device to select which of eight possible devices on the bus is to be accessed. When reading or writing ____________________________________________________________________ Dual Temperature-Controlled Resistors with Two Monitors TRANSISTOR COUNT: 44419 SUBSTRATE CONNECTED TO GROUND DS1854 the DS1854, the device-select bits must match one of two valid device addresses, 00h or the address registered in Table 01 location 8Ch. The last bit of the command/control byte (R/W) defines the operation to be performed. When set to a ‘1’ a read operation is selected, and when set to a ‘0’ a write operation is selected. The slave address can be set by the EEPROM. Following the start condition, the DS1854 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving the 1010 control code, the appropriate device address bits, and the read/write bit, the slave device outputs an acknowledge signal on the SDA line. Chip Topology SDA MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 START CONDITION 6 7 8 9 1 2 3–7 8 ACK 9 ACK REPEATED IF MORE BYTES ARE TRANSFERRED STOP CONDITION OR REPEATED START CONDITION Figure 5. 2-Wire Data Transfer Protocol ____________________________________________________________________ 21 DS1854 Dual Temperature-Controlled Resistors with Two Monitors SDA tBUF tHD:STA tLOW tR tSP tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START REPEATED START tSU:STO tHD:DAT Figure 6. 2-Wire AC Characteristics Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.