ETC MTV130

MYSON
TECHNOLOGY
MTV130
On-Screen Display for LCD Monitor
FEATURES
GENERAL DESCRIPTION
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MTV130 is designed for LCD monitor applications to
display built-in characters or fonts onto an LCD monitor
screens. The display operation occurs by transferring data
and control information from the micro-controller to RAM
through a serial data interface. It can execute full-screen
display automatically, as well as specific functions such as
character background, bordering, shadowing, blinking,
double height and width, font by font color control, frame
positioning, frame size control by character height and rowto-row spacing, horizontal display resolution, full-screen
erasing, fade-in/fade-out effect, windowing effect, shadowing on window and full-screen self-test pattern generator.
MTV130 provides true 512 fonts including 496 standard
fonts and 16 multi-color fonts and 2 font sizes, 12x16 or
12x18 for more efficacious applications. So each one of the
512 fonts can be displayed at the same time. The full OSD
menu is formed by 15 rows x 30 columns, which can be
positioned anywhere on the monitor screen by changing
vertical or horizontal delay.
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Horizontal SYNC input up to 150 KHz.
Acceptable wide-range pixel clock up to 150 MHz.
Full screen self-test pattern generator.
Full-screen display consists of 15 (rows) by 30 (columns)
characters.
Two font size 12x16 or 12x18 dot matrix per character.
True totally 512 mask ROM fonts including 496 standard
fonts and 16 multi-color fonts.
8 color selection maximum per display character.
Double character height and/or width control.
Programmable positioning for display screen center.
Character bordering, shadowing and blinking effect.
Programmable character height (18 to 71 lines) control.
Row to row spacing control to avoid expansion distortion.
4 programmable windows with multi-level operation.
Shadowing on windows with programmable shadow
width/height/color.
Software clears bit for full-screen erasing.
Intensity and fast blanking output.
Fade-in/fade-out or blending-in/blending-out effects.
4-channel/8-bit PWM D/A converter output.
Compatible with SPI bus or I2C interface with slave
address 7AH (slave address is mask option).
16-pin or 20-pin PDIP/SOP package.
BLOCK DIAGRAM
SSB
VDD
8 DATA
SERIAL DATA
INTERFACE
SCK
DATA 8
DISPLAY & ROW
CONTROL
REGISTERS
9 ROW, COL
CWS
CHS
ACK
LUMAR
LUMAG
LUMAB
BLINK
8 CRADDR
VDDA
SDA
ARWDB
HDREN
VDREN
NROW
ADDRESS BUS
ADMINISTRATOR
5
9
9
5
5
RCADDR
DADDR
FONTADDR
WINADDR
PWMADDR
DATA
8
LPN
5
CWS
VCLKS
VSP
CH 7
CHS
VERTD 8
HFLB
HSP
XIN
HORD 8
VERTICAL
DISPLAY
CONTROL
HORIZONTAL
DISPLAY CONTROL
CLOCK
GENERATOR
5 LPN
DATA 8
8 VERTD
8 HORD
7
CH
NROW
VDREN
CHARACTER ROM
USER FONT RAM
LUMA
VSSA
BORDER
LUMINANCE &
BORDGER
GENERATOR
WINDOWS &
FRAME
CONTROL
BSEN
SHADOW
OSDENB
HSP
VSP
WR
WG
WB
FBKGC
BLANK
VFLB
NC
VSS
ARWDB
HDREN
LUMAR
LUMAG
LUMAB
BLINK
VCLKX
VCLKX
ROUT
GOUT
COLOR
ENCODER
BOUT
FBKG
HTONE
PWM0
PWM1
PWM2
PWM3
PWM D/A
CONVERTER
POWER ON
RESET
8 DATA
PRB
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Revision 1.0
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TECHNOLOGY
MTV130
1.0 PIN CONNECTION
1
20
VSS
ROUT
XIN
2
19
ROUT
GOUT
NC
3
18
GOUT
13
BOUT
VDD
4
17
BOUT
12
FBKG
HFLB
5
16
FBKG
15
INT
14
VFLB
16
XIN
2
15
NC
3
14
VDD
4
HFLB
5
MTV130P-xx
1
VSS
SSB
6
11
INT
SSB
6
SDA
7
10
VFLB
SDA
7
SCK
8
9
VDD
MTV130P20-xx
VSS
VSS
SCK
8
13
VDD
PWM0
9
12
PWM3
PWM1
10
11
PWM2
2.0 PIN DESCRIPTIONS
Name
I/O
Pin No.
P16
P20
Descriptions
VSS
-
1
1
Ground. This ground pin is used to internal circuitry.
XIN
I
2
2
Pixel clock input. This is a clock input pin. MTV130 is driven by an
external pixel clock source for all the logics inside. The frequency of XIN
must be the integral time of pin HFLB.
NC
I
3
3
No connection.
VDD
-
4
4
Power supply. Positive 5 V DC supply for internal circuitry. And a 0.1uF
decoupling capacitor should be connected across to VDD and VSS.
HFLB
I
5
5
Horizontal input. This pin is used to input the horizontal synchronizing
signal. It is a leading edge triggered and has an internal pull-up resistor.
SSB
I
6
6
Serial interface enable. It is used to enable the serial data and is also
used to select the operation of I2C or SPI bus. If this pin is left floating,
I2C bus is enabled, otherwise the SPI bus is enabled.
SDA
I
7
7
Serial data input. The external data transfer through this pin to internal
display registers and control registers. It has an internal pull-up resistor.
SCK
I
8
8
Serial clock input. The clock-input pin is used to synchronize the data
transfer. It has an internal pull-up resistor.
PWM0
O
-
9
Open-Drain PWM D/A converter 0. The output pulse width is programmable by the register of Row 15, Column 23.
PWM1
O
-
10
Open-Drain PWM D/A converter 1. The output pulse width is programmable by the register of Row 15, Column 24.
PWM2
O
-
11
Open-Drain PWM D/A converter 2. The output pulse width is programmable by the register of Row 15, Column 25.
PWM3
O
-
12
Open-Drain PWM D/A converter 3. The output pulse width is programmable by the register of Row 15, Column 26.
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Name
I/O
Pin No.
P16
P20
MTV130
Descriptions
VDD
-
9
13
Power supply. Positive 5 V DC supply for internal circuitry and a 0.1uF
decoupling capacitor should be connected across to VDD and VSS.
VFLB
I
10
14
Vertical input. This pin is used to input the vertical synchronizing signal.
It is leading triggered and has an internal pull-up resistor.
INT
O
11
15
Intensity color output. 16-color selection is achievable by combining
this intensity pin with R/G/B output pins.
FBKG
O
12
16
Fast Blanking output. It is used to cut off external R, G, B signals of
VGA while this chip is displaying characters or windows.
BOUT
O
13
17
Blue color output. It is a blue color video signal output.
GOUT
O
14
18
Green color output. It is a green color video signal output.
ROUT
O
15
19
Red color output. It is a red color video signal output.
VSS
-
16
20
Ground. This ground pin is used to internal circuitry.
3.0 FUNCTIONAL DESCRIPTIONS
3.1 SERIAL DATA INTERFACE
The serial data interface receives data transmitted from an external controller. And there are 2 types of bus
can be accessed through the serial data interface, one is SPI bus and other is I2C bus.
3.1.1 SPI bus
While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission
should be starting from pulling SSB to "low" level, enabling MTV130 to receiving mode, and retain "low" level
until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.
SSB
SCK
SDA
MS
B
LSB
first byte
last byte
FIGURE 1. Data Transmission Protocol (SPI)
There are three transmission formats shown as below:
Format (a) R - C - D → R - C - D → R - C - D .....
Format (b) R - C - D → C - D → C - D → C - D .....
Format (c) R - C - D → D → D → D → D → D .....
Where R=Row address, C=Column address, D=Display data
3.1.2 I2C bus
I2C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting
from writing the slave address 7AH to MTV130. The protocol is shown in Figure 2.
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MTV130
SCK
SDA
B7
START
B6
B0
B7
B0
ACK
First byte
ACK
second byte
STOP
last byte
FIGURE 2. Data Transmission Protocol (I2C)
There are three transmission formats shown as below:
Format (a) S - R - C - D → R - C - D → R - C - D .....
Format (b) S - R - C - D → C - D → C - D → C - D .....
Format (c) S - R - C - D → D → D → D → D → D .....
Where S=Slave address, R=Row address, C=Column address, D=Display data
Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and
Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with different
row address and column address. Format (b) is recommended for updating data that has same row address
but different column address. Massive data updating or full screen data change should use format (c) to
increase transmission efficiency. The row and column address will be incremented automatically when the format (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with dummy
data.
TABLE 1. The configuration of transmission formats.
Address Bytes
of Display Reg.
Attribute Bytes
of Display Reg.
Address
b7
b6
b5
b4
b3
b2
b1
b0
Format
Row
1
0
0
x
R3
R2
R1
R0
a,b,c
Columnab
0
0
D8
C4
C3
C2
C1
C0
a,b
Columnc
0
1
D8
C4
C3
C2
C1
C0
c
Data
D7
D6
D5
D4
D3
D2
D1
D0
a,b,c
Row
1
0
1
R4
R3
R2
R1
R0
a,b,c
Columnab
0
0
x
C4
C3
C2
C1
C0
a,b
Columnc
0
1
x
C4
C3
C2
C1
C0
c
Data
D7
D6
D5
D4
D3
D2
D1
D0
a,b,c
There are 2 types of data should be accessed through the serial data interface, one is ADDRESS bytes of display registers, and other is ATTRIBUTE bytes of display registers, the protocol are same for all except the bit5
of row address and the bit5 of column address. The MSB(b7) is used to distinguish row and column
addresses when transferring data from external controller. The bit6 of column address is used to differentiate
the column address for format (a), (b) and format (c) respectively. Bit5 of row address for display register is
used to distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1". And at
address bytes, bit5 of column address is the MSB (bit8) and data bytes are the 8 LSB (bit7~bit0) of display fonts address to save half MCU memory for true 512 fonts. So each one of the 512 fonts can be displayed at the same time. See Table 1. And for format (c), since D8 is filled while program column address of
address bytes, the continued data will be the same bank of upper 256 fonts or lower 256 fonts until program
column address of address bytes again.
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format
(a) and (c), but not from format (c) back to format (a) and (b). The alternation between transmission formats is
configured as the state diagram shown in Figure 3.
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MTV130
0, X
Input = b7, b6
Initiate
1, X
ROW
1, X
format (c)
0,
0,
X, X
0
format (b)
1
0, 0
COL c
X,
format (a)
0,
1
COL ab
X,
X
1, X
X
DA c
DA ab
FIGURE 3. Transmission State Diagram
3.2 Address bus administrator
The administrator manages bus address arbitration of internal registers or user fonts RAM during external
data write in. The external data write through serial data interface to registers must be synchronized by internal display timing. In addition, the administrator also provides automatic increment to address bus when external write using format (c).
3.3 Vertical display control
The vertical display control can generates different vertical display sizes for most display standards in current
monitors. The vertical display size is calculated with the information of double character height bit(CHS), vertical display height control register(CH6-CH0).The algorithm of repeating character line display are shown as
Table 2 and Table 3. The programmable vertical size range is 270 lines to maximum 2130 lines.
The vertical display center for full screen display could be figured out according to the information of vertical
starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB,
is calculated with the following equation:
Vertical delay time = ( VERTD * 4 + 1 ) * H
Where H = one horizontal line display time
TABLE 2. Repeat line weight of character
CH6 - CH0
CH6,CH5=11
CH6,CH5=10
CH6,CH5=0x
CH4=1
CH3=1
CH2=1
CH1=1
CH0=1
Revision 1.0
Repeat Line Weight
+18*3
+18*2
+18
+16
+8
+4
+2
+1
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MTV130
TABLE 3. Repeat line number of character
Repeat Line #
Repeat Line
Weight
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17
+1
v
+2
v
v
+4
v
v
v
v
+8
v
v
v
v
v
v
v
v
+16
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
+17
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
+18
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the
character would not be repeated.
3.4 Horizontal display control
The horizontal display control is used to generate control timing for horizontal display based on double character width bit (CWS), horizontal positioning register (HORD) and HFLB input. A horizontal display line
includes 360 dots for 30 display characters and the remaining dots for blank region. The horizontal delay
starting from HFLB leading edge is calculated with the following equation,
Horizontal delay time = ( HORD * 6 + 49) * P
Where P = 1 XIN pixel display time
3.5 Display & Row control registers
The internal RAM contains display and row control registers. The display registers have 450 locations which
are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4 and Figure 5. Each display register has its corresponding character address on ADDRESS byte, its corresponding background color,
1 blink bit and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at column 30 for row 0 to row 14 of attribute bytes, it is used to set character size to each respective row. If double
width character is chosen, only even column characters could be displayed on screen and the odd column
characters will be hidden.
ROW #
COLUMN #
0 1
28 29
30
0
1
CHARACTER ADDRESS BYTES
of DISPLAY REGISTERS
ROW
ATTRIBUTE
CRTL REG
13
14
31
R
E
S
E
R
V
E
D
FIGURE 4. Address Bytes of Display Registers Memory Map
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ROW #
MTV130
COLUMN #
0 1
28 29
30
31
0
1
CHARACTER ATTRIBUTE BYTES
of DISPLAY REGISTERS
RESERVED
13
14
ROW 15
ROW 16
0
WINDOW1 ~ WINDOW4
COLUMN#
11 12
22
FRAME
CRTL REG
23
27
PWM D/A
CRTL REG
28
31
RESERVED
COLUMN#
1 2
0
31
WINDOW SHADOW COLOR
RESERVED
FIGURE 5. Attribute Bytes of Display Registers Memory Map
ADDRESS BYTES:
Address registers,
b8
b7
b6
b5
b4
CRADDR
b3
b2
b1
MSB
b0
LSB
CRADDR - Define ROM character address from address 0 to 511.
Row Control Registers, (Row 0 - 14)
b7
b6
b5
COLN 30
-
b4
b3
b2
b1
b0
-
-
-
CHS
CWS
CHS - Define double height character to the respective row.
CWS - Define double width character to the respective row.
ATTRIBUTE BYTES:
b7
b6
b5
-
BGR
BGG
b4
b3
b2
b1
b0
BGB
BLINK
R
G
B
BGR, BGG, BGB - These three bits define the color of the background for its relative address character. If all
three bits are clear, no background will be shown(transparent). Therefore, total 7 background color can be selected.
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BLINK - Enable blinking effect while this bit is set to " 1 ". And the blinking is alternate per 32 vertical frames.
R, G, B - These three bits are used to specify its relative address character color.
3.6 Character ROM
MTV130 character ROM contains 512 built-in characters and symbols including 496 standard fonts and 16
multi-color fonts. The 496 standard fonts are located from address 0 to 495. And the 16 multi-color fonts are
located from address 496 to 511. Each character and symbol consists of 12x18 dots matrix. The detail pattern
structures for each character and symbols are shown in “CHARACTERS AND SYMBOLS PATTERN” on
page 18.
3.7 Multi-Color Font
The color fonts comprises three different R, G, B fonts. When the code of color font is accessed, the separate
R/G/B dot pattern is output to corresponding R/G/B output. See Figure 6 for the sample displayed color font.
Note: No black color can defined in color font, black window underline the color font can make the dots
become black in color. The detail pattern structures for each character and symbols are shown in “CHARACTERS AND SYMBOLS PATTERN” on page 18.
B
G
R
Magent
Green
Blue
Cyan
FIGURE 6. Example of Multi-Color Font
TABLE 4. The Multi-Color Font Color Selection
Background Color
Blue
Green
Cyan
Red
Magent
Yellow
White
R
0
0
0
0
1
1
1
1
G
0
0
1
1
0
0
1
1
B
0
1
0
1
0
1
0
1
3.8 Luminance & border generator
There are 3 shift registers included in the design which can shift out of luminance and border dots to color
encoder. The bordering and shadowing feature is configured in this block. For bordering effect, the character
will be enveloped with blackedge on four sides. For shadowing effect, the character is enveloped with
blackedge for right and bottom sides only.
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MTV130
3.9 Window and frame control
The display frame position is completely controlled by the contents of VERTD and HORD. The window size
and position control are specified in column 0 to 11 on row 15 of memory map, as shown in Figure 5. Window
1 has the highest priority, and window 4 is the least, when two windows are overlapping. More detailed information is described as follows:
1. Window control registers,
ROW 15
b7
b6
b5
Column
ROW START ADDR
0,3,6,OR 9
MSB
b4
b2
b1
ROW END ADDR
LSB MSB
b7
Column
1,4,7,OR 10 MSB
b6
b5
b4
COL START ADDR
b7
b6
b5
b4
COL END ADDR
Column
2,5,8,OR 11
b3
LSB
b3
LSB
b2
b1
b0
WEN
-
WSHD
b2
b1
b0
R
G
B
b3
MSB
b0
LSB
START(END) ADDR - These addresses are used to specify the window size. It should be noted that when the
start address is greater than the end address, the window will be disabled.
WEN - Enable the relative background window display.
WSHD - Enable shadowing on the window.
R, G, B - Specify the color of the relative background window.
2. Frame control registers,
ROW 15
b7
b6
b5
Column 12
b4
b3
VERTD
b2
b1
MSB
b0
LSB
VERTD - Specify the starting position for vertical display. The total steps are 256, and the increment of each
step is 4 Horizontal display lines. The initial value is 4 after power up.
b7
b6
b5
Column 13
b4
b3
HORD
b2
b1
MSB
b0
LSB
HORD - Define the starting position for horizontal display. The total steps are 256, and the increment of each
step is 6 dots. The initial value is 15 after power up.
Column 14
b7
-
b6
CH6
b5
CH5
b4
CH4
b3
CH3
b2
CH2
b1
CH1
b0
CH0
CH6-CH0 - Define the character vertical height, the height is programmable from 18 to 71 lines. The character
vertical height is at least 18 lines if the contents of CH6-CH0 is less than 18. For example, when
the contents is " 2 ", the character vertical height is regarded as equal to 20 lines. And if the conRevision 1.0
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tents of CH4-CH0 is greater than or equal to 18, it will be regarded as equal to 17. See Table 2
and Table 3 for detail description of this operation.
Column 15
b7
b6
b5
b4
b3
Reserved
b2
b1
b0
b2
b1
RSPACE
b0
This byte is reserved for internal testing.
Column 16
b7
-
b6
-
b5
-
b4
b3
MSB
LSB
RSPACE - Define the row to row spacing in unit of horizontal line. That is, extra RSPACE horizontal lines will
be appended below each display row, and the maximum space is 31 lines. The initial value is 0
after power up.
Column 17
b7
OSDEN
b6
BSEN
b5
SHADOW
b4
FBEN
b3
BLEND
b2
WENCLR
b1
RAMCLR
b0
FBKGC
OSDEN - Activate the OSD operation when this bit is set to "1". The initial value is 0 after power up.
BSEN - Enable the bordering and shadowing effect.
SHADOW - Bordering and shadowing effect select bit. Activate the shadowing effect if this bit is set, otherwise
the bordering is chosen.
FBEN - Enable the fade-in/fade-out and blending-in/blending-out effect when OSD is turned on from off state
or vice verca.
BLEND - Fade-in/fade-out and blending-in/blending-out effect select bit. Activate the blendinf-in/blending-out
function if this bit is set, otherwise the fade-in/fade-out function is chosen. These function roughly
takes about 0.5 second to fully display the whole menu or to disappear completely.
WENCLR - Clear all WEN bits of window control registers when this bit is set to "1". The initial value is 0 after
power up.
RAMCLR - Clear all ADDRESS bytes, BGR, BGG, BGB and BLINK bits of display registers when this bit is set
to "1". The initial value is 0 after power up.
FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs high during the
displaying of characters or windows, otherwise, it outputs high only during the displaying of character.
Column 18
B7
TRIC
b6
FSS
b5
-
b4
DWE
b3
HSP
b2
VSP
b1
PWM1
b0
PWM0
TRIC - Define the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That is,
while OSD is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins are
in high impedance state. The initial value is 0 after power up.
FSS - Font size selection.
= 1 ⇒ 12x18 font size selected.
= 0 ⇒ 12x16 font size selected.
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Output display if FSS=0; first and last lines omitted
Fonts designed to be 12x18 display
FIGURE 7. 12x18 and 12x16 Fonts
DWE - Enable double width. When the bit is set to “1”, the display of OSD menu can change to half resolution
for double character width, and then the number of pixels of each line should be even. The initial value
is 0 after power up.
HSP -
= 1 ⇒ Accept positive polarity Hsync input.
= 0 ⇒ Accept negative polarity Hsync input.
VSP -
= 1 ⇒ Accept positive polarity Vsync input.
= 0 ⇒ Accept negative polarity Vsync input.
PWM1, PWM0 - Select the PWMCK output frequency.
= (0, 0) ⇒ XIN frequency /8
= (0, 1) ⇒ XIN frequency /4
= (1, 0) ⇒ XIN frequency /2
= (1, 1) ⇒ XIN frequency /1
The initial value is (0, 0) after power up.
Notes : When XIN is not present, don’t write data in any address. If data is written in any other address, a
malfunction may occur.
TABLE 5. PWMCK Frequency and PWMDA sampling rate
(PWM1, PWM0)
( 0, 0 )
( 0, 1 )
( 1, 0 )
( 1 ,1 )
Column 19
PWMCK Freq
XIN frequency /8
XIN frequency /4
XIN frequency /2
XIN frequency /1
B7
-
b6
-
b5
-
PWMDA sampling rate
XIN frequency /(8 * 256)
XIN frequency /(4 * 256)
XIN frequency /(2 * 256)
XIN frequency /(1 * 256)
b4
-
b3
-
b2
CSR
b1
CSG
b0
CSB
CSR, CSG, CSB - Define the color of bordering or shadowing on characters. The initial value is (0, 0, 0) after
power up.
Column 20
B7
FSW
b6
-
b5
-
b4
-
b3
-
b2
FSR
b1
FSG
b0
FSB
FSW - Enable full screen self-test pattern and force the FBKG pin output to high to disable video RGB while
this bit is set to "1". The self-test pattern’s color is determined by (FSR, FSG, FSB) bits.
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MYSON
TECHNOLOGY
MTV130
FSR, FSG, FSB - Define the color of full screen self-test pattern.
Column 21
B7
WW41
b6
WW40
b5
WW31
b4
WW30
b3
WW21
b2
WW20
b1
WW11
b0
WW10
WW41, WW40 - Determines the shadow width of the window 4 when WSHD bit of th window 4 is enabled.
Please refer to the Table 6 for more details.
TABLE 6. Shadow Width Setting
(WW41, WW40)
Shadow Width
(unit in Pixel)
(0, 0)
2
(0, 1)
4
(1, 0)
6
(1, 1)
8
WW31, WW30 - Determines the shadow width of the window 3 when WSHD bit of th window 3 is enabled.
WW21, WW20 - Determines the shadow width of the window 2 when WSHD bit of th window 2 is enabled.
WW11, WW10 - Determines the shadow width of the window 1 when WSHD bit of th window 1 is enabled.
Column 22
B7
WH41
b6
WH40
b5
WH31
b4
WH30
b3
WH21
b2
WH20
b1
WH11
b0
WH10
WH41, WH40 - Determines the shadow height of the window 4 when WSHD bit of th window 4 is enabled.
Please refer to the Table 7 for more details.
TABLE 7. Shadow Height Setting
(WH41, WH40)
Shadow Height
(unit in Line)
(0, 0)
2
(0, 1)
4
(1, 0)
6
(1, 1)
8
WH31, WH30 - Determines the shadow height of the window 3 when WSHD bit of th window 3 is enabled.
WH21, WH20 - Determines the shadow height of the window 2 when WSHD bit of th window 2 is enabled.
WH11, WH10 - Determines the shadow height of the window 1 when WSHD bit of th window 1 is enabled.
M Pixels
N Horizontal lines
WINDOW AREA
N Horizontal lines
Bordering
Shadowing
Note:
M and N are defined
by the registers of
row 15, column 21
and 22.
M Pixels
FIGURE 8. Character Bordering and Shadowing and Shadowing on Window
3.10 Color encoder
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MYSON
TECHNOLOGY
MTV130
The encoder generates the video output to ROUT, GOUT and BOUT by integrating window color, border
blackedge, luminance output and color selection output (R, G, B) to form the desired video outputs.
3.11 PWM D/A converter
There are 4 open-drain PWM D/A outputs (PWM0 to PWM3). These PWM D/A converter outputs pulse width
are programmable by writing data to Column 23 to 26 registers of Row 15 with 8-bit resolution to control the
pulse width duration from 0/256 to 255/256. And the sampling rate is selected by (PWM1, PWM0) shown as
table 5. In applications, all open-drain output pins should be pulled-up by external resistors to supply voltage
(5V to 9V) for desired output range.
b7
b6
b5
b4
b3
PWMDA0
|
PWMDA3
Column 23
|
Column 26
b2
b1
b0
MSB
LSB
PWMDA0 - PWMDA3 - Define the output pulse width of pin PWM0 to PWM3.
PWMCK
255
0
1
2
m
3
m+1
255
0
1
2
3
4
PWM0
PWM1
PWM2
PWM3
FIGURE 9. 5 Channel PWM Output Rising Edges Are Separated by One PWMCK
Column 27 ~ column 31 : Reserved.
Notes : The register located at column 31 of row 15 are reserved for the testing. Don’t program this
byte anytime in normal operation.
ROW 16
Column 0
B7
-
b6
R1
b5
G1
b4
B1
b3
-
b2
R2
b1
G2
b0
B2
R1, G1, B1 - Define the shadow color of window 1. The initial value is (0, 0, 0) after power up.
R2, G2, B2 - Define the shadow color of window 2. The initial value is (0, 0, 0) after power up.
Column 1
B7
-
b6
R3
b5
G3
b4
B3
b3
-
b2
R4
b1
G4
b0
B4
R3, G3, B3 - Define the shadow color of window 3. The initial value is (0, 0, 0) after power up.
R4, G4, B4 - Define the shadow color of window 4. The initial value is (0, 0, 0) after power up.
Revision 1.0
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MYSON
TECHNOLOGY
Column 2
B7
-
b6
-
b5
-
MTV130
b4
-
b3
-
b2
D2
b1
D1
b0
D0
D2-D0 - These 3 bits define the setup time of HFLB to XIN and the propagation delay R, G, B, FBKG and INT
outputs. Please refer to Figure 12 and Table 8. The initial value is (0, 0, 0) after power up.
TABLE 8. Output and HFLB timing to Pixel Clock
Symbol
tSETUP
tHOLD
tpd
(D2, D1, D0)
0
1
2
3
4
5
6
7
-
Min.
10
11
12
13
14
15
16
17
500
Typ.
-
Max.
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
-
10
11
12
13
14
15
16
17
ns
ns
ns
ns
ns
ns
ns
ns
Column 3 ~ column 31 : Reserved.
4.0 ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage(VDD,VDDA)
Voltage with respect to Ground
Storage Temperature
Ambient Operating Temperature
-0.3 to +7 V
-0.3 to VDD+0.3 V
-65 to +150 oC
0 to +70 oC
5.0 OPERATING CONDITIONS
DC Supply Voltage(VDD,VDDA)
Operating Temperature
+4.75 to +5.25 V
0 to +70 oC
6.0 ELECTRICAL CHARACTERISTICS (Under Operating Conditions)
Symbol
VIH
Revision 1.0
Parameter
Input High Voltage
(pin hflb, vflb, sda, sck, ssb)
Conditions (Notes)
Min.
Max.
Units
-
0.7 * VDD
VDD+0.3
V
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MYSON
TECHNOLOGY
Symbol
MTV130
Parameter
Input Low Voltage
(pin hflb, vflb, sda, sck)
Input Low Voltage
(pin ssb)
Conditions (Notes)
Min.
Max.
Units
-
VSS-0.3
0.3 * VDD
V
-
VSS-0.3
0.2 * VDD
V
VOH
Output High Voltage
IOH ≥ -5 mA
VDD-0.8
-
V
VOL
Output Low Voltage
IOL ≤ 5 mA
-
0.5
V
5
9
V
-
0.5
V
-
25
mA
-
12
mA
VIL
VODH
VODL
ICC
ISB
Open Drain Output High Volt- (For all OD pins, and pulled
age
up by external 5 to 9V power
supply)
5
mA
≥ IDOL
Open Drain Output Low Voltage
( For all OD pins )
Pixel rate=150MHz
Operating Current
Iload = 0uA
Standby Current
Vin = VDD,
Iload = 0uA
7.0 SWITCHING CHARACTERISTIC (Under Operating Conditions)
Symbol
fHFLB
fVFLB
Tr
Tf
tBCSU
tBCH
tDCSU
tDCH
tSCKH
tSCKL
tSU:STA
tHD:STA
tSU:STO
tHD:STO
Parameter
HFLB input frequency
VFLB input frequency
Output rise time
Output fall time
SSB to SCK set up time
SSB to SCK hold time
SDA to SCK set up time
SDA to SCK hold time
SCK high time
SCK low time
START condition setup time
START condition hold time
STOP condition setup time
STOP condition hold time
Min.
15
200
100
200
100
500
500
500
500
500
500
Typ.
3
3
-
Max.
150
200
-
Units
KHz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSETUP
minimum HFLB delay to rising edge of pixel
clock
TBD
-
TBD
ns
tHOLD
minimum pulse width of HFLB
25
-
-
ns
tpd
propagation delay of output to pixel clock
TBD
-
TBD
ns
PIXin
pixel clock input
6
-
150
MHz
Revision 1.0
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MYSON
TECHNOLOGY
MTV130
8.0 TIMING DIAGRAMS
tSCKH
SCK
tSCKL
SSB
tBCSU
tBCH
SDA
tDCSU
tDCH
FIGURE 10. Data interface timing(SPI)
tSCKH
SCK
tSCKL
tSU:STA
tHD:STO
SDA
tHD:STA
tDCSU
tDCH
tSU:STO
FIGURE 11. Data interface timing(I2C)
PlXin
R,G,B, FBKG
HTONE
tpd:: Propagation Delay
tpd
to R,G,B, FBKG
and HTONE outputs
HFLB
t SETUP
t HOLD
FIGURE 12. Output and HFLB Timing to Pixel Clock
Revision 1.0
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28/April/2000
MYSON
TECHNOLOGY
MTV130
9.0 PACKAGE DIMENSION
9.1 16 Pin PDIP 300mil
R10Max
(4X
)
312 +/-12
55 +/-20
R40
90 +/-20
350 +/-20
250 +/-4
65 +/-4
55 +/-4
310Max
75 +/-20
10
90 +/-20
750 +/-10
7
Typ
15 Max
35 +/-5
115 Min
15 Min
100Ty
p
18 +/2Typ
60 +/5Typ
9.2 20 Pin PDIP 300mil
R10Max
(4X
)
312 +/-12
55 +/-20
R40
65 +/-4
55 +/-4
310Max
75 +/-20
90 +/-20
350 +/-20
250 +/-4
10
90 +/-20
1020 +/-10
15 Max
7
Typ
35 +/-5
115 Min
15 Min
100Typ
Revision 1.0
18 +/-2Typ
60 +/-5Typ
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MYSON
TECHNOLOGY
MTV130
9.3 16 Pin SOP 300mil
0.406 +/-0.013
0.295 +/-0.004
0.015x45o
0.406 +/-0.008
7o(4x)
(4x)
0.098 +/-0.006
0.091
0.016 +/-0.004
0.028 +0.022 /-0.013
0.050
9.4 20 Pin SOP 300 mil
0.502+/-0.006inch
20
11
0.406+/-0.012inch
0.295+/-0.004inch
0.020x45
1
10
0.016typ.
0.050typ.
10.0 CHARACTERS AND SYMBOLS PATTERN
Please see the attachment.
Myson Technology, Inc.
http://www.myson.com.tw
No. 2, Industry E. Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
Tel: 886-3-5784866
Fax: 886-3-5785002
Revision 1.0
18/18
Myson Technology USA, Inc.
http://www.myson.com
20111 Stevens Creek Blvd. #138 Cupertino, Ca. 95014, U.S.A.
Tel:408-252-8788
FAX: 408-252-8789
[email protected]
28/April/2000